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WO2017117849A1 - Goa驱动电路 - Google Patents

Goa驱动电路 Download PDF

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Publication number
WO2017117849A1
WO2017117849A1 PCT/CN2016/074497 CN2016074497W WO2017117849A1 WO 2017117849 A1 WO2017117849 A1 WO 2017117849A1 CN 2016074497 W CN2016074497 W CN 2016074497W WO 2017117849 A1 WO2017117849 A1 WO 2017117849A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
signal
control signal
phase
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Application number
PCT/CN2016/074497
Other languages
English (en)
French (fr)
Inventor
肖军城
颜尧
曹尚操
戴荣磊
Original Assignee
武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US15/026,595 priority Critical patent/US9933889B2/en
Publication of WO2017117849A1 publication Critical patent/WO2017117849A1/zh

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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
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    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
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    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
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    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G09G2310/021—Double addressing, i.e. scanning two or more lines, e.g. lines 2 and 3; 4 and 5, at a time in a first field, followed by scanning two or more lines in another combination, e.g. lines 1 and 2; 3 and 4, in a second field
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0245—Clearing or presetting the whole screen independently of waveforms, e.g. on power-on
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
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    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
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    • G—PHYSICS
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    • G09G2354/00—Aspects of interface with display user

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA driving circuit.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • AMLCD Active Matrix Liquid Crystal Display
  • the active matrix liquid crystal display comprises a plurality of pixels, each of which has a Thin Film Transistor (TFT).
  • the gate of the TFT is connected to a scan line extending in a horizontal direction
  • the drain is connected to a data line extending in a vertical direction
  • the source of the TFT is connected to a corresponding pixel electrode. If a sufficient positive voltage is applied to a certain scanning line in the horizontal direction, all the TFTs connected to the scanning line are turned on, and the data signal voltage loaded on the data line is written into the pixel electrode to control different liquid crystals. The transparency then achieves the effect of controlling color.
  • the driving of the horizontal scanning line of the active liquid crystal display panel is initially completed by an external integrated circuit (IC), and the external IC can control the stepwise charging and discharging of the horizontal scanning lines of each level.
  • IC integrated circuit
  • GOA technology Gate Driver on Array
  • the driving circuit of the horizontal scanning line can be fabricated on the substrate around the display area by using an array process of the liquid crystal display panel, so that it can replace the external IC to complete the horizontal scanning line.
  • Drive GOA technology can reduce the bonding process of external ICs, have the opportunity to increase production capacity and reduce product cost, and can make LCD panels more suitable for making narrow-frame display products.
  • the embedded touch technology integrates the touch panel and the liquid crystal panel into one body, and embeds the touch panel function into the liquid crystal panel, so that the liquid crystal panel has the functions of displaying and sensing the touch input at the same time.
  • touch display panels have been widely accepted and used by people, such as smart phones, tablets, etc., using touch display panels.
  • the existing embedded touch technology is mainly divided into two types: one is that the touch circuit is on the cell type (On Cell), and the other is that the touch circuit is in the cell type (In Cell).
  • the gate scan driving signals are all Simultaneous output (All Gate On) function to open the TFT of all pixels in the panel, clear the residual potential in the pixel, and also need to stop the gate scan driving at any time during the normal operation of the GOA driving circuit during the display process.
  • the signal is output for touch scanning. After the touch scanning is finished, the GOA driving circuit returns to normal, and the output of the gate scanning driving signal is continued to be displayed.
  • the existing GOA driving circuit applied to the touch display panel has the risk of circuit failure and the stability is poor when implementing the All Gate On and the touch scanning function.
  • the object of the present invention is to provide a GOA driving circuit, which can ensure the normal display of the touch display panel after the black screen wakes up, eliminate the risk of failure of the GOA circuit in implementing the All Gate On and the touch scanning function, and improve the stability of the GOA driving circuit. Sex.
  • the present invention provides a GOA driving circuit, comprising: cascaded multi-level GOA units, each level of GOA units including: forward and reverse scanning control module, basic output module, basic output pull-down module, a node control module, a second node control module, an output control module, a reset module, a voltage stabilization module, and a second node charging module;
  • n be a positive integer, in addition to the first-level GOA unit, the second-level GOA unit, the second-order GOA unit, and the last-level GOA unit, in the n-th GOA unit:
  • the forward-reverse scan control module includes: a ninth thin film transistor, a gate of the ninth thin film transistor is connected to an output end of the two-stage n-2th GOA unit, and a source is connected to the forward scan control signal, The drain is electrically connected to the first node; and the tenth thin film transistor, the gate of the tenth thin film transistor is connected to the output end of the next two stages of the n+2th GOA unit, and the source is connected to the reverse scan control signal The drain is electrically connected to the first node;
  • the basic output module includes: a seventh thin film transistor, a gate of the seventh thin film transistor is electrically connected to a drain of the sixth thin film transistor, a source is connected to the Mth clock signal, and a drain is electrically connected to the output And a first capacitor, one end of the first capacitor is electrically connected to the drain of the sixth thin film transistor, and the other end is electrically connected to the output end;
  • the basic output pull-down module includes: an eighth thin film transistor, a gate of the eighth thin film transistor is electrically connected to the second node, a source is connected to the composite signal, and a drain is electrically connected to the output end; and the second capacitor is One end of the second capacitor is electrically connected to the second node, and the other end is connected to the composite signal;
  • the first node control module includes: a fourth thin film transistor, the gate of the fourth thin film transistor is connected to the Mth clock signal, the source is electrically connected to the drain of the fifth thin film transistor, and the drain is electrically connected And a fifth thin film transistor, the gate of the fifth thin film transistor is electrically connected to the second node, and the source is connected to the composite signal;
  • the second node control module includes: an eleventh thin film transistor, a gate of the eleventh thin film transistor is connected to a first global control signal, a source is connected to the composite signal, and a drain is electrically connected to the second node;
  • the output control module includes: a twelfth thin film transistor, a gate and a source of the twelfth thin film transistor are respectively connected to a first global control signal, a drain is electrically connected to the output end; and a thirteenth thin film transistor is The gate of the thirteenth thin film transistor is connected to the second global control signal, the source is connected to the composite signal, and the drain is electrically connected to the output end;
  • the reset module includes: a first thin film transistor, a gate and a source of the first thin film transistor are connected to a reset signal, and a drain is electrically connected to the second node;
  • the voltage stabilizing module includes: a sixth thin film transistor, a gate of the sixth thin film transistor is connected to a control potential, a source is electrically connected to the first node, and a drain is electrically connected to a gate of the seventh thin film transistor;
  • the second node charging module includes: a third thin film transistor, a gate of the third thin film transistor is connected to the M-2th clock signal, a source is connected to the control potential, and a drain is electrically connected to the second node; And a second thin film transistor, the gate of the second thin film transistor is electrically connected to the first node, the source is connected to the M-2th clock signal, and the drain is electrically connected to the second node;
  • the working process of the GOA driving circuit includes: a black screen wake-up phase, a reset phase, a normal display phase, and a touch scanning phase;
  • the first global control signal controls the twelfth thin film transistor and the eleventh thin film transistor of all stages of the GOA unit to be turned on, and the second global control signal controls the thirteenth thin film transistor of all stages of the GOA unit to be turned off;
  • the first global control signal controls the twelfth thin film transistor and the eleventh thin film transistor of all stages of the GOA unit to be turned off, and the second global control signal controls the thirteenth thin film transistor of all the GOA units to be turned off.
  • the second global control signal controls the thirteenth thin film transistor of all stages of the GOA unit to be turned on
  • the first global control signal controls the twelfth thin film transistor and the eleventh thin film transistor of all stages of the GOA unit to be turned off.
  • the reset signal provides a single pulse to control the opening of the first thin film transistor, resetting the potential of the second node, and the single pulse duration of the reset signal is at least the sum of the initial pulse durations of the first clock signal and the second clock signal;
  • the composite signal and the potential of the control potential are high and low, and the forward scan control signal and the potential of the reverse scan control signal are high and low; in the touch scan phase,
  • the composite signal is a pulse signal having the same frequency as the touch scan signal.
  • each clock signal is a periodic pulse signal; in the touch scanning phase, the potential of each clock signal is constant.
  • each clock signal is a periodic pulse signal; in the touch scanning phase, each clock signal is a pulse signal having the same frequency as the touch scan signal.
  • each of the thin film transistors is an N-type thin film transistor
  • the first global control signal is high and the second global control signal is low; in the reset phase and the normal display phase, the first global control signal and the second global control signal are both low.
  • the second global control signal is at a high potential, and the first global control signal is at a low potential;
  • each clock signal is a periodic high-potential pulse signal.
  • the potentials of the various clock signals are all at a constant low potential.
  • the forward scanning control signal is a constant voltage high potential, and the reverse scanning control signal is a constant voltage low potential; in the reverse scanning, the forward scanning control signal is a constant voltage low potential, and the reverse scanning The control signal is a constant voltage high potential.
  • each of the thin film transistors is a P-type thin film transistor
  • the first global control signal is low, and the second global control signal is high; in the reset phase and the normal display phase, the first global control signal and the second global control signal are both high. In the touch scanning phase, the second global control signal is low, and the first global control signal is high;
  • the potential of the composite signal is a high potential, and the control potential is a low potential; each clock signal is a periodic low-potential pulse signal.
  • the potentials of the various clock signals are all at a constant high potential.
  • the forward scanning control signal is a constant voltage low potential, and the reverse scanning control signal is a constant voltage high potential; in the reverse scanning, the forward scanning control signal is a constant voltage high potential, and the reverse scanning The control signal is a constant voltage low potential.
  • the gates of the ninth thin film transistors are all connected to the start signal of the circuit; in the penultimate stage GOA unit and the last stage GOA unit, the first The gate of each of the ten thin film transistors is connected to the start signal of the circuit;
  • the GOA driving circuit includes four clock signals: first, second, third, and fourth clock signals; when the Mth clock signal is the first clock signal, the M-2th clock signal is a third clock signal; when the Mth clock signal is the second clock signal, the M-2th clock signal is a fourth clock signal; in the reset phase and the normal display phase, the first and the Second, the third, and fourth clock signals have the same pulse period, and the pulse signal of the previous clock signal ends while the pulse signal of the latter clock signal is generated.
  • the invention also provides a GOA driving circuit, comprising: a cascaded multi-level GOA unit, each level GOA unit comprises: a forward and reverse scanning control module, a basic output module, a basic output pull-down module, a first node control module, a second node control module, an output control module, a reset module, a voltage stabilization module, and a second node charging module;
  • n be a positive integer, in addition to the first-level GOA unit, the second-level GOA unit, the second-order GOA unit, and the last-level GOA unit, in the n-th GOA unit:
  • the forward-reverse scan control module includes: a ninth thin film transistor, a gate of the ninth thin film transistor is connected to an output end of the two-stage n-2th GOA unit, and a source is connected to the forward scan control signal, The drain is electrically connected to the first node; and the tenth thin film transistor, the gate of the tenth thin film transistor is connected to the output end of the next two stages of the n+2th GOA unit, and the source is connected to the reverse scan control signal The drain is electrically connected to the first node;
  • the basic output module includes: a seventh thin film transistor, a gate of the seventh thin film transistor is electrically connected to a drain of the sixth thin film transistor, a source is connected to the Mth clock signal, and a drain is electrically connected to the output And a first capacitor, one end of the first capacitor is electrically connected to the drain of the sixth thin film transistor, and the other end is electrically connected to the output end;
  • the basic output pull-down module includes: an eighth thin film transistor, a gate of the eighth thin film transistor is electrically connected to the second node, a source is connected to the composite signal, and a drain is electrically connected to the output end; and the second capacitor is One end of the second capacitor is electrically connected to the second node, and the other end is connected to the composite signal;
  • the first node control module includes: a fourth thin film transistor, the gate of the fourth thin film transistor is connected to the Mth clock signal, the source is electrically connected to the drain of the fifth thin film transistor, and the drain is electrically connected And a fifth thin film transistor, the gate of the fifth thin film transistor is electrically connected to the second node, and the source is connected to the composite signal;
  • the second node control module includes: an eleventh thin film transistor, a gate of the eleventh thin film transistor is connected to a first global control signal, a source is connected to the composite signal, and a drain is electrically connected to the second node;
  • the output control module includes: a twelfth thin film transistor, a gate and a source of the twelfth thin film transistor are respectively connected to a first global control signal, a drain is electrically connected to the output end; and a thirteenth thin film transistor is The gate of the thirteenth thin film transistor is connected to the second global control signal, the source is connected to the composite signal, and the drain is electrically connected to the output end;
  • the reset module includes: a first thin film transistor, a gate and a source of the first thin film transistor are connected to a reset signal, and a drain is electrically connected to the second node;
  • the voltage stabilizing module includes: a sixth thin film transistor, a gate of the sixth thin film transistor is connected to a control potential, a source is electrically connected to the first node, and a drain is electrically connected to the seventh thin film transistor Gate
  • the second node charging module includes: a third thin film transistor, a gate of the third thin film transistor is connected to the M-2th clock signal, a source is connected to the control potential, and a drain is electrically connected to the second node; And a second thin film transistor, the gate of the second thin film transistor is electrically connected to the first node, the source is connected to the M-2th clock signal, and the drain is electrically connected to the second node;
  • the working process of the GOA driving circuit includes: a black screen wake-up phase, a reset phase, a normal display phase, and a touch scanning phase;
  • the first global control signal controls the twelfth thin film transistor and the eleventh thin film transistor of all stages of the GOA unit to be turned on, and the second global control signal controls the thirteenth thin film transistor of all stages of the GOA unit to be turned off;
  • the first global control signal controls the twelfth thin film transistor and the eleventh thin film transistor of all stages of the GOA unit to be turned off, and the second global control signal controls the thirteenth thin film transistor of all the GOA units to be turned off.
  • the second global control signal controls the thirteenth thin film transistor of all stages of the GOA unit to be turned on
  • the first global control signal controls the twelfth thin film transistor and the eleventh thin film transistor of all stages of the GOA unit to be turned off.
  • the reset signal provides a single pulse to control the opening of the first thin film transistor, resetting the potential of the second node, and the single pulse duration of the reset signal is at least the sum of the initial pulse durations of the first clock signal and the second clock signal;
  • the composite signal and the potential of the control potential are high and low, and the forward scan control signal and the potential of the reverse scan control signal are high and low;
  • the composite signal is a pulse signal having the same frequency as the touch scan signal;
  • each clock signal is a periodic pulse signal; in the touch scanning phase, the potential of each clock signal is constant;
  • each of the thin film transistors is an N-type thin film transistor
  • the first global control signal is high and the second global control signal is low; in the reset phase and the normal display phase, the first global control signal and the second global control signal are both low.
  • the second global control signal is at a high potential, and the first global control signal is at a low potential;
  • the potential of the composite signal is a low potential, and the control potential is a high potential; each clock signal is a periodic high-potential pulse signal;
  • the forward scanning control signal in the forward scanning, is a constant voltage high potential, and the reverse scanning control signal is a constant voltage low potential; in the reverse scanning, the forward scanning control signal is a constant voltage low potential, The scan control signal is a constant voltage high potential;
  • the gates of the ninth thin film transistors are all connected to the start signal of the circuit; in the penultimate stage GOA unit and the last stage GOA unit, The start signal of the gate of the tenth thin film transistor is connected to the circuit;
  • the clock signal includes: first, second, third, and fourth clock signals; when the Mth clock signal is the first clock signal, the M-2th clock signal is the third clock signal When the Mth clock signal is the second clock signal, the M-2th clock signal is the fourth clock signal; in the reset phase and the normal display phase, the first, second, third, And the pulse period of the fourth clock signal is the same, the pulse signal of the previous clock signal ends and the pulse signal of the latter clock signal is generated.
  • a GOA driving circuit controls the twelfth thin film transistor of all stages of GOA units to be turned on by a first global control signal during a black screen wake-up phase to implement the All Gate On function, through the first global
  • the control signal controls the eleventh thin film transistor of all stages of the GOA unit to be turned on, and pulls the potential of the second node to ensure the normal output of the output terminal; in the reset phase, the first thin film transistor is controlled by the reset signal to reset the potential of the second node, and set
  • the single pulse duration of the reset signal is at least the sum of the initial pulse durations of the first clock signal and the second clock signal, ensuring that the second node is at a high potential after the black screen wakes up, so that the output of the GOA driving circuit is normal, and the touch display panel is black.
  • the GOA driving circuit of the invention can ensure the normal display of the touch display panel after the black screen wakes up, eliminate the risk of failure of the GOA circuit in implementing the All Gate On and the touch scanning function, and improve the stability of the GOA driving circuit.
  • FIG. 1 is a circuit diagram of a first embodiment of a GOA driving circuit of the present invention
  • FIG. 2 is a timing diagram of the GOA circuit shown in FIG. 1 in a black screen wake-up phase and a reset phase;
  • FIG. 3 is a first timing diagram of a normal display phase and a touch scan phase of the GOA circuit shown in FIG. 1 during forward scanning;
  • FIG. 4 is a second timing diagram of a normal display phase and a touch scan phase of the GOA circuit shown in FIG. 1 during forward scanning;
  • Figure 5 is a circuit diagram of a first stage GOA unit of the first embodiment of the GOA driving circuit of the present invention.
  • Figure 6 is a circuit diagram of a second stage GOA unit of the first embodiment of the GOA driving circuit of the present invention.
  • Figure 7 is a circuit diagram of a penultimate stage GOA unit of the first embodiment of the GOA driving circuit of the present invention.
  • Figure 8 is a circuit diagram of a final stage GOA unit of the first embodiment of the GOA driving circuit of the present invention.
  • Figure 9 is a circuit diagram of a second embodiment of the GOA driving circuit of the present invention.
  • the present invention provides a GOA driving circuit, including: a cascaded multi-level GOA unit, each level of the GOA unit includes: a forward-reverse scanning control module 100, a basic output module 200, and a basic output.
  • n be a positive integer, in addition to the first-level GOA unit, the second-level GOA unit, the second-order GOA unit, and the last-level GOA unit, in the n-th GOA unit:
  • the forward-reverse scan control module 100 includes: a ninth thin film transistor T9, the gate of the ninth thin film transistor T9 is connected to the output terminal G(n-2) of the upper two-stage n-2th GOA unit, and the source
  • the pole is connected to the forward scan control signal U2D, the drain is electrically connected to the first node Q(n); and the tenth thin film transistor T10, the gate of the tenth thin film transistor T10 is connected to the next two levels n+2
  • the basic output module 200 includes: a seventh thin film transistor T7, the gate of the seventh thin film transistor T7 is electrically connected to the drain of the sixth thin film transistor T6, and the source is connected to the Mth clock signal CK(M).
  • the drain is electrically connected to the output terminal G(n); and the first capacitor C1.
  • One end of the first capacitor C1 is electrically connected to the drain of the sixth thin film transistor T6, and the other end is electrically connected to the output terminal G. (n);
  • the basic output pull-down module 300 includes: an eighth thin film transistor T8, the gate of the eighth thin film transistor T8 is electrically connected to the second node P(n), the source is connected to the composite signal CS, and the drain is electrically connected. At the output G(n); and the second capacitor C2, one end of the second capacitor C2 is electrically Connected to the second node P(n), and the other end accesses the composite signal CS;
  • the first node control module 400 includes a fourth thin film transistor T4, the gate of the fourth thin film transistor T4 is connected to the Mth clock signal CK(M), and the source is electrically connected to the fifth thin film transistor T5.
  • the drain and the drain are electrically connected to the first node Q(n); and the fifth thin film transistor T5.
  • the gate of the fifth thin film transistor T5 is electrically connected to the second node P(n), and the source is connected.
  • the second node control module 500 includes: an eleventh thin film transistor T11, the gate of the eleventh thin film transistor T11 is connected to the first global control signal Gas1, the source is connected to the composite signal CS, and the drain is electrically connected.
  • the second node P(n) At the second node P(n);
  • the output control module 600 includes a twelfth thin film transistor T12.
  • the gate and the source of the twelfth thin film transistor T12 are both connected to the first global control signal Gas1, and the drain is electrically connected to the output terminal G(n).
  • a thirteenth thin film transistor T13 the gate of the thirteenth thin film transistor T13 is connected to the second global control signal Gas2, the source is connected to the composite signal CS, and the drain is electrically connected to the output terminal G(n) ;
  • the reset module 700 includes: a first thin film transistor T1, a gate and a source of the first thin film transistor T1 are connected to a reset signal Reset, and a drain is electrically connected to the second node P(n);
  • the voltage stabilizing module 800 includes: a sixth thin film transistor T6, the gate of the sixth thin film transistor T6 is connected to the control potential CV, the source is electrically connected to the first node Q(n), and the drain is electrically connected to the drain a gate of the seventh thin film transistor T7;
  • the second node charging module 900 includes: a third thin film transistor T3, the gate of the third thin film transistor T3 is connected to the M-2th clock signal CK(M-2), and the source is connected to the control potential CV.
  • the drain is electrically connected to the second node P(n); and the second thin film transistor T2, the gate of the second thin film transistor T2 is electrically connected to the first node Q(n), and the source is connected to the M-th Two clock signals CK (M-2), and the drain is electrically connected to the second node P(n).
  • the working process of the GOA driving circuit includes: a black screen wake-up phase, a reset phase, a normal display phase, and a touch scanning phase.
  • the first global control signal Gas1 controls the twelfth thin film transistor T12 and the eleventh thin film transistor T11 of all stages of the GOA unit to be turned on, and the second global control signal Gas2 controls the thirteenth thin film of all the GOA units.
  • the transistor T13 is turned off; in the reset phase and the normal display phase, the first global control signal Gas1 controls the twelfth thin film transistor T12 and the eleventh thin film transistor T11 of all stages of the GOA unit to be turned off, and the second global control signal Gas2 controls all stages.
  • the thirteenth thin film transistor T13 of the GOA unit is turned off; in the touch scanning phase, the second global control signal Gas2 controls the thirteenth thin film transistor T13 of all stages of the GOA unit to be turned on, and the first global control signal Gas1 controls all stages of the GOA unit Twelfth thin film transistor T12 and the eleventh thin film transistor T11 are turned off;
  • the reset signal Reset provides a single pulse to control the opening of the first thin film transistor T1, resetting the potential of the second node P(n), and the single pulse duration of the reset signal Reset is at least the first clock signal CK(1) and the first The sum of the initial pulse durations of the two clock signals CK(2);
  • the potential of the composite signal CS and the control potential CV is high and low, and the potential of the forward scan control signal U2D and the reverse scan control signal D2U is high and low;
  • the composite signal CS is a pulse signal having the same frequency as the touch scan signal TP.
  • each thin film transistor is an N-type thin film transistor;
  • the first global control signal Gas1 is at a high potential, and the second global control signal Gas2 is at a low potential; in the reset phase and the normal display phase, the first global control signal Gas1 and the second global control signal Gas2 are both It is low potential; in the touch scanning phase, the second global control signal Gas2 is at a high potential, and the first global control signal Gas1 is at a low potential.
  • the single pulse duration of the reset signal Reset is at least the sum of the initial pulse durations of the first clock signal CK(1) and the second clock signal CK(2) refers to the reset signal.
  • the single pulse of Reset is generated earlier than the first pulse signal of the first clock signal CK(1) or simultaneously with the first pulse signal of the first clock signal CK(1), later than the second clock signal CK
  • the first pulse signal of (2) ends or ends at the same time as the first pulse signal of the second clock signal CK(2).
  • each clock signal is a periodic high-potential pulse signal.
  • the potentials of the respective clock signals are both constant and low; optionally, as shown in FIG. 4, after the timing shown in FIG. 3 is improved, each The strip clock signals are all pulse signals having the same frequency as the touch scan signal TP.
  • the forward scan control signal U2D is a constant voltage high potential
  • the reverse scan control signal D2U is a constant voltage low potential
  • the forward scan control signal U2D is a constant voltage Low potential
  • the reverse scan control signal D2U is a constant voltage high potential
  • each of the thin film transistors is a P-type thin film transistor; then, in the black-screen wake-up phase, the first global control signal Gas1 is low, and the second global The control signal Gas2 is at a high potential; in the reset phase and the normal display phase, the first global control signal Gas1 and the second global control signal Gas2 are both high; in the touch scanning phase, the second global control signal Gas2 is At a low potential, the first global control signal Gas1 is at a high potential.
  • each clock signal is a periodic low-potential pulse signal.
  • the potentials of the respective clock signals are constant high potential; optionally, after the timing is improved, each clock signal is a pulse signal having the same frequency as the touch scan signal TP.
  • the forward scanning control signal U2D is a constant voltage low potential
  • the reverse scanning control signal D2U is a constant voltage high potential
  • the forward scanning control signal U2D is a constant voltage
  • the high potential, reverse scan control signal D2U is a constant voltage low potential.
  • the gates of the ninth thin film transistor T9 are all connected to the start signal STV of the circuit.
  • the gates of the tenth thin film transistor T10 are all connected to the start signal STV of the circuit.
  • the GOA driving circuit includes four clock signals: first, second, third, and fourth clock signals CK(1), CK(2), CK(3), CK(4).
  • first, second, third, and fourth clock signals CK(1), CK(2), CK(3), CK(4) When the Mth clock signal CK(M) is the first clock signal CK(1), the M-2th clock signal CK(M-2) is the third clock signal CK(3); When the Mth clock signal CK(M) is the second clock signal CK(2), the M-2th clock signal CK(M-2) is the fourth clock signal CK(4).
  • the pulse periods of the first, second, third, and fourth clock signals CK(1), CK(2), CK(3), and CK(4) are the same, before
  • the pulse signal of one clock signal ends, the pulse signal of the latter clock signal is generated, that is, the first pulse signal of the first clock signal CK(1) is first generated, and the first clock signal CK(1)
  • the first pulse signal of the second clock signal CK(2) is generated while the first pulse signal ends, and the first pulse signal of the second clock signal CK(2) ends simultaneously
  • the first pulse signal of the three clock signals CK(3) is generated, and the first pulse signal of the third clock signal CK(3) ends while the first of the fourth clock signal CK(4)
  • the pulse signal is generated, and the second pulse signal of the first clock signal CK(1) is generated while the first pulse signal of the fourth clock signal CK(4) ends.
  • the falling edge of the previous clock signal is generated simultaneously with the rising edge of the next clock signal; corresponding to the second embodiment of the present invention, the previous clock is The rising edge of the signal is generated simultaneously with the falling edge of the next clock signal.
  • FIG. 1 , FIG. 2 and FIG. 3 at the same time, or refer to FIG. 1 , FIG. 2 and FIG. 4 at the same time.
  • the forward scanning of the first embodiment of the GOA driving circuit of the present invention is taken as an example to illustrate the present invention.
  • the working process of the GOA drive circuit is taken as an example to illustrate the present invention.
  • each of the thin film transistors is an N-type thin film transistor
  • the working process of the GOA driving circuit is: black screen wake-up phase, reset phase, normal display phase, and touch Control the scanning phase.
  • the specific work process is as follows:
  • the first global control signal Gas1 is at a high potential (5V), and the twelfth thin film transistor T12 of all stages of the GOA unit is controlled to be turned on, and the output of all the stages of the GOA unit outputs the high potential of the first global signal Gas1 to implement All Gate On.
  • the first global control signal Gas1 controls the eleventh thin film transistor T11 of all stages of the GOA unit to be turned on, and the composite signal CS provides a low potential (-5V) at this stage, thereby pulling down the second node of all stages of the GOA unit.
  • the potential causes the eighth thin film transistor T8 to be turned off, preventing it from being pulled down to the output terminal G(n), ensuring smooth operation of the All Gate On.
  • the second global control signal Gas2 is low (-5V), and the thirteenth thin film transistor T13 of all stages of the GOA unit is controlled to be turned off, and the composite signal CS is also prevented from being pulled down to the output terminal G(n).
  • the first global control signal Gas1 and the second global control signal Gas2 are both low (-7V), and control the eleventh thin film transistor T11, the twelfth thin film transistor T12, and the thirteenth thin film transistor of all stages of the GOA unit.
  • T13 is turned off; the reset signal Reset provides a single high-potential pulse (10V), controls the first thin film transistor T1 to be turned on, and the high potential (10V) of the control potential CV resets the potential of the second node P(n) to the high via the first thin film transistor.
  • the eighth thin film transistor T8 is turned on, and at this stage, the composite signal CS provides a low potential (-7V), thereby pulling down the output terminal G(n) to a low potential.
  • the single pulse signal of the reset signal Reset is generated earlier than the first pulse signal of the first clock signal CK(1) or simultaneously with the first pulse signal of the first clock signal CK(1),
  • the first pulse signal that is later than the second clock signal CK(2) ends or ends at the same time as the first pulse signal of the second clock signal CK(2), that is, the single pulse duration of the reset signal Reset is at least the first
  • the sum of the initial pulse durations of the clock signal CK(1) and the second clock signal CK(2) can ensure that the second node P(n) is at a high potential after the black screen wakes up, so that the output of the GOA driving circuit is normal, and the touch display The panel enters the normal display after waking up with a black screen.
  • the first global control signal Gas1 and the second global control signal Gas2 are still both low (-7V), and control the eleventh thin film transistor T11, the twelfth thin film transistor T12, and the thirteenth thin film of all stages of the GOA unit.
  • Transistor T13 is turned off; reset signal Reset becomes low (-7V), and first thin film transistor T1 is turned off.
  • the potential of the composite signal CS is a low potential (-7V)
  • the control potential CV is a high potential (10V)
  • each clock signal is a periodic high potential pulse signal
  • the forward scan control signal U2D is a constant voltage high potential ( 10V)
  • the reverse scan control signal D2U is a constant voltage low potential (-7V).
  • the output terminal G(n-2) of the n-2th GOA unit or the start signal STV of the circuit provides a high potential (10V), and the M-2th clock signal CK(M-2) Providing a high potential (10V), the ninth thin film transistor T9 is turned on, the first node Q(n) is charged to a high potential, the third thin film transistor T3 is turned on, the second node P(n) is charged to a high potential, and the eighth thin film transistor T8 is turned on. Output G(n) is still pulled down to low potential (-7V);
  • the output terminal G(n-2) of the n-2th GOA unit and the M-2th clock signal CK(M-2) both become low (-7V), and the ninth and third thin film transistors T9 T3 is turned off, the first node Q(n) is kept high by the action of the first capacitor C1, the second thin film transistor T2 is turned on, and the second node P(n) is pulled down to a low potential;
  • the Mth clock signal CK(M) becomes a high potential (10V), and since the high potential of the control potential CV always causes the sixth thin film transistor T6 to be turned on, the seventh thin film transistor T7 is controlled by the first node Q(n).
  • the output terminal G(n) When turned on, the output terminal G(n) outputs the high potential of the Mth clock signal (10V); when CK(M) goes low (-7V), the output terminal G(n) outputs the Mth clock signal CK. (M) low potential (-7V);
  • the M-2th clock signal CK(M-2) becomes high (10V) again, the third thin film transistor T3 is turned on, the second node P(n) is charged to a high potential, and the fifth and eighth thin film transistors are turned on. T5, T8 are turned on, and the output terminal G(n) is pulled down to a low potential (-7V);
  • the Mth clock signal CK(M) becomes high (10V) again, the fourth and fifth thin film transistors T4, T5 are turned on, and the first node Q(n) is pulled down to a low potential, and at this point, the output terminal G (n) maintaining a low potential (-7V) with the first node Q(n);
  • the second global signal Gas2 provides a high potential (10V)
  • the first global signal Gas1 provides a low potential (-11.5V)
  • the twelfth thin film transistor T12 and the eleventh thin film transistor T11 are turned off
  • the thirteenth thin film transistor T13 is turned on.
  • the composite signal CS is transmitted to the output terminal G(n) via the thirteenth thin film transistor T13 for output.
  • the composite signal CS is the same pulse signal as the touch scan signal TP, and the potential of the touch scan signal TP When the transition between 0V and 4.5V occurs, the potential of the composite signal CS jumps between -7V and -11.5V, which can ensure the normal operation of the touch scan.
  • the potentials of the first to fourth clock signals CK(1)-CK(4) are both constant low (-7V).
  • the timing shown in FIG. 4 is improved, and the first to fourth clock signals CK(1)-CK(4) are also the same pulse signals as the touch scan signal TP, and the potential is at - The transition between 7V and -11.5V, such an improvement can eliminate the output abnormality of the output terminal G(n) of the GOA unit whose first node Q(n) is high, further improving the stability of the GOA circuit.
  • the reverse scan works in the same way as the forward scan. It is only necessary to set the reverse scan control signal D2U to a constant voltage high potential, and the forward scan control signal U2D to a constant voltage low potential. The direction of the drawing is changed from the first level to the last level scanning to the last level to the first level scanning, and details are not described herein again.
  • the second embodiment shown in FIG. 9 is similar to the specific working process of the first embodiment described above, and only needs to change the potential of each signal and node, and details are not described herein again.
  • the present invention provides a GOA driving circuit that controls the twelfth thin film transistor of all stages of the GOA unit to be turned on by the first global control signal during the black screen wake-up phase to implement the All Gate On function through the first global control.
  • the signal controls the eleventh thin film transistor of all stages of the GOA unit to open, and pulls the potential of the second node to ensure the normal output of the output terminal; in the reset phase, the first thin film transistor is controlled by the reset signal to reset the potential of the second node, and the reset is set.
  • the single pulse duration of the signal is at least the sum of the initial pulse durations of the first clock signal and the second clock signal, ensuring that the second node is at a high potential after the black screen wakes up, so that the GOA driving circuit output is normal, and the touch display panel wakes up in a black screen. Then enter the normal display; in the touch scanning phase, the thirteenth thin film transistor of all the GOA units is controlled to be turned on by the second global control signal, so that the output end of each level of the GOA unit outputs a composite signal, and the composite signal at this stage is touch Scanning the pulse signal with the same signal frequency to ensure the normal operation of the touch scan. Therefore, the GOA driving circuit of the invention can ensure the normal display of the touch display panel after the black screen wakes up, eliminate the risk of failure of the GOA circuit in implementing the All Gate On and the touch scanning function, and improve the stability of the GOA driving circuit.

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Abstract

一种GOA驱动电路，在黑屏唤醒阶段通过第一全局控制信号（GAS1）控制第十二薄膜晶体管（T12）打开，实现All Gate On功能，同时控制第十一薄膜晶体管（T11）下拉第二节点（P（n））的电位；在复位阶段通过复位信号（Reset）控制第一薄膜晶体管（T1）来复位第二节点（P（n））的电位，并设置复位信号（Reset）的单个脉冲时长至少为第一条时钟信号（CK（M））与第二条时钟信号（CK（M-2））的初始脉冲时长之和，保证黑屏唤醒后第二节点（P（n））处于高电位，GOA驱动电路输出正常；在触控扫描阶段通过第二全局控制信号（Gas2）控制第十三薄膜晶体管（T13）打开，使得各级GOA单元的输出端输出复合信号（CS），此阶段的复合信号（CS）为与触控扫描信号频率相同的脉冲信号，保证触控扫描的正常进行。

Description

GOA驱动电路 技术领域
本发明涉及显示技术领域，尤其涉及一种GOA驱动电路。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
主动矩阵式液晶显示器(Active Matrix Liquid Crystal Display，AMLCD)是目前最常用的液晶显示装置，所述主动矩阵式液晶显示器包含多个像素，每个像素具有一个薄膜晶体管(Thin Film Transistor，TFT)，该TFT的栅极连接至沿水平方向延伸的扫描线，漏极连接至沿垂直方向延伸的数据线，而该TFT的源极连接至对应的像素电极。如果在水平方向的某一扫描线上施加足够的正电压，则会使得连接在该条扫描线上的所有TFT打开，将数据线上所加载的数据信号电压写入像素电极中，控制不同液晶的透光度进而达到控制色彩的效果。
主动式液晶显示面板水平扫描线的驱动(即栅极驱动)最初由外接的集成电路(Integrated Circuit，IC)来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。GOA技术(Gate Driver on Array)即阵列基板行驱动技术，可以运用液晶显示面板的阵列制程将水平扫描线的驱动电路制作在显示区周围的基板上，使之能替代外接IC来完成水平扫描线的驱动。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框的显示产品。
嵌入式触控技术是将触控面板和液晶面板结合为一体，并将触控面板功能嵌入到液晶面板内，使得液晶面板同时具备显示和感知触控输入的功能。随着显示技术的飞速发展，触控显示面板已经广泛地被人们所接受及使用，如智能手机、平板电脑等均使用了触控显示面板。
现有的嵌入式触控技术主要分为两种：一种是触控电路在液晶盒上型(On Cell)，另一种是触控电路在液晶盒内型(In Cell)。
应用于触控显示面板的GOA驱动电路在面板黑屏唤醒时，通常需要实现在一段时间内使各级GOA单元的输出端全部打开，栅极扫描驱动信号全 部同时输出(All Gate On)的功能，以将面板内所有像素的TFT打开，清空像素中的残留电位，同时还需要在显示过程中GOA驱动电路正常工作时，在任一时刻停止栅极扫描驱动信号输出，以进行触控扫描，触控扫描结束后，GOA驱动电路再恢复正常，继续输出栅极扫描驱动信号进行显示。然而，现有的应用于触控显示面板的GOA驱动电路在实现All Gate On和触控扫描功能时均存在电路失效的风险，稳定性较差。
发明内容
本发明的目的在于提供一种GOA驱动电路，能够保证触控显示面板在黑屏唤醒之后进行正常显示，消除GOA电路在实现All Gate On和触控扫描功能时的失效风险，提升GOA驱动电路的稳定性。
为实现上述目的，本发明提供了一种GOA驱动电路，包括：级联的多级GOA单元，每一级GOA单元均包括：正反向扫描控制模块、基本输出模块、基本输出下拉模块、第一节点控制模块、第二节点控制模块、输出控制模块、复位模块、稳压模块、以及第二节点充电模块；
设n为正整数，除第一级GOA单元、第二级GOA单元、倒数第二级GOA单元、及最后一级GOA单元外，在第n级GOA单元中：
所述正反向扫描控制模块包括：第九薄膜晶体管，所述第九薄膜晶体管的栅极接入上两级第n-2级GOA单元的输出端，源极接入正向扫描控制信号，漏极电性连接于第一节点；以及第十薄膜晶体管，所述第十薄膜晶体管的栅极接入下两级第n+2级GOA单元的输出端，源极接入反向扫描控制信号，漏极电性连接于第一节点；
所述基本输出模块包括：第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第六薄膜晶体管的漏极，源极接入第M条时钟信号，漏极电性连接于输出端；以及第一电容，所述第一电容的一端电性连接于第六薄膜晶体管的漏极，另一端电性连接于输出端；
所述基本输出下拉模块包括：第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于第二节点，源极接入复合信号，漏极电性连接于输出端；以及第二电容，所述第二电容的一端电性连接于第二节点，另一端接入复合信号；
所述第一节点控制模块包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极接入第M条时钟信号，源极电性连接于第五薄膜晶体管的漏极，漏极电性连接于第一节点；以及第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于第二节点，源极接入复合信号；
所述第二节点控制模块包括：第十一薄膜晶体管，所述第十一薄膜晶体管的栅极接入第一全局控制信号，源极接入复合信号，漏极电性连接于第二节点；
所述输出控制模块包括：第十二薄膜晶体管，所述第十二薄膜晶体管的栅极和源极均接入第一全局控制信号，漏极电性连接于输出端；以及第十三薄膜晶体管，所述第十三薄膜晶体管的栅极接入第二全局控制信号，源极接入复合信号，漏极电性连接于输出端；
所述复位模块包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极与源极均接入复位信号，漏极电性连接于第二节点；
所述稳压模块包括：第六薄膜晶体管，所述第六薄膜晶体管的栅极接入控制电位，源极电性连接于第一节点，漏极电性连接于第七薄膜晶体管的栅极；
所述第二节点充电模块包括：第三薄膜晶体管，所述第三薄膜晶体管的栅极接入第M-2条时钟信号，源极接入控制电位，漏极电性连接于第二节点；以及第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于第一节点，源极接入第M-2条时钟信号，漏极电性连接于第二节点；
所述GOA驱动电路的工作过程先后包括：黑屏唤醒阶段、复位阶段、正常显示阶段、及触控扫描阶段；
在黑屏唤醒阶段，所述第一全局控制信号控制所有级GOA单元的第十二薄膜晶体管与第十一薄膜晶体管打开，第二全局控制信号控制所有级GOA单元的第十三薄膜晶体管关闭；在复位阶段与正常显示阶段，所述第一全局控制信号控制所有级GOA单元的第十二薄膜晶体管与第十一薄膜晶体管关闭，第二全局控制信号控制所有级GOA单元的第十三薄膜晶体管关闭；在触控扫描阶段，所述第二全局控制信号控制所有级GOA单元的第十三薄膜晶体管打开，第一全局控制信号控制所有级GOA单元的第十二薄膜晶体管与第十一薄膜晶体管关闭；
在复位阶段，复位信号提供单个脉冲控制第一薄膜晶体管打开，复位第二节点的电位，且复位信号的单个脉冲时长至少为第一条时钟信号与第二条时钟信号的初始脉冲时长之和；
在复位阶段与正常显示阶段，所述复合信号与控制电位的电位一高一低，所述正向扫描控制信号与反向扫描控制信号的电位一高一低；在触控扫描阶段，所述复合信号为与触控扫描信号频率相同的脉冲信号。
可选的，在复位阶段与正常显示阶段，各条时钟信号均为周期性脉冲信号；在触控扫描阶段，各条时钟信号的电位恒定。
可选的，在复位阶段与正常显示阶段，各条时钟信号均为周期性脉冲信号；在触控扫描阶段，各条时钟信号均为与触控扫描信号频率相同的脉冲信号。
可选的，各个薄膜晶体管均为N型薄膜晶体管；
在黑屏唤醒阶段，所述第一全局控制信号为高电位，第二全局控制信号为低电位；在复位阶段与正常显示阶段，所述第一全局控制信号与第二全局控制信号均为低电位；在触控扫描阶段，所述第二全局控制信号为高电位，第一全局控制信号为低电位；
在复位阶段与正常显示阶段，所述复合信号的电位为低电位，控制电位为高电位；各条时钟信号均为周期性高电位脉冲信号。
在触控扫描阶段，各条时钟信号的电位均为恒定低电位。
正向扫描时，所述正向扫描控制信号为恒压高电位，反向扫描控制信号为恒压低电位；反向扫描时，所述正向扫描控制信号为恒压低电位，反向扫描控制信号为恒压高电位。
可选的，各个薄膜晶体管均为P型薄膜晶体管；
在黑屏唤醒阶段，所述第一全局控制信号为低电位，第二全局控制信号为高电位；在复位阶段与正常显示阶段，所述第一全局控制信号与第二全局控制信号均为高电位；在触控扫描阶段，所述第二全局控制信号为低电位，第一全局控制信号为高电位；
在复位阶段与正常显示阶段，所述复合信号的电位为高电位，控制电位为低电位；各条时钟信号均为周期性低电位脉冲信号。
在触控扫描阶段，各条时钟信号的电位均为恒定高电位。
正向扫描时，所述正向扫描控制信号为恒压低电位，反向扫描控制信号为恒压高电位；反向扫描时，所述正向扫描控制信号为恒压高电位，反向扫描控制信号为恒压低电位。
在第一级GOA单元和第二级GOA单元中，所述第九薄膜晶体管的栅极均接入电路的起始信号；在倒数第二级GOA单元和最后一级GOA单元中，所述第十薄膜晶体管的栅极均接入电路的起始信号；
所述GOA驱动电路包括四条时钟信号：第一、第二、第三、及第四条时钟信号；当所述第M条时钟信号为第一条时钟信号时，第M-2条时钟信号为第三条时钟信号；当所述第M条时钟信号为第二条时钟信号时，第M-2条时钟信号为第四条时钟信号；在复位阶段与正常显示阶段，所述第一、第二、第三、及第四条时钟信号的脉冲周期相同，前一条时钟信号的脉冲信号结束的同时后一条时钟信号的脉冲信号产生。
本发明还提供一种GOA驱动电路，包括：级联的多级GOA单元，每一级GOA单元均包括：正反向扫描控制模块、基本输出模块、基本输出下拉模块、第一节点控制模块、第二节点控制模块、输出控制模块、复位模块、稳压模块、以及第二节点充电模块；
设n为正整数，除第一级GOA单元、第二级GOA单元、倒数第二级GOA单元、及最后一级GOA单元外，在第n级GOA单元中：
所述正反向扫描控制模块包括：第九薄膜晶体管，所述第九薄膜晶体管的栅极接入上两级第n-2级GOA单元的输出端，源极接入正向扫描控制信号，漏极电性连接于第一节点；以及第十薄膜晶体管，所述第十薄膜晶体管的栅极接入下两级第n+2级GOA单元的输出端，源极接入反向扫描控制信号，漏极电性连接于第一节点；
所述基本输出模块包括：第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第六薄膜晶体管的漏极，源极接入第M条时钟信号，漏极电性连接于输出端；以及第一电容，所述第一电容的一端电性连接于第六薄膜晶体管的漏极，另一端电性连接于输出端；
所述基本输出下拉模块包括：第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于第二节点，源极接入复合信号，漏极电性连接于输出端；以及第二电容，所述第二电容的一端电性连接于第二节点，另一端接入复合信号；
所述第一节点控制模块包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极接入第M条时钟信号，源极电性连接于第五薄膜晶体管的漏极，漏极电性连接于第一节点；以及第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于第二节点，源极接入复合信号；
所述第二节点控制模块包括：第十一薄膜晶体管，所述第十一薄膜晶体管的栅极接入第一全局控制信号，源极接入复合信号，漏极电性连接于第二节点；
所述输出控制模块包括：第十二薄膜晶体管，所述第十二薄膜晶体管的栅极和源极均接入第一全局控制信号，漏极电性连接于输出端；以及第十三薄膜晶体管，所述第十三薄膜晶体管的栅极接入第二全局控制信号，源极接入复合信号，漏极电性连接于输出端；
所述复位模块包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极与源极均接入复位信号，漏极电性连接于第二节点；
所述稳压模块包括：第六薄膜晶体管，所述第六薄膜晶体管的栅极接入控制电位，源极电性连接于第一节点，漏极电性连接于第七薄膜晶体管 的栅极；
所述第二节点充电模块包括：第三薄膜晶体管，所述第三薄膜晶体管的栅极接入第M-2条时钟信号，源极接入控制电位，漏极电性连接于第二节点；以及第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于第一节点，源极接入第M-2条时钟信号，漏极电性连接于第二节点；
所述GOA驱动电路的工作过程先后包括：黑屏唤醒阶段、复位阶段、正常显示阶段、及触控扫描阶段；
在黑屏唤醒阶段，所述第一全局控制信号控制所有级GOA单元的第十二薄膜晶体管与第十一薄膜晶体管打开，第二全局控制信号控制所有级GOA单元的第十三薄膜晶体管关闭；在复位阶段与正常显示阶段，所述第一全局控制信号控制所有级GOA单元的第十二薄膜晶体管与第十一薄膜晶体管关闭，第二全局控制信号控制所有级GOA单元的第十三薄膜晶体管关闭；在触控扫描阶段，所述第二全局控制信号控制所有级GOA单元的第十三薄膜晶体管打开，第一全局控制信号控制所有级GOA单元的第十二薄膜晶体管与第十一薄膜晶体管关闭；
在复位阶段，复位信号提供单个脉冲控制第一薄膜晶体管打开，复位第二节点的电位，且复位信号的单个脉冲时长至少为第一条时钟信号与第二条时钟信号的初始脉冲时长之和；
在复位阶段与正常显示阶段，所述复合信号与控制电位的电位一高一低，所述正向扫描控制信号与反向扫描控制信号的电位一高一低；在触控扫描阶段，所述复合信号为与触控扫描信号频率相同的脉冲信号；
其中，在复位阶段与正常显示阶段，各条时钟信号均为周期性脉冲信号；在触控扫描阶段，各条时钟信号的电位恒定；
其中，各个薄膜晶体管均为N型薄膜晶体管；
在黑屏唤醒阶段，所述第一全局控制信号为高电位，第二全局控制信号为低电位；在复位阶段与正常显示阶段，所述第一全局控制信号与第二全局控制信号均为低电位；在触控扫描阶段，所述第二全局控制信号为高电位，第一全局控制信号为低电位；
在复位阶段与正常显示阶段，所述复合信号的电位为低电位，控制电位为高电位；各条时钟信号均为周期性高电位脉冲信号；
其中，在触控扫描阶段，各条时钟信号的电位均为恒定低电位；
其中，正向扫描时，所述正向扫描控制信号为恒压高电位，反向扫描控制信号为恒压低电位；反向扫描时，所述正向扫描控制信号为恒压低电位，反向扫描控制信号为恒压高电位；
其中，在第一级GOA单元和第二级GOA单元中，所述第九薄膜晶体管的栅极均接入电路的起始信号；在倒数第二级GOA单元和最后一级GOA单元中，所述第十薄膜晶体管的栅极均接入电路的起始信号；
包括四条时钟信号：第一、第二、第三、及第四条时钟信号；当所述第M条时钟信号为第一条时钟信号时，第M-2条时钟信号为第三条时钟信号；当所述第M条时钟信号为第二条时钟信号时，第M-2条时钟信号为第四条时钟信号；在复位阶段与正常显示阶段，所述第一、第二、第三、及第四条时钟信号的脉冲周期相同，前一条时钟信号的脉冲信号结束的同时后一条时钟信号的脉冲信号产生。
本发明的有益效果：本发明提供的一种GOA驱动电路，在黑屏唤醒阶段通过第一全局控制信号控制所有级GOA单元的第十二薄膜晶体管打开，以实现All Gate On功能，通过第一全局控制信号控制所有级GOA单元的第十一薄膜晶体管打开，以下拉第二节点的电位，保证输出端的正常输出；在复位阶段通过复位信号控制第一薄膜晶体管来复位第二节点的电位，并设置复位信号的单个脉冲时长至少为第一条时钟信号与第二条时钟信号的初始脉冲时长之和，保证黑屏唤醒后第二节点处于高电位，使得GOA驱动电路输出正常，触控显示面板在黑屏唤醒之后进入正常显示；在触控扫描阶段通过第二全局控制信号控制所有级GOA单元的第十三薄膜晶体管打开，使得各级GOA单元的输出端输出复合信号，此阶段的复合信号为与触控扫描信号频率相同的脉冲信号，保证触控扫描的正常进行。从而本发明的GOA驱动电路能够保证触控显示面板在黑屏唤醒之后进行正常显示，消除GOA电路在实现All Gate On和触控扫描功能时的失效风险，提升GOA驱动电路的稳定性。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。附图中，
图1为本发明的GOA驱动电路的第一实施例的电路图；
图2为图1所示的GOA电路在黑屏唤醒阶段与复位阶段的时序图；
图3为图1所示的GOA电路正向扫描时正常显示阶段和触控扫描阶段的第一种时序图；
图4为图1所示的GOA电路正向扫描时正常显示阶段和触控扫描阶段的第二种时序图；
图5为本发明的GOA驱动电路的第一实施例的第一级GOA单元的电路图；
图6为本发明的GOA驱动电路的第一实施例的第二级GOA单元的电路图；
图7为本发明的GOA驱动电路的第一实施例的倒数第二级GOA单元的电路图；
图8为本发明的GOA驱动电路的第一实施例的最后一级GOA单元的电路图；
图9为本发明的GOA驱动电路的第二实施例的电路图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1或图9，本发明提供一种GOA驱动电路，包括：级联的多级GOA单元，每一级GOA单元均包括：正反向扫描控制模块100、基本输出模块200、基本输出下拉模块300、第一节点控制模块400、第二节点控制模块500、输出控制模块600、复位模块700、稳压模块800、以及第二节点充电模块900。
设n为正整数，除第一级GOA单元、第二级GOA单元、倒数第二级GOA单元、及最后一级GOA单元外，在第n级GOA单元中：
所述正反向扫描控制模块100包括：第九薄膜晶体管T9，所述第九薄膜晶体管T9的栅极接入上两级第n-2级GOA单元的输出端G(n-2)，源极接入正向扫描控制信号U2D，漏极电性连接于第一节点Q(n)；以及第十薄膜晶体管T10，所述第十薄膜晶体管T10的栅极接入下两级第n+2级GOA单元的输出端G(n+2)，源极接入反向扫描控制信号D2U，漏极电性连接于第一节点Q(n)；
所述基本输出模块200包括：第七薄膜晶体管T7，所述第七薄膜晶体管T7的栅极电性连接于第六薄膜晶体管T6的漏极，源极接入第M条时钟信号CK(M)，漏极电性连接于输出端G(n)；以及第一电容C1，所述第一电容C1的一端电性连接于第六薄膜晶体管T6的漏极，另一端电性连接于输出端G(n)；
所述基本输出下拉模块300包括：第八薄膜晶体管T8，所述第八薄膜晶体管T8的栅极电性连接于第二节点P(n)，源极接入复合信号CS，漏极电性连接于输出端G(n)；以及第二电容C2，所述第二电容C2的一端电性 连接于第二节点P(n)，另一端接入复合信号CS；
所述第一节点控制模块400包括：第四薄膜晶体管T4，所述第四薄膜晶体管T4的栅极接入第M条时钟信号CK(M)，源极电性连接于第五薄膜晶体管T5的漏极，漏极电性连接于第一节点Q(n)；以及第五薄膜晶体管T5，所述第五薄膜晶体管T5的栅极电性连接于第二节点P(n)，源极接入复合信号CS；
所述第二节点控制模块500包括：第十一薄膜晶体管T11，所述第十一薄膜晶体管T11的栅极接入第一全局控制信号Gas1，源极接入复合信号CS，漏极电性连接于第二节点P(n)；
所述输出控制模块600包括：第十二薄膜晶体管T12，所述第十二薄膜晶体管T12的栅极和源极均接入第一全局控制信号Gas1，漏极电性连接于输出端G(n)；以及第十三薄膜晶体管T13，所述第十三薄膜晶体管T13的栅极接入第二全局控制信号Gas2，源极接入复合信号CS，漏极电性连接于输出端G(n)；
所述复位模块700包括：第一薄膜晶体管T1，所述第一薄膜晶体管T1的栅极与源极均接入复位信号Reset，漏极电性连接于第二节点P(n)；
所述稳压模块800包括：第六薄膜晶体管T6，所述第六薄膜晶体管T6的栅极接入控制电位CV，源极电性连接于第一节点Q(n)，漏极电性连接于第七薄膜晶体管T7的栅极；
所述第二节点充电模块900包括：第三薄膜晶体管T3，所述第三薄膜晶体管T3的栅极接入第M-2条时钟信号CK(M-2)，源极接入控制电位CV，漏极电性连接于第二节点P(n)；以及第二薄膜晶体管T2，所述第二薄膜晶体管T2的栅极电性连接于第一节点Q(n)，源极接入第M-2条时钟信号CK(M-2)，漏极电性连接于第二节点P(n)。
所述GOA驱动电路的工作过程先后包括：黑屏唤醒阶段、复位阶段、正常显示阶段、及触控扫描阶段。
在黑屏唤醒阶段，所述第一全局控制信号Gas1控制所有级GOA单元的第十二薄膜晶体管T12与第十一薄膜晶体管T11打开，第二全局控制信号Gas2控制所有级GOA单元的第十三薄膜晶体管T13关闭；在复位阶段与正常显示阶段，所述第一全局控制信号Gas1控制所有级GOA单元的第十二薄膜晶体管T12与第十一薄膜晶体管T11关闭，第二全局控制信号Gas2控制所有级GOA单元的第十三薄膜晶体管T13关闭；在触控扫描阶段，所述第二全局控制信号Gas2控制所有级GOA单元的第十三薄膜晶体管T13打开，第一全局控制信号Gas1控制所有级GOA单元的第十二薄膜晶体管 T12与第十一薄膜晶体管T11关闭；
在复位阶段，复位信号Reset提供单个脉冲控制第一薄膜晶体管T1打开，复位第二节点P(n)的电位，且复位信号Reset的单个脉冲时长至少为第一条时钟信号CK(1)与第二条时钟信号CK(2)的初始脉冲时长之和；
在复位阶段与正常显示阶段，所述复合信号CS与控制电位CV的电位一高一低，所述正向扫描控制信号U2D与反向扫描控制信号D2U的电位一高一低；在触控扫描阶段，所述复合信号CS为与触控扫描信号TP频率相同的脉冲信号。
请同时参阅图1、图2、与图3，或同时参阅图1、图2、与图4，对于本发明的GOA驱动电路的第一实施例，各个薄膜晶体管均为N型薄膜晶体管；在黑屏唤醒阶段，所述第一全局控制信号Gas1为高电位，第二全局控制信号Gas2为低电位；在复位阶段与正常显示阶段，所述第一全局控制信号Gas1与第二全局控制信号Gas2均为低电位；在触控扫描阶段，所述第二全局控制信号Gas2为高电位，第一全局控制信号Gas1为低电位。值得一提的是，在复位阶段，复位信号Reset的单个脉冲时长至少为第一条时钟信号CK(1)与第二条时钟信号CK(2)的初始脉冲时长之和是指所述复位信号Reset的单个脉冲早于第一条时钟信号CK(1)的第一个脉冲信号产生或与第一条时钟信号CK(1)的第一个脉冲信号同时产生，晚于第二条时钟信号CK(2)的第一个脉冲信号结束或与第二条时钟信号CK(2)的第一个脉冲信号同时结束。
在复位阶段与正常显示阶段，所述复合信号CS的电位为低电位，控制电位CV为高电位；各条时钟信号均为周期性高电位脉冲信号。可选的，如图3所示，在触控扫描阶段，各条时钟信号的电位均为恒定低电位；可选的，如图4所示，对图3所示的时序进行改进后，各条时钟信号均为与触控扫描信号TP频率相同的脉冲信号。
进一步地，正向扫描时，所述正向扫描控制信号U2D为恒压高电位，反向扫描控制信号D2U为恒压低电位；反向扫描时，所述正向扫描控制信号U2D为恒压低电位，反向扫描控制信号D2U为恒压高电位。
请参阅图9，对于本发明的GOA驱动电路的第二实施例，各个薄膜晶体管均为P型薄膜晶体管；那么，在黑屏唤醒阶段，所述第一全局控制信号Gas1为低电位，第二全局控制信号Gas2为高电位；在复位阶段与正常显示阶段，所述第一全局控制信号Gas1与第二全局控制信号Gas2均为高电位；在触控扫描阶段，所述第二全局控制信号Gas2为低电位，第一全局控制信号Gas1为高电位。
在复位阶段与正常显示阶段，所述复合信号CS的电位为高电位，控制电位CV为低电位；各条时钟信号均为周期性低电位脉冲信号。可选的，在触控扫描阶段，各条时钟信号的电位均为恒定高电位；可选的，对时序进行改进后，各条时钟信号均为与触控扫描信号TP频率相同的脉冲信号。
进一步地，正向扫描时，所述正向扫描控制信号U2D为恒压低电位，反向扫描控制信号D2U为恒压高电位；反向扫描时，所述正向扫描控制信号U2D为恒压高电位，反向扫描控制信号D2U为恒压低电位。
特别的，请参阅图5与图6，在第一级GOA单元和第二级GOA单元中，所述第九薄膜晶体管T9的栅极均接入电路的起始信号STV。请参阅图7与图8，在倒数第二级GOA单元和最后一级GOA单元中，所述第十薄膜晶体管T10的栅极均接入电路的起始信号STV。
具体地，所述GOA驱动电路包括四条时钟信号：第一、第二、第三、及第四条时钟信号CK(1)、CK(2)、CK(3)、CK(4)。当所述第M条时钟信号CK(M)为第一条时钟信号CK(1)时，第M-2条时钟信号CK(M-2)为第三条时钟信号CK(3)；当所述第M条时钟信号CK(M)为第二条时钟信号CK(2)时，第M-2条时钟信号CK(M-2)为第四条时钟信号CK(4)。在复位阶段与正常显示阶段，所述第一、第二、第三、及第四条时钟信号CK(1)、CK(2)、CK(3)、CK(4)的脉冲周期相同，前一条时钟信号的脉冲信号结束的同时后一条时钟信号的脉冲信号产生，即所述第一条时钟信号CK(1)的第一个脉冲信号首先产生，所述第一时钟信号CK(1)的第一个脉冲信号结束的同时所述第二条时钟信号CK(2)的第一个脉冲信号产生，所述第二条时钟信号CK(2)的第一个脉冲信号结束的同时所述第三条时钟信号CK(3)的第一个脉冲信号产生，所述第三条时钟信号CK(3)的第一个脉冲信号结束的同时所述第四条时钟信号CK(4)的第一个脉冲信号产生，所述第四条时钟信号CK(4)的第一个脉冲信号结束的同时所述第一条时钟信号CK(1)的第二个脉冲信号产生。进一步的，对应到本发明的第一实施例中，即为前一条时钟信号的下降沿与后一条时钟信号的上升沿同时产生；对应到本发明的第二实施例中，即为前一条时钟信号的上升沿与后一条时钟信号的下降沿同时产生。
请同时参阅图1、图2、与图3，或者同时参阅图1、图2、与图4，下面以本发明的GOA驱动电路的第一实施例进行正向扫描为例，说明本发明的GOA驱动电路的工作过程。
如上所述，在本发明的GOA驱动电路的第一实施例中，各个薄膜晶体管均为N型薄膜晶体管，GOA驱动电路的工作过程先后为：黑屏唤醒阶段、复位阶段、正常显示阶段、及触控扫描阶段。具体工作过程如下：
1、黑屏唤醒阶段
所述第一全局控制信号Gas1为高电位(5V)，控制所有级GOA单元的第十二薄膜晶体管T12打开，所有级GOA单元的输出端输出第一全局信号Gas1的高电位，实现All Gate On功能；同时，所述第一全局控制信号Gas1控制所有级GOA单元的第十一薄膜晶体管T11打开，此阶段复合信号CS提供低电位(-5V)，从而下拉所有级GOA单元的第二节点的电位，使得第八薄膜晶体管T8关闭，防止其下拉输出端G(n)，保证All Gate On的顺利进行。
第二全局控制信号Gas2为低电位(-5V)，控制所有级GOA单元的第十三薄膜晶体管T13关闭，同样防止复合信号CS下拉输出端G(n)。
2、复位阶段
所述第一全局控制信号Gas1与第二全局控制信号Gas2均为低电位(-7V)，控制所有级GOA单元的第十一薄膜晶体管T11、第十二薄膜晶体管T12、与第十三薄膜晶体管T13均关闭；复位信号Reset提供单个高电位脉冲(10V)，控制第一薄膜晶体管T1打开，控制电位CV的高电位(10V)经由第一薄膜晶体管使得第二节点P(n)的电位复位至高电位，第八薄膜晶体管T8打开，此阶段复合信号CS提供低电位(-7V)，从而下拉输出端G(n)至低电位。
特别地，所述复位信号Reset的单个脉冲信号早于第一条时钟信号CK(1)的第一个脉冲信号产生或与第一条时钟信号CK(1)的第一个脉冲信号同时产生，晚于第二条时钟信号CK(2)的第一个脉冲信号结束或与第二条时钟信号CK(2)的第一个脉冲信号同时结束，即复位信号Reset的单个脉冲时长至少为第一条时钟信号CK(1)与第二条时钟信号CK(2)的初始脉冲时长之和，能够保证黑屏唤醒后第二节点P(n)处于高电位，使得GOA驱动电路输出正常，触控显示面板在黑屏唤醒之后进入正常显示。
3、正常显示阶段
所述第一全局控制信号Gas1与第二全局控制信号Gas2仍均为低电位(-7V)，控制所有级GOA单元的第十一薄膜晶体管T11、第十二薄膜晶体管T12、与第十三薄膜晶体管T13均关闭；复位信号Reset变为低电位(-7V)，第一薄膜晶体管T1关闭。所述复合信号CS的电位为低电位(-7V)，控制电位CV为高电位(10V)；各条时钟信号均为周期性高电位脉冲信号；正向扫描控制信号U2D为恒压高电位(10V)，反向扫描控制信号D2U为恒压低电位(-7V)。首先，第n-2级GOA单元的输出端G(n-2)或电路的起始信号STV提供高电位(10V)，第M-2条时钟信号CK(M-2) 提供高电位(10V)，第九薄膜晶体管T9打开，第一节点Q(n)充电至高电位，第三薄膜晶体管T3打开，第二节点P(n)充电至高电位，第八薄膜晶体管T8打开，输出端G(n)仍被下拉至低电位(-7V)；
接着，第n-2级GOA单元的输出端G(n-2)和第M-2条时钟信号CK(M-2)均变为低电位(-7V)，第九和第三薄膜晶体管T9、T3关闭，第一节点Q(n)受第一电容C1的作用保持高电位，第二薄膜晶体管T2打开，第二节点P(n)被下拉至低电位；
随后，第M条时钟信号CK(M)变为高电位(10V)，由于控制电位CV的高电位始终使得第六薄膜晶体管T6打开，第七薄膜晶体管T7受第一节点Q(n)的控制打开，输出端G(n)输出第M条时钟信号的高电位(10V)；当CK(M)变为低电位(-7V)后，输出端G(n)则输出第M条时钟信号CK(M)的低电位(-7V)；
接下来，第M-2条时钟信号CK(M-2)再次变为高电位(10V)，第三薄膜晶体管T3打开，第二节点P(n)充电至高电位，第五和第八薄膜晶体管T5、T8打开，输出端G(n)被下拉至低电位(-7V)；
然后，第M条时钟信号CK(M)再次变为高电位(10V)，第四和第五薄膜晶体管T4、T5打开，第一节点Q(n)被下拉至低电位，至此，输出端G(n)和第一节点Q(n)保持低电位(-7V)；
4、触控扫描阶段
所述第二全局信号Gas2提供高电位(10V)，第一全局信号Gas1提供低电位(-11.5V)，第十二薄膜晶体管T12与第十一薄膜晶体管T11关闭，第十三薄膜晶体管T13打开，复合信号CS经由第十三薄膜晶体管T13传输至输出端G(n)进行输出，此阶段，所述复合信号CS为与触控扫描信号TP频率相同的脉冲信号，触控扫描信号TP的电位在0V与4.5V之间跳变，复合信号CS的电位在-7V与-11.5V之间跳变，能够保证触控扫描的正常进行。
如图3所示的时序，在该触控扫描阶段，第一至第四时钟信号CK(1)-CK(4)的电位均为恒定低电位(-7V)。相比于图3，图4所示的时序进行了改进，第一至第四时钟信号CK(1)-CK(4)也均为与触控扫描信号TP频率相同的脉冲信号，电位在-7V与-11.5V之间跳变，这样的改进能够消除第一节点Q(n)为高电位的GOA单元的输出端G(n)的输出异常，进一步提升GOA电路的稳定性。
反向扫描的工作过程与正向扫描类似，仅需要将所述反向扫描控制信号D2U设置为恒压高电位，正向扫描控制信号U2D设置为恒压低电位，扫 描的方向由第一级向最后一级扫描变为最后一级向第一级扫描即可，此处不再赘述。
图9所示的第二实施例与上述第一实施例的具体工作过程类似，仅需要将各信号、节点的电位高低进行调换即可，此处不再赘述。
综上所述，本发明提供的一种GOA驱动电路，在黑屏唤醒阶段通过第一全局控制信号控制所有级GOA单元的第十二薄膜晶体管打开，以实现All Gate On功能，通过第一全局控制信号控制所有级GOA单元的第十一薄膜晶体管打开，以下拉第二节点的电位，保证输出端的正常输出；在复位阶段通过复位信号控制第一薄膜晶体管来复位第二节点的电位，并设置复位信号的单个脉冲时长至少为第一条时钟信号与第二条时钟信号的初始脉冲时长之和，保证黑屏唤醒后第二节点处于高电位，使得GOA驱动电路输出正常，触控显示面板在黑屏唤醒之后进入正常显示；在触控扫描阶段通过第二全局控制信号控制所有级GOA单元的第十三薄膜晶体管打开，使得各级GOA单元的输出端输出复合信号，此阶段的复合信号为与触控扫描信号频率相同的脉冲信号，保证触控扫描的正常进行。从而本发明的GOA驱动电路能够保证触控显示面板在黑屏唤醒之后进行正常显示，消除GOA电路在实现All Gate On和触控扫描功能时的失效风险，提升GOA驱动电路的稳定性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (17)

  1. 一种GOA驱动电路，包括：级联的多级GOA单元，每一级GOA单元均包括：正反向扫描控制模块、基本输出模块、基本输出下拉模块、第一节点控制模块、第二节点控制模块、输出控制模块、复位模块、稳压模块、以及第二节点充电模块；
    设n为正整数，除第一级GOA单元、第二级GOA单元、倒数第二级GOA单元、及最后一级GOA单元外，在第n级GOA单元中：
    所述正反向扫描控制模块包括：第九薄膜晶体管，所述第九薄膜晶体管的栅极接入上两级第n-2级GOA单元的输出端，源极接入正向扫描控制信号，漏极电性连接于第一节点；以及第十薄膜晶体管，所述第十薄膜晶体管的栅极接入下两级第n+2级GOA单元的输出端，源极接入反向扫描控制信号，漏极电性连接于第一节点；
    所述基本输出模块包括：第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第六薄膜晶体管的漏极，源极接入第M条时钟信号，漏极电性连接于输出端；以及第一电容，所述第一电容的一端电性连接于第六薄膜晶体管的漏极，另一端电性连接于输出端；
    所述基本输出下拉模块包括：第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于第二节点，源极接入复合信号，漏极电性连接于输出端；以及第二电容，所述第二电容的一端电性连接于第二节点，另一端接入复合信号；
    所述第一节点控制模块包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极接入第M条时钟信号，源极电性连接于第五薄膜晶体管的漏极，漏极电性连接于第一节点；以及第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于第二节点，源极接入复合信号；
    所述第二节点控制模块包括：第十一薄膜晶体管，所述第十一薄膜晶体管的栅极接入第一全局控制信号，源极接入复合信号，漏极电性连接于第二节点；
    所述输出控制模块包括：第十二薄膜晶体管，所述第十二薄膜晶体管的栅极和源极均接入第一全局控制信号，漏极电性连接于输出端；以及第十三薄膜晶体管，所述第十三薄膜晶体管的栅极接入第二全局控制信号，源极接入复合信号，漏极电性连接于输出端；
    所述复位模块包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极与 源极均接入复位信号，漏极电性连接于第二节点；
    所述稳压模块包括：第六薄膜晶体管，所述第六薄膜晶体管的栅极接入控制电位，源极电性连接于第一节点，漏极电性连接于第七薄膜晶体管的栅极；
    所述第二节点充电模块包括：第三薄膜晶体管，所述第三薄膜晶体管的栅极接入第M-2条时钟信号，源极接入控制电位，漏极电性连接于第二节点；以及第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于第一节点，源极接入第M-2条时钟信号，漏极电性连接于第二节点；
    所述GOA驱动电路的工作过程先后包括：黑屏唤醒阶段、复位阶段、正常显示阶段、及触控扫描阶段；
    在黑屏唤醒阶段，所述第一全局控制信号控制所有级GOA单元的第十二薄膜晶体管与第十一薄膜晶体管打开，第二全局控制信号控制所有级GOA单元的第十三薄膜晶体管关闭；在复位阶段与正常显示阶段，所述第一全局控制信号控制所有级GOA单元的第十二薄膜晶体管与第十一薄膜晶体管关闭，第二全局控制信号控制所有级GOA单元的第十三薄膜晶体管关闭；在触控扫描阶段，所述第二全局控制信号控制所有级GOA单元的第十三薄膜晶体管打开，第一全局控制信号控制所有级GOA单元的第十二薄膜晶体管与第十一薄膜晶体管关闭；
    在复位阶段，复位信号提供单个脉冲控制第一薄膜晶体管打开，复位第二节点的电位，且复位信号的单个脉冲时长至少为第一条时钟信号与第二条时钟信号的初始脉冲时长之和；
    在复位阶段与正常显示阶段，所述复合信号与控制电位的电位一高一低，所述正向扫描控制信号与反向扫描控制信号的电位一高一低；在触控扫描阶段，所述复合信号为与触控扫描信号频率相同的脉冲信号。
  2. 如权利要求1所述的GOA驱动电路，其中，在复位阶段与正常显示阶段，各条时钟信号均为周期性脉冲信号；在触控扫描阶段，各条时钟信号的电位恒定。
  3. 如权利要求1所述的GOA驱动电路，其中，在复位阶段与正常显示阶段，各条时钟信号均为周期性脉冲信号；在触控扫描阶段，各条时钟信号均为与触控扫描信号频率相同的脉冲信号。
  4. 如权利要求2所述的GOA驱动电路，其中，各个薄膜晶体管均为N型薄膜晶体管；
    在黑屏唤醒阶段，所述第一全局控制信号为高电位，第二全局控制信号为低电位；在复位阶段与正常显示阶段，所述第一全局控制信号与第二 全局控制信号均为低电位；在触控扫描阶段，所述第二全局控制信号为高电位，第一全局控制信号为低电位；
    在复位阶段与正常显示阶段，所述复合信号的电位为低电位，控制电位为高电位；各条时钟信号均为周期性高电位脉冲信号。
  5. 如权利要求3所述的GOA驱动电路，其中，各个薄膜晶体管均为N型薄膜晶体管；
    在黑屏唤醒阶段，所述第一全局控制信号为高电位，第二全局控制信号为低电位；在复位阶段与正常显示阶段，所述第一全局控制信号与第二全局控制信号均为低电位；在触控扫描阶段，所述第二全局控制信号为高电位，第一全局控制信号为低电位；
    在复位阶段与正常显示阶段，所述复合信号的电位为低电位，控制电位为高电位；各条时钟信号均为周期性高电位脉冲信号。
  6. 如权利要求4所述的GOA驱动电路，其中，在触控扫描阶段，各条时钟信号的电位均为恒定低电位。
  7. 如权利要求5所述的GOA驱动电路，其中，在触控扫描阶段，各条时钟信号的电位均为恒定低电位。
  8. 如权利要求4所述的GOA驱动电路，其中，正向扫描时，所述正向扫描控制信号为恒压高电位，反向扫描控制信号为恒压低电位；反向扫描时，所述正向扫描控制信号为恒压低电位，反向扫描控制信号为恒压高电位。
  9. 如权利要求5所述的GOA驱动电路，其中，正向扫描时，所述正向扫描控制信号为恒压高电位，反向扫描控制信号为恒压低电位；反向扫描时，所述正向扫描控制信号为恒压低电位，反向扫描控制信号为恒压高电位。
  10. 如权利要求2所述的GOA驱动电路，其中，各个薄膜晶体管均为P型薄膜晶体管；
    在黑屏唤醒阶段，所述第一全局控制信号为低电位，第二全局控制信号为高电位；在复位阶段与正常显示阶段，所述第一全局控制信号与第二全局控制信号均为高电位；在触控扫描阶段，所述第二全局控制信号为低电位，第一全局控制信号为高电位；
    在复位阶段与正常显示阶段，所述复合信号的电位为高电位，控制电位为低电位；各条时钟信号均为周期性低电位脉冲信号。
  11. 如权利要求3所述的GOA驱动电路，其中，各个薄膜晶体管均为P型薄膜晶体管；
    在黑屏唤醒阶段，所述第一全局控制信号为低电位，第二全局控制信号为高电位；在复位阶段与正常显示阶段，所述第一全局控制信号与第二全局控制信号均为高电位；在触控扫描阶段，所述第二全局控制信号为低电位，第一全局控制信号为高电位；
    在复位阶段与正常显示阶段，所述复合信号的电位为高电位，控制电位为低电位；各条时钟信号均为周期性低电位脉冲信号。
  12. 如权利要求10所述的GOA驱动电路，其中，在触控扫描阶段，各条时钟信号的电位均为恒定高电位。
  13. 如权利要求11所述的GOA驱动电路，其中，在触控扫描阶段，各条时钟信号的电位均为恒定高电位。
  14. 如权利要求10所述的GOA驱动电路，其中，正向扫描时，所述正向扫描控制信号为恒压低电位，反向扫描控制信号为恒压高电位；反向扫描时，所述正向扫描控制信号为恒压高电位，反向扫描控制信号为恒压低电位。
  15. 如权利要求11所述的GOA驱动电路，其中，正向扫描时，所述正向扫描控制信号为恒压低电位，反向扫描控制信号为恒压高电位；反向扫描时，所述正向扫描控制信号为恒压高电位，反向扫描控制信号为恒压低电位。
  16. 如权利要求1所述的GOA驱动电路，其中，在第一级GOA单元和第二级GOA单元中，所述第九薄膜晶体管的栅极均接入电路的起始信号；在倒数第二级GOA单元和最后一级GOA单元中，所述第十薄膜晶体管的栅极均接入电路的起始信号；
    包括四条时钟信号：第一、第二、第三、及第四条时钟信号；当所述第M条时钟信号为第一条时钟信号时，第M-2条时钟信号为第三条时钟信号；当所述第M条时钟信号为第二条时钟信号时，第M-2条时钟信号为第四条时钟信号；在复位阶段与正常显示阶段，所述第一、第二、第三、及第四条时钟信号的脉冲周期相同，前一条时钟信号的脉冲信号结束的同时后一条时钟信号的脉冲信号产生。
  17. 一种GOA驱动电路，包括：级联的多级GOA单元，每一级GOA单元均包括：正反向扫描控制模块、基本输出模块、基本输出下拉模块、第一节点控制模块、第二节点控制模块、输出控制模块、复位模块、稳压模块、以及第二节点充电模块；
    设n为正整数，除第一级GOA单元、第二级GOA单元、倒数第二级GOA单元、及最后一级GOA单元外，在第n级GOA单元中：
    所述正反向扫描控制模块包括：第九薄膜晶体管，所述第九薄膜晶体管的栅极接入上两级第n-2级GOA单元的输出端，源极接入正向扫描控制信号，漏极电性连接于第一节点；以及第十薄膜晶体管，所述第十薄膜晶体管的栅极接入下两级第n+2级GOA单元的输出端，源极接入反向扫描控制信号，漏极电性连接于第一节点；
    所述基本输出模块包括：第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第六薄膜晶体管的漏极，源极接入第M条时钟信号，漏极电性连接于输出端；以及第一电容，所述第一电容的一端电性连接于第六薄膜晶体管的漏极，另一端电性连接于输出端；
    所述基本输出下拉模块包括：第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于第二节点，源极接入复合信号，漏极电性连接于输出端；以及第二电容，所述第二电容的一端电性连接于第二节点，另一端接入复合信号；
    所述第一节点控制模块包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极接入第M条时钟信号，源极电性连接于第五薄膜晶体管的漏极，漏极电性连接于第一节点；以及第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于第二节点，源极接入复合信号；
    所述第二节点控制模块包括：第十一薄膜晶体管，所述第十一薄膜晶体管的栅极接入第一全局控制信号，源极接入复合信号，漏极电性连接于第二节点；
    所述输出控制模块包括：第十二薄膜晶体管，所述第十二薄膜晶体管的栅极和源极均接入第一全局控制信号，漏极电性连接于输出端；以及第十三薄膜晶体管，所述第十三薄膜晶体管的栅极接入第二全局控制信号，源极接入复合信号，漏极电性连接于输出端；
    所述复位模块包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极与源极均接入复位信号，漏极电性连接于第二节点；
    所述稳压模块包括：第六薄膜晶体管，所述第六薄膜晶体管的栅极接入控制电位，源极电性连接于第一节点，漏极电性连接于第七薄膜晶体管的栅极；
    所述第二节点充电模块包括：第三薄膜晶体管，所述第三薄膜晶体管的栅极接入第M-2条时钟信号，源极接入控制电位，漏极电性连接于第二节点；以及第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于第一节点，源极接入第M-2条时钟信号，漏极电性连接于第二节点；
    所述GOA驱动电路的工作过程先后包括：黑屏唤醒阶段、复位阶段、 正常显示阶段、及触控扫描阶段；
    在黑屏唤醒阶段，所述第一全局控制信号控制所有级GOA单元的第十二薄膜晶体管与第十一薄膜晶体管打开，第二全局控制信号控制所有级GOA单元的第十三薄膜晶体管关闭；在复位阶段与正常显示阶段，所述第一全局控制信号控制所有级GOA单元的第十二薄膜晶体管与第十一薄膜晶体管关闭，第二全局控制信号控制所有级GOA单元的第十三薄膜晶体管关闭；在触控扫描阶段，所述第二全局控制信号控制所有级GOA单元的第十三薄膜晶体管打开，第一全局控制信号控制所有级GOA单元的第十二薄膜晶体管与第十一薄膜晶体管关闭；
    在复位阶段，复位信号提供单个脉冲控制第一薄膜晶体管打开，复位第二节点的电位，且复位信号的单个脉冲时长至少为第一条时钟信号与第二条时钟信号的初始脉冲时长之和；
    在复位阶段与正常显示阶段，所述复合信号与控制电位的电位一高一低，所述正向扫描控制信号与反向扫描控制信号的电位一高一低；在触控扫描阶段，所述复合信号为与触控扫描信号频率相同的脉冲信号；
    其中，在复位阶段与正常显示阶段，各条时钟信号均为周期性脉冲信号；在触控扫描阶段，各条时钟信号的电位恒定；
    其中，各个薄膜晶体管均为N型薄膜晶体管；
    在黑屏唤醒阶段，所述第一全局控制信号为高电位，第二全局控制信号为低电位；在复位阶段与正常显示阶段，所述第一全局控制信号与第二全局控制信号均为低电位；在触控扫描阶段，所述第二全局控制信号为高电位，第一全局控制信号为低电位；
    在复位阶段与正常显示阶段，所述复合信号的电位为低电位，控制电位为高电位；各条时钟信号均为周期性高电位脉冲信号；
    其中，在触控扫描阶段，各条时钟信号的电位均为恒定低电位；
    其中，正向扫描时，所述正向扫描控制信号为恒压高电位，反向扫描控制信号为恒压低电位；反向扫描时，所述正向扫描控制信号为恒压低电位，反向扫描控制信号为恒压高电位；
    其中，在第一级GOA单元和第二级GOA单元中，所述第九薄膜晶体管的栅极均接入电路的起始信号；在倒数第二级GOA单元和最后一级GOA单元中，所述第十薄膜晶体管的栅极均接入电路的起始信号；
    包括四条时钟信号：第一、第二、第三、及第四条时钟信号；当所述第M条时钟信号为第一条时钟信号时，第M-2条时钟信号为第三条时钟信号；当所述第M条时钟信号为第二条时钟信号时，第M-2条时钟信号为第 四条时钟信号；在复位阶段与正常显示阶段，所述第一、第二、第三、及第四条时钟信号的脉冲周期相同，前一条时钟信号的脉冲信号结束的同时后一条时钟信号的脉冲信号产生。
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