[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

WO2019184354A1 - 移位寄存器单元及驱动方法、栅极驱动电路及显示装置 - Google Patents

移位寄存器单元及驱动方法、栅极驱动电路及显示装置 Download PDF

Info

Publication number
WO2019184354A1
WO2019184354A1 PCT/CN2018/113975 CN2018113975W WO2019184354A1 WO 2019184354 A1 WO2019184354 A1 WO 2019184354A1 CN 2018113975 W CN2018113975 W CN 2018113975W WO 2019184354 A1 WO2019184354 A1 WO 2019184354A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
control
transistor
circuit
reset
Prior art date
Application number
PCT/CN2018/113975
Other languages
English (en)
French (fr)
Inventor
王志冲
郑皓亮
商广良
韩承佑
黄应龙
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2019546340A priority Critical patent/JP7264820B2/ja
Priority to EP18904492.8A priority patent/EP3779956A4/en
Priority to KR1020197025793A priority patent/KR102315250B1/ko
Priority to US16/461,818 priority patent/US11100878B2/en
Publication of WO2019184354A1 publication Critical patent/WO2019184354A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking

Definitions

  • Embodiments of the present disclosure relate to a shift register unit and a driving method, a gate driving circuit, and a display device.
  • a pixel array such as a liquid crystal display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines interleaved therewith.
  • the driving of the gate lines can be achieved by a bundled integrated driver circuit.
  • the gate line driving circuit can be directly integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array) to drive the gate lines. .
  • a GOA composed of a plurality of cascaded shift register cells can be used to provide a switching state voltage signal for a plurality of rows of gate lines of a pixel array, thereby, for example, controlling a plurality of rows of gate lines to be sequentially turned on, and simultaneously by data lines to the pixel array.
  • the pixel unit of the corresponding row provides a data signal to form a gray voltage required for each gray scale of the display image in each pixel unit, thereby displaying one frame of image.
  • Current display panels are increasingly using GOA technology to drive gate lines. GOA technology helps achieve narrow borders and reduces production costs.
  • At least one embodiment of the present disclosure provides a shift register unit including an input circuit, a first reset circuit, and an output circuit.
  • the input circuit includes an input configured to perform first control of the first control node and the first node in response to an input signal of the input, and thereafter under control of a level of the first node Performing a second control different from the first control on the first node, where the first node is located in a path where the input signal performs the first control on the first control node;
  • the reset circuit is configured to reset the first control node in response to the first reset signal;
  • the output circuit is configured to output an output signal to the output under control of a level of the first control node.
  • the input circuit includes a first input sub-circuit, a second input sub-circuit, and a first node discharge electronic circuit.
  • the first input sub-circuit is configured to perform the first control on the first node in response to the input signal;
  • the second input sub-circuit is configured to: the first control node responsive to the input signal Performing the first control;
  • the first node discharge electronic circuit is configured to perform the second control on the first node under the control of a level of the first node.
  • the first input sub-circuit includes a first transistor, and a gate of the first transistor and the input terminal are connected to receive the input signal.
  • the first pole of the first transistor is coupled to the first voltage terminal to receive the first voltage
  • the second pole of the first transistor is coupled to the first node
  • the second input sub-circuit includes a second transistor a gate of the second transistor and the input terminal are connected to receive the input signal, a first pole of the second transistor is connected to the first node, and a second pole of the second transistor and the first a control node is connected
  • the first node discharge electronic circuit includes a third transistor, a gate of the third transistor and a first pole are electrically connected to each other, and are configured to be connected to the first node, the third The second pole of the transistor is coupled to the second control path.
  • the second control path is the input end.
  • the first reset circuit is symmetrically disposed with the input circuit, and the first reset circuit includes a first reset terminal configured to be in the first reset
  • the second control may be performed on the second node under control of a first reset signal of the terminal and a level of the second node, where the second node is located at the first reset signal to the first control node In the path of performing the second control.
  • the first reset circuit includes a first reset sub-circuit, a second reset sub-circuit, and a second node discharge electronic circuit.
  • the first reset subcircuit is configured to reset a second node in response to the first reset signal;
  • the second reset subcircuit is configured to reset the first control node in response to the first reset signal
  • the second node discharge electronic circuit is configured to perform the second control on the second node under control of a level of the second node.
  • the first reset sub-circuit includes a fourth transistor, and a gate of the fourth transistor is connected to a first reset terminal to receive the first reset signal.
  • a first pole and a second voltage terminal of the fourth transistor are connected to receive a second voltage
  • a second pole of the fourth transistor is connected to the second node
  • the second reset subcircuit includes a fifth transistor a gate of the fifth transistor and the first reset terminal are connected to receive the first reset signal, a first pole of the fifth transistor is connected to the second node, and a fifth transistor is a diode is connected to the first control node
  • the second node discharge circuit includes a sixth transistor, and a gate and a first pole of the sixth transistor are electrically connected to each other, and are configured to be both Connected, the second pole of the sixth transistor is connected to the first reset terminal.
  • the output circuit includes a seventh transistor and a first storage capacitor.
  • a gate of the seventh transistor is connected to the first control node, a first pole of the seventh transistor is connected to a clock signal terminal to receive a clock signal as the output signal, and a second pole of the seventh transistor And connecting to the output end; the first pole of the first storage capacitor is connected to the first control node, and the second pole of the first storage capacitor is connected to the output end.
  • a shift register unit provided by an embodiment of the present disclosure further includes a first control circuit, a first control node noise reduction circuit, and an output noise reduction circuit.
  • the first control circuit is configured to control a level of the second control node; the first control node noise reduction circuit is configured to control the first control under a control of a level of the second control node The node performs noise reduction; the output noise reduction circuit is configured to perform noise reduction on the output terminal under the control of the level of the second control node.
  • the first control circuit includes an eighth transistor and a ninth transistor, and a gate and a first pole of the eighth transistor are electrically connected to each other, and are configured to be Connected to the third voltage terminal to receive the third voltage, the second pole of the eighth transistor is connected to the second control node, and the gate of the ninth transistor is connected to the first control node, a first pole of the ninth transistor is connected to the second control node, a second pole and a fourth voltage terminal of the ninth transistor are connected to receive a fourth voltage; and the first control node noise reduction circuit comprises a tenth transistor a gate of the tenth transistor is connected to the second control node, a first pole of the tenth transistor is connected to the first control node, and a second pole of the tenth transistor and the fourth The voltage terminal is connected to receive the fourth voltage; the output noise reduction circuit includes an eleventh transistor, a gate of the eleventh transistor is connected to the second control node, and the first one of
  • the shift register unit provided by an embodiment of the present disclosure further includes a second reset circuit, wherein the second reset circuit is configured to reset the first control node in response to the second reset signal.
  • the second reset circuit includes a twelfth transistor, and a gate of the twelfth transistor and a second reset terminal are connected to receive the second reset. a signal, a first pole of the twelfth transistor is connected to the first control node, and a second pole and a fourth voltage terminal of the twelfth transistor are connected to receive a fourth voltage.
  • a shift register unit provided by an embodiment of the present disclosure further includes a second control circuit configured to perform the second control on the second control node in response to the input signal.
  • the second control circuit includes a thirteenth transistor and a fourteenth transistor. a gate of the thirteenth transistor and the input terminal are connected to receive the input signal, a first pole of the thirteenth transistor is connected to the second control node, and a second of the thirteenth transistor a pole and a fourth voltage terminal are connected to receive a fourth voltage; a gate of the fourteenth transistor is connected to the first reset terminal to receive the first reset signal, and a first pole and a sum of the fourteenth transistor The second control node is connected, and the second pole of the fourteenth transistor and the fourth voltage terminal are connected to receive the fourth voltage.
  • At least one embodiment of the present disclosure also provides a gate driving circuit including the shift register unit of any of the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure further provides a display device including a gate driving circuit according to an embodiment of the present disclosure.
  • At least one embodiment of the present disclosure also provides a driving method of a shift register unit, including: in a first stage, the input circuit performs the first control node and the first node in response to the input signal a first control, the output circuit outputs a low level of the output signal to the output terminal; in a second stage, the input circuit performs the first node on the first node in response to a level of the first node a second control, the output circuit outputs a high level of the output signal to the output end; in a third stage, the first reset circuit is controlled by the first reset signal to the first control node Reset.
  • At least one embodiment of the present disclosure further provides a driving method of a shift register unit, wherein the input signal and the first reset signal are exchanged with each other, the driving method comprising: a first stage, the first reset circuit response Performing the first control on the first control node and the second node on the input signal, the output circuit outputs a low level of the output signal to the output end; in a second stage, the The first reset circuit performs the second control on the second node in response to the level of the second node, the output circuit outputs a high level of the output signal to the output terminal; The input circuit resets the first control node under the control of the first reset signal.
  • At least one embodiment of the present disclosure also provides a driving method of a shift register unit, including: in a first stage, the input circuit performs the first control node and the first node in response to the input signal a first control, the second control circuit performing the second control on a level of the second control node in response to the input signal, the output circuit outputting a low level of the output signal to the output a second stage, the input circuit performs the second control on the first node in response to a first level of the first node, the output circuit outputs a high level of the output signal to a
  • the first reset circuit resets the first control node under the control of the first reset signal
  • the second control circuit responds to the first reset signal
  • the second control node performs the second control.
  • FIG. 1 is a schematic diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of an example of an input circuit shown in FIG. 1;
  • FIG. 3 is a schematic diagram of an example of a first pull-up node reset circuit shown in FIG. 1;
  • 4A is a schematic diagram of another shift register unit according to an embodiment of the present disclosure.
  • 4B is a circuit diagram of an example of the shift register unit shown in FIG. 4A;
  • FIG. 5A is a schematic diagram of another shift register unit according to an embodiment of the present disclosure.
  • 5B is a circuit diagram of an example of the shift register unit shown in FIG. 5A;
  • 6A is a schematic diagram of another shift register unit according to an embodiment of the present disclosure.
  • 6B is a circuit diagram of an example of the shift register unit shown in FIG. 6A;
  • FIG. 7 is a timing diagram of signals when a shift register unit is in operation according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the demand for display panels is also increasingly diversified. Different customers have different requirements for scanning the display panel. For example, some customers want to put the panel up and down, starting from the first line; while others want to flip the panel up and start scanning from the last line.
  • GOA circuits have gradually introduced the concept of two-way scanning.
  • the so-called two-way scanning that is, the display panel can start scanning from the first line (forward scanning) or scanning from the first line of the last (reverse scanning). In this way, the display panel can finally display an upright image whether the display panel is placed upside down or inverted to match the entire machine.
  • the input transistor during forward scanning is different from the input transistor at the time of reverse scanning.
  • the input transistor connected to the high voltage terminal is prone to a negative shift of the threshold voltage due to long-term negative Bias Thermal Stress (NBTS).
  • NBTS Bias Thermal Stress
  • the threshold voltage is negatively shifted, when the scanning direction is switched, the level after the pull-up node is charged may be difficult to maintain due to leakage, resulting in no output of the GOA circuit.
  • the GOA circuit uses an oxide transistor (for example, Indium Gallium Zinc Oxide (IGZO) is used as the active layer), the output of the GOA circuit is more likely to occur due to the instability of the oxide transistor itself.
  • IGZO Indium Gallium Zinc Oxide
  • An embodiment of the present disclosure provides a shift register unit including an input circuit, a first reset circuit, and an output circuit.
  • the input circuit includes an input configured to perform a first control on the first control node and the first node in response to the input signal of the input, and then perform a different control on the first node than the first control under the control of the level of the first node a second control, the first node being located in a path in which the input signal performs the first control on the first control node; the first reset circuit is configured to reset the first control node in response to the first reset signal; the output circuit is configured to be The output signal is output to the output under the control of the level of a control node.
  • Embodiments of the present disclosure also provide a gate driving circuit, a display device, and a driving method corresponding to the shift register unit described above.
  • the shift register unit, the gate driving circuit, the display device and the driving method provided by the embodiments of the present disclosure can avoid the phenomenon that the GOA circuit has no output after switching the scanning direction due to the negative bias of the transistor threshold voltage at the input end, thereby enhancing the circuit. Stability increases the threshold voltage offset margin of the transistor.
  • FIG. 1 is a schematic diagram of a shift register unit according to an embodiment of the present disclosure.
  • the shift register unit 100 includes an input circuit 110, a first pull-up node reset circuit 120, and an output circuit 130.
  • the first pull-up node reset circuit 120 in the embodiment of the present disclosure is an example of the first reset circuit
  • the first pull-up node reset circuit 120 is taken as an example of the first reset circuit, but the present invention is described below.
  • the disclosed embodiments are not limited thereto, and the following embodiments are the same as those described herein, and are not described again.
  • the input circuit 110 includes an input terminal INT configured to perform a first control on the first control node PU (eg, the pull-up node) and the first node N1 (shown in FIG. 2) in response to the input signal of the input terminal INT (eg, Charging), for example, charging it to a first level (eg, a high level), and then performing a second control different from the first control on the first node N1 under the control of the level of the first node N1 (eg, discharging), for example, discharging to a second level (eg, low level).
  • a first control on the first control node PU eg, the pull-up node
  • the first node N1 shown in FIG. 2
  • the first node N1 is located in a path (eg, a charging path of charging) in which the input signal first controls the first control node PU.
  • the input circuit 110 is connected to the input terminal INT, the first control node PU, and the first voltage terminal VFD, and is configured to electrically connect the first control node PU and the first voltage terminal VFD under the control of the input signal provided by the input terminal INT.
  • Receiving a first voltage so that the first voltage received by the first voltage terminal can charge (eg, pull up) the first control node PU, so that the voltage of the first control node PU increases to a first level, thereby
  • the control output circuit 230 is turned on.
  • the first voltage terminal VFD can be configured, for example, to maintain an input DC high level signal.
  • the DC high level signal is referred to as a first voltage, so that the first control node PU can be charged.
  • the embodiment is the same as this, and will not be described again.
  • the first control is charging (for example, pull-up), and the second control is discharging (for example, pull-down) as an example, but the embodiment of the present disclosure does not perform this.
  • the following embodiments are the same as the above, and will not be described again.
  • the first control node in the embodiment of the present disclosure includes a pull-up node, and the following pull-up node is a first control node as an example, but the embodiment of the present disclosure is not limited thereto, and the following embodiments are the same. ,No longer.
  • the first pull up node reset circuit 120 is configured to reset the pull up node PU in response to the first reset signal.
  • the first pull-up node reset circuit 120 is configured to be connected to the first reset terminal RST1, so that the pull-up node PU and the low-level signal or can be controlled under the control of the first reset signal input by the first reset terminal RST1.
  • the low voltage terminal is electrically connected so that the pull-up node PU can be pulled down and reset.
  • the output circuit 130 is configured to output a clock signal to the output terminal OUT under the control of the level of the pull-up node PU as an output signal of the shift register unit 100 to drive, for example, a gate line connected to the output terminal OUT.
  • the output circuit 130 is connected to the clock signal terminal CLK and the output terminal OUT, and is configured to be turned on under the control of the level of the pull-up node PU, so that the clock signal terminal CLK and the output terminal OUT are electrically connected, so that the clock signal end can be The clock signal of the CLK input is output to the output terminal OUT.
  • the input circuit 110 includes a first input sub-circuit 111, a second input sub-circuit 112, and a first node discharge electronic circuit 113.
  • the first input sub-circuit 111 is configured to perform a first control of the first node N1 in response to the input signal.
  • the first input sub-circuit 111 is connected to the input terminal INT, the first node N1, and the first voltage terminal VFD, and is configured to connect the first node N1 and the first voltage terminal VFD under the control of the input signal provided by the input terminal INT.
  • the high level signal ie, the first voltage
  • the first voltage terminal VFD can charge the first node N1 to the first level.
  • the second input sub-circuit 112 is configured to perform a first control of the pull-up node PU in response to the input signal.
  • the second input sub-circuit 112 is connected to the input terminal INT, the pull-up node PU, and the first node N1, and is configured to electrically connect the first node N1 and the pull-up node PU under the control of the input signal provided by the input terminal INT. Thereby, the high level signal of the first node N1 can be charged to the first level by the pull-up node PU.
  • the first node discharge electronic circuit 113 is configured to perform a second control of the first node N1 under the control of the first level of the first node N1.
  • the first node discharge electronic circuit 113 can be connected to the input terminal INT and the first node N1, and configured to electrically connect the first node N1 and the input terminal INT under the control of the first level of the first node N1 (at this time)
  • the input terminal INT is in a low voltage state) so that the first node N1 can be discharged to the second level.
  • the first node N1 when the input signal provided by the input terminal INT has a high level to a low level, the first node N1 is discharged by the coupling action, for example, in a subsequent stage, when the input signal provided by the input terminal INT is kept low,
  • the first voltage terminal VFD maintains an input high level
  • the transistor of the first input sub-circuit 111 has a risk of a negative offset, and the potential of the first node N1 may be charged to a high level.
  • the first node N1 The first node discharge electronic circuit 113 and the input terminal INT can be discharged to a low level, so that the transistor in the second input sub-circuit 120 can maintain a zero bias state, thereby eliminating the risk of shifting the threshold voltage and preventing the upper limit.
  • the pull node PU forms a leakage path to prevent the output of the GOA circuit from switching after the scanning direction.
  • the first pull-up node reset circuit 120 includes a first reset terminal RST1, and the first pull-up node reset circuit 120 is further configured to perform second control on the second node N2 under the control of the level of the second node N2.
  • the second node N2 is located in a path (eg, a discharge path) in which the first reset signal performs a second control on the first control node PU.
  • the first pull-up node reset circuit 120 includes a first reset sub-circuit 121, a second reset sub-circuit 122, and a second node discharge circuit 123.
  • the first reset sub-circuit 121 is configured to reset the second node N2 in response to the first reset signal.
  • the first reset sub-circuit 121 is connected to the first reset terminal RST1 and the second voltage terminal VBD, and is configured to enable the second node N2 and the second voltage terminal VBD under the control of the first reset signal provided by the first reset terminal RST1. Electrically connected so that the second node N2 can be reset.
  • the second voltage terminal VBD can be configured, for example, to maintain an input DC low level signal, and the DC low level is referred to as a second voltage.
  • the second voltage is less than the first voltage, so that the second node N2 can be reset.
  • the second reset sub-circuit 122 is configured to reset the pull-up node PU in response to the first reset signal.
  • the second reset sub-circuit 122 is connected to the first reset terminal RST1, the pull-up node PU, and the second node N2, and configured to enable the second node N2 and the upper control under the control of the first reset signal provided by the first reset terminal RST1.
  • the pull node PU is electrically connected so that the low level signal of the second node N2 can be reset to the pull up node PU.
  • the second node discharge electronic circuit 123 is configured to perform a second control of the second node N2 under the control of the level of the second node N2.
  • the second node discharge electronic circuit 123 is connected to the first reset terminal RST1 and the second node N2, and is configured to electrically connect the second node N2 and the first reset terminal RST1 under the control of the level of the second node N2, thereby The second node N2 can be discharged.
  • the first pull-up node reset circuit 120 is symmetrically disposed with the input circuit 110, and thus the shift register unit can be used for bidirectional scanning.
  • the display panel of the shift register unit 100 is used for forward scanning (ie, the input signal is supplied to the input terminal INT, the first reset terminal RST1 provides the first reset signal), the operation thereof is as described above, and when the shift is employed
  • the display panel of the register unit 100 performs reverse scanning (ie, providing an input signal to the first reset terminal RST1 and providing a first reset signal to the input terminal INT)
  • the first reset sub-circuit 121 may be provided in response to the first reset terminal RST1.
  • the input signal charges the second node N2, the second reset sub-circuit 122 can charge the pull-up node PU in response to the input signal provided by the first reset terminal RST1, and the second node discharge electronic circuit 123 can be at the second node N2
  • the second node N2 is discharged under the control of the level. For example, when the input signal provided by the first reset terminal RST1 changes from a high level to a low level, the second node N2 is discharged by the coupling action, for example, in a subsequent stage.
  • the transistor of the first reset sub-circuit 121 has a negative offset wind.
  • the potential of the second node N2 may be charged to a high level.
  • the second node N2 may also be discharged to a low level through the second node discharge electronic circuit 123 and the first reset terminal RST1.
  • the transistor in the second reset sub-circuit 122 maintains a zero bias state, thereby eliminating the risk of threshold voltage shift and preventing the pull-up node PU from forming a leakage path to avoid the phenomenon that the GOA circuit has no output after switching the scanning direction.
  • the shift register unit may further include a first control circuit, a first control node noise reduction circuit, and an output noise reduction circuit.
  • FIG. 4A is a schematic diagram of another shift register unit according to an embodiment of the present disclosure. As shown in FIG. 4A, on the basis of the example shown in FIG. 1, the shift register unit 100 may further include a first pull-down node control circuit 140, a pull-up node noise reduction circuit 150, and an output noise reduction circuit 160, and the like. The structure is similar to the shift register unit 100 shown in FIG. 1, and will not be described again.
  • first pull-down node control circuit 140 in the embodiment of the present disclosure is an example of the first control circuit
  • the pull-up node noise reduction circuit 150 is an example of the first control node noise reduction circuit
  • a pull-down node control circuit 140 is a first control circuit
  • the pull-up node noise reduction circuit 150 is a first control node noise reduction circuit.
  • the embodiment of the present disclosure is not limited thereto, and the following embodiments are the same. No longer.
  • the first pull-down node control circuit 140 is configured to control the level of the second control node PD (e.g., the pull-down node) under the control of the level of the pull-up node PU.
  • the first pull-down node control circuit 140 connects the third voltage terminal VGH, the fourth voltage terminal VGL, the pull-up node PU, and the second control node PD to make the second under the control of the level of the pull-up node PU.
  • the control node PD and the fourth voltage terminal VGL are electrically connected to pull-down control the level of the second control node PD to be at a low level.
  • the first pull-down node control circuit 140 can electrically connect the second control node PD and the third voltage terminal under the control of the third voltage provided by the third voltage terminal VGH, thereby charging the second control node PD.
  • the third voltage terminal VGH may be configured to maintain an input DC high level signal, for example, the DC high level signal is referred to as a third voltage
  • the fourth voltage terminal VGL may be configured to maintain an input DC low, for example.
  • the level signal refers to the DC low level signal as a fourth voltage
  • the fourth voltage is lower than the third voltage.
  • the third voltage is the same as the first voltage
  • the fourth voltage and the second voltage are the same, and each of the following The embodiment is the same as this, and will not be described again.
  • the second control node in the embodiment of the present disclosure includes a pull-down node, and the following pull-down node is a second control node as an example.
  • the embodiments of the present disclosure are not limited thereto, and the following embodiments are the same. No longer.
  • the pull-up node noise reduction circuit 150 is configured to perform noise reduction on the pull-up node PU under the control of the level of the pull-down node PD.
  • the pull-up node noise reduction circuit 150 is configured to be connected to the fourth voltage terminal VGL, the pull-up node PU, and the pull-down node PD to enable the pull-up node PU and the fourth voltage terminal under the control of the level of the pull-down node PD.
  • the VGL is electrically connected to pull down the noise of the pull-up node PU.
  • the output noise reduction circuit 160 is configured to denoise the output terminal OUT under the control of the level of the pull-down node PD.
  • the output noise reduction circuit 160 is configured to be connected to the fourth voltage terminal VGL, the output terminal OUT, and the pull-down node PD to electrically connect the output terminal OUT and the fourth voltage terminal VGL under the control of the level of the pull-down node PD. Therefore, the output terminal OUT is pulled down and noise reduced.
  • the input circuit 110 is connected to the first voltage terminal VFD, and the first pull-up node reset circuit 120 is connected to the second voltage terminal VBD.
  • the output signals of the first voltage terminal VFD and the second voltage terminal VBD can be switched between a high level and a low level as needed.
  • the first voltage terminal VFD can be configured to maintain the input DC high-level signal.
  • the second voltage terminal VBD can be configured to maintain an input DC low level signal; the first reset signal is provided at the input terminal INT of the input circuit 110, and the first reset terminal RST1 of the first pull-up node reset circuit 120 provides an input signal.
  • the first voltage terminal VFD can be switched to maintain the input DC low level signal, and the second voltage terminal VBD can be switched to maintain the input DC high level signal.
  • the shift register unit 100 shown in FIG. 4A may be embodied in one example as the circuit structure shown in FIG. 4B.
  • each transistor is an N-type transistor as an example, but it does not constitute a limitation on the embodiment of the present disclosure.
  • the shift register unit 100 includes first to eleventh transistors T1-T11 and further includes a first storage capacitor C1.
  • the input circuit 110 includes a first input sub-circuit 111, a second input sub-circuit 112, and a first node discharge circuit 113.
  • the first input sub-circuit 111 can be implemented as the first transistor T1.
  • the gate of the first transistor T1 is configured to be connected to the input terminal INT to receive an input signal
  • the first electrode of the first transistor T1 is configured to be connected to the first voltage terminal VFD to receive the first voltage
  • the first node N1 is configured to be connected to the first node N1, so that when the first transistor T1 is turned on by the input terminal INT (the high level signal), the first voltage provided by the first voltage terminal VFD is used to be the first Node N1 is charged to be at a first level, ie a high level.
  • the second input sub-circuit 112 can be implemented as a second transistor T2.
  • the gate of the second transistor T2 is configured to be connected to the input terminal INT to receive the input signal
  • the first pole of the second transistor T2 is configured to be connected to the first node N1
  • the second pole of the second transistor T2 is configured as a pull-up node
  • the PU is connected such that when the second transistor T2 is turned on due to the turn-on signal (high level signal) received by the input terminal INT, the high level of the first node N1 is used to charge the pull-up node PU to be placed
  • the first level that is, the high level.
  • the first node discharge electronic circuit 113 can be implemented as a third transistor T3.
  • the gate and the first pole of the third transistor T3 are electrically connected to each other, and are configured to be connected to the first node N1, and the second pole of the third transistor T3 is connected to the second control path (for example, a discharge path).
  • the discharge path is, for example, an input.
  • the input signal supplied from the input terminal INT changes from a high level to a low level
  • the potential of the first node N1 is lowered by the coupling action, for example, due to the parasitic capacitance coupling of the transistor.
  • the first transistor T1 has a risk of a negative offset, and the potential of the first node N1 It may be charged to a high level.
  • the third transistor T3 is turned on by the on-level (high level) of the first node N1, so that the high level of the first node N1 is passed through the input terminal INT.
  • the first transistor T1 and the second transistor T2 are both turned on, so that the first voltage of the first voltage terminal VFD is opposite to the first node N1.
  • the pull-up node PU is charged to be at the first level, that is, the high level.
  • the first voltage terminal VFD is now configured to maintain an input DC high level signal.
  • the first transistor T1 Since the first voltage terminal VFD is kept at the input high level, the first transistor T1 has a risk of a negative offset, and the potential of the first node N1 may be charged to a high level.
  • the third transistor T3 is turned on, thereby electrically connecting the first node N1 and the input terminal INT to discharge the first node N1 to be controlled to a second level, that is, a low level. This can maintain the second transistor T2 in a zero bias state, thereby eliminating the risk of threshold voltage shift and preventing the pull-up node PU from forming a leakage path, thereby avoiding the phenomenon that the GOA circuit has no output after switching the scanning direction.
  • the first pull-up node reset circuit 120 includes a first reset sub-circuit 121, a second reset sub-circuit 122, and a second node discharge circuit 123.
  • the first reset sub-circuit 121 can be implemented as a fourth transistor T4.
  • the gate of the fourth transistor T4 is configured to be connected to the first reset terminal RST1 to receive the first reset signal
  • the first pole of the fourth transistor T4 is configured to be connected to the second voltage terminal VBD to receive the second voltage
  • the fourth transistor T4 The second pole is configured to be connected to the second node N2.
  • the second reset sub-circuit 122 can be implemented as a fifth transistor T5.
  • the gate of the fifth transistor T5 is configured to be connected to the first reset terminal RST1 to receive the first reset signal
  • the first pole of the fifth transistor T5 is configured to be connected to the second node N2
  • the second pole of the fifth transistor T5 is configured as Connected to the pull-up node PU.
  • the second node discharge electronic circuit 123 can be implemented as a sixth transistor T6.
  • the gate and the first pole of the sixth transistor T6 are electrically connected to each other, and are both connected to the second node N2, and the second pole of the sixth transistor T6 is connected to the first reset terminal RST1.
  • the fourth transistor T4 and the fifth transistor T5 are both turned on, so that the pull-up node PU and the second voltage terminal VBD are electrically connected, so that the pull-up can be performed
  • the node PU is reset to drop from a high level to a low level.
  • the second voltage terminal VBD is now configured to maintain an input DC low level signal.
  • the reverse scan is performed, the first reset terminal RST1 provides an input signal, and the second voltage terminal VBD is switched to provide a DC high level signal to charge the second node N2 and the pull-up node PU.
  • the input signal of the first reset terminal is changed from the active level to the inactive level, the level of the second node N2 is lowered due to the coupling effect, and at the same stage, the first reset terminal RST1 remains low.
  • the level signal since the second voltage terminal VBD remains at the input high level, the fourth transistor T4 has a risk of a negative offset, and the potential of the second node N2 may be charged to a high level, in which case the sixth transistor T6 is turned on under the control of the level of the second node N2, thereby electrically connecting the second node N2 and the first reset terminal RST1 to discharge the second node N2 to control it at the second level, that is, low Level.
  • the output circuit 130 can be implemented as a seventh transistor T7 and a first storage capacitor C1.
  • the gate of the seventh transistor T7 is configured to be connected to the pull-up node PU
  • the first pole of the seventh transistor T7 is configured to be connected to the clock signal terminal CLK to receive the clock signal
  • the second pole of the seventh transistor T7 is configured as an output terminal OUT connection.
  • the first pole of the first storage capacitor C1 is configured to be connected to the gate of the seventh transistor T7
  • the second pole of the first storage capacitor C1 is configured to be connected to the second pole of the seventh transistor T7.
  • the seventh transistor T7 When the level of the pull-up node PU is an active level, the seventh transistor T7 is turned on, thereby outputting a clock signal to the output terminal OUT; the first storage capacitor C1 has a bootstrap function, which is beneficial to better in the clock signal. High level output.
  • the first pull-down node control circuit 140 can be implemented as an eighth transistor T8 and a ninth transistor T9.
  • the gate and the first pole of the eighth transistor T8 are electrically connected to each other, and are both configured to be connected to the third voltage terminal VGH to receive the third voltage, and the second electrode of the eighth transistor T8 is connected to the pull-down node PD.
  • the gate of the ninth transistor T9 is connected to the pull-up node PU, the first pole of the ninth transistor T9 is connected to the pull-down node PD, and the second pole of the ninth transistor T9 and the fourth voltage terminal VGL are connected to receive the fourth voltage.
  • the eighth transistor T8 is always in an on state in response to the third voltage supplied from the third voltage terminal VGH, and when the ninth transistor T9 is turned off, the level of the pull-up node PU is controlled to a third voltage, that is, high. Level.
  • the parameters of the ninth transistor T9 and the eighth transistor T8 are designed such that the pull-down node can be turned on when the ninth transistor T9 is turned on under the control of the level of the pull-up node PU
  • the voltage of the PD is pulled down to the fourth voltage, and the following embodiments are the same as those described herein, and will not be described again.
  • the pull-up node noise reduction circuit 150 can be implemented as a tenth transistor T10.
  • the gate of the tenth transistor T10 is connected to the pull-down node PD, the first pole of the tenth transistor T10 is connected to the pull-up node PU, and the second pole of the tenth transistor T10 is connected to the fourth voltage terminal VGL to receive the fourth voltage.
  • the tenth transistor T10 is turned on when the pull-down node PD is at an active level, electrically connecting the pull-up node PU and the fourth voltage terminal VGL, so that the pull-up node PU can be pulled down to the fourth voltage to achieve noise reduction.
  • the output noise reduction circuit 160 can be implemented as the eleventh transistor T11.
  • the gate of the eleventh transistor T11 is connected to the pull-down node PD, the first pole of the eleventh transistor T11 is connected to the output terminal OUT, and the second pole of the eleventh transistor T11 is connected to the fourth voltage terminal VGL to receive the fourth voltage. .
  • the eleventh transistor T11 is turned on when the pull-down node PD is at an active level, and electrically connects the output terminal OUT and the fourth voltage terminal VGL, so that the output terminal OUT can be noise-reduced.
  • the shift register unit may further include a second reset circuit.
  • FIG. 5A is a schematic diagram of another shift register unit according to an embodiment of the present disclosure. As shown in FIG. 5A, on the basis of the example shown in FIG. 4A, the shift register unit 100 may further include a second pull-up node reset circuit 170, and other structures are similar to the shift register unit 100 shown in FIG. 4A. I will not repeat them here.
  • the second pull-up node reset circuit 170 in the embodiment of the present disclosure is an example of the second reset circuit
  • the second reset circuit is the second pull-up node reset circuit 170 as an example.
  • the disclosed embodiments are not limited thereto, and the following embodiments are the same as those described herein, and are not described again.
  • the second pull up node reset circuit 170 is configured to reset the pull up node PU in response to the second reset signal.
  • the second pull-up node reset circuit 170 is connected to the second reset terminal RST2, the pull-up node PU, and the fourth voltage terminal VGL to enable the pull-up node PU under the control of the second reset signal provided by the second reset terminal RST2.
  • the fourth voltage terminal VGL is electrically connected so that the pull-up node PU can be reset.
  • the second reset signal is a total reset signal
  • the second pull-up node reset circuit 170 can pull up the nodes of all the cascaded shift register units under the control of the second reset signal after the end of one frame image scanning. The PU is reset.
  • the shift register unit 100 shown in FIG. 5A can be embodied in one example as the circuit structure shown in FIG. 5B. As shown in FIG. 5B, the shift register unit 100 in this embodiment is similar to the shift register unit 100 described in FIG. 4B except that the twelfth transistor T12 is further included.
  • the second pull-up node reset circuit 170 can be implemented as the twelfth transistor T12.
  • the gate of the twelfth transistor T12 is connected to the second reset terminal RST2 to receive the second reset signal
  • the first pole of the twelfth transistor T2 is connected to the pull-up node PU
  • the second pole and the fourth transistor of the twelfth transistor T12 The voltage terminal VGL is connected to receive the fourth voltage.
  • the twelfth transistor T12 is turned on when the second reset signal is at an active level (for example, a high level), and electrically connects the pull-up node PU and the fourth voltage terminal VGL, so that the pull-up node PU can be reset.
  • the shift register unit further includes a second control circuit.
  • FIG. 6A is a schematic diagram of another shift register unit according to an embodiment of the present disclosure. As shown in FIG. 6A, on the basis of the example shown in FIG. 5A, the shift register unit 100 may further include a second pull-down node control circuit 180, and other structures are similar to the shift register unit 100 shown in FIG. 5A. This will not be repeated here.
  • the second pull-down node control circuit 180 in the embodiment of the present disclosure is an example of the second control circuit.
  • the second control circuit is used as the second pull-down node control circuit 180 as an example, but the implementation of the present disclosure. The examples are not limited thereto, and the following embodiments are the same as those described herein, and are not described again.
  • the second pull-down node control circuit 180 is configured to perform a second control of the pull-down node PD in response to the input signal.
  • the second pull-down node control circuit 180 is connected to the input terminal INT, the first reset terminal RST1, the pull-down node PD, and the fourth voltage terminal VGL to input an input signal (for forward scanning) or a first reset at the input terminal INT.
  • the pull-down node PD and the fourth voltage terminal VGL are electrically connected under the control of the input signal (in the case of reverse scanning) provided by the terminal RST1, so that the pull-down node PD can be discharged (for example, discharged to the second level) during the input phase, Therefore, it is fully ensured that the pull-up node is not affected by the pull-down node PD during the charging process.
  • the shift register unit 100 shown in FIG. 6A can be embodied in one example as the circuit structure shown in FIG. 6B.
  • the shift register unit 100 in this embodiment is similar in structure to the shift register unit 100 described in FIG. 5B except that the thirteenth transistor T13 and the fourteenth transistor T14 are further included.
  • the second pull-down node control circuit 180 can be implemented as a thirteenth transistor T13 and a fourteenth transistor T14.
  • the gate of the thirteenth transistor T13 is connected to the input terminal INT to receive an input signal
  • the first pole of the thirteenth transistor T13 is connected to the pull-down node PD
  • the second pole of the thirteenth transistor T13 is connected to the fourth voltage terminal VGL.
  • Receiving the fourth voltage The gate of the fourteenth transistor T14 is connected to the first reset terminal RST1 to receive the first reset signal
  • the first pole of the fourteenth transistor T14 is connected to the pull-down node PD
  • the second pole and the fourth of the fourteenth transistor T14 The voltage terminal VGL is connected to receive the fourth voltage.
  • the thirteenth transistor T13 is turned on when the input signal supplied from the input terminal INT is an active level, and electrically connects the pull-down node PD and the fourth voltage terminal VGL, so that the pull-down node PD can be discharged.
  • the fourteenth transistor T14 is turned on when the first reset signal supplied from the first reset terminal RST1 is at an active level, and electrically connects the pull-down node PD and the fourth voltage terminal VGL, so that the pull-down node PD can be discharged.
  • the fourteenth transistor T14 is turned on when the input signal provided by the first reset terminal RST1 is an active level, and electrically connects the pull-down node PD and the fourth voltage terminal VGL, so that the pull-down node PD can be The discharge is performed; the thirteenth transistor T13 is turned on when the first reset signal supplied from the input terminal INT is at an active level, and electrically connects the pull-down node PD and the fourth voltage terminal VGL, so that the pull-down node PD can be discharged.
  • the pull-up node PU, the pull-down node PD, the first node N1, and the second node N2 do not represent actual components, but represent related electrical connections in the circuit diagram. Meeting point.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor, a field effect transistor, or other switching device having the same characteristics.
  • a thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the embodiment of the present disclosure in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described.
  • the transistors in the embodiments of the present disclosure are all described by taking an N-type transistor as an example.
  • the first pole of the transistor is the drain and the second pole is the source.
  • the present disclosure includes but is not limited thereto.
  • one or more transistors in the shift register unit 100 provided by the embodiment of the present disclosure may also adopt a P-type transistor.
  • the first pole of the transistor is a source and the second pole is a drain, and only needs to be selected.
  • the poles of a given type of transistor may be connected in accordance with the respective poles of the respective transistors in the embodiments of the present disclosure.
  • ITZO Indium Gallium Zinc Oxide
  • LTPS low temperature polysilicon
  • amorphous silicon for example, hydrogenation non-hydrogenation
  • pulse-up means charging one node or one electrode of a transistor such that the level of the node or the electrode is absolute. The value is increased to achieve the operation of the corresponding transistor (eg, conduction); “pull-down” means discharging one electrode of one node or one transistor, so that the absolute value of the level of the node or the electrode is lowered, thereby achieving corresponding Operation of the transistor (eg cut-off).
  • pulse-up means discharging one electrode of one node or one transistor, so that the absolute value of the level of the node or the electrode is lowered, thereby implementing the corresponding transistor.
  • Operation eg, conduction
  • pulse-down means charging one node or one electrode of a transistor to increase the absolute value of the level of the node or the electrode to achieve operation of the corresponding transistor (eg, cutoff) .
  • FIG. 7 is a timing diagram of signals of a shift register unit during operation according to an embodiment of the present disclosure.
  • the working principle of the shift register unit 100 shown in FIG. 6B will be described below with reference to the signal timing diagram shown in FIG. 7.
  • the description will be made by taking an example in which each transistor is an N-type transistor, but the embodiment of the present disclosure is not limited thereto. this.
  • the shift register unit 100 can perform the following operations, respectively.
  • the input terminal INT provides a high level signal
  • the first voltage terminal VFD is configured to provide a DC high level signal
  • the first transistor T1 and the second transistor T2 are provided in response to the input terminal INT.
  • the high level signal is turned on, the first node N1 and the pull-up node PU are charged to the first level; the seventh transistor T7 is turned on in response to the first level of the pull-up node PU, so that the clock signal terminal CLK and the output The terminal OUT is electrically connected.
  • the output terminal OUT outputs a low level of the clock signal; and at this stage, the thirteenth transistor T13 is responsive to the input signal.
  • the ninth transistor T9 is turned on in response to the high level of the pull-up node PU, so that the pull-down node PD and the fourth voltage terminal VGL are connected, so that the pull-down node PD is pulled down to the fourth voltage (ie, low) Level), therefore, at this stage, the pull-down node does not affect the charging process of the pull-up node PU, so that the ninth transistor T9 has a larger threshold voltage offset margin, and the requirements for its process conditions are relaxed.
  • the clock signal terminal provides a high level signal. Therefore, the output terminal OUT outputs a high level of the clock signal; due to the bootstrap effect of the capacitor, the pull-up node PU is further charged to a high level ( For example, higher than the first level); the ninth transistor T9 is turned on under the control of the level of the pull-up node PU, so that the pull-down node PD is connected to the fourth voltage terminal VGL, thereby maintaining a low level; at this stage, The input signal supplied from the input terminal INT is changed from the high level of the first stage to the low level, and the potential of the first node N1 is lowered by the coupling action, for example, due to the parasitic capacitance coupling of the transistor.
  • first The potential of the node N1 may be charged to a high level.
  • the first node N1 may also be discharged to a low level through the third transistor T3 and the input terminal INT, so that the second transistor T2 can be maintained in a subsequent stage.
  • the shift register unit 100 In the zero bias state (the first pole and the second pole are both low), thereby eliminating the risk of offset of the threshold voltage, preventing the formation of the leakage path of the pull-up node PU, and therefore, when the shift register unit 100 is long
  • the time forward scan ie, the input terminal INT provides an input signal and the first reset terminal RST1 provides the first reset signal
  • the reverse scan even if the threshold voltage of the first transistor T1 is connected to the first voltage terminal VFD for a long time Negative offset is caused by Negative Bias Thermal Stress (NBTS), but since the threshold voltage of the second transistor T2 is not offset, the leakage of the pull-up node PU during charging is avoided.
  • the GOA circuit has no output after switching the scanning direction.
  • the first reset terminal RST1 provides a high level signal
  • the second voltage terminal VBD is configured to provide a DC low level signal
  • the fourth transistor T4 and the fifth transistor T5 are responsive to the first reset.
  • the high level signal provided by the terminal RST1 is turned on, thereby connecting the pull-up node PU and the second voltage terminal VBD, pulling the pull-up node PU to a low level; the fourteenth transistor T14 is provided in response to the first reset terminal RST1
  • the high level signal is turned on, thereby connecting the pull-down node PD and the fourth voltage terminal VGL. Therefore, at this stage, the pull-down node PD remains at a low level; at this stage, since the seventh transistor T7 is pulled up
  • the low level of the PU is turned off, so that the output terminal OUT outputs a low level signal.
  • the second reset terminal RST2 supplies a high level signal during the interval before the start of the next frame after the end of the one frame scan, thereby turning on the twelfth transistor T12, so that The pull node PU and the fourth voltage terminal VGL are electrically connected to further reset the pull-up node PU.
  • the input signal and the first reset signal may be exchanged with each other, that is, the input terminal INT provides a first reset signal, and the first reset terminal RST1 provides an input signal.
  • the first voltage terminal VFD provides a DC low level signal
  • the second voltage terminal VBD provides a DC high level signal.
  • the shift register unit 100 works similarly to the forward scan, and will not be described here. It should be noted that when the input signal supplied from the first reset terminal RST1 changes from a high level to a low level, the potential of the second node N2 is lowered due to the coupling action, for example, due to the parasitic capacitance coupling of the transistor.
  • the input signal provided by the first reset terminal RST1 is kept at a low level, and since the second voltage terminal VBD is kept at the input high level, the fourth transistor T4 has a risk of a negative offset.
  • the potential of the first node N1 may be charged to a high level.
  • the second node N2 may also be discharged to a low level through the sixth transistor T6 and the input terminal INT, thereby making the fifth transistor T5 at the first
  • Each stage after phase 1 maintains a zero bias state, thereby eliminating the risk of offset of the threshold voltage and preventing the pull-up node PU from forming a leakage path.
  • the gate driving circuit includes a first clock signal line CLK1, a second clock signal line CLK2, a total reset line TT_RST, and a plurality of cascaded shift register units 100.
  • the shift register unit can employ the shift register unit 100 described in any of the embodiments of the present disclosure.
  • the circuit structure shown in FIG. 6B is taken as an example for each shift register unit 100, but the embodiment of the present disclosure is not limited thereto.
  • the gate driving circuit 10 can be directly integrated on the array substrate of the display device by a process similar to that of the thin film transistor to realize a progressive scan driving function.
  • each of the shift register units further includes a clock signal terminal CLK, and is configured to be connected to the first clock signal line CLK1 or the second clock signal line CLK2 to receive the first clock signal or the second. Clock signal.
  • the clock signal terminal CLK of the first clock signal line CLK1 and the 2n-1 (n is an integer greater than 0) stage shift register unit are connected, and the second clock signal line CLK2 and the clock signal terminal CLK of the 2nth stage shift register unit are connected. connection.
  • the embodiments of the present disclosure include, but are not limited to, the foregoing connection manner.
  • the clock signal terminal CLK of the first clock signal line CLK1 and the second (n is an integer greater than 0) shift register unit may also be employed.
  • the second clock signal line CLK2 is connected to the clock signal terminal CLK of the 2n-1th stage shift register unit.
  • each of the shift register units further includes a second reset terminal RST2, and is configured to be connected to the total reset line TT_RST to receive a second reset signal to pass after each frame scan ends.
  • the second reset signal provided by the total reset line TT_RST resets all pull-up nodes of the shift register unit.
  • the gate drive circuit 10 may further include a timing controller 200.
  • the timing controller 200 can be configured to be coupled to the first clock signal line CLK1, the second clock signal line CLK2, and the total reset line TT_RST to provide a clock signal and a second reset signal to each of the shift register units.
  • the timing controller 200 can also be configured as a trigger signal STV and a reset signal RESET.
  • the first reset terminal RST1 of the remaining stages of shift register units is connected to the output terminal OUT of the next stage shift register unit.
  • the input terminals INT of the remaining stages of the shift register unit are connected to the output terminal OUT of the shift register unit of the previous stage.
  • the input INT of the first stage shift register unit can be configured to receive the trigger signal STV
  • the first reset terminal RST1 of the last stage shift register unit can be configured to receive the reset signal RESET.
  • the input INT of the first stage shift register unit can be configured to receive a reset signal RESET
  • the first reset terminal RST1 of the last stage shift register unit can be configured to receive the trigger signal STV.
  • the gate driving circuit 10 may further include four, six or eight clock signal lines, and the number of the clock signal lines is determined according to a specific situation, and the embodiment of the present disclosure is not limited herein.
  • the gate driving circuit 10 when the gate driving circuit 10 provided by the embodiment of the present disclosure drives a display panel, the gate driving circuit 10 may be disposed on one side of the display panel.
  • the display panel includes a plurality of rows of gate lines, and the output ends of the shift register units in the gate driving circuit 10 may be configured to be sequentially connected to the plurality of rows of gate lines for outputting a gate scan signal.
  • the gate driving circuit 10 may be separately disposed on both sides of the display panel to implement bilateral driving.
  • the manner in which the gate driving circuit 10 is disposed in the embodiment of the present disclosure is not limited.
  • the gate drive circuit 10 may be disposed on one side of the display panel for driving odd-numbered gate lines, and the gate drive circuit 10 may be disposed on the other side of the display panel for driving even-numbered gate lines.
  • the gate driving circuit can avoid the phenomenon that there is no output after switching the scanning direction due to the negative bias of the threshold voltage of the transistor at the input end, which enhances the stability of the circuit and makes the transistor have a larger threshold voltage offset margin.
  • An embodiment of the present disclosure further provides a display device 1 including a gate driving circuit 10 provided by an embodiment of the present disclosure, as shown in FIG.
  • the display device 1 includes a pixel array composed of a plurality of pixel units 30.
  • the display device 1 may further include a data driving circuit 20.
  • the data driving circuit 20 is for providing a data signal to the pixel array;
  • the gate driving circuit 10 is for providing a gate scanning signal to the pixel array.
  • the data driving circuit 20 is electrically connected to the pixel unit 30 through the data line 21, and the gate driving circuit 10 is electrically connected to the pixel unit 30 through the gate line 11.
  • the display device 1 in this embodiment may be: a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigation device, and the like.
  • the display device 1 may further include other conventional components such as a display panel, which is not limited by the embodiments of the present disclosure.
  • the entire structure of the display device 1 is not given for clarity and conciseness.
  • a person skilled in the art can set other structures not shown according to the specific application scenario, which is not limited by the embodiment of the present disclosure.
  • An embodiment of the present disclosure further provides a driving method, such as a shift register unit for a display device.
  • a driving method such as a shift register unit for a display device.
  • the driving method of the shift register unit includes the following operations:
  • the input circuit 110 performs a first control (eg, charging to a first level) on the pull-up node PU and the first node N1 in response to the input signal, and the output circuit 130 outputs a low power of the output signal (eg, a clock signal).
  • a first control eg, charging to a first level
  • the output circuit 130 outputs a low power of the output signal (eg, a clock signal).
  • the input circuit 110 performs a second control (eg, discharging to a second level) on the first node N1 in response to the level of the first node N1, and the output circuit 130 outputs a high level of the output signal to the output terminal OUT;
  • a second control eg, discharging to a second level
  • the first pull-up node reset circuit 120 resets the pull-up node PU under the control of the first reset signal.
  • the driving method of the shift register unit includes the following operations:
  • the input circuit 110 performs a first control on the pull-up node PU and the first node N1 in response to the input signal
  • the second pull-down node control circuit 180 performs a second control on the level of the pull-down node PD in response to the input signal, for example Pulling down to a second level (eg, a fourth voltage), the output circuit 130 outputs a low level of the output signal to the output terminal OUT;
  • a second level eg, a fourth voltage
  • the input circuit 110 performs a second control on the first node N1 in response to the first level of the first node N1, and the output circuit 130 outputs a high level of the output signal to the output terminal OUT;
  • the first pull-up node reset circuit 120 resets the pull-up node PU under the control of the first reset signal
  • the second pull-down node control circuit 180 performs the first level of the pull-down node PD in response to the first reset signal. Second control.
  • the input signal and the first reset signal may be exchanged with each other, that is, the first reset terminal RST1 provides an input signal, and the input terminal INT provides the first reset signal.
  • the driving method includes the following operations:
  • the first pull-up node reset circuit 120 performs a first control on the pull-up node PU and the second node N2 in response to the input signal, and the output circuit 130 outputs a low level of the output signal to the output terminal OUT;
  • the first pull-up node reset circuit 120 performs second control on the second node N2 in response to the first level of the second node N2, and the output circuit 130 outputs a high level of the output signal to the output terminal OUT;
  • the input circuit 110 resets the pull-up node PU under the control of the first reset signal.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)

Abstract

一种移位寄存器单元（100）及驱动方法、栅极驱动电路（10）及显示装置（1）。该移位寄存器单元（100）包括：输入电路（110），其包括输入端（INT），配置为响应于输入端（INT）的输入信号对第一控制节点（PU）和第一节点（N1）进行第一控制，以及之后在第一节点（N1）的电平的控制下对第一节点（N1）进行不同于第一控制的第二控制，第一节点（N1）位于输入信号对第一控制节点（PU）进行第一控制的路径中；第一复位电路（120），其配置为响应于第一复位信号对第一控制节点（PU）进行复位；输出电路（130），其配置为在第一控制节点（PU）的电平的控制下，将输出信号输出至输出端（OUT）。该移位寄存器单元（100）能避免由于其输入端（INT）的晶体管的阈值电压负偏导致的切换扫描方向后无输出的现象，增强了电路的稳定性，具有较大的阈值电压偏移余量。

Description

移位寄存器单元及驱动方法、栅极驱动电路及显示装置
本申请要求于2018年3月30日递交的中国专利申请第201810290682.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器单元及驱动方法、栅极驱动电路及显示装置。
背景技术
在显示技术领域，例如液晶显示面板的像素阵列通常包括多行栅线和与之交错的多列数据线。对栅线的驱动可以通过绑定的集成驱动电路实现。近几年随着非晶硅薄膜晶体管或氧化物薄膜晶体管制备工艺的不断提高，也可以将栅线驱动电路直接集成在薄膜晶体管阵列基板上构成GOA(Gate driver On Array)来对栅线进行驱动。例如，可以采用由多个级联的移位寄存器单元构成的GOA为像素阵列的多行栅线提供开关态电压信号，从而例如控制多行栅线依序打开，并且同时由数据线向像素阵列中对应行的像素单元提供数据信号，以在各像素单元形成显示图像的各灰阶所需要的灰度电压，进而显示一帧图像。目前的显示面板越来越多地采用GOA技术来对栅线进行驱动。GOA技术有助于实现窄边框，并且可以降低生产成本。
发明内容
本公开至少一实施例提供一种移位寄存器单元，包括输入电路、第一复位电路和输出电路。所述输入电路包括输入端，配置为响应于所述输入端的输入信号对所述第一控制节点和所述第一节点进行第一控制，以及之后在所述第一节点的电平的控制下对所述第一节点进行不同于所述第一控制的第二控制，所述第一节点位于所述输入信号对所述第一控制节点进行所述第一控制的路径中；所述第一复位电路配置为响应于第一复位信号对所述第一控制 节点进行复位；所述输出电路配置为在所述第一控制节点的电平的控制下，将输出信号输出至输出端。
例如，在本公开一实施例提供的移位寄存器单元中，所述输入电路包括第一输入子电路、第二输入子电路和第一节点放电子电路。所述第一输入子电路配置为响应于所述输入信号对所述第一节点进行所述第一控制；所述第二输入子电路配置为响应于所述输入信号将所述第一控制节点进行所述第一控制；所述第一节点放电子电路配置为在所述第一节点的电平的控制下可对所述第一节点进行所述第二控制。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一输入子电路包括第一晶体管，所述第一晶体管的栅极和所述输入端连接以接收所述输入信号，所述第一晶体管的第一极和第一电压端连接以接收第一电压，所述第一晶体管的第二极和所述第一节点连接；所述第二输入子电路包括第二晶体管，所述第二晶体管的栅极和所述输入端连接以接收所述输入信号，所述第二晶体管的第一极和所述第一节点连接，所述第二晶体管的第二极和所述第一控制节点连接；所述第一节点放电子电路包括第三晶体管，所述第三晶体管的栅极和第一极彼此电连接，且配置为都和所述第一节点连接，所述第三晶体管的第二极和第二控制路径连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二控制路径为所述输入端。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一复位电路与所述输入电路对称设置，所述第一复位电路包括第一复位端，配置为在所述第一复位端的第一复位信号以及所述第二节点的电平的控制下可对所述第二节点进行所述第二控制，所述第二节点位于所述第一复位信号对所述第一控制节点进行所述第二控制的路径中。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一复位电路包括第一复位子电路、第二复位子电路和第二节点放电子电路。所述第一复位子电路配置为响应于所述第一复位信号对第二节点进行复位；所述第二复位子电路配置为响应于所述第一复位信号将所述第一控制节点进行复位；所述第二节点放电子电路配置为在所述第二节点的电平的控制下对所述第二节点进行所述第二控制。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一复位子电路包括第四晶体管，所述第四晶体管的栅极和第一复位端连接以接收所述第一复位信号，所述第四晶体管的第一极和第二电压端连接以接收第二电压，所述第四晶体管的第二极和所述第二节点连接；所述第二复位子电路包括第五晶体管，所述第五晶体管的栅极和所述第一复位端连接以接收所述第一复位信号，所述第五晶体管的第一极和所述第二节点连接，所述第五晶体管的第二极和所述第一控制节点连接；所述第二节点放电子电路包括第六晶体管，所述第六晶体管的栅极和第一极彼此电连接，且配置为都和所述第二节点连接，所述第六晶体管的第二极和所述第一复位端连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出电路包括第七晶体管和第一存储电容。所述第七晶体管的栅极和所述第一控制节点连接，所述第七晶体管的第一极和时钟信号端连接以接收时钟信号作为所述输出信号，所述第七晶体管的第二极和所述输出端连接；所述第一存储电容的第一极和所述第一控制节点连接，所述第一存储电容的第二极和所述输出端连接。
例如，本公开一实施例提供的移位寄存器单元，还包括第一控制电路、第一控制节点降噪电路和输出降噪电路。所述第一控制电路配置为对第二控制节点的电平进行控制；所述第一控制节点降噪电路配置为在所述第二控制节点的电平的控制下，对所述第一控制节点进行降噪；所述输出降噪电路配置为在所述第二控制节点的电平的控制下，对所述输出端进行降噪。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一控制电路包括第八晶体管和第九晶体管，所述第八晶体管的栅极和第一极彼此电连接，且配置为都和第三电压端连接以接收第三电压，所述第八晶体管的第二极和所述第二控制节点连接，所述第九晶体管的栅极和所述第一控制节点连接，所述第九晶体管的第一极和所述第二控制节点连接，所述第九晶体管的第二极和第四电压端连接以接收第四电压；所述第一控制节点降噪电路包括第十晶体管，所述第十晶体管的栅极和所述第二控制节点连接，所述第十晶体管的第一极和所述第一控制节点连接，所述第十晶体管的第二极和所述第四电压端连接以接收所述第四电压；所述输出降噪电路包括第十一晶体管，所述第十一晶体管的栅极和所述第二控制节点连接，所述第十一晶体管的第一极 和所述输出端连接，所述第十一晶体管的第二极和所述第四电压端连接以接收所述第四电压。
例如，本公开一实施例提供的移位寄存器单元，还包括第二复位电路，其中，所述第二复位电路配置为响应于第二复位信号对所述第一控制节点进行复位。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二复位电路包括第十二晶体管，所述第十二晶体管的栅极和第二复位端连接以接收所述第二复位信号，所述第十二晶体管的第一极和所述第一控制节点连接，所述第十二晶体管的第二极和第四电压端连接以接收第四电压。
例如，本公开一实施例提供的移位寄存器单元，还包括第二控制电路，所述第二控制电路配置为响应于所述输入信号对第二控制节点进行所述第二控制。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二控制电路包括第十三晶体管和第十四晶体管。所述第十三晶体管的栅极和所述输入端连接以接收所述输入信号，所述第十三晶体管的第一极和所述第二控制节点连接，所述第十三晶体管的第二极和第四电压端连接以接收第四电压；所述第十四晶体管的栅极和第一复位端连接以接收所述第一复位信号，所述第十四晶体管的第一极和和所述第二控制节点连接，所述第十四晶体管的第二极和所述第四电压端连接以接收所述第四电压。
本公开至少一实施例还提供一种栅极驱动电路，包括本公开任一实施例所述的移位寄存器单元。
本公开至少一实施例还提供一种显示装置，包括本公开一实施例所述的栅极驱动电路。
本公开至少一实施例还提供一种移位寄存器单元的驱动方法，包括：第一阶段，所述输入电路响应于所述输入信号对所述第一控制节点和所述第一节点进行所述第一控制，所述输出电路输出所述输出信号的低电平至所述输出端；第二阶段，所述输入电路响应于所述第一节点的电平对所述第一节点进行所述第二控制，所述输出电路输出所述输出信号的高电平至所述输出端；第三阶段，所述第一复位电路在所述第一复位信号的控制下对所述第一控制节点进行复位。
本公开至少一实施例还提供一种移位寄存器单元的驱动方法，将所述输入信号和所述第一复位信号彼此交换，所述驱动方法包括：第一阶段，所述第一复位电路响应于所述输入信号对所述第一控制节点和所述第二节点进行所述第一控制，所述输出电路输出所述输出信号的低电平至所述输出端；第二阶段，所述第一复位电路响应于所述第二节点的电平对所述第二节点进行所述第二控制，所述输出电路输出所述输出信号的高电平至所述输出端；第三阶段，所述输入电路在所述第一复位信号的控制下对所述第一控制节点进行复位。
本公开至少一实施例还提供一种移位寄存器单元的驱动方法，包括：第一阶段，所述输入电路响应于所述输入信号对所述第一控制节点和所述第一节点进行所述第一控制，所述第二控制电路响应于所述输入信号对所述第二控制节点的电平进行所述第二控制，所述输出电路输出所述输出信号的低电平至所述输出端；第二阶段，所述输入电路响应于所述第一节点的第一电平对所述第一节点进行所述第二控制，所述输出电路输出所述输出信号的高电平至所述输出端；第三阶段，所述第一复位电路在所述第一复位信号的控制下对所述第一控制节点进行复位，所述第二控制电路响应于所述第一复位信号对所述第二控制节点的进行所述第二控制。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一实施例提供的一种移位寄存器单元的示意图；
图2为图1中所示的输入电路的示例的示意图；
图3为图1中所示的第一上拉节点复位电路的示例的示意图；
图4A为本公开一实施例提供的另一种移位寄存器单元的示意图；
图4B为图4A中所示的移位寄存器单元的示例的电路示意图；
图5A为本公开一实施例提供的另一种移位寄存器单元的示意图；
图5B为图5A中所示的移位寄存器单元的示例的电路示意图；
图6A为本公开一实施例提供的另一种移位寄存器单元的示意图；
图6B为图6A中所示的移位寄存器单元的示例的电路示意图；
图7为本公开一实施例提供的一种移位寄存器单元工作时的信号时序图；
图8为本公开一实施例提供的一种栅极驱动电路的示意图；以及
图9为本公开一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
随着显示面板相关产品的客户越来越多，对显示面板的需求也日益多样化。不同的客户对显示面板的扫描方式需求不同。例如，一部分客户希望把面板正放，从第一行开始扫描；而另一部分客户希望把面板倒放，从倒数第一行开始扫描。为了满足客户的需求，GOA电路也渐渐引入了双向扫描的概念。所谓双向扫描，即显示面板可以从第一行开始扫描(正向扫描)，也可以从倒数第一行开始扫描(反向扫描)。在这种方式下，不论将显示面板正放还是倒放以匹配整机，显示面板最终都能显示正立的图像。
然而，在具有双向扫描功能的GOA电路中，正向扫描时的输入晶体管 与反向扫描时的输入晶体管所受的应力不同。与高电压端连接的输入晶体管由于长时间受负偏压热应力(Negative Bias Thermal Stress,NBTS)，容易发生阈值电压负向偏移。若发生阈值电压负向偏移，当切换扫描方向后，上拉节点充电后的电平会因为漏电而难以保持，从而造成GOA电路无输出的现象。若GOA电路采用氧化物晶体管(例如采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为有源层)，由于氧化物晶体管本身的不稳定性，则更容易发生GOA电路无输出的现象。
本公开一实施例提供一种移位寄存器单元，包括输入电路、第一复位电路和输出电路。输入电路包括输入端，配置为响应于输入端的输入信号对第一控制节点和第一节点进行第一控制，以及之后在第一节点的电平的控制下对第一节点进行不同于第一控制的第二控制，第一节点位于输入信号对第一控制节点进行第一控制的路径中；第一复位电路配置为响应于第一复位信号对第一控制节点进行复位；输出电路配置为在第一控制节点的电平的控制下，将输出信号输出至输出端。本公开的实施例还提供对应于上述移位寄存器单元的栅极驱动电路、显示装置及驱动方法。
本公开的实施例提供的移位寄存器单元、栅极驱动电路、显示装置以及驱动方法，可以避免GOA电路因为输入端的晶体管阈值电压负偏导致的切换扫描方向后无输出的现象，增强了电路的稳定性，增大了晶体管的阈值电压偏移余量。
下面结合附图对本公开的实施例及其示例进行详细说明。
本公开一实施例提供一种移位寄存器单元，例如，该移位寄存器单元包括输入电路、第一复位电路和输出电路。图1为本公开一实施例提供的一种移位寄存器单元的示意图。如图1所示，该移位寄存器单元100包括输入电路110、第一上拉节点复位电路120和输出电路130。需要注意的是，本公开实施例中的第一上拉节点复位电路120为第一复位电路的一个示例，下面以第一上拉节点复位电路120为第一复位电路为例进行说明，但是本公开的实施例不限于此，以下实施例与此相同，不再赘述。
输入电路110包括输入端INT，配置为响应于输入端INT的输入信号对第一控制节点PU(例如，上拉节点)和第一节点N1(如图2所示)进行第一控制(例如，充电)，例如，将其充点至第一电平(例如，高电平)，以 及之后在第一节点N1的电平的控制下对第一节点N1进行不同于第一控制的第二控制(例如，放电)，例如，放电至第二电平(例如，低电平)。例如，如图2所示，第一节点N1位于输入信号对第一控制节点PU进行第一控制的路径(例如充电的充电路径)中。例如，输入电路110与输入端INT、第一控制节点PU以及第一电压端VFD连接，配置为在输入端INT提供的输入信号的控制下使第一控制节点PU和第一电压端VFD电连接以接收第一电压，从而可以使第一电压端接收的第一电压对第一控制节点PU进行充电(例如，上拉)，以使得第一控制节点PU的电压增加至第一电平，从而控制输出电路230导通。需要说明的是，第一电压端VFD例如可以配置为保持输入直流高电平信号，例如，将该直流高电平信号称为第一电压，从而可以对第一控制节点PU进行充电，以下各实施例与此相同，不再赘述。
需要注意的是，在本公开实施例中，以第一控制为充电(例如，上拉)，第二控制为放电(例如，下拉)为例进行说明，但是本公开的实施例对此不进行限制，以下实施例与此相同，不再赘述。
需要注意的是，本公开实施例中的第一控制节点包括上拉节点，下面以上拉节点为第一控制节点为例进行说明，但是本公开的实施例不限于此，以下实施例与此相同，不再赘述。
该第一上拉节点复位电路120配置为响应于第一复位信号对上拉节点PU进行复位。例如，该第一上拉节点复位电路120配置为和第一复位端RST1连接，从而可以在第一复位端RST1输入的第一复位信号的控制下，使得上拉节点PU和低电平信号或低电压端电连接，从而可以对上拉节点PU进行下拉复位。
输出电路130配置为在上拉节点PU的电平的控制下，将时钟信号输出至输出端OUT，作为该移位寄存器单元100的输出信号，以驱动例如与该输出端OUT连接的栅线。例如，输出电路130与时钟信号端CLK和输出端OUT连接，配置为在上拉节点PU的电平的控制下导通，使时钟信号端CLK和输出端OUT电连接，从而可以将时钟信号端CLK输入的时钟信号输出至输出端OUT。
图2为图1中所示的移位寄存器单元的输入电路的示例的示意图。如图2所示，该输入电路110包括第一输入子电路111、第二输入子电路112和第 一节点放电子电路113。
第一输入子电路111配置为响应于输入信号对第一节点N1进行第一控制。例如，第一输入子电路111和输入端INT、第一节点N1以及第一电压端VFD连接，配置为在输入端INT提供的输入信号的控制下使第一节点N1和第一电压端VFD连接，从而可以使第一电压端VFD接收的高电平信号(即第一电压)将第一节点N1充电至第一电平。
第二输入子电路112配置为响应于输入信号对上拉节点PU进行第一控制。例如，第二输入子电路112和输入端INT、上拉节点PU以及第一节点N1连接，配置为在输入端INT提供的输入信号的控制下使第一节点N1和上拉节点PU电连接，从而可以使第一节点N1的高电平信号对上拉节点PU充电至第一电平。
第一节点放电子电路113配置为在第一节点N1的第一电平的控制下可对第一节点N1进行第二控制。例如，第一节点放电子电路113可以和输入端INT以及第一节点N1连接，配置为在第一节点N1的第一电平的控制下使第一节点N1和输入端INT电连接(此时输入端INT处于低电压状态)，从而可以使第一节点N1放电至第二电平。例如，在输入端INT提供的输入信号有高电平变为低电平时，第一节点N1通过耦合作用放电，例如，在后续的阶段中，输入端INT提供的输入信号保持低电平时，由于第一电压端VFD保持输入高电平，第一输入子电路111的晶体管存在负向偏移风险，第一节点N1的电位可能会被充电至高电平，在这种情形下，第一节点N1可以通过第一节点放电子电路113和输入端INT放电至低电平，这种方式可以使第二输入子电路120中的晶体管维持零偏压状态，从而消除阈值电压的偏移风险，防止上拉节点PU形成漏电通路，以避免GOA电路切换扫描方向后出现无输出的现象。
图3为图1中所示的移位寄存器单元的第一上拉节点复位电路的示例的示意图。例如，第一上拉节点复位电路120包括第一复位端RST1，第一上拉节点复位电路120还配置为在第二节点N2的电平的控制下可对第二节点N2进行第二控制，例如，第二节点N2位于第一复位信号对第一控制节点PU进行第二控制的路径(例如，放电路径)中。更具体地，如图3所示，第一上拉节点复位电路120包括第一复位子电路121、第二复位子电路122 和第二节点放电子电路123。
第一复位子电路121配置为响应于第一复位信号对第二节点N2进行复位。例如，第一复位子电路121和第一复位端RST1以及第二电压端VBD连接，配置为在第一复位端RST1提供的第一复位信号的控制下使第二节点N2和第二电压端VBD电连接，从而可以对第二节点N2进行复位。该第二电压端VBD例如可以配置为保持输入直流低电平信号，将该直流低电平称为第二电压，例如，第二电压小于第一电压，从而可以对第二节点N2进行复位，以下各实施例与此相同，不再赘述。
第二复位子电路122配置为响应于第一复位信号对上拉节点PU进行复位。例如，第二复位子电路122和第一复位端RST1、上拉节点PU以及第二节点N2连接，配置为在第一复位端RST1提供的第一复位信号的控制下使第二节点N2和上拉节点PU电连接，从而可以使第二节点N2的低电平信号对上拉节点PU进行复位。
第二节点放电子电路123配置为在第二节点N2的电平的控制下可对第二节点N2进行第二控制。例如，第二节点放电子电路123和第一复位端RST1以及第二节点N2连接，配置为在第二节点N2的电平的控制下使第二节点N2和第一复位端RST1电连接，从而可以使第二节点N2放电。
在该实施例中，第一上拉节点复位电路120与输入电路110对称设置，因此该移位寄存器单元可以用于双向扫描。当采用该移位寄存器单元100的显示面板进行正向扫描时(即对输入端INT提供输入信号，第一复位端RST1提供第一复位信号)，其操作如上所述，而当采用该移位寄存器单元100的显示面板进行反向扫描时(即对第一复位端RST1提供输入信号，对输入端INT提供第一复位信号)，第一复位子电路121可以响应于第一复位端RST1提供的输入信号对第二节点N2进行充电，第二复位子电路122可以响应于第一复位端RST1提供的输入信号对上拉节点PU进行充电，第二节点放电子电路123可以在第二节点N2的电平的控制下对第二节点N2放电，例如，在第一复位端RST1提供的输入信号由高电平变为低电平时，第二节点N2通过耦合作用放电，例如，在后续的阶段中，在第一复位端RST1提供的输入信号保持低电平时，由于第二电压端VBD保持输入高电平，第一复位子电路121的晶体管存在负向偏移风险，第二节点N2的电位可能会被充电至 高电平，在这种情形下，第二节点N2也可以通过第二节点放电子电路123和第一复位端RST1放电至低电平，以使第二复位子电路122中的晶体管维持零偏压状态，从而消除阈值电压偏移风险，防止上拉节点PU形成漏电通路，以避免GOA电路切换扫描方向后无输出的现象。
例如，移位寄存器单元还可以包括第一控制电路、第一控制节点降噪电路和输出降噪电路。图4A为本公开一实施例提供的另一种移位寄存器单元的示意图。如图4A所示，在图1所示的示例的基础上，该移位寄存器单元100还可以包括第一下拉节点控制电路140、上拉节点降噪电路150和输出降噪电路160，其他结构与图1中所示的移位寄存器单元100类似，在此不再赘述。需要注意的是，本公开实施例中的第一下拉节点控制电路140为第一控制电路的一个示例，上拉节点降噪电路150为第一控制节点降噪电路的一个示例，下面以第一下拉节点控制电路140为第一控制电路、上拉节点降噪电路150为第一控制节点降噪电路为例进行说明，但是本公开的实施例不限于此，以下实施例与此相同，不再赘述。
第一下拉节点控制电路140配置为在上拉节点PU的电平的控制下，对第二控制节点PD(例如，下拉节点)的电平进行控制。例如，第一下拉节点控制电路140连接第三电压端VGH、第四电压端VGL、上拉节点PU和第二控制节点PD，以在上拉节点PU的电平的控制下，使第二控制节点PD和第四电压端VGL电连接，从而对第二控制节点PD的电平进行下拉控制，使其处于低电平。同时，第一下拉节点控制电路140可以在第三电压端VGH提供的第三电压的控制下，使第二控制节点PD和第三电压端电连接，从而在对第二控制节点PD进行充电。需要说明的是，第三电压端VGH例如可以配置为保持输入直流高电平信号，例如，将该直流高电平信号称为第三电压，第四电压端VGL例如可以配置为保持输入直流低电平信号，例如，将该直流低电平信号称为第四电压，第四电压低于第三电压，例如，第三电压和第一电压相同，第四电压和第二电压相同，以下各实施例与此相同，不再赘述。
需要注意的是，本公开实施例中的第二控制节点包括下拉节点，下面以下拉节点为第二控制节点为例进行说明，但是本公开的实施例不限于此，以下实施例与此相同，不再赘述。
上拉节点降噪电路150配置为在下拉节点PD的电平的控制下，对上拉 节点PU进行降噪。例如，上拉节点降噪电路150配置为和第四电压端VGL、上拉节点PU和下拉节点PD连接，以在下拉节点PD的电平的控制下，使上拉节点PU和第四电压端VGL电连接，从而对上拉节点PU进行下拉降噪。
输出降噪电路160配置为在下拉节点PD的电平的控制下，对输出端OUT进行降噪。例如，输出降噪电路160配置为和第四电压端VGL、输出端OUT和下拉节点PD连接，以在下拉节点PD的电平的控制下，使输出端OUT和第四电压端VGL电连接，从而对输出端OUT进行下拉降噪。
需要说明的是，在该实施例中，输入电路110与第一电压端VFD连接，第一上拉节点复位电路120与第二电压端VBD连接。例如，第一电压端VFD和第二电压端VBD的输出信号可以根据需求在高电平和低电平之间切换。例如，在输入电路110的输入端INT提供输入信号，第一上拉节点复位电路120的第一复位端RST1提供第一复位信号时，第一电压端VFD可以配置为保持输入直流高电平信号，第二电压端VBD可以配置为保持输入直流低电平信号；在输入电路110的输入端INT提供第一复位信号，第一上拉节点复位电路120的第一复位端RST1提供输入信号时，第一电压端VFD可以切换为保持输入直流低电平信号，第二电压端VBD可以切换为保持输入直流高电平信号。以下各实施例与此相同，不再赘述。
例如，图4A中所示的移位寄存器单元100在一个示例中可以具体实现为图4B所示的电路结构。在下面的说明中以各晶体管为N型晶体管为例进行说明，但并不构成对本公开实施例的限制。如图4B所示，该移位寄存器单元100包括第一晶体管至第十一晶体管T1-T11以及还包括第一存储电容C1。
例如，输入电路110包括第一输入子电路111、第二输入子电路112和第一节点放电子电路113。如图4B所示，第一输入子电路111可以实现为第一晶体管T1。第一晶体管T1的栅极配置为和输入端INT连接以接收输入信号，第一晶体管T1的第一极配置为和第一电压端VFD连接以接收第一电压，第一晶体管T1的第二极配置为和第一节点N1连接，从而当第一晶体管T1由于输入端INT接收到的导通信号(高电平信号)导通时，使用第一电压端VFD提供的第一电压以对第一节点N1进行充电，使其处于第一电平，即高电平。第二输入子电路112可以实现为第二晶体管T2。第二晶体管T2的栅 极配置为和输入端INT连接以接收输入信号，第二晶体管T2的第一极配置为和第一节点N1连接，第二晶体管T2的第二极配置为和上拉节点PU连接，从而当第二晶体管T2由于输入端INT接收到的导通信号(高电平信号)导通时，使用第一节点N1的高电平以对上拉节点PU进行充电，使其处于第一电平，即高电平。第一节点放电子电路113可以实现为第三晶体管T3。第三晶体管T3的栅极和第一极彼此电连接，且配置为都和第一节点N1连接，第三晶体管T3的第二极和第二控制路径(例如，放电路径)连接。例如，该放电路径例如为输入端。例如，当输入端INT提供的输入信号由高电平变为低电平时，第一节点N1的电位因为耦合作用而降低，例如因为晶体管的寄生电容耦合作用而降低。例如，在后续的阶段中，在输入端INT提供的输入信号保持低电平时，由于第一电压端VFD保持输入高电平，第一晶体管T1存在负向偏移风险，第一节点N1的电位可能会被充电至高电平，在这种情形下，第三晶体管T3由于第一节点N1的导通电平(高电平)导通，使第一节点N1的高电平通过输入端INT进行放电，使其处于低电平，这样可以使第二晶体管T2在后续阶段维持在零偏压状态(第一极和第二极均为低电平)，从而消除阈值电压的偏移风险，防止上拉节点PU形成漏电通路。
当输入端INT提供的输入信号为有效电平(例如，高电平)时，第一晶体管T1和第二晶体管T2均导通，以使第一电压端VFD的第一电压对第一节点N1和上拉节点PU进行充电，使其处于第一电平，即高电平。例如，第一电压端VFD此时配置为保持输入直流高电平信号。充电结束后，当输入端提供的输入信号由有效电平变为无效电平(例如，低电平)时，第一节点N1的电平因耦合作用而变低，同时，在后续的阶段中，输入端INT保持提供低电平信号，由于第一电压端VFD保持输入高电平，第一晶体管T1存在负向偏移风险，第一节点N1的电位可能会被充电至高电平，在这种情形下，第三晶体管T3导通，从而将第一节点N1和输入端INT电连接，以对第一节点N1进行放电，将其控制在第二电平，即低电平。这样可以使第二晶体管T2维持零偏压状态，从而消除阈值电压偏移风险，防止上拉节点PU形成漏电通路，以避免GOA电路切换扫描方向后无输出的现象。
例如，第一上拉节点复位电路120包括第一复位子电路121、第二复位子电路122和第二节点放电子电路123。如图4B所示，第一复位子电路121 可以实现为第四晶体管T4。第四晶体管T4的栅极配置为和第一复位端RST1连接以接收第一复位信号，第四晶体管T4的第一极配置为和第二电压端VBD连接以接收第二电压，第四晶体管T4的第二极配置为和第二节点N2连接。第二复位子电路122可以实现为第五晶体管T5。第五晶体管T5的栅极配置为和第一复位端RST1连接以接收第一复位信号，第五晶体管T5的第一极配置为和第二节点N2连接，第五晶体管T5的第二极配置为和上拉节点PU连接。第二节点放电子电路123可以实现为第六晶体管T6。第六晶体管T6的栅极和第一极彼此电连接，且配置为都和第二节点N2连接，第六晶体管T6的第二极和第一复位端RST1连接。
当第一复位端RST1提供的第一复位信号为有效电平时，第四晶体管T4和第五晶体管T5均导通，以使上拉节点PU和第二电压端VBD电连接，从而可以对上拉节点PU进行复位，使其从高电平下降至低电平。例如，第二电压端VBD此时配置为保持输入直流低电平信号。当进行反向扫描时，第一复位端RST1提供输入信号，第二电压端VBD切换为提供直流高电平信号，以对第二节点N2和上拉节点PU进行充电。充电结束后，第一复位端的输入信号由有效电平变为无效电平，第二节点N2的电平因耦合作用而变低，同时，在后续的阶段中，第一复位端RST1保持提供低电平信号，由于第二电压端VBD保持输入高电平，第四晶体管T4存在负向偏移风险，第二节点N2的电位可能会被充电至高电平，在这种情形下，第六晶体管T6在第二节点N2的电平的控制下导通，从而将第二节点N2和第一复位端RST1电连接，以对第二节点N2进行放电，将其控制在第二电平，即低电平。这样可以使第五晶体管T5维持零偏压状态，从而消除阈值电压偏移风险，防止上拉节点PU形成漏电通路，以避免GOA电路切换扫描方向后无输出的现象。
输出电路130可以实现为第七晶体管T7和第一存储电容C1。第七晶体管T7的栅极配置为和上拉节点PU连接，第七晶体管T7的第一极配置为和时钟信号端CLK连接以接收时钟信号，第七晶体管T7的第二极配置为和输出端OUT连接。第一存储电容C1的第一极配置为和第七晶体管T7的栅极连接，第一存储电容C1的第二极配置为和第七晶体管T7的第二极连接。当上拉节点PU的电平为有效电平时，第七晶体管T7导通，从而将时钟信号输出至输出端OUT；第一存储电容C1具有自举作用，有利于更好地将时钟信 号中的高电平输出。
第一下拉节点控制电路140可以实现为第八晶体管T8和第九晶体管T9。第八晶体管T8的栅极和第一极彼此电连接，且配置为都和第三电压端VGH连接以接收第三电压，第八晶体管T8的第二极和下拉节点PD连接。第九晶体管T9的栅极和上拉节点PU连接，第九晶体管T9的第一极和下拉节点PD连接，第九晶体管T9的第二极和第四电压端VGL连接以接收第四电压。
例如，第八晶体管T8响应于第三电压端VGH提供的第三电压而始终处于导通状态，且在第九晶体管T9截止时，将上拉节点PU的电平控制在第三电压，即高电平。设计第九晶体管T9与第八晶体管T8的参数(包括沟道宽长比或导通电阻)，使得在第九晶体管T9在上拉节点PU的电平的控制下导通时，能够将下拉节点PD的电压下拉至第四电压，以下实施例与此相同，不再赘述。
上拉节点降噪电路150可以实现为第十晶体管T10。第十晶体管T10的栅极和下拉节点PD连接，第十晶体管T10的第一极和上拉节点PU连接，第十晶体管T10的第二极和第四电压端VGL连接以接收第四电压。第十晶体管T10在下拉节点PD处于有效电平时导通，将上拉节点PU和第四电压端VGL电连接，从而可以对上拉节点PU下拉至第四电压以实现降噪。
输出降噪电路160可以实现为第第十一晶体管T11。第十一晶体管T11的栅极和下拉节点PD连接，第十一晶体管T11的第一极和输出端OUT连接，第十一晶体管T11的第二极和第四电压端VGL连接以接收第四电压。第十一晶体管T11在下拉节点PD处于有效电平时导通，将输出端OUT和第四电压端VGL电连接，从而可以对输出端OUT降噪。
例如，该移位寄存器单元还可以包括第二复位电路。图5A为本公开一实施例提供的另一种移位寄存器单元的示意图。如图5A所示，在图4A所示的示例的基础上，移位寄存器单元100还可以包括第二上拉节点复位电路170，其他结构与图4A中所示的移位寄存器单元100类似，在此不再赘述。需要注意的是，本公开实施例中的第二上拉节点复位电路170为第二复位电路的一个示例，下面以第二复位电路为第二上拉节点复位电路170为例进行说明，但是本公开的实施例不限于此，以下实施例与此相同，不再赘述。
第二上拉节点复位电路170配置为响应于第二复位信号对上拉节点PU 进行复位。例如，第二上拉节点复位电路170和第二复位端RST2、上拉节点PU以及第四电压端VGL连接，以在第二复位端RST2提供的第二复位信号的控制下使上拉节点PU和第四电压端VGL电连接，从而可以对上拉节点PU进行复位。例如，该第二复位信号为总复位信号，第二上拉节点复位电路170可以在一帧图像扫描结束后在该第二复位信号的控制下对所有级联的移位寄存器单元的上拉节点PU进行复位。
例如，图5A中所示的移位寄存器单元100在一个示例中可以具体实现为图5B所示的电路结构。如图5B所示，该实施例中的移位寄存器单元100和图4B中描述的移位寄存器单元100类似，区别在于还包括第十二晶体管T12。
在该实施例中，第二上拉节点复位电路170可以实现为第十二晶体管T12。第十二晶体管T12的栅极和第二复位端RST2连接以接收第二复位信号，第十二晶体管T2的第一极和上拉节点PU连接，第十二晶体管T12的第二极和第四电压端VGL连接以接收第四电压。第十二晶体管T12在第二复位信号为有效电平(例如高电平)时而导通，将上拉节点PU和第四电压端VGL电连接，从而可以对上拉节点PU进行复位。
例如，该移位寄存器单元还包括第二控制电路。图6A为本公开一实施例提供的另一种移位寄存器单元的示意图。如图6A所示，在图5A所示的示例的基础上，移位寄存器单元100还可以包括第二下拉节点控制电路180，其他结构与图5A中所示的移位寄存器单元100类似，在此不再赘述。需要注意的是，本公开实施例中的第二下拉节点控制电路180为第二控制电路的一个示例下面以第二控制电路为第二下拉节点控制电路180为例进行说明，但是本公开的实施例不限于此，以下实施例与此相同，不再赘述。
第二下拉节点控制电路180配置为响应于输入信号对下拉节点PD进行第二控制。例如，第二下拉节点控制电路180和输入端INT、第一复位端RST1、下拉节点PD以及第四电压端VGL连接，以在输入端INT输入的输入信号(正向扫描时)或第一复位端RST1提供的输入信号(反向扫描时)的控制下使下拉节点PD和第四电压端VGL电连接，从而可以在输入阶段对下拉节点PD进行放电(例如，放电至第二电平)，从而充分保证了上拉节点在充电过程中不受下拉节点PD的影响。
例如，图6A中所示的移位寄存器单元100在一个示例中可以具体实现为图6B所示的电路结构。如图6B所示，该实施例中的移位寄存器单元100和图5B中描述的移位寄存器单元100的结构类似，区别在于还包括第十三晶体管T13和第十四晶体管T14。
在该实施例中，第二下拉节点控制电路180可以实现为第十三晶体管T13和第十四晶体管T14。第十三晶体管T13的栅极和输入端INT连接以接收输入信号，第十三晶体管T13的第一极和下拉节点PD连接，第十三晶体管T13的第二极和第四电压端VGL连接以接收第四电压。第十四晶体管T14的栅极和第一复位端RST1连接以接收第一复位信号，第十四晶体管T14的第一极和和下拉节点PD连接，第十四晶体管T14的第二极和第四电压端VGL连接以接收第四电压。
例如，在正向扫描时，第十三晶体管T13在输入端INT提供的输入信号为有效电平时而导通，将下拉节点PD和第四电压端VGL电连接，从而可以对下拉节点PD进行放电；第十四晶体管T14在第一复位端RST1提供的第一复位信号为有效电平时而导通，将下拉节点PD和第四电压端VGL电连接，从而可以对下拉节点PD进行放电。例如，在反向扫描时，第十四晶体管T14在第一复位端RST1提供的输入信号为有效电平时而导通，将下拉节点PD和第四电压端VGL电连接，从而可以对下拉节点PD进行放电；第十三晶体管T13在输入端INT提供的第一复位信号为有效电平时而导通，将下拉节点PD和第四电压端VGL电连接，从而可以对下拉节点PD进行放电。
需要注意的是，在本公开的各个实施例的说明中，上拉节点PU、下拉节点PD、第一节点N1和第二节点N2并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，在本公开的实施例中的晶体管均以N型晶体管为例进行说明，此 时，晶体管的第一极是漏极，第二极是源极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的移位寄存器单元100中的一个或多个晶体管也可以采用P型晶体管，此时，晶体管第一极是源极，第二极是漏极，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接即可。当采用N型晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
在本公开的实施例中，例如，当各个电路实现为N型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。又例如，当各个电路实现为P型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如截止)。
图7为本公开一实施例提供的一种移位寄存器单元在工作时的信号时序图。下面结合图7所示的信号时序图，对图6B所示的移位寄存器单元100的工作原理进行说明，并且这里以各个晶体管为N型晶体管为例进行说明，但是本公开的实施例不限于此。在图7所示的第一阶段1、第二阶段2、第三阶段3以及第四阶段4共四个阶段中，该移位寄存器单元100可以分别进行如下操作。
在第一阶段1(即输入阶段)，输入端INT提供高电平信号，第一电压端VFD配置为提供直流高电平信号，第一晶体管T1和第二晶体管T2响应于输入端INT提供的高电平信号而导通，第一节点N1和上拉节点PU被充电至第一电平；第七晶体管T7响应于上拉节点PU的第一电平导通，使得时钟信号端CLK和输出端OUT电连接，由于在此阶段，时钟信号端CLK提供的时钟信号为低电平，因此输出端OUT输出时钟信号的低电平；同时在 此阶段，第十三晶体管T13响应于输入信号的高电平而导通，第九晶体管T9响应于上拉节点PU的高电平而导通，使得下拉节点PD和第四电压端VGL连接，从而下拉节点PD被下拉至第四电压(即低电平)，因此在此阶段，下拉节点不会对上拉节点PU的充电过程造成影响，从而使得第九晶体管T9有较大的阈值电压偏移余量，对其工艺条件的要求宽松。
第二阶段2(即输出阶段)，时钟信号端提供高电平信号，因此，输出端OUT输出时钟信号的高电平；由于电容的自举效应，上拉节点PU被进一步充电至高电平(例如，高于第一电平)；第九晶体管T9在上拉节点PU的电平的控制下导通，使得下拉节点PD与第四电压端VGL连接，从而保持低电平；在此阶段，输入端INT提供的输入信号由第一阶段的高电平变为低电平，第一节点N1的电位因为耦合作用而降低，例如因为晶体管的寄生电容耦合作用而降低。同时，在后续的阶段中，在输入端INT提供的输入信号保持在低电平的情况下，由于第一电压端VFD保持输入高电平，第一晶体管T1存在负向偏移风险，第一节点N1的电位可能会被充电至高电平，在这种情形下，第一节点N1也可以通过第三晶体管T3和输入端INT放电至低电平，这样可以使第二晶体管T2在后续阶段维持在零偏压状态(第一极和第二极均为低电平)，从而消除阈值电压的偏移风险，防止形成上拉节点PU的漏电通路，因此，当该移位寄存器单元100由长时间正向扫描(即输入端INT提供输入信号，第一复位端RST1提供第一复位信号)切换为反向扫描时，即使第一晶体管T1的阈值电压因长时间与第一电压端VFD连接而受负偏压热应力(Negative Bias Thermal Stress,NBTS)发生负向偏移，但由于第二晶体管T2的阈值电压未偏移，因此避免了上拉节点PU在充电过程中出现漏电而造成的GOA电路切换扫描方向后无输出的现象。
在第三阶段3(即复位阶段)，第一复位端RST1提供高电平信号，第二电压端VBD配置为提供直流低电平信号，第四晶体管T4和第五晶体管T5响应于第一复位端RST1提供的高电平信号而导通，从而将上拉节点PU和第二电压端VBD连接，将上拉节点PU下拉至低电平；第十四晶体管T14响应于第一复位端RST1提供的高电平信号而导通，从而将下拉节点PD和第四电压端VGL连接，因此，在此阶段，下拉节点PD依然保持低电平；在此阶段，由于第七晶体管T7被上拉节点PU的低电平截止，从而使输出端 OUT输出低电平信号。
在第四阶段4(即总复位阶段)，在一帧扫描结束后下一帧开始前的间隔阶段，第二复位端RST2提供高电平信号，从而使得第十二晶体管T12导通，使得上拉节点PU和第四电压端VGL电连接，以对上拉节点PU进一步复位。
例如，该移位寄存器单元100进行反向扫描时，将输入信号和第一复位信号彼此交换即可，即输入端INT提供第一复位信号，而第一复位端RST1提供输入信号。此时，第一电压端VFD提供直流低电平信号，而第二电压端VBD提供直流高电平信号。反向扫描时，移位寄存器单元100的工作原理与正向扫描时类似，此处不再赘述。需要注意的是，在第一复位端RST1提供的输入信号由高电平变为低电平时，第二节点N2的电位因为耦合作用而降低，例如因为晶体管的寄生电容耦合作用而降低。同时，在反向扫描的后续的阶段中，第一复位端RST1提供的输入信号保持在低电平，由于第二电压端VBD保持输入高电平，第四晶体管T4存在负向偏移风险，第一节点N1的电位可能会被充电至高电平，在这种情形下，第二节点N2也可以通过第六晶体管T6和输入端INT放电至低电平，从而使第五晶体管T5在第一阶段1之后的各个阶段维持零偏压状态，从而消除阈值电压的偏移风险，防止上拉节点PU形成漏电通路。
本公开至少一实施例还提供一种栅极驱动电路。例如，如图8所示，该栅极驱动电路包括第一时钟信号线CLK1、第二时钟信号线CLK2、总复位线TT_RST和多个级联的移位寄存器单元100。移位寄存器单元可以采用本公开任一实施例所述的移位寄存器单元100。例如，这里以每个移位寄存器单元100采用如图6B所示电路结构为例进行说明，但是本公开的实施例不限于此。该栅极驱动电路10可以采用与薄膜晶体管同样制程的工艺直接集成在显示装置的阵列基板上，以实现逐行扫描驱动功能。
例如，如图8所示，该移位寄存器单元的每个还包括时钟信号端CLK，且配置为和第一时钟信号线CLK1或第二时钟信号线CLK2连接以接收第一时钟信号或第二时钟信号。第一时钟信号线CLK1和第2n-1(n为大于0的整数)级移位寄存器单元的时钟信号端CLK连接，第二时钟信号线CLK2和第2n级移位寄存器单元的时钟信号端CLK连接。需要说明的是，本公开 的实施例包括但不限于上述连接方式，例如还可以采用：第一时钟信号线CLK1和第2n(n为大于0的整数)级移位寄存器单元的时钟信号端CLK连接，第二时钟信号线CLK2和第2n-1级移位寄存器单元的时钟信号端CLK连接。
例如，如图8所示，该移位寄存器单元的每个还包括第二复位端RST2，且配置为和总复位线TT_RST连接以接收第二复位信号，以在每一帧扫描结束后，通过该总复位线TT_RST提供的第二复位信号对所有的移位寄存器单元的上拉节点进行复位。
例如，如图8所示，该栅极驱动电路10还可以包括时序控制器200。例如，该时序控制器200可以被配置为和第一时钟信号线CLK1、第二时钟信号线CLK2以及总复位线TT_RST连接，以向各移位寄存器单元提供时钟信号和第二复位信号。例如，时序控制器200还可以被配置为触发信号STV和复位信号RESET。
例如，如图8所示，除最后一级移位寄存器单元外，其余各级移位寄存器单元的第一复位端RST1和下一级移位寄存器单元的输出端OUT连接。除第一级移位寄存器单元外，其余各级移位寄存器单元的输入端INT和上一级移位寄存器单元的输出端OUT连接。例如，对于正向扫描，第一级移位寄存器单元的输入端INT可以被配置为接收触发信号STV，最后一级移位寄存器单元的第一复位端RST1可以被配置为接收复位信号RESET。对于反向扫描，第一级移位寄存器单元的输入端INT可以被配置为接收复位信号RESET，最后一级移位寄存器单元的第一复位端RST1可以被配置为接收触发信号STV。
需要注意的是，根据不同的配置，该栅极驱动电路10还可以包括四条、六条或八条时钟信号线，时钟信号线的条数视具体情况而定，本公开的实施例在此不作限定。
需要说明的是，当采用本公开的实施例提供的栅极驱动电路10驱动一显示面板时，可以将该栅极驱动电路10设置于显示面板的一侧。例如，该显示面板包括多行栅线，栅极驱动电路10中的各级移位寄存器单元的输出端可以配置为依序和该多行栅线连接，以用于输出栅极扫描信号。需要说明的是，还可以分别在显示面板的两侧设置该栅极驱动电路10，以实现双边驱动，本 公开的实施例对栅极驱动电路10的设置方式不作限定。例如，可以在显示面板的一侧设置栅极驱动电路10以用于驱动奇数行栅线，而在显示面板的另一侧设置栅极驱动电路10以用于驱动偶数行栅线。
该栅极驱动电路可以避免因为输入端的晶体管的阈值电压负偏导致的切换扫描方向后无输出的现象，增强了电路的稳定性，使晶体管具有较大的阈值电压偏移余量。
本公开的实施例还提供一种显示装置1，如图9所示，该显示装置1包括本公开实施例提供的栅极驱动电路10。该显示装置1包括由多个像素单元30构成的像素阵列。例如，该显示装置1还可以包括数据驱动电路20。数据驱动电路20用于提供数据信号给像素阵列；栅极驱动电路10用于提供栅极扫描信号给像素阵列。数据驱动电路20通过数据线21与像素单元30电连接，栅极驱动电路10通过栅线11与像素单元30电连接。
需要说明的是，本实施例中的显示装置1可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置1还可以包括显示面板等其他常规部件，本公开的实施例对此不作限定。
本公开的实施例提供的显示装置1的技术效果可以参考上述实施例中关于栅极驱动电路10的相应描述，这里不再赘述。
需要说明的是，为表示清楚、简洁，并没有给出该显示装置1的全部结构。为实现显示装置的必要功能，本领域技术人员可以根据具体应用场景进行设置其他未示出的结构，本公开的实施例对此不做限制。
本公开一实施例还提供一种驱动方法，例如用于显示装置的移位寄存器单元，例如，在图4B或图5B所示的示例中，该移位寄存器单元的驱动方法包括如下操作：
第一阶段，输入电路110响应于输入信号对上拉节点PU和第一节点N1进行第一控制(例如充电至第一电平)，输出电路130输出输出信号(例如，时钟信号)的低电平至输出端OUT；
第二阶段，输入电路110响应于第一节点N1的电平对第一节点N1进行第二控制(例如放电至第二电平)，输出电路130输出输出信号的高电平至输出端OUT；
第三阶段，第一上拉节点复位电路120在第一复位信号的控制下对上拉节点PU进行复位。
例如，在图6B所示的示例中，该移位寄存器单元的驱动方法包括如下操作：
第一阶段，输入电路110响应于输入信号对上拉节点PU和第一节点N1进行第一控制，第二下拉节点控制电路180响应于输入信号对下拉节点PD的电平进行第二控制，例如拉低至第二电平(例如，第四电压)，输出电路130输出输出信号的低电平至输出端OUT；
第二阶段，输入电路110响应于第一节点N1的第一电平对第一节点N1进行第二控制，输出电路130输出输出信号的高电平至输出端OUT；
第三阶段，第一上拉节点复位电路120在第一复位信号的控制下对上拉节点PU进行复位，第二下拉节点控制电路180响应于第一复位信号对下拉节点PD的电平进行第二控制。
例如，在另一个示例中，当采用该移位寄存器单元100的显示面板进行反向扫描时，可以将输入信号和第一复位信号彼此交换，即第一复位端RST1提供输入信号，而输入端INT提供第一复位信号。此时，该驱动方法包括如下操作：
第一阶段，第一上拉节点复位电路120响应于输入信号对上拉节点PU和第二节点N2进行第一控制，输出电路130输出输出信号的低电平至输出端OUT；
第二阶段，第一上拉节点复位电路120响应于第二节点N2的第一电平对第二节点N2进行第二控制，输出电路130输出输出信号的高电平至输出端OUT；
第三阶段，输入电路110在第一复位信号的控制下对上拉节点PU进行复位。
需要说明的是，关于该驱动方法的详细描述以及技术效果可以参考本公开的实施例中对于移位寄存器单元100的工作原理的描述，这里不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种移位寄存器单元，包括：输入电路、第一复位电路和输出电路；其中，
    所述输入电路包括输入端，配置为响应于所述输入端的输入信号对所述第一控制节点和第一节点进行第一控制，以及之后在所述第一节点的控制下对所述第一节点进行不同于所述第一控制的第二控制，所述第一节点位于所述输入信号对所述第一控制节点进行所述第一控制的路径中；
    所述第一复位电路配置为响应于第一复位信号对所述第一控制节点进行复位；
    所述输出电路配置为在所述第一控制节点的电平的控制下，将输出信号输出至输出端。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述输入电路包括第一输入子电路、第二输入子电路和第一节点放电子电路；
    所述第一输入子电路配置为响应于所述输入信号对所述第一节点进行所述第一控制；
    所述第二输入子电路配置为响应于所述输入信号将对所述第一控制节点的进行所述第一控制；
    所述第一节点放电子电路配置为在所述第一节点的电平的控制下可对所述第一节点进行所述第二控制。
  3. 根据权利要求2所述移位寄存器单元，其中，
    所述第一输入子电路包括：
    第一晶体管，其中，所述第一晶体管的栅极和所述输入端连接以接收所述输入信号，所述第一晶体管的第一极和第一电压端连接以接收第一电压，所述第一晶体管的第二极和所述第一节点连接；
    所述第二输入子电路包括：
    第二晶体管，其中，所述第二晶体管的栅极和所述输入端连接以接收所述输入信号，所述第二晶体管的第一极和所述第一节点连接，所述第二晶体管的第二极和所述第一控制节点连接；
    所述第一节点放电子电路包括：
    第三晶体管，其中，所述第三晶体管的栅极和第一极彼此电连接，且配置为都和所述第一节点连接，所述第三晶体管的第二极和第二控制路径连接。
  4. 根据权利要求3所述移位寄存器单元，其中，所述第二控制路径为所述输入端。
  5. 根据权利要求1所述移位寄存器单元，其中，所述第一复位电路与所述输入电路对称设置，其中所述第一复位电路包括第一复位端，配置为在所述第一复位端的第一复位信号以及第二节点的电平的控制下可对所述第二节点进行所述第二控制，所述第二节点位于所述第一复位信号对所述第一控制节点进行所述第二控制的路径中。
  6. 根据权利要求5所述的移位寄存器单元，其中，所述第一复位电路包括第一复位子电路、第二复位子电路和第二节点放电子电路；其中，
    所述第一复位子电路配置为响应于所述第一复位信号对所述第二节点进行复位；
    所述第二复位子电路配置为响应于所述第一复位信号将所述第一控制节点进行复位；
    所述第二节点放电子电路配置为在所述第二节点的电平的控制下对所述第二节点进行所述第二控制。
  7. 根据权利要求6所述的移位寄存器单元，其中，
    所述第一复位子电路包括：
    第四晶体管，其中，所述第四晶体管的栅极和所述第一复位端连接以接收所述第一复位信号，所述第四晶体管的第一极和第二电压端连接以接收第二电压，所述第四晶体管的第二极和所述第二节点连接；
    所述第二复位子电路包括：
    第五晶体管，其中，所述第五晶体管的栅极和所述第一复位端连接以接收所述第一复位信号，所述第五晶体管的第一极和所述第二节点连接，所述第五晶体管的第二极和所述第一控制节点连接；
    所述第二节点放电子电路包括：
    第六晶体管，其中，所述第六晶体管的栅极和第一极彼此电连接，且配置为都和所述第二节点连接，所述第六晶体管的第二极和所述第一复位端连接。
  8. 根据权利要求1-7任一所述的移位寄存器单元，其中，所述输出电路包括：
    第七晶体管，其中，所述第七晶体管的栅极和所述第一控制节点连接，所述第七晶体管的第一极和时钟信号端连接以接收时钟信号作为所述输出信号，所述第七晶体管的第二极和所述输出端连接；
    第一存储电容，其中，所述第一存储电容的第一极和所述第一控制节点连接，所述第一存储电容的第二极和所述输出端连接。
  9. 根据权利要求1-7任一所述的移位寄存器单元，还包括第一控制电路、第一控制节点降噪电路和输出降噪电路；其中，
    所述第一控制电路配置为对第二控制节点的电平进行控制；
    所述第一控制节点降噪电路配置为在所述第二控制节点的电平的控制下，对所述第一控制节点进行降噪；
    所述输出降噪电路配置为在所述第二控制节点的电平的控制下，对所述输出端进行降噪。
  10. 根据权利要求9所述的移位寄存器单元，其中，
    所述第一控制电路包括：
    第八晶体管，其中，所述第八晶体管的栅极和第一极彼此电连接，且配置为都和第三电压端连接以接收第三电压，所述第八晶体管的第二极和所述第二控制节点连接；
    第九晶体管，其中，所述第九晶体管的栅极和所述第一控制节点连接，所述第九晶体管的第一极和所述第二控制节点连接，所述第九晶体管的第二极和第四电压端连接以接收第四电压；
    所述第一控制节点降噪电路包括：
    第十晶体管，其中，所述第十晶体管的栅极和所述第二控制节点连接，所述第十晶体管的第一极和所述第一控制节点连接，所述第十晶体管的第二极和所述第四电压端连接以接收所述第四电压；
    所述输出降噪电路包括：
    第十一晶体管，其中，所述第十一晶体管的栅极和所述第二控制节点连接，所述第十一晶体管的第一极和所述输出端连接，所述第十一晶体管的第二极和所述第四电压端连接以接收所述第四电压。
  11. 根据权利要求1-7任一所述的移位寄存器单元，还包括第二复位电路，其中，所述第二复位电路配置为响应于第二复位信号对所述第一控制节点进行复位。
  12. 根据权利要求11所述的移位寄存器单元，其中，所述第二复位电路包括：
    第十二晶体管，其中，所述第十二晶体管的栅极和第二复位端连接以接收所述第二复位信号，所述第十二晶体管的第一极和所述第一控制节点连接，所述第十二晶体管的第二极和第四电压端连接以接收第四电压。
  13. 根据权利要求1-7任一所述的移位寄存器单元，还包括第二控制电路，其中，所述第二控制电路配置为响应于所述输入信号对第二控制节点进行所述第二控制。
  14. 根据权利要求13所述的移位寄存器单元，其中，所述第二控制电路包括：
    第十三晶体管，其中，所述第十三晶体管的栅极和所述输入端连接以接收所述输入信号，所述第十三晶体管的第一极和所述第二控制节点连接，所述第十三晶体管的第二极和第四电压端连接以接收第四电压；
    第十四晶体管，其中，所述第十四晶体管的栅极和第一复位端连接以接收所述第一复位信号，所述第十四晶体管的第一极和所述第二控制节点连接，所述第十四晶体管的第二极和所述第四电压端连接以接收所述第四电压。
  15. 一种栅极驱动电路，包括如权利要求1-14任一所述的移位寄存器单元。
  16. 一种显示装置，包括如权利要求15所述的栅极驱动电路。
  17. 一种如权利要求1-14任一所述的移位寄存器单元的驱动方法，包括：
    第一阶段，所述输入电路响应于所述输入信号对所述第一控制节点和所述第一节点进行所述第一控制，所述输出电路输出所述输出信号的低电平至所述输出端；
    第二阶段，所述输入电路响应于所述第一节点的电平对所述第一节点进行所述第二控制，所述输出电路输出所述输出信号的高电平至所述输出端；
    第三阶段，所述第一复位电路在所述第一复位信号的控制下对所述第一控制节点进行复位。
  18. 一种如权利要求5所述的移位寄存器单元的驱动方法，其中，将所述输入信号和所述第一复位信号彼此交换，所述驱动方法包括：
    第一阶段，所述第一复位电路响应于所述输入信号将所述第一控制节点和所述第二节点进行所述第一控制，所述输出电路输出所述输出信号的低电平至所述输出端；
    第二阶段，所述第一复位电路响应于所述第二节点的电平对所述第二节点进行所述第二控制，所述输出电路输出所述输出信号的高电平至所述输出端；
    第三阶段，所述输入电路在所述第一复位信号的控制下对所述第一控制节点进行复位。
  19. 一种如权利要求13所述的移位寄存器单元的驱动方法，包括：
    第一阶段，所述输入电路响应于所述输入信号对所述第一控制节点和所述第一节点进行所述第一控制，所述第二控制电路响应于所述输入信号将所述第二控制节点的电平进行所述第二控制，所述输出电路输出所述输出信号的低电平至所述输出端；
    第二阶段，所述输入电路响应于所述第一节点的电平对所述第一节点进行所述第二控制，所述输出电路输出所述输出信号的高电平至所述输出端；
    第三阶段，所述第一复位电路在所述第一复位信号的控制下对所述第一控制节点进行复位，所述第二控制电路响应于所述第一复位信号对所述第二控制节点的电平进行所述第二控制。
PCT/CN2018/113975 2018-03-30 2018-11-05 移位寄存器单元及驱动方法、栅极驱动电路及显示装置 WO2019184354A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2019546340A JP7264820B2 (ja) 2018-03-30 2018-11-05 シフトレジスタユニット及び駆動方法、ゲート駆動回路及び表示装置
EP18904492.8A EP3779956A4 (en) 2018-03-30 2018-11-05 OFFSET REGISTER UNIT AND CONTROL PROCESS, GRILLE CONTROL CIRCUIT AND DISPLAY DEVICE
KR1020197025793A KR102315250B1 (ko) 2018-03-30 2018-11-05 시프트 레지스터 유닛 및 그 구동 방법, 게이트 구동 회로 및 디스플레이 디바이스
US16/461,818 US11100878B2 (en) 2018-03-30 2018-11-05 Shift register unit and driving method thereof, gate drive circuit and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810290682.2 2018-03-30
CN201810290682.2A CN108648705B (zh) 2018-03-30 2018-03-30 移位寄存器单元及驱动方法、栅极驱动电路及显示装置

Publications (1)

Publication Number Publication Date
WO2019184354A1 true WO2019184354A1 (zh) 2019-10-03

Family

ID=63745602

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/113975 WO2019184354A1 (zh) 2018-03-30 2018-11-05 移位寄存器单元及驱动方法、栅极驱动电路及显示装置

Country Status (6)

Country Link
US (1) US11100878B2 (zh)
EP (1) EP3779956A4 (zh)
JP (1) JP7264820B2 (zh)
KR (1) KR102315250B1 (zh)
CN (1) CN108648705B (zh)
WO (1) WO2019184354A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021099488A (ja) * 2019-12-23 2021-07-01 シェンジェン ロイオル テクノロジーズ カンパニー リミテッドＳｈｅｎｚｈｅｎ Ｒｏｙｏｌｅ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｃｏ．， Ｌｔｄ． 画素走査駆動回路、アレイ基板及び表示端末

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108648705B (zh) * 2018-03-30 2020-03-27 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路及显示装置
EP3882901B1 (en) * 2018-11-14 2024-07-24 BOE Technology Group Co., Ltd. Shift register unit, drive method, gate drive circuit, and display device
CN208938619U (zh) * 2018-11-26 2019-06-04 北京京东方技术开发有限公司 移位寄存器单元、栅极驱动电路和显示装置
CN109599144B (zh) * 2018-11-29 2020-12-11 合肥鑫晟光电科技有限公司 移位寄存单元、栅极驱动电路、显示装置及驱动方法
CN109658888B (zh) 2019-01-02 2022-01-14 合肥京东方光电科技有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN109727568B (zh) * 2019-03-11 2022-05-06 合肥鑫晟光电科技有限公司 栅极驱动单元及方法、栅极驱动电路和显示装置
KR20210028774A (ko) * 2019-09-04 2021-03-15 삼성디스플레이 주식회사 스캔 드라이버 및 표시 장치
EP4047591A4 (en) * 2019-10-18 2022-10-26 BOE Technology Group Co., Ltd. SLIDER REGISTER UNIT, DRIVE METHOD, GATE DRIVER CIRCUIT AND DISPLAY DEVICE
CN111243547B (zh) * 2020-03-18 2021-06-01 Tcl华星光电技术有限公司 Goa电路及显示面板
CN111540328B (zh) * 2020-05-25 2021-03-16 武汉华星光电技术有限公司 Goa电路及显示面板
KR20220037659A (ko) * 2020-09-18 2022-03-25 엘지디스플레이 주식회사 게이트 드라이버를 갖는 디스플레이 장치
CN115394232A (zh) * 2022-09-28 2022-11-25 信利(仁寿)高端显示科技有限公司 一种栅极扫描电路及方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6426743B1 (en) * 1999-02-09 2002-07-30 Lg. Philips Lcd Co., Ltd Shift register
CN101242178A (zh) * 2007-02-07 2008-08-13 三菱电机株式会社 半导体装置以及移位寄存器电路
CN101546607A (zh) * 2008-03-26 2009-09-30 北京京东方光电科技有限公司 移位寄存器及液晶显示器栅极驱动装置
CN103489484A (zh) * 2013-09-22 2014-01-01 京东方科技集团股份有限公司 一种移位寄存器单元及栅极驱动电路
CN104332182A (zh) * 2014-10-03 2015-02-04 友达光电股份有限公司 移位寄存装置
CN104332181A (zh) * 2014-11-03 2015-02-04 合肥鑫晟光电科技有限公司 一种移位寄存器及栅极驱动装置
CN106531117A (zh) * 2017-01-05 2017-03-22 京东方科技集团股份有限公司 移位寄存器、其驱动方法、栅极集成驱动电路及显示装置
CN107657983A (zh) * 2017-11-09 2018-02-02 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN108648705A (zh) * 2018-03-30 2018-10-12 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路及显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101217177B1 (ko) * 2006-06-21 2012-12-31 삼성디스플레이 주식회사 게이트 구동회로 및 이를 갖는 표시 장치
CN101515431B (zh) * 2008-02-22 2011-01-19 财团法人工业技术研究院 栅极驱动器用的平移寄存器
CN102842278B (zh) * 2012-08-06 2015-09-02 北京大学深圳研究生院 栅极驱动电路单元、栅极驱动电路及显示器
CN203644373U (zh) * 2013-12-05 2014-06-11 华南理工大学 栅极驱动单元及栅极扫描驱动器
CN107274856A (zh) * 2017-08-22 2017-10-20 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路
KR102381884B1 (ko) * 2017-10-18 2022-03-31 엘지디스플레이 주식회사 디스플레이 장치
CN108877721B (zh) * 2018-07-26 2020-07-24 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置以及驱动方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6426743B1 (en) * 1999-02-09 2002-07-30 Lg. Philips Lcd Co., Ltd Shift register
CN101242178A (zh) * 2007-02-07 2008-08-13 三菱电机株式会社 半导体装置以及移位寄存器电路
CN101546607A (zh) * 2008-03-26 2009-09-30 北京京东方光电科技有限公司 移位寄存器及液晶显示器栅极驱动装置
CN103489484A (zh) * 2013-09-22 2014-01-01 京东方科技集团股份有限公司 一种移位寄存器单元及栅极驱动电路
CN104332182A (zh) * 2014-10-03 2015-02-04 友达光电股份有限公司 移位寄存装置
CN104332181A (zh) * 2014-11-03 2015-02-04 合肥鑫晟光电科技有限公司 一种移位寄存器及栅极驱动装置
CN106531117A (zh) * 2017-01-05 2017-03-22 京东方科技集团股份有限公司 移位寄存器、其驱动方法、栅极集成驱动电路及显示装置
CN107657983A (zh) * 2017-11-09 2018-02-02 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN108648705A (zh) * 2018-03-30 2018-10-12 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路及显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3779956A4

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021099488A (ja) * 2019-12-23 2021-07-01 シェンジェン ロイオル テクノロジーズ カンパニー リミテッドＳｈｅｎｚｈｅｎ Ｒｏｙｏｌｅ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｃｏ．， Ｌｔｄ． 画素走査駆動回路、アレイ基板及び表示端末

Also Published As

Publication number Publication date
JP2021516839A (ja) 2021-07-08
US11100878B2 (en) 2021-08-24
EP3779956A1 (en) 2021-02-17
EP3779956A4 (en) 2021-11-10
CN108648705A (zh) 2018-10-12
KR102315250B1 (ko) 2021-10-20
JP7264820B2 (ja) 2023-04-25
KR20190115041A (ko) 2019-10-10
US20200273419A1 (en) 2020-08-27
CN108648705B (zh) 2020-03-27

Similar Documents

Publication Publication Date Title
WO2019184354A1 (zh) 移位寄存器单元及驱动方法、栅极驱动电路及显示装置
JP7282677B2 (ja) シフトレジスタユニット、ゲート駆動回路、表示装置及び駆動方法
US11302276B2 (en) Gate drive circuit, touch display device and driving method
US10770163B2 (en) Shift register unit, method of driving shift register unit, gate driving circuit and display device
EP3611720B1 (en) Shift register unit, gate driving circuit, and driving method
US11315471B2 (en) Shift register unit, driving device, display device and driving method
WO2018209937A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2020015569A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
US11227524B2 (en) Shift register unit and driving method thereof, gate driving circuit and driving method thereof, and display device
US10431143B2 (en) Shift register, driving method thereof, gate driving circuit and display device
EP3217387A1 (en) Shift register unit, gate driving circuit and display device
WO2018209938A1 (zh) 移位寄存器单元、栅极驱动电路、显示器以及栅极驱动方法
US9928922B2 (en) Shift register and method for driving the same, gate driving circuit and display device
WO2020093796A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路和显示装置
WO2019218625A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
US11094389B2 (en) Shift register unit and driving method, gate driving circuit, and display device
WO2019056803A1 (zh) 移位寄存器单元、栅极驱动电路、显示装置以及驱动方法
EP3882901B1 (en) Shift register unit, drive method, gate drive circuit, and display device
WO2021072750A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
WO2021081703A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
CN118974816A (zh) 显示基板和显示装置
CN111696490A (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2019546340

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 20197025793

Country of ref document: KR

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18904492

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2018904492

Country of ref document: EP