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WO2018216661A1 - Power supply device and electronic device - Google Patents

Power supply device and electronic device Download PDF

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Publication number
WO2018216661A1
WO2018216661A1 PCT/JP2018/019540 JP2018019540W WO2018216661A1 WO 2018216661 A1 WO2018216661 A1 WO 2018216661A1 JP 2018019540 W JP2018019540 W JP 2018019540W WO 2018216661 A1 WO2018216661 A1 WO 2018216661A1
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Prior art keywords
voltage
detection circuit
output
control circuit
input voltage
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PCT/JP2018/019540
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French (fr)
Japanese (ja)
Inventor
昌弘 竹田
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シャープ株式会社
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Publication of WO2018216661A1 publication Critical patent/WO2018216661A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

Definitions

  • the present invention relates to a power supply device including a PMIC (Power Management IC) that acquires a voltage from a power source and distributes the voltage to each member of an electronic device.
  • PMIC Power Management IC
  • PMIC Power Management IC
  • An electronic device can distribute an appropriate voltage to each member by mounting the PMIC.
  • the output OFF control circuit 212 stops voltage generation in the voltage generation unit 214, and
  • the output ON control circuit 213 generates voltage in the voltage generation unit 214 and outputs the output voltage Vout.
  • Japanese Patent Publication Japanese Patent Laid-Open No. 2016-154384 (published on August 25, 2016)”
  • the power of the electronic device when the power of the electronic device is turned off, the power is turned off based on the OFF sequence determined for each member of the electronic device by the output OFF control circuit 212 described above.
  • An object of one embodiment of the present invention is to realize a power supply device that does not cause a malfunction in which the PMIC is turned on again when the power is turned off.
  • a power supply device generates a voltage of various power supplies, outputs a generated voltage, and reduces a voltage output from the power control circuit.
  • a voltage drop detection circuit that detects and transmits a signal indicating a drop in the detected output voltage to the power control circuit, and the power control circuit receives the signal from the voltage drop detection circuit, The generation operation is stopped.
  • FIG. 3 is a waveform diagram of input / output voltages when the power is turned off in the PMIC shown in FIG. 2.
  • FIG. 5 is a waveform diagram of input / output voltages when the power is turned off in the PMIC shown in FIG. 4. It is a block diagram for demonstrating the state of the load at the time of the power supply OFF in PMIC.
  • Embodiment 1 Hereinafter, embodiments of the present invention will be described in detail.
  • the power supply device of the present invention is mounted on a liquid crystal display device as an electronic device.
  • FIG. 1 is a block diagram illustrating a schematic configuration of the power supply apparatus 101.
  • the power supply device 101 acquires a voltage (IC power supply voltage) from a power supply and distributes the voltage (output voltage) to each part (various drivers, etc.) of the liquid crystal display device.
  • (Power control circuit) 10 and a voltage drop detection circuit 20 that detects a drop in the voltage output from the PMIC 10 and transmits a signal indicating the detected voltage drop to the PMIC 10.
  • the PMIC 10 When the PMIC 10 receives the signal from the voltage drop detection circuit 20 when the power is turned off, the PMIC 10 stops the voltage generation operation.
  • the voltage drop detection circuit 20 realizes a drop in the output voltage output from the PMIC 10 by detecting the fall of the output voltage with respect to the reference voltage. Then, the voltage drop detection circuit 20 transmits to the PMIC 10 a signal indicating that the falling of the output voltage has been detected with respect to the reference voltage.
  • FIG. 2 is a block diagram showing a schematic configuration of the PMIC 10.
  • the PMIC 10 includes an input voltage detection circuit 11 that detects the input voltage Vin, an output OFF control circuit 12 that performs output OFF control based on an instruction from the input voltage detection circuit 11, and an output based on an instruction from the input voltage detection circuit 11.
  • An output ON control circuit 13 that performs ON control of the voltage
  • a voltage generation unit 14 that generates a voltage Vout to be output to each member of the liquid crystal display device
  • a voltage drop detection circuit 20 receive signals, and the detection operation of the input voltage detection circuit 11 is performed.
  • An operation invalid signal generation circuit 15 for generating an operation invalid signal to be invalidated is included.
  • the input voltage detection circuit 11 is a circuit that detects the falling or rising of the input voltage Vin with respect to the reference voltage. That is, when the input voltage detection circuit 11 detects the falling of the input voltage Vin with respect to the reference voltage, the input voltage detection circuit 11 instructs the output OFF control circuit 12 to execute output OFF control. On the other hand, when the input voltage detection circuit 11 detects the rising edge of the input voltage Vin with respect to the reference voltage, the input voltage detection circuit 11 instructs the output ON control circuit 13 to execute output ON control.
  • the output OFF control circuit 12 executes output OFF control based on an instruction from the input voltage detection circuit 11.
  • the output ON control circuit 13 executes output ON control based on an instruction from the input voltage detection circuit 11.
  • the output ON control is control for instructing the voltage generation unit 14 to generate voltage so that the output voltage Vout output from the PMIC 10 becomes a voltage necessary for each member. That is, if the output ON control is executed, the output voltage of the PMIC 10 is output as Vout> 0V.
  • the voltage generation unit 14 generates a voltage according to instructions from the output OFF control circuit 12 and the output ON control circuit 13 and outputs the voltage as the output voltage Vout.
  • the voltage drop of the output voltage Vout is detected by the voltage drop detection circuit 20.
  • the operation invalid signal generation circuit 15 invalidates the detection operation of the input voltage detection circuit 11 from a signal indicating that the voltage drop detection circuit 20 detects a decrease in the output voltage Vout, that is, a fall with respect to the reference voltage. An operation invalid signal is generated. The operation invalid signal generation circuit 15 outputs the generated operation invalid signal to the input voltage detection circuit 11.
  • the input voltage detection circuit 11 receives the operation invalid signal from the operation invalid signal generation circuit 15 and stops the operation of detecting the input voltage Vin, that is, the operation of detecting the falling or rising of the reference voltage.
  • the input voltage Vin is not detected by the input voltage detection circuit 11 until the power supply device 101 is reset.
  • FIG. 3 is a waveform diagram of input / output voltages when the PMIC 10 is turned off.
  • the IC power supply voltage is the input voltage Vin of the PMIC 10
  • the output voltage is the summer Vout at the output of the PMIC 10
  • the voltage drop detection circuit 20 It is a signal that has detected a fall.
  • the operation of the input voltage detection circuit 11 in the PMIC is stopped when the output voltage of the PMIC 10 is reduced.
  • the PMIC is stopped.
  • the operation of the voltage generation unit 14 (FIG. 2) is invalidated instead of invalidating the operation of the input voltage detection circuit 11 therein.
  • the PMIC stops the voltage generation operation as in the case where the operation of the input voltage detection circuit 11 is invalidated.
  • the PMIC 10 does not malfunction when the power is turned off.
  • a liquid crystal display device is assumed as an electronic device to which the power supply device 101 is applied.
  • the electronic device is not limited to the liquid crystal display device, and a PMIC is used. Any device can be used.
  • the power supply device generates a voltage of various power supplies, detects a decrease in voltage output from the power control circuit (PMIC 10) that outputs the generated voltage, and the power control circuit (PMIC 10), A voltage drop detection circuit 20 for transmitting a signal indicating a drop in the detected output voltage to the power control circuit (PMIC 10).
  • the power control circuit (PMIC 10) receives the signal from the voltage drop detection circuit 20 In this case, the voltage generation operation is stopped.
  • the power control circuit when the power control circuit receives a signal indicating that the voltage drop output from the power control circuit is detected from the voltage drop detection circuit, the power control circuit invalidates the voltage generation operation by the power control circuit. Thus, even if the input voltage to the power control circuit increases and reaches the voltage at which the power control circuit operates, the operation of the power control circuit is invalid, and therefore the power control circuit is not turned on again. Absent.
  • the power control circuit includes an input voltage detection circuit 11 that detects an input voltage, and various power supplies based on the input voltage detected by the input voltage detection circuit 11. And a voltage generation unit 14 that generates the voltage of the input voltage detection circuit 11.
  • the detection operation of the input voltage detection circuit 11 may be invalidated.
  • the power supply device is the power supply device according to aspect 1 described above, wherein the power control circuit (PMIC 10), the input voltage detection circuit 11 that detects an input voltage, and various power A voltage generation unit 14 that generates the voltage of the voltage, and when the signal is received from the voltage drop detection circuit 20, the voltage generation operation by the voltage generation unit 14 may be invalidated.
  • PMIC 10 power control circuit
  • the input voltage detection circuit 11 that detects an input voltage
  • various power A voltage generation unit 14 that generates the voltage of the voltage, and when the signal is received from the voltage drop detection circuit 20, the voltage generation operation by the voltage generation unit 14 may be invalidated.
  • the power control circuit (PMIC 10) is configured such that when the input voltage detected by the input voltage detection circuit 11 rises with respect to a reference voltage, Voltage generation by the voltage generator 14 when the output ON control circuit 13 that instructs the voltage generator 14 to generate voltage and the input voltage detected by the input voltage detector 11 falls with respect to a reference voltage And an output OFF control circuit 12 for instructing to stop the operation.
  • the power supply device is the power supply device according to any one of the aspects 2 to 4, wherein the voltage drop detection circuit 20 corresponds to a reference voltage of an output voltage output from the power control circuit (PMIC 10).
  • the voltage drop detection circuit 20 corresponds to a reference voltage of an output voltage output from the power control circuit (PMIC 10).
  • An electronic apparatus is characterized by including the power supply device 101 according to any one of aspects 1 to 4.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Direct Current Feeding And Distribution (AREA)

Abstract

The purpose of the present invention is to prevent a power management circuit from erroneously switching on the power source that was switched off. Provided is a power supply device (101) comprising a voltage drop detection circuit (20) for detecting a drop in voltage outputted by a PMIC (10) and transmitting to the PMIC (10) a signal indicating the detected output voltage drop. Upon receiving the signal from the voltage drop detection circuit (20), the PMIC (10) interrupts voltage-generating behavior.

Description

電源装置及び電子機器Power supply device and electronic device
　本発明は、電源から電圧を取得し電子機器の各部材へと電圧を配分するＰＭＩＣ（Power Management IC）を備えた電源装置に関する。 The present invention relates to a power supply device including a PMIC (Power Management IC) that acquires a voltage from a power source and distributes the voltage to each member of an electronic device.
　従来から、電源から電圧を取得し電子機器の各部材へと電圧を配分する電力制御ＩＣとしてＰＭＩＣ（Power Management IC）が知られている（例えば特許文献１）。電子機器は、ＰＭＩＣを搭載することにより各部材に適切な大きさの電圧を配分することができる。例えば図４に示すように、ＰＭＩＣ２００は、入力電圧検出回路２１１において基準電圧に対する入力電圧Ｖｉｎの立ち下がりを検出すると、出力ＯＦＦ制御回路２１２により電圧生成部２１４における電圧生成を停止させ、基準電圧に対する入力電圧Ｖｉｎの立ち上がりを検出すれば、出力ＯＮ制御回路２１３により電圧生成部２１４における電圧生成を行なわせて、出力電圧Ｖｏｕｔを出力する。 Conventionally, PMIC (Power Management IC) is known as a power control IC that acquires a voltage from a power source and distributes the voltage to each member of an electronic device (for example, Patent Document 1). An electronic device can distribute an appropriate voltage to each member by mounting the PMIC. For example, as illustrated in FIG. 4, when the PMIC 200 detects the falling edge of the input voltage Vin with respect to the reference voltage in the input voltage detection circuit 211, the output OFF control circuit 212 stops voltage generation in the voltage generation unit 214, and When the rising edge of the input voltage Vin is detected, the output ON control circuit 213 generates voltage in the voltage generation unit 214 and outputs the output voltage Vout.
日本国公開特許公報「特開２０１６－１５４３８４号公報（２０１６年８月２５日公開）」Japanese Patent Publication “Japanese Patent Laid-Open No. 2016-154384 (published on August 25, 2016)”
　ところで、電子機器の電源ＯＦＦ時には、上述した出力ＯＦＦ制御回路２１２により当該電子機器の各部材について決められたＯＦＦシーケンスに基づき電源がＯＦＦされる。 By the way, when the power of the electronic device is turned off, the power is turned off based on the OFF sequence determined for each member of the electronic device by the output OFF control circuit 212 described above.
　しかしながら、電源ＯＦＦ時には、図５に示すように、ＰＭＩＣの出力側に接続された各種負荷回路（例えばタイミングコントロールＩＣ）についても同様にＯＦＦするためＰＭＩＣからみると負荷が軽くなる（電圧波形(ア)部分）。このため、ＩＣ電源電圧（ＰＭＩＣの入力電圧）が上昇し、ＰＭＩＣが動作するＶｏｎｔｈ（ＯＮスレッシュ電圧）に達した時（電圧波形(イ)部分）、ＰＭＩＣが再度ＯＮし意図しない誤動作をすることがある（電圧波形(ウ)部分）。 However, when the power is turned off, as shown in FIG. 5, various load circuits (for example, timing control ICs) connected to the output side of the PMIC are similarly turned off. )portion). For this reason, when the IC power supply voltage (PMIC input voltage) rises and reaches the Vonth (ON threshold voltage) at which the PMIC operates (voltage waveform (b) part), the PMIC is turned ON again and an unintended malfunction occurs. There is (voltage waveform (c) part).
　これは、図６に示す電源回路において説明できる。すなわち、図６において、Ｖを入力電源、ＶｏをＰＭＩＣの入力電圧、ＲＬを、ＰＭＩＣを含めた部材の負荷、ｉｏを負荷電流としたとき、Ｖｏ＝Ｖ―ｉｏ・ＲＬの関係式が成り立つ。ここで、負荷が軽くなることを、ｉｏが０になることと考えれば、Ｖｏ＝Ｖとなり、ＰＭＩＣの入力電圧Ｖｏは上がる。このため、図５に示すグラフのように、電源ＯＦＦ時に一旦下がったＩＣ電源電圧（入力電圧：Ｖｏ）が再び持ちあがり、Ｖｏｎｔｈ（ＯＮスレッシュ電圧）に達し、ＰＭＩＣが再度ＯＮすることになる。 This can be explained in the power supply circuit shown in FIG. That is, in FIG. 6, when V is an input power source, Vo is an input voltage of the PMIC, RL is a load of a member including the PMIC, and io is a load current, a relational expression Vo = V−io · RL is established. Here, if the load becomes lighter and io becomes 0, Vo = V, and the input voltage Vo of the PMIC increases. For this reason, as shown in the graph of FIG. 5, the IC power supply voltage (input voltage: Vo) once lowered when the power is turned off rises again, reaches Vonth (ON threshold voltage), and the PMIC is turned on again.
　本発明の一態様は、電源ＯＦＦ時に、ＰＭＩＣが再度ＯＮするという誤動作を生じさせない電源装置を実現することを目的とする。 An object of one embodiment of the present invention is to realize a power supply device that does not cause a malfunction in which the PMIC is turned on again when the power is turned off.
　上記の課題を解決するために、本発明の一態様に係る電源装置は、各種電源の電圧を生成し、生成した電圧を出力する電力制御回路と、上記電力制御回路が出力する電圧の低下を検出し、検出した出力電圧の低下を示す信号を当該電力制御回路に送信する電圧低下検出回路と、を備え、上記電力制御回路は、上記電圧低下検出回路から上記信号を受信したとき、電圧の生成動作を停止することを特徴としている。 In order to solve the above problem, a power supply device according to one embodiment of the present invention generates a voltage of various power supplies, outputs a generated voltage, and reduces a voltage output from the power control circuit. A voltage drop detection circuit that detects and transmits a signal indicating a drop in the detected output voltage to the power control circuit, and the power control circuit receives the signal from the voltage drop detection circuit, The generation operation is stopped.
　本発明の一態様によれば、電源ＯＦＦ時に、電力制御回路が再度ＯＮするという誤動作を生じさせないという効果を奏する。 According to one aspect of the present invention, there is an effect of preventing a malfunction that the power control circuit is turned on again when the power is turned off.
本発明の実施形態１に係る電源装置の概略構成を示すブロック図である。It is a block diagram which shows schematic structure of the power supply device which concerns on Embodiment 1 of this invention. 図１に示す電源装置のＰＭＩＣの概略構成を示すブロック図である。It is a block diagram which shows schematic structure of PMIC of the power supply device shown in FIG. 図２に示すＰＭＩＣにおける電源ＯＦＦ時の入出力電圧の波形図である。FIG. 3 is a waveform diagram of input / output voltages when the power is turned off in the PMIC shown in FIG. 2. 従来のＰＭＩＣの概略構成を示すブロック図である。It is a block diagram which shows schematic structure of the conventional PMIC. 図４に示すＰＭＩＣにおける電源ＯＦＦ時の入出力電圧の波形図である。FIG. 5 is a waveform diagram of input / output voltages when the power is turned off in the PMIC shown in FIG. 4. ＰＭＩＣにおける電源ＯＦＦ時の負荷の状態を説明するためのブロック図である。It is a block diagram for demonstrating the state of the load at the time of the power supply OFF in PMIC.
　〔実施形態１〕
　以下、本発明の実施の形態について、詳細に説明する。なお、本実施形態では、本発明の電源装置を、電子機器として液晶表示装置に搭載した例について説明する。 Embodiment 1
Hereinafter, embodiments of the present invention will be described in detail. In this embodiment, an example in which the power supply device of the present invention is mounted on a liquid crystal display device as an electronic device will be described.
　＜電源装置１０１の概要＞
　図１は、電源装置１０１の概略構成を示すブロック図である。電源装置１０１は、図１に示すように、電源から電圧（ＩＣ電源電圧）を取得し液晶表示装置の各部（各種ドライバ等）へと電圧（出力電圧）を配分する、ＰＭＩＣ（Power Management IC）（電力制御回路）１０と、ＰＭＩＣ１０から出力された電圧の低下を検出し、検出した電圧の低下を示す信号をＰＭＩＣ１０に送信する電圧低下検出回路２０とを含んでいる。 <Outline of Power Supply Device 101>
FIG. 1 is a block diagram illustrating a schematic configuration of the power supply apparatus 101. As shown in FIG. 1, the power supply device 101 acquires a voltage (IC power supply voltage) from a power supply and distributes the voltage (output voltage) to each part (various drivers, etc.) of the liquid crystal display device. (Power control circuit) 10 and a voltage drop detection circuit 20 that detects a drop in the voltage output from the PMIC 10 and transmits a signal indicating the detected voltage drop to the PMIC 10.
　ＰＭＩＣ１０は、電源ＯＦＦ時に、電圧低下検出回路２０から上記信号を受信したとき、電圧生成の動作を停止する。 When the PMIC 10 receives the signal from the voltage drop detection circuit 20 when the power is turned off, the PMIC 10 stops the voltage generation operation.
　電圧低下検出回路２０は、ＰＭＩＣ１０から出力される出力電圧の低下を、基準電圧に対して出力電圧の立ち下がりを検出することで実現している。そして、電圧低下検出回路２０は、基準電圧に対して出力電圧の立ち下がりを検出したことを示す信号をＰＭＩＣ１０に送信する。 The voltage drop detection circuit 20 realizes a drop in the output voltage output from the PMIC 10 by detecting the fall of the output voltage with respect to the reference voltage. Then, the voltage drop detection circuit 20 transmits to the PMIC 10 a signal indicating that the falling of the output voltage has been detected with respect to the reference voltage.
　＜ＰＭＩＣ１０の詳細＞
　図２は、ＰＭＩＣ１０の概略構成を示すブロック図である。ＰＭＩＣ１０は、入力電圧Ｖｉｎを検出する入力電圧検出回路１１、入力電圧検出回路１１からの指示に基づいて出力のＯＦＦ制御を行なう出力ＯＦＦ制御回路１２、入力電圧検出回路１１からの指示に基づいて出力のＯＮ制御を行なう出力ＯＮ制御回路１３、液晶表示装置の各部材に出力する電圧Ｖｏｕｔを生成する電圧生成部１４、電圧低下検出回路２０から信号を受信し、入力電圧検出回路１１の検出動作を無効にする動作無効信号を生成する動作無効信号生成回路１５を含んでいる。 <Details of PMIC10>
FIG. 2 is a block diagram showing a schematic configuration of the PMIC 10. The PMIC 10 includes an input voltage detection circuit 11 that detects the input voltage Vin, an output OFF control circuit 12 that performs output OFF control based on an instruction from the input voltage detection circuit 11, and an output based on an instruction from the input voltage detection circuit 11. An output ON control circuit 13 that performs ON control of the voltage, a voltage generation unit 14 that generates a voltage Vout to be output to each member of the liquid crystal display device, and a voltage drop detection circuit 20 receive signals, and the detection operation of the input voltage detection circuit 11 is performed. An operation invalid signal generation circuit 15 for generating an operation invalid signal to be invalidated is included.
　入力電圧検出回路１１は、基準電圧に対する入力電圧Ｖｉｎの立ち下がりまたは立ち上がりを検出する回路である。つまり、入力電圧検出回路１１は、基準電圧に対する入力電圧Ｖｉｎの立ち下がりを検出すると、出力のＯＦＦ制御を実行するように、出力ＯＦＦ制御回路１２に指示をする。一方、入力電圧検出回路１１は、基準電圧に対する入力電圧Ｖｉｎの立ち上がりを検出すると、出力のＯＮ制御を実行するように、出力ＯＮ制御回路１３に指示をする。 The input voltage detection circuit 11 is a circuit that detects the falling or rising of the input voltage Vin with respect to the reference voltage. That is, when the input voltage detection circuit 11 detects the falling of the input voltage Vin with respect to the reference voltage, the input voltage detection circuit 11 instructs the output OFF control circuit 12 to execute output OFF control. On the other hand, when the input voltage detection circuit 11 detects the rising edge of the input voltage Vin with respect to the reference voltage, the input voltage detection circuit 11 instructs the output ON control circuit 13 to execute output ON control.
　出力ＯＦＦ制御回路１２は、入力電圧検出回路１１からの指示に基づいて、出力のＯＦＦ制御を実行する。ここで、出力のＯＦＦ制御とは、ＰＭＩＣ１０から出力される出力電圧Ｖｏｕｔが０Ｖになるように、電圧生成部１４に電圧生成の行なわないように指示する制御である。つまり、出力のＯＦＦ制御が実行されれば、ＰＭＩＣ１０の出力電圧は、Ｖｏｕｔ＝０Ｖとなる。 The output OFF control circuit 12 executes output OFF control based on an instruction from the input voltage detection circuit 11. Here, the output OFF control is control for instructing the voltage generation unit 14 not to generate voltage so that the output voltage Vout output from the PMIC 10 becomes 0V. That is, when the output OFF control is executed, the output voltage of the PMIC 10 becomes Vout = 0V.
　一方、出力ＯＮ制御回路１３は、入力電圧検出回路１１からの指示に基づいて、出力のＯＮ制御を実行する。ここで、出力のＯＮ制御とは、ＰＭＩＣ１０から出力される出力電圧Ｖｏｕｔが各部材で必要な電圧になるように、電圧生成部１４に電圧生成を行なうように指示する制御である。つまり、出力のＯＮ制御が実行されれば、ＰＭＩＣ１０の出力電圧は、Ｖｏｕｔ＞０Ｖが出力されることになる。 On the other hand, the output ON control circuit 13 executes output ON control based on an instruction from the input voltage detection circuit 11. Here, the output ON control is control for instructing the voltage generation unit 14 to generate voltage so that the output voltage Vout output from the PMIC 10 becomes a voltage necessary for each member. That is, if the output ON control is executed, the output voltage of the PMIC 10 is output as Vout> 0V.
　電圧生成部１４は、出力ＯＦＦ制御回路１２、出力ＯＮ制御回路１３の指示に応じた電圧を生成し、出力電圧Ｖｏｕｔとして出力する。出力電圧Ｖｏｕｔの電圧低下は、電圧低下検出回路２０によって検出される。 The voltage generation unit 14 generates a voltage according to instructions from the output OFF control circuit 12 and the output ON control circuit 13 and outputs the voltage as the output voltage Vout. The voltage drop of the output voltage Vout is detected by the voltage drop detection circuit 20.
　動作無効信号生成回路１５は、電圧低下検出回路２０によって出力電圧Ｖｏｕｔの低下、すなわち基準電圧に対して立ち下がったことを検出したことを示す信号から、入力電圧検出回路１１の検出動作を無効にする動作無効信号を生成する。動作無効信号生成回路１５は、生成した動作無効信号を入力電圧検出回路１１に出力する。 The operation invalid signal generation circuit 15 invalidates the detection operation of the input voltage detection circuit 11 from a signal indicating that the voltage drop detection circuit 20 detects a decrease in the output voltage Vout, that is, a fall with respect to the reference voltage. An operation invalid signal is generated. The operation invalid signal generation circuit 15 outputs the generated operation invalid signal to the input voltage detection circuit 11.
　入力電圧検出回路１１は、動作無効信号生成回路１５からの動作無効信号を受信することで、入力電圧Ｖｉｎの検出動作、すなわち基準電圧に対する立ち下がりまたは立ち上がりを検出する動作を停止する。なお、電源装置１０１がリセットされるまで、入力電圧検出回路１１による入力電圧Ｖｉｎの検出を行なわない。 The input voltage detection circuit 11 receives the operation invalid signal from the operation invalid signal generation circuit 15 and stops the operation of detecting the input voltage Vin, that is, the operation of detecting the falling or rising of the reference voltage. The input voltage Vin is not detected by the input voltage detection circuit 11 until the power supply device 101 is reset.
　＜効果＞
　図３は、ＰＭＩＣ１０における電源ＯＦＦ時の入出力電圧の波形図である。図３において、ＩＣ電源電圧は、ＰＭＩＣ１０の入力電圧Ｖｉｎであり、出力電圧は、ＰＭＩＣ１０の出力で夏Ｖｏｕｔであり、ＰＭＩＣ　ＦＢ入力信号は、電圧低下検出回路２０は、出力電圧の基準電圧に対する立ち下がりを検出した信号である。 <Effect>
FIG. 3 is a waveform diagram of input / output voltages when the PMIC 10 is turned off. In FIG. 3, the IC power supply voltage is the input voltage Vin of the PMIC 10, the output voltage is the summer Vout at the output of the PMIC 10, and the voltage drop detection circuit 20 It is a signal that has detected a fall.
　電源ＯＦＦ時には、図３に示すように、ＰＭＩＣの出力側に接続された各種負荷回路（例えばタイミングコントロールＩＣ)についても同様にＯＦＦするためＰＭＩＣからみると負荷が軽くなる(電圧波形(ア)部分）。このため、ＩＣ電源電圧（ＰＭＩＣの入力電圧）が上昇し、ＰＭＩＣが動作するＶｏｎｔｈ（ＯＮスレッシュ電圧）に達する（電圧波形(イ)部分）。しかしながら、電源ＯＦＦ時には、ローレベルのＰＭＩＣ　ＦＢ入力信号がＰＭＩＣ１０（厳密には入力電圧検出回路１１）に入力され、当該入力電圧検出回路１１の動作が無効になっているので、ＰＭＩＣ１０にＶｏｎｔｈ（ＯＮスレッシュ電圧）に達する電圧が入力されようとも、出力電圧は、ローレベルのままである。つまり、電源ＯＦＦ時に、ＰＭＩＣ１０が誤動作することがない。 When the power is turned off, as shown in FIG. 3, various load circuits (for example, timing control ICs) connected to the output side of the PMIC are also turned off in the same manner, so the load becomes lighter when viewed from the PMIC (voltage waveform (a) portion ). For this reason, the IC power supply voltage (input voltage of the PMIC) increases and reaches Vonth (ON threshold voltage) at which the PMIC operates (voltage waveform (A) portion). However, when the power is turned off, a low-level PMIC FB input signal is input to the PMIC 10 (strictly, the input voltage detection circuit 11), and the operation of the input voltage detection circuit 11 is disabled. Even if a voltage reaching the threshold voltage is input, the output voltage remains at a low level. That is, the PMIC 10 does not malfunction when the power is turned off.
　〔実施形態２〕
　以下、本発明の他の実施の形態について、詳細に説明する。 [Embodiment 2]
Hereinafter, other embodiments of the present invention will be described in detail.
　前記の実施形態１では、ＰＭＩＣ１０の出力電圧が低下した場合、ＰＭＩＣ内の入力電圧検出回路１１の動作を停止する例を記載したが、本実施形態では、ＰＭＩＣの出力電圧が低下した場合、ＰＭＩＣ内の入力電圧検出回路１１の動作を無効にするのではなく、電圧生成部１４（図２）の動作を無効にしている。この場合、電圧生成部１４の動作が無効になれば、入力電圧検出回路１１の動作を無効にした場合と同様に、ＰＭＩＣは電圧生成の動作を停止する。 In the first embodiment, an example in which the operation of the input voltage detection circuit 11 in the PMIC is stopped when the output voltage of the PMIC 10 is reduced is described. However, in this embodiment, when the output voltage of the PMIC is reduced, the PMIC is stopped. The operation of the voltage generation unit 14 (FIG. 2) is invalidated instead of invalidating the operation of the input voltage detection circuit 11 therein. In this case, if the operation of the voltage generation unit 14 becomes invalid, the PMIC stops the voltage generation operation as in the case where the operation of the input voltage detection circuit 11 is invalidated.
　電圧生成部１４の動作を無効にするには、例えば、当該電圧生成部１４内部の電圧生成に使用する内部発振回路の動作を停止することが考えられる。 In order to invalidate the operation of the voltage generation unit 14, for example, it is conceivable to stop the operation of the internal oscillation circuit used for voltage generation inside the voltage generation unit 14.
　以上のように、本実施形態においても、前記実施形態１と同様に、電源ＯＦＦ時に、ＰＭＩＣ１０が誤動作することがない。 As described above, also in this embodiment, as in the first embodiment, the PMIC 10 does not malfunction when the power is turned off.
　なお、前記実施形態１，２では、電源装置１０１を適用する電子機器として液晶表示装置を想定して説明したが、電子機器としては液晶表示装置に限定されるものではなく、ＰＭＩＣを使用している機器であればよい。 In the first and second embodiments, a liquid crystal display device is assumed as an electronic device to which the power supply device 101 is applied. However, the electronic device is not limited to the liquid crystal display device, and a PMIC is used. Any device can be used.
　〔まとめ〕
　本発明の態様１に係る電源装置は、各種電源の電圧を生成し、生成した電圧を出力する電力制御回路（ＰＭＩＣ１０）と、上記電力制御回路（ＰＭＩＣ１０）が出力する電圧の低下を検出し、検出した出力電圧の低下を示す信号を当該電力制御回路（ＰＭＩＣ１０）に送信する電圧低下検出回路２０と、を備え、上記電力制御回路（ＰＭＩＣ１０）は、上記電圧低下検出回路２０から上記信号を受信したとき、電圧の生成動作を停止することを特徴としている。 [Summary]
The power supply device according to aspect 1 of the present invention generates a voltage of various power supplies, detects a decrease in voltage output from the power control circuit (PMIC 10) that outputs the generated voltage, and the power control circuit (PMIC 10), A voltage drop detection circuit 20 for transmitting a signal indicating a drop in the detected output voltage to the power control circuit (PMIC 10). The power control circuit (PMIC 10) receives the signal from the voltage drop detection circuit 20 In this case, the voltage generation operation is stopped.
　上記構成によれば、電力制御回路は、電圧低下検出回路から当該電力制御回路が出力する電圧の低下を検出したことを示す信号を受信したとき、当該電力制御回路による電圧の生成動作を無効にすることで、当該電力制御回路への入力電圧が高まって、当該電力制御回路が動作する電圧に達しても、当該電力制御回路の動作は無効であるため、再度電力制御回路がＯＮすることはない。 According to the above configuration, when the power control circuit receives a signal indicating that the voltage drop output from the power control circuit is detected from the voltage drop detection circuit, the power control circuit invalidates the voltage generation operation by the power control circuit. Thus, even if the input voltage to the power control circuit increases and reaches the voltage at which the power control circuit operates, the operation of the power control circuit is invalid, and therefore the power control circuit is not turned on again. Absent.
　これにより、電力制御回路は、電源ＯＦＦ時に、入力電圧の状況に関わらずＯＦＦシーケンスが継続されるので、意図しない電圧の出力が発生することがない。つまり、電源ＯＦＦ時に、電力制御回路が再度ＯＮするという誤動作が生じることはない。 This allows the power control circuit to continue the OFF sequence regardless of the input voltage status when the power is turned off, so that an unintended voltage output does not occur. That is, there is no malfunction that the power control circuit is turned on again when the power is turned off.
　本発明の態様２に係る電源装置は、上記態様１において、電力制御回路（ＰＭＩＣ１０）は、入力電圧を検出する入力電圧検出回路１１と、上記入力電圧検出回路１１が検出した入力電圧から各種電源の電圧を生成する電圧生成部１４と、を備え、上記電圧低下検出回路２０から上記信号を受信したとき、上記入力電圧検出回路１１の検出動作を無効にしてもよい。 In the power supply device according to aspect 2 of the present invention, in the above aspect 1, the power control circuit (PMIC 10) includes an input voltage detection circuit 11 that detects an input voltage, and various power supplies based on the input voltage detected by the input voltage detection circuit 11. And a voltage generation unit 14 that generates the voltage of the input voltage detection circuit 11. When the signal is received from the voltage drop detection circuit 20, the detection operation of the input voltage detection circuit 11 may be invalidated.
　本発明の態様３に係る電源装置は、上記態様１において、上記電力制御回路（ＰＭＩＣ１０）、入力電圧を検出する入力電圧検出回路１１と、上記入力電圧検出回路１１が検出した入力電圧から各種電源の電圧を生成する電圧生成部１４と、を備え、上記電圧低下検出回路２０から上記信号を受信したとき、上記電圧生成部１４による電圧生成動作を無効にしてもよい。 The power supply device according to aspect 3 of the present invention is the power supply device according to aspect 1 described above, wherein the power control circuit (PMIC 10), the input voltage detection circuit 11 that detects an input voltage, and various power A voltage generation unit 14 that generates the voltage of the voltage, and when the signal is received from the voltage drop detection circuit 20, the voltage generation operation by the voltage generation unit 14 may be invalidated.
　上記の構成によれば、電力制御回路の入力電圧検出回路または電圧生成部の動作を無効にすることで、当該入力電圧検出回路または電圧生成部の後段にある全ての回路の動作を無効にできるため、電源ＯＦＦ時に、電力制御回路が再度ＯＮするという誤動作を確実に生じさせない。 According to the above configuration, by disabling the operation of the input voltage detection circuit or voltage generation unit of the power control circuit, the operation of all circuits subsequent to the input voltage detection circuit or voltage generation unit can be disabled. Therefore, when the power is turned off, the malfunction that the power control circuit is turned on again is not caused.
　本発明の態様４に係る電源装置は、上記態様２または３において、上記電力制御回路（ＰＭＩＣ１０）は、上記入力電圧検出回路１１が検出した入力電圧が基準電圧に対して立ち上がっている場合に、上記電圧生成部１４に電圧生成を指示する出力ＯＮ制御回路１３と、上記入力電圧検出回路１１が検出した入力電圧が基準電圧に対して立ち下がっている場合に、上記電圧生成部１４による電圧生成の停止を指示する出力ＯＦＦ制御回路１２と、をさらに備えていてもよい。 In the power supply device according to aspect 4 of the present invention, in the aspect 2 or 3, the power control circuit (PMIC 10) is configured such that when the input voltage detected by the input voltage detection circuit 11 rises with respect to a reference voltage, Voltage generation by the voltage generator 14 when the output ON control circuit 13 that instructs the voltage generator 14 to generate voltage and the input voltage detected by the input voltage detector 11 falls with respect to a reference voltage And an output OFF control circuit 12 for instructing to stop the operation.
　本発明の態様５に係る電源装置は、上記態様２～４の何れか１態様において、上記電圧低下検出回路２０は、上記電力制御回路（ＰＭＩＣ１０）から出力された出力電圧の基準電圧に対して立ち下がったことを検出したとき、電圧が低下したことを示す信号を当該電力制御回路（ＰＭＩＣ１０）に送信し、上記電力制御回路（ＰＭＩＣ１０）は、上記電圧低下検出回路２０から電圧が低下したことを示す信号を受信したとき、上記入力電圧検出回路１１の検出動作を無効にしてもよい。 The power supply device according to aspect 5 of the present invention is the power supply device according to any one of the aspects 2 to 4, wherein the voltage drop detection circuit 20 corresponds to a reference voltage of an output voltage output from the power control circuit (PMIC 10). When it is detected that the voltage has fallen, a signal indicating that the voltage has dropped is transmitted to the power control circuit (PMIC 10), and the power control circuit (PMIC 10) has received a voltage drop from the voltage drop detection circuit 20. When the signal indicating is received, the detection operation of the input voltage detection circuit 11 may be invalidated.
　上記の構成によれば、出力電圧の低下を、出力電圧の基準電圧に対する立ち下がりを検出するだけでよいため、簡単な構成で、且つ容易に、電源ＯＦＦ時に、電力制御回路が再度ＯＮするという誤動作を生じさせないようにできる。 According to the above configuration, it is only necessary to detect the fall of the output voltage with respect to the reference voltage, so that the power control circuit can be easily turned on again when the power is turned off with a simple configuration. It is possible to prevent malfunctions.
　本発明の態様６に係る電子機器は、上記態様１～４の何れか１態様に記載の電源装置１０１を備えたことを特徴としている。 An electronic apparatus according to aspect 6 of the present invention is characterized by including the power supply device 101 according to any one of aspects 1 to 4.
　上記の構成によれば、電源ＯＦＦ時に、電力制御回路が再度ＯＮするという誤動作を生じさせない電子機器を実現することができる。 According to the above configuration, it is possible to realize an electronic device that does not cause a malfunction that the power control circuit is turned on again when the power is turned off.
　本発明は上述した各実施形態に限定されるものではなく、請求項に示した範囲で種々の変更が可能であり、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本発明の技術的範囲に含まれる。さらに、各実施形態にそれぞれ開示された技術的手段を組み合わせることにより、新しい技術的特徴を形成することができる。 The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention. Furthermore, a new technical feature can be formed by combining the technical means disclosed in each embodiment.
１０　ＰＭＩＣ（電力制御回路）
１１　入力電圧検出回路
１２　出力ＯＦＦ制御回路（出力ＯＦＦ制御部）
１３　出力ＯＮ制御回路（出力ＯＮ制御部）
１４　電圧生成部
１５　動作無効信号生成回路
２０　電圧低下検出回路
１０１　電源装置
Ｖｉｎ　入力電圧
Ｖｏｕｔ　出力電圧 10 PMIC (Power Control Circuit)
11 Input Voltage Detection Circuit 12 Output OFF Control Circuit (Output OFF Control Unit)
13 Output ON control circuit (Output ON control unit)
14 Voltage generation unit 15 Operation invalid signal generation circuit 20 Voltage drop detection circuit 101 Power supply device Vin Input voltage Vout Output voltage

Claims (6)

  1. 　電子機器の各部に必要な各種電圧を生成し、生成した電圧を出力する電力制御回路と、
    　上記電力制御回路が出力する電圧の低下を検出し、検出した電圧の低下を示す信号を当該電力制御回路に送信する電圧低下検出回路と、を備え、
    　上記電力制御回路は、
    　上記電圧低下検出回路から上記信号を受信したとき、電圧の生成動作を停止することを特徴とする電源装置。     A power control circuit that generates various voltages necessary for each part of the electronic device and outputs the generated voltage;
    A voltage drop detection circuit that detects a drop in the voltage output by the power control circuit and transmits a signal indicating the detected voltage drop to the power control circuit, and
    The power control circuit is
    A power supply apparatus, wherein when the signal is received from the voltage drop detection circuit, the voltage generation operation is stopped.
  2. 　上記電力制御回路は、
    　入力電圧を検出する入力電圧検出回路と、
    　上記入力電圧検出回路が検出した入力電圧から各種電源の電圧を生成する電圧生成部と、を備え、
    　上記電圧低下検出回路から上記信号を受信したとき、上記入力電圧検出回路の検出動作を無効にすることを特徴とする請求項１に記載の電源装置。     The power control circuit is
    An input voltage detection circuit for detecting an input voltage;
    A voltage generation unit that generates voltages of various power sources from the input voltage detected by the input voltage detection circuit;
    2. The power supply device according to claim 1, wherein when the signal is received from the voltage drop detection circuit, the detection operation of the input voltage detection circuit is invalidated.
  3. 　上記電力制御回路は、
    　入力電圧を検出する入力電圧検出回路と、
    　上記入力電圧検出回路が検出した入力電圧から各種電源の電圧を生成する電圧生成部と、を備え、
    　上記電圧低下検出回路から上記信号を受信したとき、上記電圧生成部による電圧生成動作を無効にすることを特徴とする請求項１に記載の電源装置。     The power control circuit is
    An input voltage detection circuit for detecting an input voltage;
    A voltage generation unit that generates voltages of various power sources from the input voltage detected by the input voltage detection circuit;
    The power supply device according to claim 1, wherein when the signal is received from the voltage drop detection circuit, the voltage generation operation by the voltage generation unit is invalidated.
  4. 　上記電力制御回路は、
    　上記入力電圧検出回路が検出した入力電圧が基準電圧に対して立ち上がっている場合に、上記電圧生成部に電圧生成を指示する出力ＯＮ制御部と、
    　上記入力電圧検出回路が検出した入力電圧が基準電圧に対して立ち下がっている場合に、上記電圧生成部による電圧生成の停止を指示する出力ＯＦＦ制御部と、をさらに備えていることを特徴とする請求項２または３に記載の電源装置。     The power control circuit is
    An output ON control unit that instructs the voltage generation unit to generate a voltage when the input voltage detected by the input voltage detection circuit rises with respect to a reference voltage;
    An output OFF control unit for instructing stop of voltage generation by the voltage generation unit when the input voltage detected by the input voltage detection circuit falls with respect to a reference voltage; The power supply device according to claim 2 or 3.
  5. 　上記電圧低下検出回路は、
    　上記電力制御回路から出力された出力電圧の基準電圧に対して立ち下がったことを検出したとき、電圧が低下したことを示す信号を当該電力制御回路に送信し、
    　上記電力制御回路は、
    　上記電圧低下検出回路から電圧の低下を示す信号を受信したとき、電圧の生成動作を停止することを特徴とする請求項２～４の何れか１項に記載の電源装置。     The voltage drop detection circuit is
    When detecting that the output voltage has fallen with respect to the reference voltage of the output voltage output from the power control circuit, a signal indicating that the voltage has dropped is transmitted to the power control circuit,
    The power control circuit is
    The power supply apparatus according to any one of claims 2 to 4, wherein when the signal indicating the voltage drop is received from the voltage drop detection circuit, the voltage generation operation is stopped.
  6. 　請求項１～５の何れか１項に記載の電源装置を備えたことを特徴とする電子機器。 An electronic device comprising the power supply device according to any one of claims 1 to 5.
PCT/JP2018/019540 2017-05-26 2018-05-21 Power supply device and electronic device WO2018216661A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017-104919 2017-05-26
JP2017104919 2017-05-26

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Publication number Priority date Publication date Assignee Title
TWI836524B (en) * 2022-07-25 2024-03-21 聯詠科技股份有限公司 Feedback control system

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JPH10337007A (en) * 1997-06-03 1998-12-18 Murata Mfg Co Ltd Dc-dc converter
JP2009100496A (en) * 2007-10-12 2009-05-07 Funai Electric Co Ltd Voltage supply unit
JP2010015348A (en) * 2008-07-03 2010-01-21 Mitsubishi Electric Corp Power supply circuit
JP2013153585A (en) * 2012-01-25 2013-08-08 Asahi Kasei Electronics Co Ltd Dc-dc converter
JP2014057465A (en) * 2012-09-13 2014-03-27 Nichicon Corp Dc/dc converter and power supply system

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JPH01116712A (en) * 1987-10-30 1989-05-09 Sony Corp Stabilizing power source circuit
JPH10337007A (en) * 1997-06-03 1998-12-18 Murata Mfg Co Ltd Dc-dc converter
JP2009100496A (en) * 2007-10-12 2009-05-07 Funai Electric Co Ltd Voltage supply unit
JP2010015348A (en) * 2008-07-03 2010-01-21 Mitsubishi Electric Corp Power supply circuit
JP2013153585A (en) * 2012-01-25 2013-08-08 Asahi Kasei Electronics Co Ltd Dc-dc converter
JP2014057465A (en) * 2012-09-13 2014-03-27 Nichicon Corp Dc/dc converter and power supply system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI836524B (en) * 2022-07-25 2024-03-21 聯詠科技股份有限公司 Feedback control system

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