WO2018001182A1 - Photovoltaic cell, photovoltaic cell assembly, photovoltaic array, and solar cell - Google Patents

Abstract

A photovoltaic cell, photovoltaic cell assembly, photovoltaic array, and solar cell. The photovoltaic cell comprises: a silicon wafer (1), a front gate line layer (2), a first electrode (4), and a second electrode (5). The silicon wafer (1) comprises a silicon substrate (11), a first type of front diffusion layer (12), and a side division layer (13). The first type of front diffusion layer (12) is disposed on a light incident layer of the silicon substrate (11). The side division layer (13) is disposed on a side surface of the silicon substrate (11). The front gate line layer (2) is disposed above the first type of front diffusion layer (12). The first electrode (4) is disposed on the side division layer (13) and is electrically connected to the front gate line layer (2). The second electrode (5) is disposed on another side surface of the silicon substrate (11) and is not in contact with the first electrode (4).

Description

Cell, cell assembly, cell matrix and solar cell Technical field

The present disclosure relates to the field of solar cell technologies, and in particular, to a battery chip, a battery chip assembly, a battery chip matrix, and a solar cell.

Background technique

In the crystalline silicon solar cell sheet of the related art, the backlight surface and the light receiving surface respectively have 2-3 silver main gate lines as the positive and negative electrodes of the battery sheet, and these silver main gate lines not only consume a large amount of silver paste, but also block incident light. This results in a decrease in the efficiency of the battery. In addition, since the positive and negative electrodes are respectively distributed on the backlight surface and the light receiving surface of the battery sheet, when the battery sheets are connected in series, it is necessary to use a conductive member to solder the negative electrode of the light receiving surface of the battery sheet to the positive electrode of the backlight surface of the adjacent battery sheet. As a result, the welding process is cumbersome and the welding material is used more. Moreover, the battery sheets and the conductive members are easily broken during soldering and subsequent lamination processes.

In addition, the matrix of the battery in the related art is usually composed of 72 pieces or 60 pieces of cells in series, which constitutes three circuits composed of six strings of battery strings. At this time, at least three diodes are generally required to make each circuit. By providing a diode for bypass protection, since the diode is usually disposed in the junction box of the battery, the cost of the integrated junction box is increased, resulting in an increase in the structural complexity of the battery. Moreover, when the series components in which a plurality of battery cells are connected in series are connected in series again, the amount of the connecting cable is large, and the material is wasted a lot, resulting in an increase in the cost of the power station.

Summary of the invention

The present disclosure is intended to address at least one of the technical problems existing in the prior art. To this end, the present disclosure is directed to a battery sheet that is excellent in leakage resistance and high in power.

The present disclosure also proposes a battery chip assembly having the above battery sheet.

The present disclosure also proposes a battery chip matrix having the above-described battery chip assembly.

The present disclosure also proposes a solar cell having the above-described battery chip matrix.

A battery sheet according to a first aspect of the present disclosure, comprising: a silicon wafer including a silicon substrate, a front first diffusion layer, and a side spacer, wherein the front diffusion layer is provided on the silicon substrate The light-receiving surface is disposed on one side surface of the silicon substrate, wherein the side spacer is an insulating layer and/or a diffusion layer of the same type as the front first diffusion layer; a front gate line layer, the front gate line layer is disposed on the front surface first type diffusion layer; the first electrode, the first electrode is disposed on the side spacer layer and electrically connected to the front gate line layer Second electrode, the second The electrode is disposed on the other side surface of the silicon substrate and is not in contact with the first electrode, the front gate line layer, and the front first diffusion layer.

The battery sheet according to the present disclosure has good leakage resistance and high power.

In some embodiments, the silicon substrate includes opposite first and second side surfaces, and the first electrode and the second electrode are respectively disposed on the first side surface and the second side On the side surface.

In some embodiments, the first electrode and the second electrode respectively fill the first side surface and the second side surface.

In some embodiments, the first side surface and the second side surface are disposed in parallel.

In some embodiments, the distance between the first side surface and the second side surface is between 20 mm and 60 mm.

In some embodiments, the silicon wafer is a rectangular sheet, and the first side surface and the second side surface are two long side surfaces of the silicon wafer.

In some embodiments, the front gate line layer includes a plurality of front sub-gate lines extending in a direction perpendicular to the first electrode direction.

In some embodiments, the battery chip includes: a backing layer disposed on a backlight surface of the silicon substrate, the backing layer electrically connected to the second electrode and The first electrode is not in contact.

In some embodiments, the back surface of the silicon substrate has a backside spacer, which is an insulating layer and/or a diffusion layer of the same type as the front type first diffusion layer, the cell sheet The method includes a back first gate line layer electrically connected to the first electrode and not in contact with the second electrode.

In some embodiments, the back first gate line layer includes a plurality of back first sub-gate lines extending in a direction perpendicular to the first electrode direction.

In some embodiments, the back surface of the silicon substrate has a back type first diffusion layer of the same type as the front type first diffusion layer, and the back first gate line layer is disposed on the back side. On the diffusion layer.

In some embodiments, the backside first type of diffusion layer is a non-discrete layer.

In some embodiments, the cell sheet further includes a back second gate line layer electrically connected to the second electrode and not in contact with the first electrode.

In some embodiments, the back second gate line layer includes a plurality of back second sub-gate lines extending in a direction perpendicular to the second electrode direction.

In some embodiments, the back surface of the silicon substrate has a back type second diffusion layer different from the front type first diffusion layer type, and the back second gate line layer is disposed on the back side second On the diffusion layer.

In some embodiments, the backside second type of diffusion layer is a non-discrete layer.

In some embodiments, the silicon wafer further includes a passivation layer that is overlaid on a backlight surface of the silicon substrate.

In some embodiments, the silicon wafer further includes an anti-reflection layer that is overlaid on the front first diffusion layer and/or the side spacer.

In some embodiments, the side spacer is an insulating layer.

In some embodiments, the side spacer is a side first diffusion layer of the same type as the front first diffusion layer.

In some embodiments, the silicon substrate is P-type, and the front first diffusion layer is a phosphorus diffusion layer.

In some embodiments, the silicon substrate is N-type and the front first diffusion layer is a boron diffusion layer.

A battery sheet assembly according to a second aspect of the present disclosure, comprising the battery sheet according to the first aspect of the present disclosure, wherein the silicon wafer in each of the battery sheets each includes a pair of side surfaces that are oppositely disposed in a longitudinal direction, The first electrode and the second electrode are respectively disposed on the pair of side surfaces, the plurality of battery sheets are sequentially arranged along the longitudinal direction; and the conductive members are adjacent to each other and respectively located Two electrodes on two adjacent ones of the cells are electrically connected such that two adjacent cells are connected in series or in parallel.

In some embodiments, the conductive member is interposed between a pair of side surfaces of the adjacent two of the battery sheets that are adjacent to each other in the longitudinal direction and respectively with two electrodes on the set of side surfaces Contact electrical connection.

According to the cell sheet assembly of the present disclosure, the power of the cell sheet assembly is improved by providing the cell sheet of the above first aspect.

A battery chip matrix according to a third aspect of the present disclosure includes the battery chip assembly according to the second aspect of the present disclosure, the battery chip assembly being plural and connected in series and/or in parallel.

According to the cell sheet matrix of the present disclosure, the power of the cell matrix is improved by providing the cell matrix of the second aspect described above.

A solar cell according to a fourth aspect of the present disclosure, comprising a first panel, a first bonding layer, a battery, a second bonding layer, and a second panel disposed in order from a light receiving side to a backlight side, wherein the battery is according to the present invention A battery chip assembly of the second aspect or a battery chip matrix according to the third aspect of the present disclosure is disclosed.

According to the solar cell of the present disclosure, the power of the solar cell is improved by providing the cell sheet assembly of the above second aspect or the cell sheet matrix of the above third aspect.

The additional aspects and advantages of the present disclosure will be set forth in part in the description which follows.

DRAWINGS

1 is a schematic view of a light receiving side of a battery sheet according to Embodiment 1 of the present disclosure;

Figure 2 is a schematic view of the backlight side of the battery chip shown in Figure 1;

Figure 3 is a schematic view of the side of the battery chip shown in Figure 2;

Figure 4 is a state diagram in which two battery sheets shown in Figure 3 are connected, and the battery sheet is a simplified schematic view;

Figure 5 is a schematic side view of the backlight of the two cells shown in Figure 4;

Figure 6 is a schematic view of the two battery sheets shown in Figure 5 before being connected;

7 is a schematic view of a backlight side of a battery chip according to Embodiment 2 of the present disclosure;

Figure 8 is a side elevational view of the battery sheet shown in Figure 7;

9 is a schematic view of a backlight side of a battery chip according to Embodiment 3 of the present disclosure;

Figure 10 is a side elevational view of the battery sheet shown in Figure 9;

11 is a side view of a battery chip according to Embodiment 4 of the present disclosure;

Figure 12 is a side view of a battery chip according to Embodiment 5 of the present disclosure;

Figure 13 is a schematic view of a backlight side of a battery chip according to Embodiment 6 of the present disclosure;

Figure 14 is a side elevational view of the battery sheet shown in Figure 13;

Figure 15 is another side view of the battery sheet shown in Figure 13;

16 is a schematic diagram of a cell sheet matrix in accordance with an embodiment of the present disclosure;

Figure 17 is a circuit diagram of the battery chip matrix shown in Figure 16.

Reference mark:

Cell series assembly 1000; battery parallel assembly 2000; battery matrix 10000;

Conductive member 1001; bus bar 1002; battery panel assembly 100A;

Battery chip 100;

Silicon wafer 1; silicon substrate 11; anti-reflection layer 101; passivation layer 102;

a front type first diffusion layer 12; a side spacer 13; a back spacer 14; a back type second diffusion layer 15;

Front gate line layer 2; front sub-gate line 21;

First electrode 4; second electrode 5;

a second gate line layer 6 on the back surface; a second sub-gate line 61 on the back surface; an electrical back layer 60;

The first gate line layer 7 on the back side and the first sub-gate line 71 on the back side.

detailed description

The embodiments of the present disclosure are described in detail below, and the examples of the embodiments are illustrated in the drawings, wherein the same or similar reference numerals are used to refer to the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the drawings are illustrative, and are not intended to be construed as limiting.

Many different embodiments or examples are provided below to implement the different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of the specific examples are described below. Of course, they are merely examples and are not intended to limit the disclosure. Furthermore, the present disclosure may repeat reference numerals and/or letters in different examples. This repetition is for simplicity and For the sake of clarity, it does not itself indicate the relationship between the various embodiments and/or arrangements discussed. Moreover, the present disclosure provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials.

Hereinafter, a battery sheet 100 according to an embodiment of the first aspect of the present disclosure will be described with reference to FIGS. The battery chip 100 is a back contact solar cell that converts solar energy into electrical energy.

The battery sheet 100 according to an embodiment of the present disclosure includes: a silicon wafer 1, a front gate line layer 2, a first electrode 4, and a second electrode 5. The silicon wafer 1 includes a silicon substrate 11, a front first diffusion layer 12, and a side spacer 13.

The silicon substrate 11 has a sheet shape, and the two surfaces in the thickness direction of the silicon substrate 11 are respectively a light receiving surface and a backlight surface, and the light receiving surface is connected to the backlight surface through the side surface. Wherein the front first diffusion layer 12 is disposed on the light receiving surface of the silicon substrate 11, for example, in an alternative embodiment of the present disclosure, the front first diffusion layer 12 is non-discretely disposed on the silicon substrate 11. The surface occupies more than 90% of the area of the light receiving surface, thereby reducing the processing difficulty of the front type first diffusion layer 12, improving the processing efficiency and reducing the processing cost.

The front gate line layer 2 is disposed on the front first diffusion layer 12. That is, the front gate line layer 2 may be directly or indirectly disposed on the front first type diffusion layer 12. At this time, the front gate line layer 2 is disposed on the light receiving surface of the silicon wafer 1 and the front side first type diffusion layer 12 Correspondingly, in other words, projected in the thickness direction of the silicon wafer 1, the front gate line layer 2 does not exceed the outline of the front first type diffusion layer 12.

For example, in some embodiments of the present disclosure, the silicon wafer 1 may further include an anti-reflection layer 101, and the anti-reflection layer 101 may be disposed on the front first diffusion layer 12. Thus, when the silicon wafer 1 includes the anti-reflection layer 101, the front gate line layer 2 can be directly provided on the anti-reflection layer 101. When the silicon wafer 1 does not include the anti-reflection layer 101, the front gate line layer 2 may be directly disposed on the front first diffusion layer 12.

Here, it should be noted that when the conductive medium (directly or indirectly through the anti-reflection layer, the passivation layer) is disposed on the front first diffusion layer 12, or (directly or indirectly through the anti-reflection layer, the passivation layer) When on the same diffusion layer as the front type first diffusion layer 12 (such as the side first diffusion layer and the back first diffusion layer as described below), one type of charge can be collected; and when the conductive medium is directly Or indirectly through the passivation layer) on the surface of the silicon substrate 11 which does not have the front first type diffusion layer 12, or (directly or indirectly through the passivation layer) is disposed opposite to the front type first diffusion type 12 When a diffusion layer (such as the back type second diffusion layer described below) is used, another kind of charge can be collected. Here, it should be noted that the principle that the conductive medium collects charges on the silicon wafer should be well known to those skilled in the art and will not be described in detail herein.

In addition, it should be noted that the passivation layer is covered on the backlight surface of the silicon substrate 11, and the anti-reflection layer is covered on the front first diffusion layer 12 and/or the side spacer 13. For example, the entire light-receiving surface of the silicon wafer 1 and the outermost surface of one side surface in Embodiments 1-7 herein may each have an anti-reflection layer 101, and the entire backlight surface of the silicon wafer 1 in Embodiments 2-6 herein. The outermost surface may also have a passivation layer 102 to facilitate processing and fabrication. In addition, it should be noted that The concepts of the anti-reflection layer and the passivation layer described herein are well known to those skilled in the art and serve primarily to reduce reflection and enhance charge collection. For example, the materials of the anti-reflection layer and the passivation layer may include, but are not limited to, TiO2, Al2O3, SiNxOy, SiNxCy.

For example, when the silicon substrate 11 is P-type silicon, the front first diffusion layer 12 may be a phosphorus diffusion layer, and the conductive medium disposed on the phosphorus diffusion layer may collect a negative charge and be disposed on the non-phosphorus diffusion layer. The conductive medium collects a positive charge. Thus, since the front gate line layer 2 is provided on the front side first diffusion layer 12 (for example, directly or through the anti-reflection layer), the front gate line layer 2 can collect the first kind of charge (for example, a negative charge). The second electrode 5 described later is disposed on the side surface of the silicon substrate 11 (for example, directly or indirectly through the passivation layer), so that the second electrode 5 can collect the second kind of charge (for example) positive charge).

The side spacer 13 is provided on one side surface of the silicon substrate 11. For example, the side spacers 13 may fill the side surfaces. Thereby, the processing and manufacture of the side spacers are facilitated. The first electrode 4 is provided on the side spacer 13. That is, the first electrode 4 may be directly or indirectly disposed on the side spacer 13, and at this time, the first electrode 4 is disposed on the side surface of the silicon wafer 1 and corresponds to the side spacer 13, that is, along the edge Projected perpendicular to the side surface of the side spacer 13 , the first electrode 4 does not extend beyond the outline of the side spacer 13 . Wherein, the first electrode 4 is electrically connected to the front gate line layer 2, so that the first kind of charge (for example, a negative charge) collected by the front gate line layer 2 can be transmitted to the first electrode 4 (for example, the negative electrode).

The second electrode 5 is provided on the other side surface of the silicon substrate. That is, the second electrode 5 may be disposed directly or indirectly on the other side surface of the silicon substrate 11, that is, on the side surface of the silicon substrate 11 where the side spacer 13 is not provided, and at this time, the second electrode 5 corresponds to the side surface, in other words, projected in the thickness direction of the silicon wafer 1, and the second electrode 5 does not extend beyond the outline of the side surface. Wherein, since the second electrode 5 is provided on the surface of the silicon substrate 11 which is not provided directly on or through the passivation layer described herein, which does not have the front first type diffusion layer 12, another A kind of electric charge (for example, a positive electric charge) is used as an electrode (for example, a positive electrode) having a polarity opposite to that of the first electrode 4. Thereby, the first electrode 4 and the second electrode 5 can output electric energy as positive and negative poles of the battery sheet 100.

In this way, since the first electrode 4 and the second electrode 5 are both disposed on the side surface of the silicon wafer 1 and are not embedded in the interior of the silicon wafer 1, the processing difficulty of the entire battery sheet 100 can be reduced, and the processing process can be simplified. Improve processing efficiency and reduce processing costs. In addition, it is also possible to effectively prevent the first electrode 4 and the second electrode 5 from blocking the light-receiving surface and the backlight surface of the silicon wafer 1, thereby increasing the power of the battery sheet 100.

It can be understood by those skilled in the art that since the first electrode 4 and the second electrode 5 are electrodes of opposite polarity, the first electrode 4 and the second electrode 5 are insulated from each other, that is, mutually non-conducting, that is, mutual There is no electrical connection between them, and at this time, the first electrode 4 and all the components electrically connected to the first electrode 4 are not directly electrically connected to the second electrode 5 and all components electrically connected to the second electrode 5, It is also impossible to conduct indirectly through any external conductive medium, for example, it may not be contacted or isolated by an insulating material, etc., thereby avoiding short circuit between the first electrode 4 and the second electrode 5.

Wherein, the side spacer 13 is configured to prevent the first electrode 4 from being short-circuited by the silicon substrate 11 and the second electrode 5, that is, It is said that the first electrode 4 is prevented from directly contacting the silicon substrate 11 to cause a short circuit. For example, the side spacer 13 may be an insulating layer and/or a diffusion layer of the same type as the front first diffusion layer 12, that is, the side spacer 13 may be All of them are diffusion layers of the same type as the front first diffusion layer 12, and may be entirely of an insulating layer, or a part of the diffusion layer of the same type as the front type first diffusion layer 12, and the other part may be an insulating layer.

When the first electrode 4 is provided on the silicon substrate 11 through the insulating layer, the first electrode 4 can be directly insulated from the silicon substrate 11 to prevent the first electrode 4 from being collected from the silicon substrate 11 and collected by the second electrode 5. The charge of the same type of charge can effectively prevent the first electrode 4 from being electrically connected to the second electrode 5 through the silicon substrate 11 to cause a short circuit, that is, avoiding direct contact between the first electrode 4 and the silicon substrate 11 to cause a short circuit. When the first electrode 4 is provided on the silicon substrate 11 through a diffusion layer of the same type as the front first diffusion layer 12, the first electrode 4 can be collected from the diffused silicon substrate 11 and the front gate layer 2 The collected charge of the same type of charge, that is, the charge of the type of charge collected by the second electrode 5, can also prevent the first electrode 4 and the second electrode 5 from being short-circuited, and the power of the cell 100 can be improved.

In addition, in order to prevent the first electrode 4 and the second electrode 5 from being short-circuited, the second electrode 5 is disposed not to be in contact with the first electrode 4, the front gate line layer 2, the front first diffusion layer 12, and the side spacer 13. Thereby, the insulation effect of the first electrode 4 and the second electrode 5 can be conveniently ensured. Here, it should be noted that the concepts of the silicon substrate, the diffusion layer, the anti-reflection layer, the passivation layer, and the like, and the principle that the conductive medium collects charges from the silicon wafer are well known to those skilled in the art and will not be described in detail herein.

Optionally, the front gate line layer 2, and the back second gate line layer 6 and the back first gate line layer 7 described later may each be a conductive medium composed of a plurality of spaced apart conductive thin gate lines. The layer, wherein the fine gate line may be composed of a silver material, thereby increasing the conduction rate on the one hand and reducing the light-shielding area on the other hand, thereby increasing the power of the battery sheet 100 in a disguised manner. Further, the front gate line layer 2 includes a plurality of front sub-gate lines 21 extending in a direction perpendicular to the first electrode 4. Thereby, the path of the charge of the front gate line layer 2 to the first electrode 4 can be shortened, and the charge transfer efficiency can be improved, thereby further increasing the power of the cell sheet 100.

In summary, according to the battery sheet 100 of the embodiment of the present disclosure, by providing the first electrode 4 and the second electrode 5 on the side surface of the silicon substrate 11, the first electrode 4 and the second electrode 5 can be prevented from being applied to the silicon wafer 1. Shading, increasing the power of the battery sheet 100, and allowing the first electrode 4 and the second electrode 5 to be located on opposite side surfaces of the silicon wafer 1, thereby facilitating electrical connection between the plurality of battery sheets 100, and reducing welding difficulty. The amount of solder used is reduced, while the probability of breakage of the cell 100 during soldering and subsequent lamination processes is reduced.

In addition, by arranging the first electrode 4 and the second electrode 5 on opposite side surfaces of the silicon wafer 1, the processing difficulty of the battery sheet 100 is greatly reduced (for example, it is not necessary to process the opening on the silicon wafer 1 and The processing of injecting a conductive medium into the opening, thereby increasing the processing rate and reducing the processing failure rate and the processing cost. In addition, when the first electrode 4 and the second electrode 5 are provided on both side surfaces in the width direction of the silicon substrate 11, the path of transferring charges from the light-receiving side surface of the silicon wafer 1 can be effectively shortened, Increasing the charge transfer rate, thereby increasing the work of the cell 100 in a phased manner rate.

Optionally, the silicon wafer 1 includes opposite first and second side surfaces, and the first electrode 4 and the second electrode 5 are respectively disposed on the first side surface and the second side surface, that is, the first The electrode 4 is disposed on the first side surface, and the second electrode 5 is disposed on the second side surface, so that the first electrode 4 and the second electrode 5 can be oppositely disposed, so that the first electrode 4 and the second electrode 5 can be effectively avoided. Short circuit, and extremely convenient processing of the first electrode 4 and the second electrode 5, reducing processing difficulty and processing cost.

Here, it should be noted that the oppositely disposed side surfaces refer to two side surfaces that are not connected to each other and are disposed face to face. For example, for a rectangular sheet, the two wide side surfaces are a pair of opposite side surfaces. The two long side surfaces are also a pair of opposite side surfaces. Optionally, the first side surface and the second side surface are disposed in parallel. Thereby, the short circuit of the first electrode 4 and the second electrode 5 can be prevented more effectively.

Optionally, the first electrode 4 and the second electrode 5 respectively fill the first side surface and the second side surface. That is, the first electrode 4 is covered with the first side surface, and the second electrode 5 is covered with the second side surface, whereby the space can be utilized sufficiently to increase the power of the battery sheet 100.

In one embodiment, when the first side surface is disposed in parallel with the second side surface, the distance between the first side surface and the second side surface is 20 mm to 60 mm. For example, in the examples shown in FIGS. 2 and 3, when the silicon wafer 1 is a rectangular sheet, and the first electrode 4 and the second electrode 5 are respectively provided on the two long side surfaces of the silicon wafer 1, the silicon wafer The width of 1 is 20mm to 60mm. For example, in another example of the present disclosure (this example is not shown), when the silicon wafer 1 is a rectangular sheet, and the first electrode 4 and the second electrode 5 are respectively provided on the two wide side surfaces of the silicon wafer 1. In the upper case, the length of the silicon wafer 1 is 20 mm to 60 mm. Thereby, the path of charge transfer can be shortened, thereby increasing the charge transfer rate, thereby increasing the power of the cell sheet 100. The first electrode 4 and the second electrode 5 may both be rectangular plates and have the same length as the length of the silicon substrate 11, so that the ends of the first electrode 4 and the second electrode 5 in the longitudinal direction may be The outlines of the two wide side surfaces of the silicon substrate 11 are respectively aligned, thereby making full use of the space, improving the power of the battery sheet 100, and facilitating the connection of the subsequent battery sheet 100 to the battery sheet 100.

Next, a battery chip assembly 100A according to an embodiment of the second aspect of the present disclosure will be described with reference to FIGS.

The battery chip assembly 100A according to the embodiment of the second aspect of the present disclosure includes: at least two battery sheets 100 and a conductive member 1001. Wherein, the battery sheet 100 is a back contact solar cell sheet according to the above first embodiment of the present disclosure.

In one embodiment, the plurality of battery sheets 100 are arranged in the longitudinal direction such that the light-receiving surfaces are all facing the same side, for example, facing the sun, and the backlight surfaces are all facing the same side, for example, all facing away from the sun. Here, it should be noted that "transverse direction" as used herein refers to the direction in which the transverse lines extend, such as the horizontal direction shown in FIG. 5, and "longitudinal direction" refers to the direction in which the longitudinal lines extend, such as in FIG. In the vertical direction shown, the transverse line and the longitudinal line are mutually perpendicular straight lines; in addition, "extending in the lateral direction" is to be understood in a broad sense, that is, it should include "extending in a direction parallel to the transverse line" and "along with the transverse line" The angle extends less than 45°". Hereinafter, only the vertical direction shown in FIG. 5 is "longitudinal", FIG. The horizontal direction shown in the figure is "lateral" as an example. Of course, after reading the following technical solutions, those skilled in the art can clearly understand other technical solutions in the "longitudinal direction". In addition, it should be noted that the orientation or positional relationship shown in the drawings of the present application is only for the convenience of describing the present disclosure and the simplified description, and does not indicate or imply that the device or component referred to has a specific orientation to be specific. The orientation and construction of the orientation are not to be construed as limiting the disclosure.

Wherein, the silicon wafer 1 in each of the battery sheets 100 includes a pair of side surfaces which are oppositely disposed in the longitudinal direction, that is, the first side surface and the second side surface described above, the first electrode 4 and the second electrode 5 They are respectively disposed on a pair of side surfaces, that is, the first electrode 4 is disposed on the first side surface, the second electrode 5 is disposed on the second side surface, and the first electrode 4 and the second electrode 5 are disposed opposite to each other in the longitudinal direction.

Thus, when the plurality of battery sheets 100 are sequentially arranged in the longitudinal direction and the first electrode 4 and the second electrode 5 are respectively disposed on the opposite side surfaces of each of the silicon wafers 1, the adjacent battery sheets 100 are adjacent to each other. The electrodes on the side surfaces may be connected to each other such that adjacent cells 100 are connected in series or in parallel. Specifically, the conductive members (e.g., solder) are electrically connected to two electrodes that are adjacent to each other and respectively located on the adjacent two battery sheets such that the adjacent two battery sheets 100 are connected in series or in parallel. That is, when the two electrodes electrically connected together by the conductive member have the same polarity, the two battery sheets 100 can be connected in parallel, and when the two electrodes electrically connected together with the conductive members are different in polarity, two The battery sheets 100 can be connected in series.

Here, for the sake of clear expression, by way of example, referring to FIGS. 3 and 4, each of the battery sheets 100 is vertically disposed, and each of the battery sheets 100 has a second electrode 5 on the top side surface thereof, and the bottom of each of the battery sheets 100 There is a first electrode 4 on the side surface. When the plurality of battery sheets 100 are sequentially disposed in the vertical direction, for the two battery sheets 100 adjacent to each other, the first electrode 4 on the bottom side surface of the upper battery sheet 100 and the lower battery sheet 100 The second electrodes 5 on the top side surface are close to each other. The two electrodes can be soldered together using solder so that the two cells 100 are turned on. When the polarity of the first electrode 4 on the upper cell sheet 100 and the second electrode 5 on the lower cell sheet 100 are the same (that is, both positive electrodes or negative electrodes), the two cell sheets 100 may be connected in parallel. When the polarity of the first electrode 4 on the upper cell sheet 100 and the second electrode 5 on the lower cell sheet are different (ie, one is a positive electrode and the other is a negative electrode), the two cell sheets 100 may be connected in series.

When the cell sheet assembly 100A is prepared, the plurality of cell sheets 100 may be arranged in a vertical direction, and then the plurality of cell sheets 100 may be cross-welded by solder paste, thereby enabling seamless soldering (ie, making adjacent two The battery sheets 100 have no gap in the longitudinal direction, even if the lower end edge of the upper battery sheet 100 shown in FIG. 5 abuts against the upper end edge of the lower battery sheet 100, or when between the two battery sheets 100 After the conductive member 1001, there is no gap between the two battery sheets 100 in the longitudinal direction, the power of the battery assembly 100A is effectively increased, the welding process complexity is reduced, the amount of solder used is reduced, the heat loss of the solder is reduced, and the battery sheet is improved. The power of component 100A.

Alternatively, the conductive member 1001 is interposed, that is, filled between two side surfaces of the adjacent two battery sheets 100 that are adjacent to each other in the longitudinal direction and is electrically connected to the two electrodes on the two side surfaces. Thereby, two adjacent cells can be ensured There is no gap between the 100s, thereby effectively increasing the power of the cell assembly 100A, reducing the welding process complexity, reducing the amount of solder used, reducing the heat loss of the solder, and increasing the power of the cell assembly 100A.

Next, a battery chip matrix 10000 according to an embodiment of the third aspect of the present disclosure will be described with reference to FIGS. 16 and 17.

In one embodiment, the cell array 10000 includes the cell assembly 100A of the second aspect embodiment described above, and the cell assembly 100A is plural and connected in series and/or in parallel, that is, the plurality of cell assemblies 100A may be sequentially The battery cell matrix 10000 is formed in series, and the plurality of cell components 100A may also be connected in parallel to form a cell matrix 10000. The plurality of cell components 100A may also be connected in series and then connected in parallel to form a cell matrix 10000, and the plurality of cell components 100A may also be Parallel and then connected in series to form a cell matrix 10000. In the following, the battery cell matrix 10000 of other embodiments will be apparent to those skilled in the art after reading the following technical solutions by taking a plurality of cell modules 100A in parallel and then connecting them in series to form a cell matrix 10000.

When a plurality of battery sheets 100 in the battery module assembly 100A are sequentially connected in series by the conductive members 1001, the battery sheet assembly 100A is a battery sheet series assembly 1000. The cell matrix 10000 is comprised of a plurality of cell parallel assemblies 2000 in series, wherein each cell parallel assembly 2000 is formed by a plurality of cell series assemblies 1000 connected in parallel. That is to say, the plurality of cell series units 1000 are first connected in parallel to form a plurality of cell parallel units 2000, and the plurality of cell parallel units 2000 are connected in series to form a cell matrix 10000. Thereby, the power of the cell matrix 10000 is effectively increased, and the diode is not required to be bypass protected, thereby reducing the cost of the battery. In addition, the positive and negative junction boxes can be distributed on both sides of the cell matrix 10000, thereby reducing The amount of connecting cables between adjacent components reduces the cost of the power station.

For example, in an alternative embodiment of the present disclosure, there are two battery-parallel assemblies 2000, and each of the battery-parallel assemblies 2000 is formed by three battery-series series assemblies 1000 in parallel. That is to say, the six cell series series components 1000 are formed into a cell matrix 10000 by using the method of “first three and then two strings”, that is, six cell series components 1000 and three three are connected in parallel to form two cell parallel components 2000. Then, the two cell parallel assemblies 2000 are connected in series to form a cell matrix 10000.

Here, it should be noted that the battery chip matrix in the related art generally includes 60 battery cells connected in series, wherein each of the 10 battery cells is first connected in series to form a battery chip string, and the six battery chip strings are sequentially connected in series, thereby 60. The battery cells can all be connected in series. When the voltage of each cell is 0.5V, the voltage of 60 cells connected in series is 30V. At this time, if there is a problem with a cell string, the entire cell matrix will not work properly, so It is necessary to connect three diodes in parallel, so that even if there is a problem with the battery string, the circuit will form a loop through the parallel diodes, and the cell matrix can continue to work normally, not to be scrapped, but the power is smaller. However, on the one hand, the production cost of the diode is high. On the other hand, since the diode needs to be disposed in the junction box, the junction box is disposed at the edge of the width direction of the panel, and the positive and negative poles are led out through the junction box, and the integrated wiring used in the assembly. The box also increases production costs. In addition, since the junction box is in the center of the assembly, when the components are connected in series with the components, the amount of the connection cable is large, material is wasted, and the power station cost is also increased.

In comparison, the width of the battery sheet 100 herein may be 1/4 of the width of the conventional battery sheet. At this time, the total voltage of the battery series unit 1000 formed by connecting 10 battery sheets 100 in series is 20V (ie, 40×). 0.5V = 20V), then, by connecting two such cell series devices 1000 in series, a voltage of 40V can be achieved, so that the operating voltage can be effectively achieved. In addition, when the cell matrix 10000 is constructed by the above-mentioned "first three and then two strings" manner, since the parallel structure itself can protect the parallel bypass, it is not necessary to add another diode. Road protection reduces production costs. In addition, since the positive and negative junction boxes can be distributed on both sides of the cell matrix 10000, the amount of components and component connection cables is reduced, further reducing the cost of the power station.

A solar cell module according to an embodiment of the third aspect of the present disclosure is described below.

In one embodiment, the solar cell module includes a first panel, a first bonding layer, a battery, a second bonding layer, and a second panel disposed in order from the light receiving side to the backlight side. The battery may be the battery chip assembly 100A of the second embodiment described above, or may be the battery chip matrix 10000 of the third embodiment. As a result, the solar cell module has better power, better energy efficiency, easier processing, and lower cost.

A method of preparing a solar cell module according to an embodiment of the fourth aspect of the present disclosure is described below.

First, a battery is prepared.

In one embodiment, when the battery is the battery module 100A, the adjacent two battery cells 100 may be first connected in series or in parallel using the conductive member 1001 to obtain the battery chip assembly 100A, and then the battery chip assembly is used by the bus bar 1002. The positive electrode and the negative electrode of 100A are respectively taken out.

In one embodiment, when the battery is a cell matrix 10000, the adjacent two battery cells 100 may be first connected in series by the conductive member 1001 to obtain a plurality of battery chip series components 1000, and then the plurality of batteries are used by the bus bar 1002. The chip series components 1000 are connected in parallel to obtain a plurality of cell parallel components 2000, and then the plurality of cell parallel assemblies 2000 are connected in series by the bus bar 1002 to obtain a cell matrix 10000, and finally the bus bars 10000 are used to connect the positive electrodes of the cell matrix 10000. The negative electrodes are respectively taken out.

Next, the first panel, the first bonding layer, the battery, the second bonding layer, and the second panel are sequentially laid in the up and down direction to obtain a laminated structure, and then the laminated structure is laminated and packaged. For example, a first panel (eg, glass), a first bonding layer (eg, EVA), a battery, a second bonding layer (eg, EVA), and a second panel may be sequentially laid in order from bottom to top. The battery back sheet or glass is used to obtain a laminated structure. Next, the laminated structure in the previous step is laminated in a laminator, and the junction box and the bezel are mounted, thereby realizing packaging and fabrication of the solar cell module.

A battery sheet 100 according to various embodiments of the present disclosure will be described below with reference to FIGS.

Referring to Embodiment 1 below, the battery sheet 100 further includes: a backing layer 60, the backing layer 60 is disposed on the backlight surface of the silicon substrate 11, and the backing layer 60 is electrically connected to the second electrode 5 and not to the first electrode 4 contact.

Referring to Embodiment 3-6 below, the back surface of the silicon substrate 11 has a back surface layer 14, and the battery sheet 100 further includes: a back first gate line layer 7 on the back side and a back gate layer 7 on the back side layer and Electrically connected to the first electrode 4 and to the second Pole 5 does not touch. Optionally, the back first gate line layer 7 includes a plurality of back first sub-gate lines 71 extending in a direction perpendicular to the first electrode 4. Further, the back spacer 14 is a back type first diffusion layer of the same type as the front first diffusion layer 12, and the back first gate line 7 is provided on the back first diffusion layer. Optionally, the backside barrier layer 14 is a non-discrete layer. That is, when the backside barrier layer 14 is arbitrarily divided into a plurality of sub-regions, the plurality of sub-regions may be connected to form a continuous backside barrier layer 14. The back spacer 14 may be an insulating layer and/or a diffusion layer of the same type as the front diffusion layer 12, that is, the back spacers 14 may all be the same diffusion layer as the front first diffusion layer 12, or All of them are insulating layers, and some may be the same type of diffusion layer as the front type first diffusion layer 12, and the remaining part is an insulating layer.

Referring to Embodiments 2-6 below, the battery sheet 100 further includes: a back second gate line layer 6 disposed on the backlight surface of the silicon wafer 1 and electrically connected to the second electrode 5 and first The electrode 4 is not in contact. Optionally, the back second gate line layer 6 includes a plurality of back second sub-gate lines 61 extending in a direction perpendicular to the second electrode 5.

Referring to the following embodiments 2-4, 6, the backlight surface of the silicon substrate 11 has a back surface second type diffusion layer 15 different from the front type first diffusion layer 12, and the back second gate line layer 6 is provided on the back side. On the diffusion-like layer 15. Optionally, the backside diffusion layer 15 is a non-discrete layer. That is, when the back surface type second diffusion layer 15 is arbitrarily divided into a plurality of sub-regions, the plurality of sub-regions may be connected to form a continuous back surface second type diffusion layer 15.

Example 1

Referring to FIGS. 1 to 6, the silicon substrate 11 is a rectangular sheet, and the silicon substrate 11 can be divided by a square-sized silicon wafer body in a manner of constant length (only "separating" rather than "taking a cutting process") That is, the square-sized silicon wafer body can be divided into a plurality of rectangular-shaped silicon substrate 11 in a manner of constant length. At this time, each silicon substrate 11 has a length of square silicon. The lengths of the sheet bodies are equal, and the sum of the widths of the plurality of silicon substrates 11 is equal to the width of the square-sized silicon wafer body.

The light-receiving surface of the silicon substrate 11 has a front-first diffusion layer 12, the front-end diffusion layer 12 is provided with an anti-reflection layer 101, and the anti-reflection layer 101 is provided with a front gate layer 2, and the silicon substrate 11 is provided. A long side surface (for example, the bottom side surface shown in FIGS. 1-3) is provided with a side spacer 13 which may be of the same type as the front type first diffusion layer 12. In the layer, the side spacer 13 is provided with a first electrode 4, and the first electrode 4 is in contact with and electrically connected to the front gate line layer 2.

The back surface of the silicon substrate 11 has a backing layer 60 (for example, an aluminum back field), and the other long side surface of the silicon substrate 11 (for example, the top side surface shown in FIGS. 1 to 3) is provided with a first surface. The second electrode 5 and the second electrode 5 are in contact with and electrically connected to the backing layer 60.

Wherein, the front first diffusion layer 12 and the front gate layer 2 both maintain a certain safe distance from the side surface (for example, the top side surface) of the silicon substrate 11 on which the second electrode 5 is disposed, and the backing layer 60 Maintaining a certain safe distance from the side surface (for example, the bottom side surface) of the silicon substrate 11 on which the first electrode 4 is provided, thereby effectively avoiding the first One electrode 4 and the second electrode 5 are short-circuited.

Next, a method of preparing the battery sheet 100 of the first embodiment will be briefly described.

Step a1, aliquoting a square conventional silicon substrate body (for example, a conventional silicon substrate having a size of 156 mm*156 mm) by laser and cutting into 3-15 parts (optionally 5-10 parts) of a rectangular sheet shape having a constant length The silicon substrate 11 (for example, each having a length of 156 mm) is then subjected to a subsequent process of fabricating the cell 100. Of course, the present disclosure is not limited thereto, and a rectangular sheet-like silicon substrate 11 may be obtained by other means or processes. Here, it should be noted that the square conventional silicon substrate body can be divided into three or more parts, thereby shortening the distance that the electric charge migrates from the light receiving surface to the backlight surface, so that the charge collection is efficient and easy, thereby improving the battery sheet 100. Power, and, when the square conventional silicon substrate body is divided into fifteen parts and fifteen or less parts, the cutting process is easy, and the subsequent series-parallel cell sheet 100 consumes less solder, thereby improving the overallity of the cell sheets 100 after being connected in series and in parallel. Power, reduce costs.

Step a2, cleaning and texturing: cleaning and removing the dirt on the surface of the silicon substrate 11, and the texturing reduces the surface reflectance;

Step a3, diffusion-knotting: the silicon substrate 11 is a P-type silicon, and a P-N junction is prepared by diffusing phosphorus through a diffusion furnace;

Step a4, etching: removing the backlight surface of the silicon substrate 11 and the diffusion layers on the three side surfaces to obtain a front type first diffusion layer 12 on the light receiving surface of the silicon substrate 11 and the remaining one on the silicon substrate 11. a first type of diffusion layer on the side surface, thereby obtaining a silicon wafer 1;

Step a5, removing the phosphosilicate glass;

Step a6, vapor deposition of the anti-reflection layer 101 on the front side of the silicon wafer 1, the material of the anti-reflection layer 101 includes but is not limited to TiO2, Al2O3, SiNxOy, SiNxCy;

Step a7, screen printing an aluminum back field on the backlight surface of the silicon wafer 1 to obtain a backing layer 60, and sintering, the backing layer 60 is rectangular and the two width sides are flush with the two width sides of the silicon wafer 1. There is a certain safe distance between one length side of the backing layer 60 and the long side surface provided with the side first type of diffusion layer, and the other length side of the backing layer 60 is opposite to the side first type of diffusion layer. The long side surfaces are aligned. For example, in the examples shown in FIGS. 2 and 3, the upper edge, the left edge, and the right edge of the backing layer 60 are respectively aligned with the upper edge, the left edge, and the right edge of the silicon wafer 1, and the lower edge of the backing layer 60. Maintaining a certain safe distance from the lower edge of the silicon wafer 1 respectively;

Step a8, screen printing the fine silver gate lines in the width direction of the silicon wafer 1 on the light receiving surface of the silicon wafer 1 to obtain the front gate line layer 2, one end of each of the front sub-gate lines 21 (for example, in FIGS. 2 and 3) The lower end of the drawing is perpendicular to and in contact with the side surface provided with the side diffusion layer of the first type, and the other end (such as the upper end shown in FIGS. 2 and 3) does not exceed the edge of the front diffusion layer 12 of the first type;

In step a9, the first electrode 4 and the second electrode 5 are respectively formed on the two long side surfaces of the battery sheet 100, and sintered. Specifically, the second electrode 5 is prepared on the long side surface (for example, the upper surface shown in FIG. 3) opposite to the side first type diffusion layer, and the first side is formed on the side first type diffusion layer. Electrode 4.

Example 2

Referring to Figures 7 and 8, the structure of the embodiment 2 is substantially the same as that of the embodiment 1, wherein the same components are given the same reference numerals, except that the backlight surface of the silicon substrate 11 in the embodiment 1 is used. The backing layer 60 is disposed on the backlight surface of the silicon substrate 11 in the second embodiment, and the back surface second diffusion layer 15 and the back surface second diffusion layer 15 are disposed. The passivation layer 102 and the back second gate line layer 6.

Specifically, the backlight surface of the silicon substrate 11 has a back surface second type diffusion layer 15 different from the front type first diffusion layer 12, and the back surface second type diffusion layer 15 may be provided with a passivation layer 102, which is passivated. The layer 102 may be provided with a second gate line layer 6 on the back side, and the second gate line layer 6 on the back side is in contact with and electrically connected to the second electrode 5.

For example, when the silicon substrate 11 is P-type silicon, the front first diffusion layer 12 is a phosphorus diffusion layer, and the back second diffusion layer 15 is a boron diffusion layer. For another example, for example, when the silicon substrate 11 is N-type silicon, the front first diffusion layer 12 is a boron diffusion layer, and the back second diffusion layer 15 is a phosphorus diffusion layer. Here, it will be understood by those skilled in the art that conductive media disposed on different types of diffusion layers can collect different charges. Therefore, the front gate line layer 2 disposed on the front first type diffusion layer 12 and the back second gate line layer 6 disposed on the back surface second type diffusion layer 15 are different in charge type, that is, one collects a positive charge, and the other collects a positive charge. A second electrode 5 that collects a negative charge so as to be connected to the second gate line layer 6 on the back side and a first electrode 4 connected to the front gate line layer 2 can output electric energy as electrodes of opposite polarities. Thereby, by providing the gate line layers on the front and back sides of the battery sheet 100, the battery sheet 100 can be a double-sided battery, thereby further increasing the power of the battery sheet 100.

Wherein, the back type second diffusion layer 15 and the back second gate line layer 6 and the one side surface (for example, the bottom side surface) of the silicon substrate 11 on which the first electrode 4 is provided are maintained at a certain safe distance, thereby The short circuit of the first electrode 4 and the second electrode 5 can be effectively prevented.

Specifically, the method for preparing the battery sheet 100 in the second embodiment is substantially the same as the method for preparing the battery sheet 1 in the first embodiment, except that when the silicon wafer 1 in the second embodiment is prepared, The silicon substrate 11 is subjected to different types of diffusion on both sides, and even if the light-receiving surface and the backlight surface of the silicon substrate 11 are respectively diffused, the front type first diffusion layer 12 and the back second diffusion layer 15 are different in type, and then on the back side. The second type of diffusion layer 15 is vapor-deposited with the same passivation layer 102 as the anti-reflection layer 101, and then the back second gate line layer 6 is screen printed on the passivation layer 102.

Example 3

Referring to FIG. 9 and FIG. 10, the structure of the embodiment 3 is substantially the same as that of the embodiment 2, wherein the same components are given the same reference numerals, except that the backlight surface of the silicon substrate 11 in the third embodiment is used. A back diffusion layer 14 is also provided, and a passivation layer 102 and a back gate line layer 7 are provided on the back diffusion layer 14.

Specifically, the back surface of the silicon substrate 11 has a back type first diffusion layer 14 of the same type as the front type first diffusion layer 12, and the back surface first type diffusion layer 14 may be provided with a passivation layer 102, which is passivated. The layer 102 may be provided with a back first gate line layer 7, and the back first gate line layer 7 is in contact with and electrically connected to the first electrode 4.

Here, it will be understood by those skilled in the art that a conductive medium disposed on the same type of diffusion layer can collect phases. The same charge. Therefore, the front gate line layer 2 disposed on the front first diffusion layer 12 and the back first gate line 7 disposed on the back first diffusion layer 14 are of the same type of charge, thereby being connected to the first electrode 4. The front gate line layer 2 and the back first gate line layer 7 can simultaneously transfer charges to the first electrode 4, thereby further increasing the power of the cell sheet 100.

Wherein, the back first diffusion layer 14 and the back first gate line 7 and the back second diffusion layer 15 and the back second gate layer 6 maintain a certain safe distance, thereby effectively avoiding the first electrode 4 and the second electrode 5 are short-circuited.

For example, the backlight surface of the silicon substrate 11 may include a first region and a second region that are non-discrete and do not overlap each other, that is, when the first region is arbitrarily divided into a plurality of sub-regions, a plurality of sub-regions may be connected. Into a continuous first area. When the second area is arbitrarily divided into a plurality of sub-areas, the plurality of sub-areas may be connected to form a continuous second area. Wherein, the back diffusion layer 14 of the first type is disposed only on the first region, and the diffusion layer 15 on the back surface is disposed only on the second region, that is, the backlight of the silicon substrate 11 The region other than the first region on the surface does not have the back diffusion layer 14 of the first type, and the region other than the second region on the backlight surface of the silicon substrate 11 does not have the second diffusion layer 15 on the back surface.

In this embodiment 3, the first region and the second region are both rectangular and do not contact each other to maintain a certain safe distance. At this time, the edge of the first gate line layer 7 on the back surface of the back diffusion layer 14 may be The edges of the first region are aligned, and the edge of the second gate line layer 6 disposed on the back surface of the second type of diffusion layer 15 may be aligned with the edge of the second region, thereby improving the back first gate line layer 7 and the back surface second gate The area of the wire layer 6 is to increase the power of the battery sheet 100.

Specifically, the method for preparing the battery sheet 100 in the second embodiment is substantially the same as the method for preparing the battery sheet 1 in the first embodiment, except that when the silicon wafer 1 in the third embodiment is prepared, When the silicon substrate 11 is subjected to different types of diffusion on both sides, the front diffusion layer is extended from one side surface of the silicon substrate 11 to the backlight surface of the silicon substrate 11 to obtain a front first diffusion layer 12 and a side surface first. a diffusion-like layer and a back diffusion layer 14 of the first type, and then a passivation layer 102 of the same material as the anti-reflection layer 101 is deposited on the back diffusion layer 14 of the back surface, and then the back surface is screen printed on the passivation layer 102. The first gate line layer 6.

Example 4

Referring to FIG. 11, the structure of the embodiment 4 is substantially the same as that of the embodiment 3, wherein the same components are denoted by the same reference numerals, except that the first region and the second region in the third embodiment are in contact with each other, that is, The first diffusion layer 14 on the back side is in contact with the diffusion diffusion layer 15 on the back surface. At this time, in order to avoid short circuit between the first electrode 4 and the second electrode 5, the edge of the second gate line layer 6 on the back surface is located on the back surface of the second diffusion layer. The inner side of the edge of 15 is such that the edge of the back first gate line layer 7 is located inside the edge of the back type first diffusion layer 14.

Example 5

Referring to FIG. 12, the structure of the embodiment 5 is substantially the same as that of the embodiment 4, wherein the same components are given the same reference numerals, except that the backlight surface of the silicon substrate 11 in the embodiment 5 does not have a second type of diffusion layer 15 on the back surface, the passivation layer 102 is directly disposed on the backlight surface of the silicon substrate 11, and the second gate line layer 6 on the back surface is directly disposed on the passivation layer 102. At this time, the back second gate line layer 6 can also collect charges different from the types of charges collected on the back first gate line layer 7.

Example 6

Referring to FIGS. 13-15, the structure of the embodiment 6 is substantially the same as that of the embodiment 3, wherein the same components are given the same reference numerals, except that the first region and the second region in the embodiment 3 are both The rectangle is rectangular, and the first region and the second region in the sixth embodiment are in a non-contact type cross-shaped distribution.

In one embodiment, the first area includes a first communication area and a plurality of first dispersion areas, the plurality of first dispersion areas are spaced apart in the length direction of the first connection area and are both in communication with the first communication area, and second The area includes a second communication area and a plurality of second dispersion areas, the plurality of second dispersion areas being spaced apart in the longitudinal direction of the second communication area and each communicating with the second communication area. The number of the first dispersion region and the second dispersion region is not limited, and the shapes of the first communication region, the plurality of first dispersion regions, the second communication region, and the plurality of second dispersion regions are not limited, for example, a plurality of A dispersion region and a plurality of second dispersion regions may each be formed into a triangle, a semicircle, a rectangle, or the like, and the plurality of first dispersion regions and the plurality of second dispersion regions may be formed in a rectangular shape, a wavy band shape, or the like.

The first communication region is disposed opposite to the second communication region. For example, the first communication region is parallel or substantially parallel (having a small angle) with the second communication region, and the plurality of first dispersion regions and the plurality of second dispersion regions are disposed at The first communication region and the second communication region are alternated one by one, that is, a first dispersion region and a second dispersion are sequentially arranged along the first communication region, that is, along the length direction of the second communication region. The region, the further first dispersed region, the further second dispersed region, and so on, the plurality of first dispersed regions and the plurality of second dispersed regions are alternately alternately alternately distributed. Wherein, the contour line of the first communication region is not in contact with the contour line of the second communication region and the contour line of the second dispersion region, and the contour line of the second communication region and the contour line of the first communication region and the first dispersion region The outlines are not in contact. Thereby, it can be ensured that the first area and the second area are in a non-contact finger cross arrangement.

Example 7

FIG. 7 is substantially the same as the structure of Embodiment 6, wherein the same components are given the same reference numerals, except that the first region and the second region in this embodiment 7 are in contact. The formula refers to a cross-shaped distribution. That is, the outline of the first connected area is in contact with the outline of the second dispersed area, and the outline of the second connected area is in contact with the outline of the first dispersed area. Thereby, it can be ensured that the first area and the second area are arranged in a contact finger cross arrangement.

In the description of the present disclosure, it is to be understood that the terms "upper", "lower", "left", "right", "longitudinal", "transverse", "vertical", "horizontal", etc. indicate the orientation or The positional relationship is based on the orientation or positional relationship shown in the drawings, and is merely for the convenience of describing the present disclosure and the simplified description, and does not indicate or imply that the device or component referred to has a specific orientation, and is constructed and operated in a specific orientation. Therefore, it should not be construed as limiting the disclosure.

In the present disclosure, the terms "installation", "connected", "connected", "fixed" and the like should be understood broadly, and may be directly connected or indirectly through intermediaries, unless expressly stated otherwise. Connected, it can be the internal communication of two components or the interaction of two components. For those of ordinary skill in the art, roots can be The specific meaning of the above terms in the present disclosure is understood on a case-by-case basis. In the present disclosure, the first feature "on" or "under" the second feature may be a direct contact of the first and second features, or the first and second features may be indirectly through an intermediate medium, unless otherwise explicitly stated and defined. contact.

In the description of the present specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means a specific feature described in connection with the embodiment or example. A structure, material, or feature is included in at least one embodiment or example of the present disclosure. In the present specification, the schematic representation of the above terms is not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, various embodiments or examples described in the specification, as well as features of various embodiments or examples, may be combined and combined.

While the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art The scope of the disclosure is defined by the claims and their equivalents.

Claims (26)

1. A battery sheet, comprising:

   a silicon wafer comprising a silicon substrate, a front first diffusion layer, and a side spacer, wherein the front first diffusion layer is disposed on a light receiving surface of the silicon substrate, and the side spacer Provided on one side surface of the silicon substrate, wherein the side spacer is an insulating layer and/or a diffusion layer of the same type as the front first diffusion layer;

   a front gate line layer, the front gate line layer is disposed on the front first diffusion layer;

   a first electrode, the first electrode is disposed on the side spacer and electrically connected to the front gate line layer;

   a second electrode disposed on the other side surface of the silicon substrate and not in contact with the first electrode, the front gate line layer, and the front first diffusion layer.
2. The battery sheet according to claim 1, wherein said silicon substrate comprises opposite first and second side surfaces, said first electrode and said second electrode being respectively disposed in said first On one side surface and the second side surface.
3. The battery chip according to claim 2, wherein the first electrode and the second electrode respectively fill the first side surface and the second side surface.
4. The battery chip according to claim 2, wherein the first side surface and the second side surface are disposed in parallel.
5. The battery chip according to claim 4, wherein a distance between the first side surface and the second side surface is 20 mm to 60 mm.
6. The battery chip according to claim 5, wherein the silicon wafer is a rectangular sheet, and the first side surface and the second side surface are two long side surfaces of the silicon wafer.
7. The battery chip according to claim 1, wherein said front gate line layer comprises a plurality of front sub-gate lines extending in a direction perpendicular to said first electrode direction.
8. The battery chip according to claim 1, comprising:

   The backing layer is disposed on a backlight surface of the silicon substrate, and the backing layer is electrically connected to the second electrode and is not in contact with the first electrode.
9. The battery chip according to claim 1, wherein the back surface of the silicon substrate has a back surface layer, the back surface layer is an insulating layer and/or the same type as the front type first diffusion layer a diffusion layer, the battery sheet includes:

   a first gate line layer on the back surface, the back surface of the first gate line being disposed on the backside spacer and electrically connected to the first electrode and not in contact with the second electrode.
10. The battery chip according to claim 9, wherein said back first gate line layer comprises vertical a plurality of back first sub-gate lines extending in the first electrode direction.
11. The battery sheet according to claim 9, wherein the back spacer is a back type first diffusion layer of the same type as the front first diffusion layer, and the back first gate line is disposed at On the back side of the first type of diffusion layer.
12. The battery chip according to claim 11, wherein said back diffusion type first diffusion layer is a non-discrete layer.
13. The battery chip according to claim 1, further comprising:

    a second gate line layer on the back surface, the back second gate line layer being disposed on the backlight surface of the silicon substrate and electrically connected to the second electrode and not in contact with the first electrode.
14. The battery chip according to claim 13, wherein said back second gate line layer comprises a plurality of back surface second sub-gate lines extending in a direction perpendicular to said second electrode direction.
15. The battery chip according to claim 13, wherein the back surface of the silicon substrate has a back type second diffusion layer different from the front type first diffusion layer type, and the back second gate line A layer is disposed on the back diffusion layer of the second type.
16. The battery chip according to claim 15, wherein said back second diffusion layer is a non-discrete layer.
17. The battery chip according to claim 1, wherein the silicon wafer further comprises: a passivation layer, the passivation layer being overlaid on a backlight surface of the silicon substrate.
18. The battery chip according to claim 1, wherein the silicon wafer further comprises: an anti-reflection layer, the anti-reflection layer being overlaid on the front first diffusion layer and/or the side spacer on.
19. The battery chip according to claim 1, wherein the side spacer is an insulating layer.
20. The battery sheet according to claim 1, wherein the side spacer is a side first diffusion layer of the same type as the front first diffusion layer.
21. The battery sheet according to any one of claims 8 to 20, wherein the silicon substrate is P-type, and the front first diffusion layer is a phosphorus diffusion layer.
22. The battery sheet according to any one of claims 9 to 20, wherein the silicon substrate is N-type, and the front first diffusion layer is a boron diffusion layer.
23. A battery chip assembly, comprising:

    The battery sheet according to any one of claims 1 to 2, wherein each of the silicon wafers in each of the battery sheets includes a pair of side surfaces that are oppositely disposed in a longitudinal direction, the first electrode and the The second electrodes are respectively disposed on the pair of side surfaces, and the plurality of battery sheets are sequentially arranged in the longitudinal direction;

    a conductive member electrically connected to two electrodes adjacent to each other and respectively located on two adjacent ones of the battery sheets such that two adjacent ones of the cells are connected in series or in parallel.
24. The battery panel assembly according to claim 23, wherein said conductive member is interposed between two side surfaces of adjacent ones of said battery sheets in said longitudinal direction and adjacent to said two Two electrode points on one side surface Do not touch the electrical connection.
25. A battery chip matrix, comprising: the battery chip assembly according to claim 23 or 24, wherein the battery chip assembly is plural and connected in series and/or in parallel.
26. A solar cell, comprising: a first panel, a first bonding layer, a battery, a second bonding layer, and a second panel disposed in order from a light receiving side to a backlight side, wherein the battery is in accordance with the right A battery chip assembly according to claim 23 or 24 or a battery chip matrix according to claim 25.

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