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WO2018059375A1 - 芯片通用批键合装置及方法 - Google Patents

芯片通用批键合装置及方法 Download PDF

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Publication number
WO2018059375A1
WO2018059375A1 PCT/CN2017/103332 CN2017103332W WO2018059375A1 WO 2018059375 A1 WO2018059375 A1 WO 2018059375A1 CN 2017103332 W CN2017103332 W CN 2017103332W WO 2018059375 A1 WO2018059375 A1 WO 2018059375A1
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WIPO (PCT)
Prior art keywords
chip
area
pick
place
batch bonding
Prior art date
Application number
PCT/CN2017/103332
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English (en)
French (fr)
Inventor
郭耸
朱岳彬
陈飞彪
夏海
Original Assignee
上海微电子装备（集团）股份有限公司
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Publication date
Application filed by 上海微电子装备（集团）股份有限公司 filed Critical 上海微电子装备（集团）股份有限公司
Priority to JP2019517245A priority Critical patent/JP6847206B2/ja
Priority to KR1020197012198A priority patent/KR102191261B1/ko
Priority to US16/338,673 priority patent/US10770320B2/en
Publication of WO2018059375A1 publication Critical patent/WO2018059375A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67712—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrate being handled substantially vertically
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/67742—Mechanical parts of transfer devices
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    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
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    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75743—Suction holding means
    • H01L2224/75745—Suction holding means in the upper part of the bonding apparatus, e.g. in the bonding head
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75753—Means for optical alignment, e.g. sensors
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/758—Means for moving parts
    • H01L2224/75821—Upper part of the bonding apparatus, i.e. bonding head
    • H01L2224/75822—Rotational mechanism
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/758—Means for moving parts
    • H01L2224/75821—Upper part of the bonding apparatus, i.e. bonding head
    • H01L2224/75824—Translational mechanism
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    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7598—Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/9512—Aligning the plurality of semiconductor or solid-state bodies

Definitions

  • the present invention relates to the field of chip bonding, and in particular to a chip universal batch bonding device and method.
  • the flip chip bonding process is an interconnection form formed by connecting a chip and a carrier.
  • a plurality of chips 2 on the carrier 1 are batch-bonded to the substrate 4 in a manner of being carried by the carrier 5 .
  • the position of the plurality of chips 2 on the carrier 5 is accurately placed and adsorbed, and the chip 2 and the carrier 5 are firmly positioned during the bonding process, and the distance L between the chip 2 and the chip 2 is accurately maintained, so the string of the single chip 2
  • the row bonding is replaced by the parallel bonding of the plurality of chips 2 to effectively increase the device yield.
  • the application of chip bonding technology is increasing.
  • the chip bonding process can produce smaller package sizes and performance. Higher package form. If the chip bonding process is combined with the TSV (through-silicon via) process, a chip structure that is more cost- and performance-competitive can be produced.
  • TSV through-silicon via
  • the chip-out bonding process based on chip First is a widely used mainstream process. As shown in Figures 2a and 2b, the fan-out bonding process mainly has two types of patching methods: die-up (on-chip mark-up) and die-down (on-chip mark-down).
  • the mark 3 in the -up patch mode chip 2 is not in contact with the substrate 4, and the mark 3 of the chip 2 is in contact with the substrate 4 in the die-down patch mode.
  • different bonding devices are required for bonding, that is, the bonding device cannot be used universally, which increases the production cost.
  • Bonding technology enables maximum chip stacking and integration in a limited area without reducing linewidth, while reducing the SoC chip package size and line conduction length, thereby increasing wafer transfer efficiency.
  • Chip-to-wafer (C2W) has higher yield and lower product cost than wafer-to-wafer (W2W). Therefore, how C2W technology has higher yield while ensuring high bonding precision is the goal of the industry.
  • the invention provides a chip universal batch bonding device and method to solve the above technical problems.
  • the present invention provides a chip universal batch bonding device, which comprises a material pick-and-place area and a transfer work area, wherein:
  • the material pick-and-place area includes a blue film pick-and-place area for providing a chip, and a substrate pick-and-place area for storing the substrate, wherein the blue film pick-and-place area and the substrate pick-and-place are disposed in the transfer work area.
  • the transfer working area includes a chip pick-up and separation area, a chip alignment and fine adjustment area, and a chip batch bonding area in a direction from the blue film pick-and-place area to the substrate pick-and-place area;
  • a chip carrier transmission device is disposed in the transmission working area, the chip carrier transmission device runs through the transmission working area, in the chip picking and separating area, chip alignment and fine adjustment area, and chip batch bonding The feed is moved between zones.
  • the chip carrier transport device includes a first motion stage, a pressurizing device mounted on the first motion stage, and a carrier mounted on the pressurizing device.
  • the chip pick-up and separation area is provided with a separation table, a flipping hand and a pick-and-place device, wherein the chip alignment and fine adjustment area is provided with a fine adjustment unit, and the chip batch bonding area is provided Carrying platform.
  • the pick-and-place device comprises a bracket, the bracket is mounted with a horizontally movable shifting device, and the shifting device is mounted with a vertically movable lifting device, and the lifting device is fixedly mounted thereon Take it away.
  • the lifting device is mounted with a first alignment system.
  • the fine adjustment unit comprises a second motion stage, and a fine adjustment robot and a second alignment system mounted on the second motion stage.
  • a third alignment system is mounted on the carrier.
  • the shifting device is mounted with a plurality of lifting devices, and the pick and place hands are respectively installed under the lifting device.
  • the blue film pick-and-place area is provided with a slide table and a first robot, and the first robot picks up the chip on the slide table and transfers it to the separation table.
  • the substrate pick-and-place area is provided with a substrate library and a second robot, and the second robot picks up the bonded substrate on the loading table and transfers it to the substrate library.
  • an ejector mechanism is disposed under the separation table for jacking up the chip placed on the separation table.
  • the invention also provides a chip universal batch bonding method, which is applied to the chip universal batch bonding device as described above, comprising the following steps:
  • S2 a plurality of chips are picked up in the chip picking and separating area and simultaneously transferred to the chip alignment and fine adjustment area by the chip carrier transfer device for positional precision adjustment;
  • step S2 when the mark on the chip is required to be turned down, the flip chip pick-up chip in the chip pick-up and separation area is turned over and the chip is handed over to the chip carrier transport device.
  • the pick-and-place device in the pick-up and separation area of the chip picks up the chip, and adjusts the precision through the chip alignment and fine adjustment area, and then transfers the chip to the chip carrier device.
  • the present invention provides a chip universal batch bonding apparatus and method, the device comprising a material pick-and-place area and a transport working area, wherein: the material pick-and-place area comprises a blue film for providing a chip a discharge zone and a substrate pick-and-place area for storing the substrate, the blue film pick-and-place area and the substrate pick-and-place area Separatingly disposed at two ends of the transmission working area; the transmission working area includes a chip picking and separating area, a chip alignment and a fine adjustment area, and sequentially, in a direction from the blue film pick-and-place area to the substrate pick-and-place area; a chip carrier bonding area; a chip carrier transmission device is disposed in the transmission working area, the chip carrier transmission device runs through the transmission working area, in the chip picking and separating area, chip alignment and fine adjustment area And moving the feed between the chip batch bonding areas.
  • the invention makes the device common to two kinds of patching modes, and expands the application
  • 1 is a schematic diagram of a process flow of flip chip batch bonding
  • FIGS. 2a and 2b are schematic views of two patching methods of a diffusion bonding process, respectively;
  • FIG. 3 is a front view of a general-purpose batch bonding device for a chip according to Embodiment 1 of the present invention.
  • FIG. 4 is a top plan view of a general-purpose batch bonding device for a chip according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic structural diagram of a chip carrier transmission device according to Embodiment 1 of the present invention.
  • FIG. 6 is a schematic structural view of a pick-and-place device according to Embodiment 1 of the present invention.
  • FIG. 7 is a schematic flow chart of a method for universal batch bonding of a chip according to Embodiment 1 of the present invention.
  • FIG. 8 is a front view of a universal batch bonding device for a chip according to a second embodiment of the present invention.
  • FIG. 9 is a top plan view of a universal batch bonding device for a chip according to Embodiment 2 of the present invention.
  • FIG. 10 is a schematic structural diagram of a pick-and-place device according to Embodiment 2 of the present invention.
  • the chip universal batch bonding device provided by the invention, as shown in FIG. 3 and FIG. 4, comprises a material pick-and-place area and a transfer work area, wherein:
  • the material pick-and-place area includes a blue film pick-and-place area 110 for providing the chip 113 and a substrate pick-and-place area 120 for storing the substrate 123.
  • the blue film pick-and-place area 110 and the substrate pick-and-place area 120 are respectively disposed on The two ends of the transfer working area, the chip 113 is loaded from the blue film pick-and-place area 110, after the bonding is completed, collected to the substrate pick-and-place area 120;
  • the transfer working area includes a chip pick-up and separation area 210, a chip alignment and fine adjustment area 220, and a chip batch bonding area 230 in a direction from the blue film pick-and-place area 110 to the substrate pick-and-place area 120;
  • a chip carrier transport device 300 is disposed in the transport working area, and the chip carrier transport device 300 extends through the transport working area, in the chip pick-and-drop area 210, the chip alignment and fine adjustment area 220, and The feed is moved between the chip batch bonding areas 230.
  • the device is widely used in the die-up and die-down patching modes, and the application range of the device is expanded; in addition, the modular design can be configured according to requirements, and the market gradient of the device is increased; In addition, the invention adopts a chip batch bonding method to balance chip picking, The precise position of the chip and the bonding time of the chip enable the bonding device to improve the yield while ensuring the bonding precision.
  • the chip carrier transport device 300 includes a first motion stage 310, a pressurization device 320 mounted on the first motion stage 310, and a press device 320 mounted thereon.
  • Carrier board 330 is used for adsorbing and carrying the batch of chips 113, and bonding the batch of chips 113 to the substrate 123.
  • the pressing device 320 is used for firmly bonding the batch of chips 113 adsorbed on the carrier 330 to the substrate 123. .
  • the chip pick-up and separation area 210 is provided with a separation table 211, a flipping hand 212, and a pick-and-place device 213.
  • the chip alignment and fine adjustment area 220 is disposed.
  • the fine adjustment unit is provided with a carrying platform 231 in the chip batch bonding area 230.
  • the separation table 211 is provided with a carrier for carrying a set of chips 113 (for example, a total of n chips 113 from 1 to n).
  • each of the chips 113 is provided with a mark 114 on the die-down.
  • the flipping hand 212 is used to achieve the purpose of picking up and flipping the chip 113; in the die-up patching mode, the pick-and-place device 213 picks up and places the chip 113, and after being adjusted by the positional precision of the fine tuning unit, the chip carries
  • the board transfer device 300 transfers the chip 113 to the chip batch bonding area 230 for batch bonding with the substrate 123 on the stage 231.
  • an ejector mechanism 219 is disposed under the separating table 211 for jacking up the chip 113 placed on the separating table 211 to facilitate the flipping of the hand 212 or the taking Picking up of the device 213.
  • the pick-and-place device 213 includes a bracket 214 , and the bracket 214 is mounted with a horizontally movable shifting device 215 , and the shifting device 215 is mounted with a vertically movable
  • the lifting device 216 is fixedly mounted with the pick-and-place hand 217.
  • the shifting device 215 drives the lifting device 216 to move horizontally (X direction), and the lifting device 216 drives the pick-and-place hand 217 to move vertically (Z-direction).
  • the pick and place device 213 picks up the chip 113 from the separation table 211 and the chip 113 is accurately handed over to the fine adjustment unit.
  • the bracket 214 is further mounted with a first alignment system 218.
  • the pick and place device 213 first utilizes the first alignment system 218 when picking up the chip 113 on the separation table 211.
  • the position of the chip 113 is scanned to ensure that the take-off hand 217 accurately picks up the chip 113.
  • the fine adjustment unit includes a second motion stage 221, and a fine adjustment robot 222 and a second alignment system 223 mounted on the second motion stage 221, the second The motion stage 221 drives the fine adjustment robot 222 and the second alignment system 223 to move in the horizontal direction (X direction), so that the second alignment system 223 sequentially scans the positions of the plurality of chips 113 on the carrier 330, using the fine adjustment robot 222.
  • the plurality of chips 113 are accurately placed on the carrier 330 in accordance with the scanned position information and the required position information.
  • a third alignment system 232 is mounted on the carrier 231 for determining the position of the mark on the substrate 123 and the marking on the chip 113. Position so that the two are fully aligned.
  • the blue film pick-and-place area 110 is provided with a stage 111 and a first robot 112, and the first robot 112 picks up the stage 111.
  • the chip 113 is transferred to the separation table 211.
  • the substrate pick-up area 120 is provided with a substrate library 121 and a second robot 122.
  • the second robot 122 picks up the substrate after the bonding on the carrier 231. 123 and transferred to the substrate library 121.
  • the present invention further provides a chip universal batch bonding method, which is applied to the chip universal batch bonding apparatus as described above, and includes the following steps:
  • the chip 113 is transferred from the blue film pick-and-place area 110 and handed over to the chip pick-up and separation area 210, specifically, the first robot hand 112 grabs the slide on the stage 111 placed on the separation table 211;
  • S2 a plurality of chips 113 are picked up in the chip picking and separating area 210 and simultaneously transferred to the chip alignment and fine adjustment area 220 by the chip carrier transfer device 300 for positional precision adjustment;
  • the invention adopts the chip batch bonding mode, balances the time of chip picking, chip position fine adjustment and chip bonding, so that the bonding equipment improves the yield while ensuring the bonding precision.
  • step S2 when the mark 114 on the chip 113 is required to be bonded downward, the flipping hand 212 in the chip picking and separating area 210 picks up the chip 113, and after flipping, the chip 113 is handed over to the
  • the chip carrier transport device 300 is adjusted to the accuracy and then sent to the carrier 231 for batch bonding; when the mark 114 on the chip 113 is required to be bonded upward, the pick and place device 213 in the chip picking and separating area 210 picks up
  • the chip 113 is adjusted to the chip carrier transfer device 300 via the chip alignment and fine adjustment area 220, and is directly sent to the carrier 231 for batch bonding.
  • the invention can be widely used in the die-up and die-down patching modes, and expands the application range.
  • the present embodiment has the following differences compared with the first embodiment: a plurality of lifting devices 216 are mounted on the shifting device 215, and the lifting device 216 is respectively mounted below the lifting device 216.
  • the hand 217 is removed, that is, one movement of the shifting device 215 on the bracket 214 can simultaneously drive the movement of the plurality of chips 113, thereby improving work efficiency.
  • a plurality of fine adjustment robots 222 (shown in FIG. 8) are disposed in the chip alignment and fine adjustment area 220 to further improve work efficiency.
  • the present invention provides a chip universal batch bonding apparatus and method, the apparatus comprising a material pick-and-place area and a transport working area, wherein: the material pick-and-place area includes a blue film pick-and-place for providing the chip 113 a region 110 and a substrate pick-and-place area 120 for storing the substrate 123, the blue film pick-and-place area 110 and the substrate pick-and-place area 120 are disposed at two ends of the transfer working area;
  • the blue film pick-and-place area 110 to the substrate pick-and-place area 120 sequentially includes a chip pick-and-place area 210, a chip alignment and fine adjustment area 220, and a chip-batch bonding area 230; the chip is disposed in the transfer working area
  • the carrier board transport device 300, the chip carrier transport device 300 runs through the transfer working area, and moves between the chip pick-and-drop area 210, the chip alignment and fine adjustment area 220, and the chip batch bonding area 230. Feeding.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Robotics (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

一种芯片通用批键合装置及方法，装置包括物料取放区和传输工作区，其中：物料取放区包括用于提供芯片（113）的蓝膜片取放区（110）和用于存放基底（123）的基底取放区（120），蓝膜片取放区（110）和基底取放区（120）分设于传输工作区的两端；传输工作区沿从蓝膜片取放区（110）至基底取放区（120）的方向依次包括芯片拾取及分离区（210）、芯片对准及精调区（220）、以及芯片批键合区（230）；传输工作区内设有芯片载板传输装置（300），芯片载板传输装置（300）贯穿传输工作区，在芯片拾取及分离区（210）、芯片对准及精调区（220）、以及芯片批键合区（230）之间移动送料。通过兼容性设计，使装置通用于两种贴片方式，拓展了设备的应用范围；另外，模块化的设计可以根据需求进行配置，增加了设备的市场梯度。

Description

芯片通用批键合装置及方法 技术领域
本发明涉及芯片键合领域，特别涉及一种芯片通用批键合装置及方法。
背景技术
倒装芯片键合工艺是将芯片与载片连接形成的一种互连形式，如图1所示，将载片1上的多个芯片2以载板5承载的方式批量键合到基底4上，多个芯片2在载板5上位置被精确放置并吸附，键合过程中芯片2与载板5间被牢固定位，芯片2与芯片2间距L被精确保持，因此单个芯片2的串行键合被多个芯片2的并行键合取代从而有效提高了设备产率。另外，由于电子产品朝着轻、薄和小型化的趋势发展，使得芯片键合技术的应用日益增多，将芯片键合工艺与晶圆级封装工艺相结合，能够制作出封装尺寸更小、性能更高的封装形式。如果将芯片键合工艺与TSV(硅通孔)工艺相结合，能够制作出成本和性能更有竞争力的芯片结构。目前市场上存在3种fan-out(扩散型)键合工艺，其中基于chip First的fan-out键合工艺是得到广泛应用的主流工艺形式。如图2a和2b所示，fan-out(扩散型)键合工艺主要有die-up(芯片上标记朝上)和die-down(芯片上标记朝下)两种贴片方式，其中，die-up贴片方式芯片2中标记3不与基底4接触，die-down贴片方式中，芯片2的标记3与基底4接触。针对上述两种贴片方式，需要采用不同的键合装置进行键合，即键合装置不能通用，增加了生产成本。
另一方面，键合技术能够在不缩小线宽的情况下，在有限面积内进行最大程度的芯片叠加与整合，同时缩减SoC晶片封装体积与线路传导长度，进而提升晶片传输效率。芯片-晶圆键合技术(chip-to-wafer，C2W)相对于晶圆-晶圆键合技术(wafer-to-wafer，W2W)具有更高的良率和更低的产品成本。 因此，C2W技术如何在保证高键合精度的同时具有更高的产率是业界努力的目标。
发明内容
本发明提供一种芯片通用批键合装置及方法，以解决上述技术问题。
为解决上述技术问题，本发明提供一种芯片通用批键合装置，包括物料取放区和传输工作区，其中：
所述物料取放区包括用于提供芯片的蓝膜片取放区和用于存放基底的基底取放区，所述蓝膜片取放区和基底取放区分设于所述传输工作区的两端；
所述传输工作区沿从所述蓝膜片取放区至基底取放区的方向依次包括芯片拾取及分离区、芯片对准及精调区、以及芯片批键合区；
所述传输工作区内设有芯片载板传输装置，所述芯片载板传输装置贯穿所述传输工作区，在所述芯片拾取及分离区、芯片对准及精调区、以及芯片批键合区之间移动送料。
较佳地，所述芯片载板传输装置包括第一运动台、安装于所述第一运动台上的加压装置以及安装于所述加压装置上的载板。
较佳地，所述芯片拾取及分离区内设有分离台、翻转手以及取放装置，所述芯片对准及精调区内设有精调单元，所述芯片批键合区内设有承载台。
较佳地，所述取放装置包括支架，所述支架上安装有可水平移动的移位装置，所述移位装置上安装有可垂向移动的升降装置，所述升降装置上固定安装有取放手。
较佳地，所述升降装置上安装有第一对准系统。
较佳地，所述精调单元包括第二运动台、以及安装于所述第二运动台上的精调机械手和第二对准系统。
较佳地，所述承载台上安装有第三对准系统。
较佳地，所述移位装置上安装有多个升降装置，每个所述升降装置下方分别安装有所述取放手。
较佳地，所述蓝膜片取放区内设有载片台和第一机械手，所述第一机械手拾取所述载片台上的芯片移送至所述分离台上。
较佳地，所述基底取放区内设有基片库和第二机械手，所述第二机械手拾取所述承载台上键合完成后的基底，并移送至所述基片库。
较佳地，所述分离台下方设有顶出机构，用于将放置于所述分离台上的芯片顶起。
本发明还提供了一种芯片通用批键合方法，应用于如上所述的芯片通用批键合装置中，包括如下步骤：
S1：将芯片从所述蓝膜片取放区传输并交接至所述芯片拾取及分离区；
S2：多个芯片在所述芯片拾取及分离区内被拾取并利用芯片载板传输装置同时传递至所述芯片对准及精调区进行位置精度调整；
S3：位置调整完成后的所述多个芯片利用所述芯片载板传输装置传递至所述芯片批键合区完成批量键合。
较佳地，在步骤S2中，当要求芯片上的标记朝下键合时，所述芯片拾取及分离区内的翻转手拾取芯片，翻转后将所述芯片交接至所述芯片载板传输装置；当要求芯片上的标记朝上键合时，所述芯片拾取及分离区内的取放装置拾取芯片，经由所述芯片对准及精调区调整精度后交接至所述芯片载板传输装置。
与现有技术相比，本发明提供的芯片通用批键合装置及方法，该装置包括物料取放区和传输工作区，其中：所述物料取放区包括用于提供芯片的蓝膜片取放区和用于存放基底的基底取放区，所述蓝膜片取放区和基底取放区 分设于所述传输工作区的两端；所述传输工作区沿从所述蓝膜片取放区至基底取放区的方向依次包括芯片拾取及分离区、芯片对准及精调区、以及芯片批键合区；所述传输工作区内设有芯片载板传输装置，所述芯片载板传输装置贯穿所述传输工作区，在所述芯片拾取及分离区、芯片对准及精调区、以及芯片批键合区之间移动送料。本发明通过兼容性设计，使装置通用于两种贴片方式，拓展了设备的应用范围；另外，模块化的设计可以根据需求进行配置，增加了设备的市场梯度。
附图说明
图1为倒装芯片批键合的工艺流程示意图；
图2a和2b分别为扩散型键合工艺的两种贴片方法的示意图；
图3为本发明实施例一中芯片通用批键合装置的主视图；
图4为本发明实施例一中芯片通用批键合装置的俯视图；
图5为本发明实施例一中芯片载板传输装置的结构示意图；
图6为本发明实施例一中取放装置的结构示意图；
图7为本发明实施例一中芯片通用批键合方法的流程示意图；
图8为本发明实施例二中芯片通用批键合装置的主视图；
图9为本发明实施例二中芯片通用批键合装置的俯视图；
图10为本发明实施例二中取放装置的结构示意图。
图1-2b中：1-载片、2-芯片、3-标记、4-基底、5-载板；
图3-10中：110-蓝膜片取放区、111-载片台、112-第一机械手、113-芯片、114-标记；120-基底取放区、121-基片库、122-第二机械手、123-基底；210-芯片拾取及分离区、211-分离台、212-翻转手、213-取放装置、214-支架、215-移位装置、216-升降装置、217-取放手、218-第一对准系统、219-顶出机构；220-芯片对准及精调区、221-第二运动台、222-精调机械手、223-第二对准系 统；230-芯片批键合区、231-承载台、232-第三对准系统；300-芯片载板传输装置、310-第一运动台、320-加压装置、330-载板。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。需说明的是，本发明附图均采用简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
实施例一
本发明提供的芯片通用批键合装置，如图3和图4所示，包括物料取放区和传输工作区，其中：
所述物料取放区包括用于提供芯片113的蓝膜片取放区110和用于存放基底123的基底取放区120，所述蓝膜片取放区110和基底取放区120分设于所述传输工作区的两端，芯片113从蓝膜片取放区110上料，键合完成后，收集至基底取放区120；
所述传输工作区沿从所述蓝膜片取放区110至基底取放区120的方向依次包括芯片拾取及分离区210、芯片对准及精调区220、以及芯片批键合区230；
所述传输工作区内设有芯片载板传输装置300，所述芯片载板传输装置300贯穿所述传输工作区，在所述芯片拾取及分离区210、芯片对准及精调区220、以及芯片批键合区230之间移动送料。
本发明通过兼容性设计，使装置通用于die-up和die-down两种贴片方式，拓展了设备的应用范围；另外，模块化的设计可以根据需求进行配置，增加了设备的市场梯度；另外，本发明采用芯片批键合方式，平衡了芯片拾取、 芯片位置精调和芯片键合的时间，使键合设备在保证键合精度的同时提高了产率。
较佳地，请重点参考图5，所述芯片载板传输装置300包括第一运动台310、安装于所述第一运动台310上的加压装置320以及安装于所述加压装置320上的载板330。所述载板330用于吸附、承载批量的芯片113，并将批量的芯片113键合到基底123上，加压装置320用于使载板330上吸附的批量的芯片113与基底123牢固结合。
较佳地，请重点参考图3和图4，所述芯片拾取及分离区210内设有分离台211、翻转手212以及取放装置213，所述芯片对准及精调区220内设有精调单元，所述芯片批键合区230内设有承载台231。具体地，分离台211上设有一用于承载一组芯片113(例如从1～n共n个芯片113)的载片，当然，每个芯片113上方均设有标记114，在die-down贴片方式时，采用翻转手212实现拾取和翻转芯片113的目的；在die-up贴片方式时，采用取放装置213拾取和放置芯片113，经过精调单元的位置精度调整后，由芯片载板传输装置300将芯片113移送至芯片批键合区230，与承载台231上的基底123进行批键合。
较佳地，请继续参考图3，所述分离台211下方设有顶出机构219，用于将放置于所述分离台211上的芯片113顶起，便于所述翻转手212或所述取放装置213的拾取。
较佳地，请重点参考图6，所述取放装置213包括支架214，所述支架214上安装有可水平移动的移位装置215，所述移位装置215上安装有可垂向移动的升降装置216，所述升降装置216上固定安装有取放手217，所述移位装置215带动升降装置216水平移动(X向)，升降装置216带动取放手217垂向(Z向)移动，便于取放装置213从分离台211上拾取芯片113以及将芯片 113准确交接至精调单元。
较佳地，请继续参考图3，所述支架214上还安装有第一对准系统218，所述取放装置213在拾取分离台211上的芯片113时，先利用第一对准系统218对芯片113位置进行扫描，确保取放手217准确拾取芯片113。
较佳地，请继续参考图3，所述精调单元包括第二运动台221、以及安装于所述第二运动台221上的精调机械手222和第二对准系统223，所述第二运动台221带动精调机械手222和第二对准系统223在水平向(X向)移动，使第二对准系统223依次扫描载板330上的多个芯片113的位置，利用精调机械手222按照扫描的位置信息及所需的位置信息将多个芯片113精确放置到载板330上。
较佳地，请继续参考图3，所述承载台231上安装有第三对准系统232，所述第三对准系统232用于确定基底123上标记的位置，以及芯片113上的标记的位置，使二者完全对准键合。
较佳地，请继续参考图3和图4，所述蓝膜片取放区110内设有载片台111和第一机械手112，所述第一机械手112拾取所述载片台111上的芯片113移送至所述分离台211上；所述基底取放区120内设有基片库121和第二机械手122，所述第二机械手122拾取所述承载台231上键合完成后的基底123，并移送至所述基片库121。
请重点参考图7，本发明还提供了一种芯片通用批键合方法，应用于如上所述的芯片通用批键合装置中，包括如下步骤：
S1：将芯片113从所述蓝膜片取放区110传输并交接至芯片拾取及分离区210，具体地，第一机械手112抓取载片台111上的载片放置于分离台211；
S2：多个芯片113在所述芯片拾取及分离区210内被拾取并利用芯片载板传输装置300同时传递至所述芯片对准及精调区220进行位置精度调整；
S3：位置调整完成后，利用所述芯片载板传输装置300将所述多个芯片113传递至所述芯片批键合区230完成批量键合。
本发明采用芯片批键合方式，平衡了芯片拾取、芯片位置精调和芯片键合的时间，使键合设备在保证键合精度的同时提高了产率。
较佳地，在步骤S2中，当要求芯片113上的标记114朝下键合时，所述芯片拾取及分离区210内的翻转手212拾取芯片113，翻转后将所述芯片113交接至所述芯片载板传输装置300，调整精度后送至承载台231上批键合；当要求芯片113上的标记114朝上键合时，所述芯片拾取及分离区210内的取放装置213拾取芯片113，经由所述芯片对准及精调区220调整精度后交接至所述芯片载板传输装置300，直接送至承载台231上批键合。本发明可通用于die-up和die-down两种贴片方式，拓展了应用范围。
实施例二
请重点参考图8至图10，本实施例相较于实施例一具有如下区别：所述移位装置215上安装有多个升降装置216，每个所述升降装置216下方分别安装有所述取放手217，也就是说，移位装置215在支架214上的一次移动，可同时带动多个芯片113移动，提高工作效率，当然，为了配合多个取放手217的同时取放，还可在芯片对准及精调区220内设置多个精调机械手222(如图8所示)，进一步提高工作效率。
综上所述，本发明提供的芯片通用批键合装置及方法，该装置包括物料取放区和传输工作区，其中：所述物料取放区包括用于提供芯片113的蓝膜片取放区110和用于存放基底123的基底取放区120，所述蓝膜片取放区110和基底取放区120分设于所述传输工作区的两端；所述传输工作区沿从所述 蓝膜片取放区110至基底取放区120的方向依次包括芯片拾取及分离区210、芯片对准及精调区220、以及芯片批键合区230；所述传输工作区内设有芯片载板传输装置300，所述芯片载板传输装置300贯穿所述传输工作区，在所述芯片拾取及分离区210、芯片对准及精调区220、以及芯片批键合区230之间移动送料。本发明通过兼容性设计，使装置通用于两种贴片方式，拓展了设备的应用范围；另外，模块化的设计可以根据需求进行配置，增加了设备的市场梯度。
显然，本领域的技术人员可以对发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包括这些改动和变型在内。

Claims (13)

  1. 一种芯片通用批键合装置，其特征在于，包括物料取放区和传输工作区，其中：
    所述物料取放区包括用于提供芯片的蓝膜片取放区和用于存放基底的基底取放区，所述蓝膜片取放区和基底取放区分设于所述传输工作区的两端；
    所述传输工作区沿从所述蓝膜片取放区至基底取放区的方向依次包括芯片拾取及分离区、芯片对准及精调区、以及芯片批键合区；
    所述传输工作区内设有芯片载板传输装置，所述芯片载板传输装置贯穿所述传输工作区，在所述芯片拾取及分离区、芯片对准及精调区、以及芯片批键合区之间移动送料。
  2. 如权利要求1所述的芯片通用批键合装置，其特征在于，所述芯片载板传输装置包括第一运动台、安装于所述第一运动台上的加压装置以及安装于所述加压装置上的载板。
  3. 如权利要求2所述的芯片通用批键合装置，其特征在于，所述芯片拾取及分离区内设有分离台、翻转手以及取放装置，所述芯片对准及精调区内设有精调单元，所述芯片批键合区内设有承载台。
  4. 如权利要求3所述的芯片通用批键合装置，其特征在于，所述取放装置包括支架，所述支架上安装有可水平移动的移位装置，所述移位装置上安装有可垂向移动的升降装置，所述升降装置上固定安装有取放手。
  5. 如权利要求4所述的芯片通用批键合装置，其特征在于，所述升降装置上安装有第一对准系统。
  6. 如权利要求5所述的芯片通用批键合装置，其特征在于，所述精调单元包括第二运动台、以及安装于所述第二运动台上的精调机械手和第二对准系统。
  7. 如权利要求6所述的芯片通用批键合装置，其特征在于，所述承载台上安装有第三对准系统。
  8. 如权利要求4所述的芯片通用批键合装置，其特征在于，所述移位装置上安装有多个升降装置，每个所述升降装置下方分别安装有所述取放手。
  9. 如权利要求3所述的芯片通用批键合装置，其特征在于，所述蓝膜片取放区内设有载片台和第一机械手，所述第一机械手拾取所述载片台上的芯片移送至所述分离台上。
  10. 如权利要求3所述的芯片通用批键合装置，其特征在于，所述基底取放区内设有基片库和第二机械手，所述第二机械手拾取所述承载台上键合完成后的基底，并移送至所述基片库。
  11. 如权利要求3所述的芯片通用批键合装置，其特征在于，所述分离台下方设有顶出机构，用于将放置于所述分离台上的芯片顶起。
  12. 一种芯片通用批键合方法，应用于如权利要求1所述的芯片通用批键合装置中，其特征在于，包括如下步骤：
    S1：将芯片从所述蓝膜片取放区传输并交接至所述芯片拾取及分离区；
    S2：多个芯片在所述芯片拾取及分离区内被拾取并利用芯片载板传输装置同时传递至所述芯片对准及精调区进行位置精度调整；
    S3：位置调整完成后的所述多个芯片利用所述芯片载板传输装置传递至所述芯片批键合区完成批量键合。
  13. 如权利要求12所述的芯片通用批键合方法，其特征在于，在步骤S2中，当要求芯片上的标记朝下键合时，所述芯片拾取及分离区内的翻转手拾取芯片，翻转后将所述芯片交接至所述芯片载板传输装置；当要求芯片上的标记朝上键合时，所述芯片拾取及分离区内的取放装置拾取芯片，经由所述芯片对准及精调区调整精度后交接至所述芯片载板传输装置。
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