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WO2017222151A1 - Epoxy resin composition for sealing solid state semiconductor device, encapsulating material comprising same, and semiconductor package - Google Patents

Epoxy resin composition for sealing solid state semiconductor device, encapsulating material comprising same, and semiconductor package Download PDF

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Publication number
WO2017222151A1
WO2017222151A1 PCT/KR2017/003325 KR2017003325W WO2017222151A1 WO 2017222151 A1 WO2017222151 A1 WO 2017222151A1 KR 2017003325 W KR2017003325 W KR 2017003325W WO 2017222151 A1 WO2017222151 A1 WO 2017222151A1
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WO
WIPO (PCT)
Prior art keywords
group
resin composition
sealing
epoxy resin
substrate
Prior art date
Application number
PCT/KR2017/003325
Other languages
French (fr)
Korean (ko)
Inventor
이윤만
배경철
박용엽
이은정
Original Assignee
삼성에스디아이 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 삼성에스디아이 주식회사 filed Critical 삼성에스디아이 주식회사
Priority to CN201780038924.2A priority Critical patent/CN109328204B/en
Publication of WO2017222151A1 publication Critical patent/WO2017222151A1/en

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    • CCHEMISTRY; METALLURGY
    • C08ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08GMACROMOLECULAR COMPOUNDS OBTAINED OTHERWISE THAN BY REACTIONS ONLY INVOLVING UNSATURATED CARBON-TO-CARBON BONDS
    • C08G59/00Polycondensates containing more than one epoxy group per molecule; Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups
    • C08G59/18Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups ; e.g. general methods of curing
    • C08G59/20Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups ; e.g. general methods of curing characterised by the epoxy compounds used
    • C08G59/22Di-epoxy compounds
    • C08G59/28Di-epoxy compounds containing acyclic nitrogen atoms
    • CCHEMISTRY; METALLURGY
    • C08ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08JWORKING-UP; GENERAL PROCESSES OF COMPOUNDING; AFTER-TREATMENT NOT COVERED BY SUBCLASSES C08B, C08C, C08F, C08G or C08H
    • C08J5/00Manufacture of articles or shaped materials containing macromolecular substances
    • C08J5/18Manufacture of films or sheets
    • CCHEMISTRY; METALLURGY
    • C08ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08LCOMPOSITIONS OF MACROMOLECULAR COMPOUNDS
    • C08L63/00Compositions of epoxy resins; Compositions of derivatives of epoxy resins
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • H01L23/296Organo-silicon compounds
    • CCHEMISTRY; METALLURGY
    • C08ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08LCOMPOSITIONS OF MACROMOLECULAR COMPOUNDS
    • C08L2203/00Applications
    • C08L2203/16Applications used for films
    • C08L2203/162Applications used for films sealable films
    • CCHEMISTRY; METALLURGY
    • C08ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08LCOMPOSITIONS OF MACROMOLECULAR COMPOUNDS
    • C08L2203/00Applications
    • C08L2203/20Applications use in electrical or conductive gadgets

Definitions

  • the present invention relates to an epoxy resin composition for semiconductor encapsulation, an encapsulant and a semiconductor package including the same. More specifically, the present invention relates to an epoxy resin composition for sealing a solid phase semiconductor, which can minimize warpage due to a low coefficient of thermal expansion and a high glass transition temperature, and an encapsulant and a semiconductor package including the same.
  • the method of sealing a semiconductor element with an epoxy resin composition is commercially performed for the purpose of protecting a semiconductor element from external environments, such as moisture or a mechanical shock.
  • semiconductor chips are manufactured by cutting a wafer to manufacture semiconductor chips, and then packaging is performed in units of semiconductor chips, but packaging is performed in a wafer state not recently cut, and then semiconductor chips.
  • a process of cutting with a has been developed. In general, the former method is called Chip Scale Package (CSP) and the latter process is called Wafer Level Packaging (WLP).
  • CSP Chip Scale Package
  • WLP Wafer Level Packaging
  • Wafer-level packaging has advantages in that the process is simpler than the chip scale packaging process, and the package thickness is reduced, thereby reducing the semiconductor mounting space.
  • the wafer level packaging has a problem in that warpage due to the difference in thermal expansion rate between the wafer and the encapsulant is large because the film forming area is larger than that of the chip scale packaging for sealing the individual chips. If warping occurs, it will affect the yield and wafer handling of subsequent processes.
  • liquid type epoxy resin or silicone resin is mainly used as an encapsulant for wafer level packaging.
  • these encapsulants have poor storage stability, which is poor in storageability, impossible to re-storage after aging, and a filler content in the composition.
  • Another object of the present invention is to provide an epoxy resin composition for solid-state particulate semiconductor sealing, which can realize excellent durability even when applied to wafer level packaging, and is easy to store and use.
  • Still another object of the present invention is to provide an epoxy resin composition for semiconductor encapsulation having excellent adhesion to a redistribution layer (RDL).
  • RDL redistribution layer
  • Still another object of the present invention is to provide an epoxy resin composition for semiconductor encapsulation, which can realize excellent reliability with low moisture absorption.
  • Still another object of the present invention is to provide an encapsulant and a semiconductor package including the epoxy resin composition for semiconductor encapsulation as described above.
  • the solid-state semiconductor element sealing resin composition is an epoxy resin containing a compound represented by the formula (1); Curing agent; And inorganic fillers.
  • R1 to R12 are each independently hydrogen, a substituent containing a nitrogen atom, a substituted or unsubstituted C1-C20 alkyl group, a substituted or unsubstituted C6-C30 aryl group, a substituted or unsubstituted C3-C30 A heteroaryl group, a substituted or unsubstituted C3-C10 heterocycloalkyl group, a substituted or unsubstituted C7-C30 arylalkyl group, or a substituted or unsubstituted C1-C30 heteroalkyl group, at least one of the above R1 to R12 At least one is a substituted or unsubstituted C 6 -C 30 aryl group or a substituent containing a nitrogen atom.
  • the C6 ⁇ C30 aryl group may be a phenyl group, biphenyl group, naphthyl group, naphthol group, or anthracenyl group.
  • the epoxy resin may include at least one or more of the compounds represented by Formulas 1a to 1d.
  • the composition may comprise about 0.1 to about 15 weight percent of the epoxy resin, about 0.1 to about 13 weight percent of the curing agent and about 70 to about 95 weight percent of the inorganic filler.
  • the encapsulant includes the resin composition for sealing the solid-state semiconductor element.
  • the encapsulant may be tablet type, film type or sheet type.
  • Another aspect of the invention relates to a semiconductor package.
  • the semiconductor package comprises a substrate; A semiconductor device mounted on the substrate; A sealing layer formed on the substrate to encapsulate at least a portion of the semiconductor device; And a connection terminal formed under the substrate, wherein the sealing layer includes the resin composition for sealing the solid-state semiconductor element.
  • the substrate may be a circuit board, a lead frame substrate or a substrate including a redistribution layer.
  • the semiconductor device may be one in which a plurality of semiconductor chips are electrically stacked through a through silicon via (TSV).
  • TSV through silicon via
  • the semiconductor package includes a substrate including a redistribution layer; A semiconductor device disposed on the redistribution layer; A sealing layer formed on the redistribution layer to seal at least a portion of the semiconductor device; And a connection terminal formed under the substrate, wherein the sealing layer includes the resin composition for sealing the solid-state semiconductor element.
  • the semiconductor package comprises a substrate; A semiconductor device mounted on the substrate through an adhesive member, wherein a plurality of semiconductor chips are electrically stacked through a through silicon via (TSV); A connection terminal is formed below the substrate, and the sealing layer includes the resin composition for sealing the solid-state semiconductor device.
  • TSV through silicon via
  • the present invention has a low coefficient of thermal expansion, high glass transition temperature to minimize warpage, excellent durability even when applied to wafer level packaging, and is easy to store and use in a solid rather than liquid form.
  • RDL re-distribution layer
  • FIG. 1 is a view schematically showing an embodiment of a semiconductor package according to the present invention.
  • FIG. 2 is a view schematically showing another embodiment of a semiconductor package according to the present invention.
  • Positional relationships such as 'top', 'top', 'bottom', and 'bottom' are described based on the drawings and do not represent absolute positional relationships. That is, the positions of the 'top' and 'bottom' or 'top' and 'bottom' may be changed depending on the position to be observed.
  • substituted in “substituted or unsubstituted” means that at least one hydrogen atom of the functional group is a hydroxyl group, a halogen, an amino group, a nitro group, a cyano group, a carboxyl group, a C1-C20 alkyl group, a C1-C20 Alkenyl group, C1-C20 alkynyl group, C1-C20 haloalkyl group, C6-C30 aryl group, C3-C30 heteroaryl group, C3-C10 cycloalkyl group, C3-C10 heterocycloalkyl group, C7-C30 An arylalkyl group, C1 ⁇ C30 It is substituted with a heteroalkyl group, "halogen” means fluorine, chlorine, iodine or bromine.
  • aryl group means a substituent in which all elements of a cyclic substituent have p-orbital and p-orbital forms a conjugate, and a single ring structure or two or more rings are fused. It includes a multi-ring structure, for example, it may mean a phenyl group, biphenyl group, naphthyl group, naphthol group, anthracenyl group and the like, but is not limited thereto.
  • the "heteroaryl group” means one to three atoms selected from the group consisting of nitrogen, oxygen, sulfur and phosphorus in the aryl group of C6 to C30 and the rest are carbon, for example, Dinyl, pyrazinyl, pyrimidinyl, pyridazinyl, triazinyl, quinolinyl, isoquinolinyl, quinoxalinyl, acridinyl, quinazolinyl, cshinolinyl, phthalazinyl, thiazolyl, benzothia Zolyl, isoxazolyl, benzisoxazolyl, oxazolyl, benzoxazolyl, pyrazolyl, indazolyl, imidazolyl, benzimidazolyl, furinyl, thiophenyl, benzothiophenyl, furanyl, benzofuranyl, iso Benzofuranyl, and the like,
  • 'hetero' in the 'heterocycloalkyl group', 'heteroaryl group', 'heterocycloalkylene group', and 'heteroarylene group' means nitrogen, oxygen, sulfur or phosphorus atoms.
  • X-Y which shows a range means "X or more and Y or less.”
  • the epoxy resin composition of this invention contains (A) epoxy resin, (B) hardening
  • the epoxy resin used in the present invention includes an alicyclic epoxy compound represented by the following formula (1).
  • R1 to R12 are each independently a substituent containing a hydrogen, a nitrogen atom, substituted or unsubstituted C1 ⁇ C20 alkyl group, substituted or unsubstituted C6 ⁇ C30 aryl group, substituted or unsubstituted C3 ⁇ C30 heteroaryl group, substituted or unsubstituted C3 ⁇ C10 heterocycloalkyl group, substituted or unsubstituted C7 ⁇ C30 is an arylalkyl group or a substituted or unsubstituted C1-C30 heteroalkyl group, and at least one of R1 to R12 is a substituted or unsubstituted C6 to C30 aryl group or a substituent containing a nitrogen atom.
  • the C6 to C30 aryl group may be a phenyl group, biphenyl group, naphthyl group, naphthol group or anthracenyl group.
  • the compound having an alicyclic epoxy structure as shown in Formula 1 has a high coefficient of thermal expansion and a high glass transition temperature, it is possible to effectively suppress warpage of a semiconductor package by using an epoxy resin to which the compound is applied.
  • the compound having an alicyclic epoxy structure as shown in Formula 1 and containing a substituent containing a nitrogen atom as the epoxy resin it is possible to excellently implement the adhesive force with the redistribution layer (Re-Distribution Layer, RDL).
  • the semiconductor device is sealed on the carrier wafer to facilitate packaging of the input / output terminals, the carrier wafer is removed, and the sealed semiconductor device is formed on the substrate on which the dielectric and metal layers are alternately stacked. A method of relocating on (Re-Distribution Layer, RDL) is used.
  • the redistribution layer (RDL) is formed by using a negative photoresist such as polybenzoazole, the adhesion force between the epoxy resin and the redistribution layer when a substituent containing a nitrogen atom is included in the epoxy resin. This improved effect can be obtained.
  • the compound having an alicyclic epoxy structure as shown in the general formula (1) and containing a C6 ⁇ C30 aryl group as the epoxy resin it is possible to obtain the effect of improving the moisture absorption of the epoxy resin.
  • the moisture absorption is high and the reliability of the semiconductor after packaging is somewhat lowered.
  • the C6-C30 aryl group is included as a substituent in the alicyclic epoxy structure as in the present invention, the moisture absorption rate is lowered, thereby improving reliability.
  • the epoxy resin may include at least one or more of the compounds represented by Formulas 1a to 1d.
  • the epoxy resin comprising the compound represented by Formula 1 is about 0.1 to about 15% by weight of the epoxy resin composition for sealing semiconductor devices, for example about 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7 , 0.8, 0.9, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 or 15% by weight, one or more of the above values and a range below one of the above values It may be included as. It may also be included in an amount of about 3 to about 15 weight percent, more specifically about 3 to about 12 weight percent.
  • curing agents generally used for sealing semiconductor devices may be used without limitation, and preferably, curing agents having two or more reactors may be used.
  • a phenol aralkyl type phenol resin such as acid anhydride, metaphenylenediamine, diaminodiphenylmethane, diaminodiphenylsulfone, and the like may be used, but are not limited thereto.
  • the curing agent may include one or more of phenol novolak-type phenol resin, xylox phenol resin, phenol aralkyl type phenol resin, and polyfunctional phenol resin.
  • the phenol novolak type phenol resin may be, for example, a phenol novolak type phenol resin represented by the following formula (2).
  • the phenol novolak-type phenolic resin represented by Chemical Formula 2 has a short crosslinking point spacing, and when reacted with an epoxy resin, the crosslinking density becomes high, thereby increasing the glass transition temperature of the cured product, thereby lowering the coefficient of linear expansion of the cured product. The warpage of the package can be more effectively suppressed.
  • the phenol aralkyl type phenol resin may be, for example, a phenol aralkyl type phenol resin having a novolak structure containing a biphenyl derivative in a molecule represented by the following formula (3).
  • the phenol aralkyl type phenol resin represented by Chemical Formula 3 forms a carbon layer (char) by reacting with the epoxy resin to block the transfer of heat and oxygen in the surroundings to achieve flame retardancy.
  • Xylox type phenol resin may be, for example, "xylok” type phenol resin represented by the following formula (4).
  • the average value of f is 0 to 7.
  • the xylox phenol resin represented by the formula (4) is preferable in view of fluidity and reliability strengthening of the resin composition.
  • the polyfunctional phenol resin may be, for example, a polyfunctional phenol resin containing a repeating unit represented by the following formula (5).
  • the polyfunctional phenol resin containing the repeating unit represented by the formula (5) is preferable in view of enhancing the high temperature bending characteristics of the epoxy resin composition.
  • curing agents may be used alone or in combination.
  • addition agent which made the said hardening agent and other components such as an epoxy resin, a hardening accelerator, a mold release agent, a coupling agent, and a stress relaxation agent, pre-reacts, such as a melt master batch, can also be used as a compound.
  • the curing agent is about 0.1 to about 13% by weight of the epoxy resin composition for sealing the semiconductor device, for example about 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 2, 3 , 4, 5, 6, 7, 8, 9, 10, 11, 12 or 13% by weight, may be included in the range of one or more of the above values and one or less of the above values. It may also be included in an amount of about 0.1 to about 10% by weight, more specifically about 0.1 to about 8% by weight.
  • the blending ratio of the epoxy resin and the curing agent may be adjusted according to the requirements of mechanical properties and moisture resistance reliability in the package.
  • the chemical equivalent ratio of the epoxy resin to the curing agent may be about 0.95 to about 3, specifically about 1 to about 2, more specifically about 1 to about 1.75.
  • the inorganic filler is for improving the mechanical properties and low stress of the epoxy resin composition.
  • general inorganic fillers used in semiconductor sealing materials can be used without limitation, and are not particularly limited.
  • fused silica, crystalline silica, calcium carbonate, magnesium carbonate, alumina, magnesia, clay, talc, calcium silicate, titanium oxide, antimony oxide, glass fiber, etc. may be used. Can be. These may be used alone or in combination.
  • molten silica having a low coefficient of linear expansion is used to reduce stress.
  • Fused silica refers to amorphous silica having a specific gravity of about 2.3 or less, and also includes amorphous silica made by melting crystalline silica or synthesized from various raw materials.
  • the shape and particle diameter of the molten silica are not particularly limited, but about 1 to about spherical molten silica having a spherical molten silica having an average particle diameter of about 5 to about 30 ⁇ m, and an average particle diameter of about 0.001 to about 1 ⁇ m.
  • the molten silica mixture including about 50% by weight, is included from about 40% to about 100% by weight of the total filler.
  • the maximum particle diameter can be adjusted to any one of about 45 micrometers, about 55 micrometers, and about 75 micrometers, and can be used.
  • conductive carbon may be included as a foreign material on the silica surface, but it is also important to select a material containing less polar foreign matter.
  • the amount of the inorganic filler used depends on the required physical properties such as formability, low stress, and high temperature strength.
  • the inorganic filler is about 70 to about 95 weight percent of the epoxy resin composition, for example about 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94 or 95% by weight, may be included in the range of one or more of the above values and one or less of the above values. It may also specifically comprise about 80 to about 90% by weight or about 83 to about 97% by weight.
  • the epoxy resin composition according to the present invention may further include one or more of a curing accelerator, a coupling agent, a mold releasing agent, and a coloring agent.
  • a hardening accelerator is a substance which accelerates reaction of an epoxy resin and a hardening
  • a tertiary amine, an organometallic compound, an organophosphorus compound, an imidazole, a boron compound, etc. can be used, for example.
  • Tertiary amines include benzyldimethylamine, triethanolamine, triethylenediamine, diethylaminoethanol, tri (dimethylaminomethyl) phenol, 2-2- (dimethylaminomethyl) phenol, 2,4,6-tris (diaminomethyl ) Phenol and tri-2-ethylhexyl acid salt.
  • organometallic compound examples include chromium acetylacetonate, zinc acetylacetonate, nickel acetylacetonate, and the like.
  • Organophosphorus compounds include tris-4-methoxyphosphine, tetrabutylphosphonium bromide, tetraphenylphosphonium bromide, phenylphosphine, diphenylphosphine, triphenylphosphine, triphenylphosphine triphenylborane, triphenylphosphate And pin-1,4-benzoquinones adducts.
  • the imidazoles include 2-phenyl-4methylimidazole, 2-methylimidazole, # 2-phenylimidazole, # 2-aminoimidazole, 2-methyl-1-vinylimidazole, and 2-ethyl-4.
  • boron compound examples include tetraphenylphosphonium-tetraphenylborate, triphenylphosphine tetraphenylborate, tetraphenylboron salt, trifluoroborane-n-hexylamine, trifluoroborane monoethylamine, tetrafluoro Roboranetriethylamine, tetrafluoroboraneamine, and the like.
  • 1, 5- diazabicyclo [4.3.0] non-5-ene (1, 5- diazabicyclo [4.3.0] non-5-ene: DBN)
  • 1, 8- diazabicyclo [5.4. 0] undec-7-ene 1,8-diazabicyclo [5.4.0] undec-7-ene: DBU
  • phenol novolak resin salts and the like.
  • an organophosphorus compound, a boron compound, an amine type, or an imidazole series hardening accelerator can be used individually or in mixture as said hardening accelerator.
  • the curing accelerator may also use an epoxy resin or an adduct made by preliminary reaction with a curing agent.
  • the amount of the curing accelerator used in the present invention may be about 0.01 to about 2% by weight, specifically about 0.02 to about 1.5% by weight, and more specifically about 0.05 to about 1% by weight, based on the total weight of the epoxy resin composition. In the above range, there is an advantage that the curing of the epoxy resin composition is promoted and the degree of curing is also good.
  • the coupling agent is for improving the interfacial strength by reacting between the epoxy resin and the inorganic filler.
  • the coupling agent may be a silane coupling agent.
  • the said silane coupling agent may react between an epoxy resin and an inorganic filler, and what is necessary is just to improve the interface strength of an epoxy resin and an inorganic filler,
  • the kind is not specifically limited.
  • Specific examples of the silane coupling agent include epoxysilane, aminosilane, ureidosilane, mercaptosilane, and the like.
  • the coupling agents may be used alone or in combination.
  • the coupling agent may be included in an amount of about 0.01 to about 5 wt%, specifically about 0.05 to about 3 wt%, more specifically about 0.1 to about 2 wt%, based on the total weight of the epoxy resin composition. In the above range, the strength of the cured epoxy resin composition may be improved.
  • the release agent may be used at least one selected from the group consisting of paraffin wax, ester wax, higher fatty acid, higher fatty acid metal salt, natural fatty acid and natural fatty acid metal salt.
  • the release agent may be included in about 0.1 to about 1% by weight of the epoxy resin composition.
  • the colorant is for laser marking of the semiconductor device sealant, and colorants well known in the art may be used, and are not particularly limited.
  • the colorant may include one or more of carbon black, titanium black, titanium nitride, copper hydroxide phosphate, iron oxide, and mica.
  • the colorant may be included in an amount of about 0.01 to about 5 wt%, specifically about 0.05 to about 3 wt%, more specifically about 0.1 to about 2 wt%, based on the total weight of the epoxy resin composition.
  • the epoxy resin composition of the present invention may be selected from the group consisting of stress relieving agents such as modified silicone oil, silicone powder, and silicone resin within the scope of not impairing the object of the present invention; Antioxidants such as Tetrakis [methylene-3- (3,5-di-tertbutyl-4-hydroxyphenyl) propionate] methane; And the like may be further added as necessary.
  • the epoxy resin composition is uniformly sufficiently mixed with the above components at a predetermined mixing ratio using a Henschel mixer or Lodige mixer, and then roll-mill or kneader ( After kneading with a kneader), it can be prepared in the form of a solid powder through cooling and grinding.
  • the storage stability is higher than that of the liquid epoxy resin composition, so that storage and transporting are easy.
  • the content of the inorganic filler is higher than the liquid epoxy resin, it is excellent in durability and reliability.
  • the epoxy resin composition of the present invention uses an alicyclic epoxy resin having a low thermal expansion coefficient and a high glass transition temperature as the epoxy resin, warpage generation of the semiconductor package can be minimized.
  • This invention provides the sealing material containing the resin composition for semiconductor element sealing of this invention as mentioned above.
  • the sealing material of this invention only needs to contain the resin composition for semiconductor element sealing of above-mentioned this invention, and the kind in particular is not restrict
  • the encapsulant may be a variety of encapsulation materials commonly used in the art, such as granule encapsulation, tablet encapsulation, film encapsulation, or sheet. It may be a (sheet) -type encapsulant.
  • the film encapsulant means a film-type encapsulant that is flexible enough to be wound on a winding roll
  • the sheet encapsulant means an encapsulant that cannot be wound on a roll because it is relatively hard as compared to the film encapsulant. do.
  • the encapsulant of the present invention has less warpage than the encapsulant for semiconductor encapsulation, which can be used in the wafer level packaging process.
  • 1 and 2 illustrate embodiments of a semiconductor package according to the present invention.
  • the semiconductor packages 100 and 200 of the present invention may include the substrates 110 and 210, the semiconductor elements 120 and 220, the sealing layers 130 and 230, and the connection terminals 140. 240).
  • the substrates 110 and 210 support the semiconductor devices 120 and 220 and provide electrical signals to the semiconductor devices 120 and 220, and the semiconductor mounting substrates generally used in the art are not limited. Can be used.
  • the substrates 110 and 210 may be a circuit board, a lead frame substrate, or a substrate including a redistribution layer.
  • the circuit board may be made of an insulating material, for example, a flat plate to which a heat-curable film such as an epoxy resin or a polyimide is attached, or a heat-resistant organic film such as a liquid crystal polyester film or a polyamide film.
  • a circuit pattern is formed on the circuit board, and the circuit pattern includes a power line for supplying power, a ground line, a signal line for signal transmission, and the like.
  • Each of the wires may be separated from each other by an interlayer insulating layer.
  • the circuit board may be a printed circuit board (PCB) in which a circuit pattern is formed by a printing process.
  • PCB printed circuit board
  • the lead frame substrate may be made of a metal material such as nickel, iron, copper, nickel alloy, iron alloy, copper alloy, or the like.
  • the lead frame substrate may include a semiconductor chip mounting part for mounting a semiconductor chip and a connection terminal part electrically connected to an electrode part of the semiconductor chip.
  • the lead frame substrate is not limited thereto, and leads of various structures and materials known in the art may be used. Frame substrates can be used without limitation.
  • the substrate including the redistribution layer may include a redistribution layer (RDL) 113 at an outermost layer of the laminate in which the dielectric layer 111 and the metal layer 112 are alternately stacked.
  • RDL redistribution layer
  • the dielectric layer 111 may be made of, for example, photosensitive polyimide
  • the metal layer 112 may be made of, for example, copper.
  • dielectric layers and metal layers of various materials used in the art may be used without limitation.
  • the redistribution layer 113 may include, for example, a photoresist such as polybenzoazole, but is not limited thereto.
  • Various redistribution layer forming materials used in the art may be used without limitation.
  • the semiconductor devices 120 and 220 are mounted on the substrates 110 and 210.
  • the semiconductor device mounting method is not particularly limited, and semiconductor chip mounting techniques known in the art may be used without limitation.
  • the semiconductor device may be mounted on a substrate by a flip chip or a wire bonding method.
  • a bump is formed on a bottom surface of a semiconductor chip, and a semiconductor device is fused to a circuit board using the bump.
  • an additional connection structure such as a wire is not required, which is advantageous in miniaturization and light weight of the semiconductor package, and has a merit of high integration since the distance between electrodes can be reduced.
  • the wire bonding method is a method of electrically connecting an electrode portion of a semiconductor device and a substrate with a metal wire.
  • an adhesive member 250 such as a die bonding film, may be interposed between the semiconductor device 220 and the substrate 210.
  • the semiconductor device 220 is fixed on the substrate 210 by 250.
  • the semiconductor device may be formed of one semiconductor chip or may include a plurality of semiconductor chips.
  • the semiconductor device may be a stacked semiconductor device in which a plurality of semiconductor chips 222 are electrically stacked through a through silicon via (TSV) 224.
  • TSV through silicon via
  • the sealing layers 130 and 230 are for protecting the semiconductor devices 120 and 220 from the external environment, and include the epoxy resin composition according to the present invention. Since the epoxy resin composition has been described above, a detailed description thereof will be omitted.
  • the sealing layer is formed to encapsulate at least a portion of the semiconductor device on the substrate. 1 and 2, the sealing layer is illustrated as encapsulating the side surface of the semiconductor device, but is not limited thereto. That is, the sealing layer may be formed so as to seal both the side surface and the upper surface of the semiconductor device.
  • Connection terminals 140 and 240 for electrically connecting the substrates 110 and 210 and an external power source are formed on the lower surfaces of the substrates 110 and 210, that is, opposite surfaces on which the semiconductor devices are mounted.
  • the connection terminal may be any of various connection terminals well known in the art, for example, a lead, a ball grid array, and the like, without limitation.
  • the semiconductor package according to the present invention as shown in Figure 1, the substrate 110 including a redistribution layer (113), and on the redistribution layer 113 A semiconductor device 120 disposed, a sealing layer 130 formed on the redistribution layer 113 and encapsulating at least a portion of the semiconductor device 120, and a connection terminal formed under the substrate 110. 140 may be included.
  • the sealing layer comprises an epoxy resin composition according to the present invention.
  • the semiconductor package according to the present invention is mounted on the substrate 210, the adhesive member 250 on the substrate 210, a plurality of semiconductor chips ( 222 may include a semiconductor device 220 that is electrically stacked through a through silicon via (TSV) 224, and a connection terminal 240 formed under the substrate 210.
  • the sealing layer comprises an epoxy resin composition according to the present invention.
  • a single silicon chip was rearranged on top of a carrier wafer having an adhesive tape by using a pick-and-place process. The chips were rearranged and then pre-baked at 120 ° C. Then, after raising the temperature to 120 ⁇ 170 °C, the sealing material prepared in Examples and Comparative Examples was applied on a carrier wafer and then cooled to room temperature to form a sealing layer at the wafer level. After the sealing layer was formed, (7) about 70,000 points of the height and cross section of the wafer were measured using a laser technology WDM-300, and the average of the measured values was expressed as warpage at the wafer level.
  • the temperature of the carrier wafer was raised to 150-200 ° C. to separate the carrier wafer and the sealed semiconductor chip.
  • a spin coating of the polybenzoazole precursor solution was formed on the molded wafer to form a redistribution layer, and a semiconductor chip separated on the redistribution layer was disposed and then UV cured.
  • the individual semiconductor packages were manufactured by dicing. The warpage of the individual semiconductor packages manufactured as described above was measured using a profile according to JESD22-B112 using AKRO MATRIX of Shadow Moire (USA).
  • Test specimens were prepared using the epoxy resin compositions according to Examples and Comparative Examples. Test specimens were prepared by making a disk-type hardened specimen of 5 cm in diameter and 5 mm in depth using a 30 ton press molding machine and post-curing at 175 ° C. for 2 hours in a dry oven. After measuring the initial weight of the prepared test specimen to 0.001g unit, the test specimen was placed in a chamber of a pressure cooking tester (PCT) (EHS-211MD, EPEC Co., Ltd.) at 120 ° C, 2 atmospheres, and a relative humidity of 100%. After 24 hours of exposure at, the weight was measured to 0.001g units after exposure to calculate the absorption. The mean value is shown after three measurements.
  • PCT pressure cooking tester
  • Substrate with an RDL layer formed by performing a plasma treatment on a Ni metal plate having a width ⁇ length ⁇ depth of 35 ⁇ 35 ⁇ 2 mm, followed by spin coating a PBO-based liquid type RDL to a thickness of 15 to 20 ⁇ m and curing at 200 ° C. was prepared.
  • the epoxy resin compositions of Examples and Comparative Examples were molded on the substrate under conditions of a mold temperature of 175 ° C., a transfer pressure of 9 MPa, a feed rate of 1 mm / sec, and a curing time of 90 seconds, a cured specimen was obtained, and then the cured specimen was ovened at 175 ° C. And post-cured (PMC) for 4 hours.
  • PMC post-cured
  • C-SAM C-SAM
  • Scanning Acoustic Microscope Sonix Co., Ltd., a device for determining the presence or absence of peeling by sound waves, was measured for tensile strength (kgf).
  • the area of the epoxy resin composition in contact with the substrate is 1 ⁇ 1cm and the tensile force measurement was carried out using a universal testing machine (UTM) for three specimens for each measurement process and the average value was calculated.
  • UPM universal testing machine
  • connection terminal 140, 240 connection terminal

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Abstract

The present invention relates to: a resin composition for sealing a solid state semiconductor device, comprising an epoxy resin containing a compound represented by chemical formula 1, a curing agent, and an inorganic filler; an encapsulating material comprising the same; and a semiconductor package. The resin composition for sealing a semiconductor device has a low coefficient of thermal expansion and a high glass transition temperature, thereby enabling warpage to be minimized.

Description

고체상 반도체 소자 밀봉용 에폭시 수지 조성물 및 이를 포함하는 봉지재 및 반도체 패키지Epoxy resin composition for sealing solid-state semiconductor device, encapsulant and semiconductor package comprising same
본 발명은 반도체 밀봉용 에폭시 수지 조성물, 이를 포함하는 봉지재 및 반도체 패키지에 관한 것이다. 보다 상세하게는, 본 발명은 열팽창계수가 낮고, 유리전이온도가 높아 휨(warpage) 발생을 최소화할 수 있는 고체상 반도체 밀봉용 에폭시 수지 조성물, 이를 포함하는 봉지재 및 반도체 패키지에 관한 것이다.The present invention relates to an epoxy resin composition for semiconductor encapsulation, an encapsulant and a semiconductor package including the same. More specifically, the present invention relates to an epoxy resin composition for sealing a solid phase semiconductor, which can minimize warpage due to a low coefficient of thermal expansion and a high glass transition temperature, and an encapsulant and a semiconductor package including the same.
반도체 소자를 수분이나 기계적 충격 등의 외부 환경으로부터 보호하기 위한 목적으로 에폭시 수지 조성물로 반도체 소자를 밀봉하는 방법이 상업적으로 행해지고 있다. 종래에는 반도체 소자 밀봉 방법으로, 웨이퍼를 절단(dicing)하여 반도체 칩(chip)을 제조한 후, 반도체 칩 단위로 패키징이 이루어졌으나, 최근에 절단되지 않은 웨이퍼 상태에서 패키징을 수행한 다음, 반도체 칩으로 절단(dicing)하는 공정이 개발되었다. 일반적으로, 전자의 방법을 칩 스케일 패키징(Chip Scale Package, CSP), 후자의 공정을 웨이퍼 레벨 패키징(Wafer Level Packaging, WLP)이라고 한다.The method of sealing a semiconductor element with an epoxy resin composition is commercially performed for the purpose of protecting a semiconductor element from external environments, such as moisture or a mechanical shock. Conventionally, semiconductor chips are manufactured by cutting a wafer to manufacture semiconductor chips, and then packaging is performed in units of semiconductor chips, but packaging is performed in a wafer state not recently cut, and then semiconductor chips. A process of cutting with a has been developed. In general, the former method is called Chip Scale Package (CSP) and the latter process is called Wafer Level Packaging (WLP).
웨이퍼 레벨 패키징은 칩 스케일 패키징 공정에 비해 공정이 단순하고, 패키지 두께가 얇아 반도체 실장 공간을 감소시킬 수 있다는 장점이 있다. 그러나 웨이퍼 레벨 패키징의 경우, 개개의 칩을 밀봉하는 칩 스케일 패키징에 비해 제막 면적이 넓기 때문에 웨이퍼와 봉지재의 열 팽창율 차이로 인한 휨(warpage)이 크게 발생한다는 문제점이 있다. 휨이 발생할 경우, 후속 공정의 수율 및 웨이퍼 핸들링에 영향을 미치게 된다. 또한, 현재 웨이퍼 레벨 패키징의 봉지재로는 주로 액상 타입의 에폭시 수지 또는 실리콘 수지가 사용되고 있으나, 이들 봉지재의 경우 저장 안정성이 나빠 보관성이 떨어지고, 에이징 후에 재보관이 불가능하며, 조성물 내 필러 함량이 낮아 상대적으로 얇은 두께로 구현되는 웨이퍼 레벨 패키징에 적용할 경우 내구성 및 신뢰성이 떨어진다는 문제점이 있다.Wafer-level packaging has advantages in that the process is simpler than the chip scale packaging process, and the package thickness is reduced, thereby reducing the semiconductor mounting space. However, the wafer level packaging has a problem in that warpage due to the difference in thermal expansion rate between the wafer and the encapsulant is large because the film forming area is larger than that of the chip scale packaging for sealing the individual chips. If warping occurs, it will affect the yield and wafer handling of subsequent processes. In addition, liquid type epoxy resin or silicone resin is mainly used as an encapsulant for wafer level packaging. However, these encapsulants have poor storage stability, which is poor in storageability, impossible to re-storage after aging, and a filler content in the composition. When applied to wafer-level packaging, which is implemented to have a relatively low thickness, a problem of low durability and reliability is low.
따라서, 웨이퍼 레벨 패키징 적용 시에도 휨 발생이 적고, 보관 및 사용이 용이하며, 우수한 내구성을 구현할 수 있는 반도체 소자 밀봉용 조성물을 개발할 필요가 있다.Therefore, there is a need to develop a composition for sealing a semiconductor device capable of less warpage, easy storage and use, and excellent durability even when applying wafer level packaging.
관련 선행기술이 한국공개특허 제2014-0064638호 등에 개시되어 있다.Related prior art is disclosed in Korea Patent Publication No. 2014-0064638.
본 발명의 목적은 열팽창계수가 낮고, 유리전이온도가 높아 휨(warpage) 발생을 최소화할 수 있는 반도체 밀봉용 에폭시 수지 조성물을 제공하는 것이다.It is an object of the present invention to provide an epoxy resin composition for semiconductor encapsulation that can minimize warpage due to low thermal expansion coefficient and high glass transition temperature.
본 발명의 다른 목적은 웨이퍼 레벨 패키징에 적용하는 경우에도 우수한 내구성을 구현할 수 있고, 보관 및 사용이 용이한 고상의 입자형 반도체 밀봉용 에폭시 수지 조성물을 제공하는 것이다.Another object of the present invention is to provide an epoxy resin composition for solid-state particulate semiconductor sealing, which can realize excellent durability even when applied to wafer level packaging, and is easy to store and use.
본 발명의 또 다른 목적은 재배선층(Re-Distribution Layer, RDL)과의 접착력이 우수한 반도체 밀봉용 에폭시 수지 조성물을 제공하는 것이다.Still another object of the present invention is to provide an epoxy resin composition for semiconductor encapsulation having excellent adhesion to a redistribution layer (RDL).
본 발명의 또 다른 목적은 흡습율이 낮아 우수한 신뢰성을 구현할 수 있는 반도체 밀봉용 에폭시 수지 조성물을 제공하는 것이다.Still another object of the present invention is to provide an epoxy resin composition for semiconductor encapsulation, which can realize excellent reliability with low moisture absorption.
본 발명의 또 다른 목적은 상기와 같은 반도체 밀봉용 에폭시 수지 조성물을 포함하는 봉지재 및 반도체 패키지를 제공하는 것이다.Still another object of the present invention is to provide an encapsulant and a semiconductor package including the epoxy resin composition for semiconductor encapsulation as described above.
본 발명의 하나의 관점은 고체상 반도체 소자 밀봉용 수지 조성물에 관한 것이다. 상기 고체상 반도체 소자 밀봉용 수지 조성물은 하기 화학식 1로 표시되는 화합물을 포함하는 에폭시 수지; 경화제; 및 무기 충전제를 포함한다.One aspect of the present invention relates to a resin composition for sealing a solid state semiconductor element. The solid-state semiconductor element sealing resin composition is an epoxy resin containing a compound represented by the formula (1); Curing agent; And inorganic fillers.
[화학식 1][Formula 1]
Figure PCTKR2017003325-appb-I000001
Figure PCTKR2017003325-appb-I000001
상기 화학식 1에서, R1 내지 R12는 각각 독립적으로 수소, 질소 원자를 함유하는 치환기, 치환 또는 비치환된 C1~C20 알킬기, 치환 또는 비치환된 C6~C30 아릴기, 치환 또는 비치환된 C3~C30의 헤테로아릴기, 치환 또는 비치환된 C3~C10의 헤테로시클로알킬기, 치환 또는 비치환된 C7~C30의 아릴알킬기, 또는 치환 또는 비치환된 C1~C30의 헤테로알킬기이며, 상기 R1 내지 R12 중 적어도 하나 이상이 치환 또는 비치환된 C6~C30 아릴기 또는 질소 원자를 함유하는 치환기임.In Formula 1, R1 to R12 are each independently hydrogen, a substituent containing a nitrogen atom, a substituted or unsubstituted C1-C20 alkyl group, a substituted or unsubstituted C6-C30 aryl group, a substituted or unsubstituted C3-C30 A heteroaryl group, a substituted or unsubstituted C3-C10 heterocycloalkyl group, a substituted or unsubstituted C7-C30 arylalkyl group, or a substituted or unsubstituted C1-C30 heteroalkyl group, at least one of the above R1 to R12 At least one is a substituted or unsubstituted C 6 -C 30 aryl group or a substituent containing a nitrogen atom.
구체예에서, 상기 질소 원자를 함유하는 치환기는 이소시아네이트기(-N=C=O), 시아노기, 니트로기, 아미노기, 아민기, 질소 원자를 포함하는 C3~C30의 헤테로아릴기 또는 질소 원자를 포함하는 C3~C10의 헤테로시클로알킬기일 수 있다.In an embodiment, the substituent containing a nitrogen atom may be selected from an isocyanate group (-N = C = O), a cyano group, a nitro group, an amino group, an amine group, a C3-C30 heteroaryl group or nitrogen atom including a nitrogen atom. It may be a C3-C10 heterocycloalkyl group containing.
구체예에서, 상기 C6~C30 아릴기는 페닐기, 비페닐기, 나프틸기, 나프톨기, 또는 안트라세닐기일 수 있다.In embodiments, the C6 ~ C30 aryl group may be a phenyl group, biphenyl group, naphthyl group, naphthol group, or anthracenyl group.
구체예에서, 상기 에폭시 수지는 하기 화학식 1a 내지 1d로 표시되는 화합물들 중 적어도 하나 이상을 포함할 수 있다.In an embodiment, the epoxy resin may include at least one or more of the compounds represented by Formulas 1a to 1d.
[화학식 1a][Formula 1a]
Figure PCTKR2017003325-appb-I000002
Figure PCTKR2017003325-appb-I000002
[화학식 1b][Formula 1b]
Figure PCTKR2017003325-appb-I000003
Figure PCTKR2017003325-appb-I000003
[화학식 1c][Formula 1c]
Figure PCTKR2017003325-appb-I000004
Figure PCTKR2017003325-appb-I000004
[화학식 1d][Formula 1d]
Figure PCTKR2017003325-appb-I000005
Figure PCTKR2017003325-appb-I000005
구체예에서, 상기 조성물은 상기 에폭시 수지 약 0.1 내지 약 15 중량%, 경화제 약 0.1 내지 약 13 중량% 및 무기 충전제 약 70 내지 약 95 중량%를 포함할 수 있다.In embodiments, the composition may comprise about 0.1 to about 15 weight percent of the epoxy resin, about 0.1 to about 13 weight percent of the curing agent and about 70 to about 95 weight percent of the inorganic filler.
본 발명의 다른 관점은 봉지재에 관한 것이다. 상기 봉지재는 상기 고체상 반도체 소자 밀봉용 수지 조성물을 포함한다.Another aspect of the invention relates to an encapsulant. The encapsulant includes the resin composition for sealing the solid-state semiconductor element.
구체예에서, 상기 봉지재는 타블렛형, 필름형 또는 시트형일 수 있다.In an embodiment, the encapsulant may be tablet type, film type or sheet type.
본 발명의 또 다른 관점은 반도체 패키지에 관한 것이다.Another aspect of the invention relates to a semiconductor package.
일 실시예에서, 상기 반도체 패키지는 기판; 상기 기판 상부에 실장되는 반도체 소자; 상기 기판 상부에 형성되어 상기 반도체 소자의 적어도 일부를 봉지하는 밀봉층; 및 상기 기판 하부에 형성되는 접속단자를 포함하며, 상기 밀봉층은 상기 고체상 반도체 소자 밀봉용 수지 조성물을 포함한다.In one embodiment, the semiconductor package comprises a substrate; A semiconductor device mounted on the substrate; A sealing layer formed on the substrate to encapsulate at least a portion of the semiconductor device; And a connection terminal formed under the substrate, wherein the sealing layer includes the resin composition for sealing the solid-state semiconductor element.
구체예에서, 상기 기판은 회로기판, 리드 프레임 기판 또는 재배선층(redistribution layer)을 포함하는 기판일 수 있다.In embodiments, the substrate may be a circuit board, a lead frame substrate or a substrate including a redistribution layer.
구체예에서, 상기 반도체 소자는 다수의 반도체 칩이 관통 실리콘 비아(Through silicon Via, TSV)을 통해 통전 가능하게 적층되어 있는 것일 수 있다.In an embodiment, the semiconductor device may be one in which a plurality of semiconductor chips are electrically stacked through a through silicon via (TSV).
다른 실시예에서, 상기 반도체 패키지는 재배선층(redistribution layer)을 포함하는 기판; 상기 재배선층 상부에 배치되는 반도체 소자; 상기 재배선층 상부에 형성되어 상기 반도체 소자의 적어도 일부를 봉지하는 밀봉층; 및 상기 기판의 하부에 형성되는 접속 단자를 포함하며, 상기 밀봉층은 상기 고체상 반도체 소자 밀봉용 수지 조성물을 포함한다.In another embodiment, the semiconductor package includes a substrate including a redistribution layer; A semiconductor device disposed on the redistribution layer; A sealing layer formed on the redistribution layer to seal at least a portion of the semiconductor device; And a connection terminal formed under the substrate, wherein the sealing layer includes the resin composition for sealing the solid-state semiconductor element.
또 다른 실시예에서, 상기 반도체 패키지는 기판; 상기 기판 상에 접착 부재를 통해 실장되며, 복수의 반도체 칩이 관통 실리콘 비아(Through silicon Via, TSV)을 통해 통전가능하게 적층되어 있는 반도체 소자; 상기 기판 하부에 형성되는 접속단자를 포함하며, 상기 밀봉층은 상기 고체상 반도체 소자 밀봉용 수지 조성물을 포함한다.In yet another embodiment, the semiconductor package comprises a substrate; A semiconductor device mounted on the substrate through an adhesive member, wherein a plurality of semiconductor chips are electrically stacked through a through silicon via (TSV); A connection terminal is formed below the substrate, and the sealing layer includes the resin composition for sealing the solid-state semiconductor device.
본 발명은 열팽창계수가 낮고, 유리전이온도가 높아 휨(warpage) 발생을 최소화할 수 있으며, 웨이퍼 레벨 패키징에 적용하는 경우에도 우수한 내구성을 구현할 수 있고, 액상이 아닌 고체상으로 보관 및 사용이 용이하며, 재배선층(Re-Distribution Layer, RDL)과의 접착력이 우수하고, 흡습율이 낮아 우수한 신뢰성을 구현할 수 있는 반도체 밀봉용 에폭시 수지 조성물 및 이를 포함하는 봉지재 및 반도체 패키지를 제공하는 발명의 효과를 갖는다.The present invention has a low coefficient of thermal expansion, high glass transition temperature to minimize warpage, excellent durability even when applied to wafer level packaging, and is easy to store and use in a solid rather than liquid form. , The effect of the invention to provide an epoxy resin composition for sealing a semiconductor and an encapsulant and a semiconductor package including the same, which has excellent adhesion to a re-distribution layer (RDL), low moisture absorption rate and can implement excellent reliability Have
도 1은 본 발명에 따른 반도체 패키지의 일 실시예를 개략적으로 도시한 도면이다.1 is a view schematically showing an embodiment of a semiconductor package according to the present invention.
도 2는 본 발명에 따른 반도체 패키지의 다른 실시예를 개략적으로 도시한 도면이다.2 is a view schematically showing another embodiment of a semiconductor package according to the present invention.
이하, 첨부된 도면을 참조하여 본 발명을 보다 구체적으로 설명한다. 다만, 하기 도면은 본 발명에 대한 이해를 돕기 위해 제공되는 것일 뿐, 본 발명이 하기 도면에 의해 한정되는 것은 아니다.Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail. However, the following drawings are provided only to assist in understanding the present invention, and the present invention is not limited by the following drawings.
또한, 도면에 개시된 형상, 크기, 비율, 각도, 개수 등은 예시적인 것이므로 본 발명이 도시된 사항에 한정되는 것은 아니다. 명세서 전체에 걸쳐 동일 참조 부호는 동일 구성 요소를 지칭한다. 또한, 본 발명을 설명함에 있어서, 관련된 공지 기술에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우 그 상세한 설명은 생략한다.In addition, the shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings are exemplary, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.
본 명세서에서, '포함한다', '갖는다', '이루어진다' 등이 사용되는 경우 '~만'이 사용되지 않는 이상 다른 부분이 추가될 수 있다. 구성 요소를 단수로 표현한 경우에 특별히 명시적인 기재 사항이 없는 한 복수를 포함하는 경우를 포함한다.In the present specification, when 'comprises', 'haves', 'consists of' and the like are used, other parts may be added unless 'only' is used. In the case where the component is expressed in the singular, the plural includes the plural unless specifically stated otherwise.
구성 요소를 해석함에 있어서, 별도의 명시적 기재가 없더라도 오차 범위를 포함하는 것으로 해석한다.In interpreting a component, it is interpreted to include an error range even if there is no separate description.
'~상에', '~상부에', '~하부에', '~옆에' 등으로 두 부분의 위치 관계가 설명되는 경우, '바로' 또는 '직접'이 사용되지 않는 이상 두 부분 사이에 하나 이상의 다른 부분이 위치할 수 있다.If the positional relationship between the two parts is described as 'upper', 'upper', 'lower', 'beside', etc., the two parts are not used unless 'right' or 'direct' is used. One or more other parts may be located in the.
'상부', '상면', '하부', '하면' 등과 같은 위치 관계는 도면을 기준으로 기재된 것일 뿐, 절대적인 위치 관계를 나타내는 것은 아니다. 즉, 관찰하는 위치에 따라, '상부'와 '하부' 또는 '상면'과 '하면'의 위치가 서로 변경될 수 있다. Positional relationships such as 'top', 'top', 'bottom', and 'bottom' are described based on the drawings and do not represent absolute positional relationships. That is, the positions of the 'top' and 'bottom' or 'top' and 'bottom' may be changed depending on the position to be observed.
본 명세서에서, "치환 또는 비치환된"에서 "치환된"은 해당 작용기 중 하나 이상의 수소 원자가 하이드록시기, 할로겐, 아미노기, 니트로기, 시아노기, 카르복실기, C1~C20의 알킬기, C1~C20의 알케닐기, C1~C20의 알키닐기, C1~C20의 할로알킬기, C6~C30의 아릴기, C3~C30의 헤테로아릴기, C3~C10의 시클로알킬기, C3~C10의 헤테로시클로알킬기, C7~C30의 아릴알킬기, C1~C30의 헤테로알킬기로 치환된 것을 의미하고, '할로겐'은 불소, 염소, 요오드 또는 브롬을 의미한다.In this specification, "substituted" in "substituted or unsubstituted" means that at least one hydrogen atom of the functional group is a hydroxyl group, a halogen, an amino group, a nitro group, a cyano group, a carboxyl group, a C1-C20 alkyl group, a C1-C20 Alkenyl group, C1-C20 alkynyl group, C1-C20 haloalkyl group, C6-C30 aryl group, C3-C30 heteroaryl group, C3-C10 cycloalkyl group, C3-C10 heterocycloalkyl group, C7-C30 An arylalkyl group, C1 ~ C30 It is substituted with a heteroalkyl group, "halogen" means fluorine, chlorine, iodine or bromine.
본 명세서에서, "아릴기"는 환형인 치환기의 모든 원소가 p-오비탈을 가지며 p-오비탈이 공액을 형성하는 치환기를 의미하는 것으로, 단일 고리 구조 또는 2개 이상의 고리가 융합되어 있는(fused) 다중 고리 구조를 포함하며, 예를 들면 페닐기, 비페닐기, 나프틸기, 나프톨기, 안트라세닐기 등을 의미할 수 있지만 이에 제한되지 않는다.As used herein, "aryl group" means a substituent in which all elements of a cyclic substituent have p-orbital and p-orbital forms a conjugate, and a single ring structure or two or more rings are fused. It includes a multi-ring structure, for example, it may mean a phenyl group, biphenyl group, naphthyl group, naphthol group, anthracenyl group and the like, but is not limited thereto.
본 명세서에서, "헤테로아릴기"는 C6 내지 C30의 아릴기 내에 질소, 산소, 황 및 인으로 이루어진 군에서 선택되는 원자가 1 내지 3개 포함되고 나머지는 탄소인 것을 의미하고, 예를 들면, 피리디닐, 피라지닐, 피리미디닐, 피리다지닐, 트리아지닐, 퀴놀리닐, 이소퀴놀리닐, 퀴녹살리닐, 아크리디닐, 퀴나졸리닐, 신노리닐, 프탈라지닐, 티아졸릴, 벤조티아졸릴, 이속사졸릴, 벤즈이속사졸릴, 옥사졸릴, 벤즈옥사졸릴, 피라졸릴, 인다졸릴, 이미다졸릴, 벤즈이미다졸릴, 퓨리닐, 티오페닐, 벤조티오페닐, 푸라닐, 벤조푸라닐, 이소벤조푸라닐 등을 의미할 수 있지만 이에 제한되지 않는다. In the present specification, the "heteroaryl group" means one to three atoms selected from the group consisting of nitrogen, oxygen, sulfur and phosphorus in the aryl group of C6 to C30 and the rest are carbon, for example, Dinyl, pyrazinyl, pyrimidinyl, pyridazinyl, triazinyl, quinolinyl, isoquinolinyl, quinoxalinyl, acridinyl, quinazolinyl, cshinolinyl, phthalazinyl, thiazolyl, benzothia Zolyl, isoxazolyl, benzisoxazolyl, oxazolyl, benzoxazolyl, pyrazolyl, indazolyl, imidazolyl, benzimidazolyl, furinyl, thiophenyl, benzothiophenyl, furanyl, benzofuranyl, iso Benzofuranyl, and the like, but is not limited thereto.
본 명세서에서, '헤테로시클로알킬기', '헤테로아릴기', '헤테로시클로알킬렌기', '헤테로아릴렌기'에서 '헤테로'는 질소, 산소, 황 또는 인 원자를 의미한다.In the present specification, 'hetero' in the 'heterocycloalkyl group', 'heteroaryl group', 'heterocycloalkylene group', and 'heteroarylene group' means nitrogen, oxygen, sulfur or phosphorus atoms.
또한, 본 명세서에 있어서, 범위를 나타내는 「X 내지 Y」는 「X 이상 Y 이하」를 의미한다.In addition, in this specification, "X-Y" which shows a range means "X or more and Y or less."
에폭시 수지 조성물Epoxy resin composition
먼저, 본 발명에 따른 반도체 밀봉용 에폭시 수지 조성물에 대해 설명한다.First, the epoxy resin composition for semiconductor sealing which concerns on this invention is demonstrated.
본 발명의 에폭시 수지 조성물은 (A) 에폭시 수지, (B) 경화제 및 (C) 무기 충전제를 포함한다.The epoxy resin composition of this invention contains (A) epoxy resin, (B) hardening | curing agent, and (C) inorganic filler.
(A) 에폭시 수지(A) epoxy resin
본 발명에서 사용되는 에폭시 수지는 하기 화학식 1로 표시되는 지환식 에폭시 화합물을 포함한다.The epoxy resin used in the present invention includes an alicyclic epoxy compound represented by the following formula (1).
[화학식 1][Formula 1]
Figure PCTKR2017003325-appb-I000006
Figure PCTKR2017003325-appb-I000006
상기 화학식 1에서, R1 내지 R12(R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11 및 R12)는 각각 독립적으로 수소, 질소 원자를 함유하는 치환기, 치환 또는 비치환된 C1~C20 알킬기, 치환 또는 비치환된 C6~C30 아릴기, 치환 또는 비치환된 C3~C30의 헤테로아릴기, 치환 또는 비치환된 C3~C10의 헤테로시클로알킬기, 치환 또는 비치환된 C7~C30의 아릴알킬기, 또는 치환 또는 비치환된 C1~C30의 헤테로알킬기이며, 상기 R1 내지 R12 중 적어도 하나 이상이 치환 또는 비치환된 C6~C30 아릴기 또는 질소 원자를 함유하는 치환기다.In Formula 1, R1 to R12 (R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11 and R12) are each independently a substituent containing a hydrogen, a nitrogen atom, substituted or unsubstituted C1 ~ C20 alkyl group, substituted or unsubstituted C6 ~ C30 aryl group, substituted or unsubstituted C3 ~ C30 heteroaryl group, substituted or unsubstituted C3 ~ C10 heterocycloalkyl group, substituted or unsubstituted C7 ~ C30 is an arylalkyl group or a substituted or unsubstituted C1-C30 heteroalkyl group, and at least one of R1 to R12 is a substituted or unsubstituted C6 to C30 aryl group or a substituent containing a nitrogen atom.
상기 질소 원자를 함유하는 치환기는, 예를 들면, 이소시아네이트기(-N=C=O), 시아노기, 니트로기, 아미노기, 아민기, 질소 원자를 포함하는 C3~C30의 헤테로아릴기 또는 질소 원자를 포함하는 C3~C10의 헤테로시클로알킬기일 수 있으며, 바람직하게는, 이소시아네이트기, 시아노기, 니트로기, 아미노기 또는 아민기이다.The substituent containing the said nitrogen atom is C3-C30 heteroaryl group or nitrogen atom containing an isocyanate group (-N = C = O), a cyano group, a nitro group, an amino group, an amine group, and a nitrogen atom, for example. It may be a C3-C10 heterocycloalkyl group containing, preferably, isocyanate group, cyano group, nitro group, amino group or amine group.
상기 C6~C30 아릴기는 페닐기, 비페닐기, 나프틸기, 나프톨기 또는 안트라세닐기일 수 있다.The C6 to C30 aryl group may be a phenyl group, biphenyl group, naphthyl group, naphthol group or anthracenyl group.
상기 화학식 1과 같이 지환식 에폭시 구조를 갖는 화합물은 열팽창계수가 높고, 유리전이온도가 높기 때문에 이를 적용한 에폭시 수지를 이용하면, 반도체 패키지의 휨(warpage)를 효과적으로 억제할 수 있다.Since the compound having an alicyclic epoxy structure as shown in Formula 1 has a high coefficient of thermal expansion and a high glass transition temperature, it is possible to effectively suppress warpage of a semiconductor package by using an epoxy resin to which the compound is applied.
또한, 상기 에폭시 수지로 화학식 1과 같은 지환식 에폭시 구조를 갖고, 질소 원자를 함유하는 치환기를 포함하는 화합물을 사용할 경우, 재배선층(Re-Distribution Layer, RDL)과의 접착력을 우수하게 구현할 수 있다. 웨이퍼 레벨 패키징 공정의 경우, 입출력 단자의 패키징을 용이하게 하기 위해 반도체 소자를 캐리어 웨이퍼 상에서 밀봉하고, 캐리어 웨이퍼를 제거한 후, 밀봉된 반도체 소자를 유전체층과 금속층이 교대로 적층된 기판 상에 형성된 재배선층(Re-Distribution Layer, RDL) 상에 재배치하는 방법이 사용되고 있다. 이때, 상기 재배선층(Re-Distribution Layer, RDL)은 폴리벤조아졸 등과 같은 네가티브 포토레지스트를 이용하여 형성되기 때문에, 에폭시 수지 내에 질소 원자를 함유하는 치환기가 포함될 경우, 에폭시 수지와 재배선층과의 부착력이 향상되는 효과를 얻을 수 있다. In addition, when the compound having an alicyclic epoxy structure as shown in Formula 1 and containing a substituent containing a nitrogen atom as the epoxy resin, it is possible to excellently implement the adhesive force with the redistribution layer (Re-Distribution Layer, RDL). . In the wafer level packaging process, the semiconductor device is sealed on the carrier wafer to facilitate packaging of the input / output terminals, the carrier wafer is removed, and the sealed semiconductor device is formed on the substrate on which the dielectric and metal layers are alternately stacked. A method of relocating on (Re-Distribution Layer, RDL) is used. In this case, since the redistribution layer (RDL) is formed by using a negative photoresist such as polybenzoazole, the adhesion force between the epoxy resin and the redistribution layer when a substituent containing a nitrogen atom is included in the epoxy resin. This improved effect can be obtained.
또한, 상기 에폭시 수지로 화학식 1과 같이 지환식 에폭시 구조를 갖고, C6~C30 아릴기를 포함하는 화합물을 사용하는 경우에는 에폭시 수지의 흡습율을 개선하는 효과를 얻을 수 있다. 일반적으로 지환식 에폭시 화합물의 경우, 흡습율이 높아 패키징 후의 반도체의 신뢰성이 다소 떨어진다는 문제점이 있다. 그러나, 본 발명과 같이 지환식 에폭시 구조에 치환기로 C6~C30 아릴기를 포함할 경우, 흡습율이 낮아져 신뢰성을 개선할 수 있다.In addition, when the compound having an alicyclic epoxy structure as shown in the general formula (1) and containing a C6 ~ C30 aryl group as the epoxy resin, it is possible to obtain the effect of improving the moisture absorption of the epoxy resin. In general, in the case of an alicyclic epoxy compound, there is a problem that the moisture absorption is high and the reliability of the semiconductor after packaging is somewhat lowered. However, when the C6-C30 aryl group is included as a substituent in the alicyclic epoxy structure as in the present invention, the moisture absorption rate is lowered, thereby improving reliability.
구체예에서, 상기 에폭시 수지는 하기 화학식 1a 내지 1d로 표시되는 화합물들 중 적어도 하나 이상을 포함할 수 있다.In an embodiment, the epoxy resin may include at least one or more of the compounds represented by Formulas 1a to 1d.
[화학식 1a][Formula 1a]
Figure PCTKR2017003325-appb-I000007
Figure PCTKR2017003325-appb-I000007
[화학식 1b][Formula 1b]
Figure PCTKR2017003325-appb-I000008
Figure PCTKR2017003325-appb-I000008
[화학식 1c][Formula 1c]
Figure PCTKR2017003325-appb-I000009
Figure PCTKR2017003325-appb-I000009
[화학식 1d][Formula 1d]
Figure PCTKR2017003325-appb-I000010
Figure PCTKR2017003325-appb-I000010
구체예에서, 상기 화학식 1로 표시되는 화합물을 포함하는 에폭시 수지는 반도체 소자 밀봉용 에폭시 수지 조성물 중 약 0.1 내지 약 15 중량%, 예를 들면 약 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 또는 15 중량%, 상기 수치 중 하나 이상 및 상기 수치 중 하나 이하의 범위로 포함될 수 있다. 또한, 구체적으로 약 3 내지 약 15 중량%, 더욱 구체적으로 약 3 내지 약 12 중량%의 함량으로 포함될 수 있다.In one embodiment, the epoxy resin comprising the compound represented by Formula 1 is about 0.1 to about 15% by weight of the epoxy resin composition for sealing semiconductor devices, for example about 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7 , 0.8, 0.9, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 or 15% by weight, one or more of the above values and a range below one of the above values It may be included as. It may also be included in an amount of about 3 to about 15 weight percent, more specifically about 3 to about 12 weight percent.
(B) 경화제(B) curing agent
상기 경화제로는 반도체 소자 밀봉용으로 일반적으로 사용되는 경화제들이 제한 없이 사용될 수 있으며, 바람직하게는 2개 이상의 반응기를 가진 경화제가 사용될 수 있다.As the curing agent, curing agents generally used for sealing semiconductor devices may be used without limitation, and preferably, curing agents having two or more reactors may be used.
구체적으로는, 상기 경화제로는, 페놀아랄킬형 페놀수지, 페놀노볼락형 페놀수지, 자일록(xylok)형 페놀수지, 크레졸 노볼락형 페놀수지, 나프톨형 페놀수지, 테르펜형 페놀수지, 다관능형 페놀수지, 디시클로펜타디엔계 페놀수지, 비스페놀 A와 레졸로부터 합성된 노볼락형 페놀수지, 트리스(하이드록시페닐)메탄, 디하이드록시바이페닐을 포함하는 다가 페놀 화합물, 무수 말레인산 및 무수 프탈산을 포함하는 산무수물, 메타페닐렌디아민, 디아미노디페닐메탄, 디아미노디페닐설폰 등의 방향족 아민 등이 사용될 수 있으나, 이에 한정되는 것은 아니다.Specifically, as the curing agent, a phenol aralkyl type phenol resin, a phenol phenol novolak type phenol resin, a xylok type phenol resin, a cresol novolak type phenol resin, a naphthol type phenol resin, a terpene type phenol resin, a polyfunctional type Phenol resins, dicyclopentadiene phenol resins, polyhydric phenol compounds including novolac-type phenol resins synthesized from bisphenol A and resol, tris (hydroxyphenyl) methane, dihydroxybiphenyl, maleic anhydride and phthalic anhydride Aromatic amines such as acid anhydride, metaphenylenediamine, diaminodiphenylmethane, diaminodiphenylsulfone, and the like may be used, but are not limited thereto.
예를 들어, 상기 경화제는 페놀노볼락형 페놀수지, 자일록형 페놀수지, 페놀아랄킬형 페놀수지 및 다관능형 페놀수지 중 하나 이상을 포함할 수 있다. For example, the curing agent may include one or more of phenol novolak-type phenol resin, xylox phenol resin, phenol aralkyl type phenol resin, and polyfunctional phenol resin.
상기 페놀노볼락형 페놀수지는, 예를 들면, 하기 화학식 2로 표시되는 페놀노볼락형 페놀수지일 수 있다.The phenol novolak type phenol resin may be, for example, a phenol novolak type phenol resin represented by the following formula (2).
[화학식 2][Formula 2]
Figure PCTKR2017003325-appb-I000011
Figure PCTKR2017003325-appb-I000011
상기 화학식 2에서 d의 평균치는 1 내지 7이다.In Formula 2, the average value of d is 1 to 7.
상기 화학식 2로 표시되는 페놀노볼락형 페놀수지는 가교점 간격이 짧아, 에폭시 수지와 반응할 경우 가교밀도가 높아져 그 경화물의 유리전이온도를 높일 수 있고, 이에 따라 경화물 선팽창계수를 낮추어 반도체 소자 패키지의 휨을 더욱 효과적으로 억제할 수 있다. The phenol novolak-type phenolic resin represented by Chemical Formula 2 has a short crosslinking point spacing, and when reacted with an epoxy resin, the crosslinking density becomes high, thereby increasing the glass transition temperature of the cured product, thereby lowering the coefficient of linear expansion of the cured product. The warpage of the package can be more effectively suppressed.
상기 페놀아랄킬형 페놀수지는 예를 들면, 하기 화학식 3으로 표시되는 분자 중에 바이페닐 유도체를 포함하는 노볼락 구조의 페놀아랄킬형 페놀수지일 수 있다. The phenol aralkyl type phenol resin may be, for example, a phenol aralkyl type phenol resin having a novolak structure containing a biphenyl derivative in a molecule represented by the following formula (3).
[화학식 3][Formula 3]
Figure PCTKR2017003325-appb-I000012
Figure PCTKR2017003325-appb-I000012
상기 화학식 3에서, e의 평균치는 1 내지 7이다.In Formula 3, the average value of e is 1 to 7.
상기 화학식 3로 표시되는 페놀아랄킬형 페놀수지는 에폭시 수지와 반응하여 탄소층(char)을 형성하여 주변의 열 및 산소의 전달을 차단함으로써 난연성을 달성하게 된다. The phenol aralkyl type phenol resin represented by Chemical Formula 3 forms a carbon layer (char) by reacting with the epoxy resin to block the transfer of heat and oxygen in the surroundings to achieve flame retardancy.
또한, 상기 자일록형 페놀수지는, 예를 들면, 하기 화학식 4로 표시되는 자일록(xylok)형 페놀수지일 수 있다.In addition, the "Xylox type phenol resin" may be, for example, "xylok" type phenol resin represented by the following formula (4).
[화학식 4][Formula 4]
Figure PCTKR2017003325-appb-I000013
Figure PCTKR2017003325-appb-I000013
상기 화학식 4에서, f의 평균치는 0 내지 7이다.In Formula 4, the average value of f is 0 to 7.
상기 화학식 4로 표시되는 자일록형 페놀수지는 수지 조성물의 유동성 및 신뢰성 강화 측면에서 바람직하다. The xylox phenol resin represented by the formula (4) is preferable in view of fluidity and reliability strengthening of the resin composition.
상기 다관능형 페놀수지는, 예를 들면, 하기 화학식 5로 표시되는 반복 단위를 포함하는 다관능형 페놀수지일 수 있다.The polyfunctional phenol resin may be, for example, a polyfunctional phenol resin containing a repeating unit represented by the following formula (5).
[화학식 5][Formula 5]
Figure PCTKR2017003325-appb-I000014
Figure PCTKR2017003325-appb-I000014
상기 화학식 5에서 g의 평균치는 1 내지 7이다.In Formula 5, the average value of g is 1 to 7.
상기 화학식 5로 표시되는 반복단위를 포함하는 다관능형 페놀수지는 에폭시 수지 조성물의 고온 휨 특성 강화 측면에서 바람직하다.The polyfunctional phenol resin containing the repeating unit represented by the formula (5) is preferable in view of enhancing the high temperature bending characteristics of the epoxy resin composition.
이들 경화제는 단독 혹은 병용하여 사용될 수 있다. 또한, 상기 경화제에 에폭시 수지, 경화 촉진제, 이형제, 커플링제, 및 응력완화제 등의 기타 성분과 멜트 마스터 배치와 같은 선반응을 시켜 만든 부가 화합물로도 사용할 수 있다.These curing agents may be used alone or in combination. Moreover, the addition agent which made the said hardening agent and other components, such as an epoxy resin, a hardening accelerator, a mold release agent, a coupling agent, and a stress relaxation agent, pre-reacts, such as a melt master batch, can also be used as a compound.
구체예에서, 상기 경화제는 반도체 소자 밀봉용 에폭시 수지 조성물 중 약 0.1 내지 약 13 중량%, 예를 들면 약 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 또는 13 중량%, 상기 수치 중 하나 이상 및 상기 수치 중 하나 이하의 범위로 포함될 수 있다. 또한, 구체적으로 약 0.1 내지 약 10 중량%, 더욱 구체적으로 약 0.1 내지 약 8 중량%의 함량으로 포함될 수 있다.In embodiments, the curing agent is about 0.1 to about 13% by weight of the epoxy resin composition for sealing the semiconductor device, for example about 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 2, 3 , 4, 5, 6, 7, 8, 9, 10, 11, 12 or 13% by weight, may be included in the range of one or more of the above values and one or less of the above values. It may also be included in an amount of about 0.1 to about 10% by weight, more specifically about 0.1 to about 8% by weight.
상기 에폭시 수지와 경화제와의 배합비는 패키지에서의 기계적 성질 및 내습 신뢰성의 요구에 따라 조절될 수 있다. 예를 들면, 경화제에 대한 에폭시 수지의 화학 당량비가 약 0.95 내지 약 3일 수 있으며, 구체적으로 약 1 내지 약 2, 더욱 구체적으로 약 1 내지 약 1.75일 수 있다. 에폭시 수지와 경화제의 배합비가 상기의 범위를 만족할 경우, 에폭시 수지 조성물 경화 후에 우수한 강도를 구현할 수 있다.The blending ratio of the epoxy resin and the curing agent may be adjusted according to the requirements of mechanical properties and moisture resistance reliability in the package. For example, the chemical equivalent ratio of the epoxy resin to the curing agent may be about 0.95 to about 3, specifically about 1 to about 2, more specifically about 1 to about 1.75. When the compounding ratio of the epoxy resin and the curing agent satisfies the above range, it is possible to implement excellent strength after curing the epoxy resin composition.
무기 충전제Inorganic filler
상기 무기 충전제는 에폭시 수지 조성물의 기계적 물성 및 저응력화를 향상시키기 위한 것이다. 상기 무기 충전제로는, 반도체 밀봉재에 사용되는 일반적인 무기 충전제들이 제한 없이 사용될 수 있으며, 특별히 한정되지 않는다. 예를 들면, 상기 무기 충전제로는 용융실리카, 결정성실리카, 탄산칼슘, 탄산마그네슘, 알루미나, 마그네시아, 클레이(clay), 탈크(talc), 규산칼슘, 산화티탄, 산화안티몬, 유리섬유 등이 사용될 수 있다. 이들은 단독 또는 혼합하여 사용될 수 있다.The inorganic filler is for improving the mechanical properties and low stress of the epoxy resin composition. As the inorganic filler, general inorganic fillers used in semiconductor sealing materials can be used without limitation, and are not particularly limited. For example, as the inorganic filler, fused silica, crystalline silica, calcium carbonate, magnesium carbonate, alumina, magnesia, clay, talc, calcium silicate, titanium oxide, antimony oxide, glass fiber, etc. may be used. Can be. These may be used alone or in combination.
바람직하게는 저응력화를 위해서 선팽창계수가 낮은 용융실리카를 사용한다. 용융실리카는 진비중이 약 2.3 이하인 비결정성 실리카를 의미하는 것으로 결정성 실리카를 용융하여 만들거나 다양한 원료로부터 합성한 비결정성 실리카도 포함된다. 용융실리카의 형상 및 입경은 특별히 한정되지는 않지만, 평균 입경 약 5 내지 약 30 ㎛의 구상 용융실리카를 약 50 내지 약 99 중량%, 평균입경 약 0.001 내지 약 1 ㎛의 구상 용융실리카를 약 1 내지 약 50 중량%를 포함한 용융실리카 혼합물을 전체 충전제에 대하여 약 40 내지 약 100 중량%가 되도록 포함하는 것이 좋다. 또한, 용도에 맞춰 그 최대 입경을 약 45 ㎛, 약 55 ㎛ 및 약 75 ㎛ 중 어느 하나로 조정해서 사용할 수가 있다. 상기 구상 용융실리카에는 도전성의 카본이 실리카 표면에 이물질로서 포함되는 경우가 있으나 극성 이물질의 혼입이 적은 물질을 선택하는 것도 중요하다.Preferably, molten silica having a low coefficient of linear expansion is used to reduce stress. Fused silica refers to amorphous silica having a specific gravity of about 2.3 or less, and also includes amorphous silica made by melting crystalline silica or synthesized from various raw materials. The shape and particle diameter of the molten silica are not particularly limited, but about 1 to about spherical molten silica having a spherical molten silica having an average particle diameter of about 5 to about 30 μm, and an average particle diameter of about 0.001 to about 1 μm. Preferably, the molten silica mixture, including about 50% by weight, is included from about 40% to about 100% by weight of the total filler. Moreover, according to a use, the maximum particle diameter can be adjusted to any one of about 45 micrometers, about 55 micrometers, and about 75 micrometers, and can be used. In the spherical molten silica, conductive carbon may be included as a foreign material on the silica surface, but it is also important to select a material containing less polar foreign matter.
상기 무기 충전제의 사용량은 성형성, 저응력성, 및 고온강도 등의 요구 물성에 따라 다르다. 구체예에서, 상기 무기 충전제는 에폭시 수지 조성물 중 약 70 내지 약 95 중량%, 예를 들면 약 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94 또는 95 중량%, 상기 수치 중 하나 이상 및 상기 수치 중 하나 이하의 범위로 포함될 수 있다. 또한, 구체적으로 약 80 내지 약 90 중량% 또는 약 83 내지 약 97 중량%로 포함될 수 있다.The amount of the inorganic filler used depends on the required physical properties such as formability, low stress, and high temperature strength. In an embodiment, the inorganic filler is about 70 to about 95 weight percent of the epoxy resin composition, for example about 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94 or 95% by weight, may be included in the range of one or more of the above values and one or less of the above values. It may also specifically comprise about 80 to about 90% by weight or about 83 to about 97% by weight.
기타 성분Other ingredients
한편, 상기 성분들 이외에 본 발명에 따른 에폭시 수지 조성물은 경화촉진제, 커플링제, 이형제 및 착색제 중 하나 이상을 더 포함할 수 있다.Meanwhile, in addition to the above components, the epoxy resin composition according to the present invention may further include one or more of a curing accelerator, a coupling agent, a mold releasing agent, and a coloring agent.
경화 촉진제Curing accelerator
경화 촉진제는 에폭시 수지와 경화제의 반응을 촉진하는 물질이다. 상기 경화 촉진제로는, 예를 들면, 3급 아민, 유기금속화합물, 유기인화합물, 이미다졸, 및 붕소화합물 등이 사용 가능하다. 3급 아민에는 벤질디메틸아민, 트리에탄올아민, 트리에틸렌디아민, 디에틸아미노에탄올, 트리(디메틸아미노메틸)페놀, 2-2-(디메틸아미노메틸)페놀, 2,4,6-트리스(디아미노메틸)페놀과 트리-2-에틸헥실산염 등이 있다.A hardening accelerator is a substance which accelerates reaction of an epoxy resin and a hardening | curing agent. As said hardening accelerator, a tertiary amine, an organometallic compound, an organophosphorus compound, an imidazole, a boron compound, etc. can be used, for example. Tertiary amines include benzyldimethylamine, triethanolamine, triethylenediamine, diethylaminoethanol, tri (dimethylaminomethyl) phenol, 2-2- (dimethylaminomethyl) phenol, 2,4,6-tris (diaminomethyl ) Phenol and tri-2-ethylhexyl acid salt.
상기 유기 금속화합물의 구체적인 예로는, 크로뮴아세틸아세토네이트, 징크아세틸아세토네이트, 니켈아세틸아세토네이트 등이 있다. 유기인화합물에는 트리스-4-메톡시포스핀, 테트라부틸포스포늄브로마이드, 테트라페닐포스포늄브로마이드, 페닐포스핀, 디페닐포스핀, 트리페닐포스핀, 트리페닐포스핀트리페닐보란, 트리페닐포스핀-1,4-벤조퀴논 부가물 등이 있다. 이미다졸류에는 2-페닐-4메틸이미다졸, 2-메틸이미다졸, 2-페닐이미다졸, 2-아미노이미다졸, 2-메틸-1-비닐이미다졸, 2-에틸-4-메틸이미다졸, 2-헵타데실이미다졸 등을 들 수 있으나, 이에 한정되는 것은 아니다. 상기 붕소화합물의 구체적인 예로는, 테트라페닐포스포늄-테트라페닐보레이트, 트리페닐포스핀 테트라페닐보레이트, 테트라페닐보론염, 트리플루오로보란-n-헥실아민, 트리플루오로보란모노에틸아민, 테트라플루오로보란트리에틸아민, 테트라플루오로보란아민 등이 있다. 이외에도 1,5-디아자바이시클로[4.3.0]논-5-엔(1,5-diazabicyclo[4.3.0]non-5-ene:DBN), 1,8-디아자바이시클로[5.4.0]운덱-7-엔(1,8-diazabicyclo[5.4.0]undec-7-ene: DBU) 및 페놀노볼락 수지염 등을 들 수 있으나, 이에 한정되는 것은 아니다.Specific examples of the organometallic compound include chromium acetylacetonate, zinc acetylacetonate, nickel acetylacetonate, and the like. Organophosphorus compounds include tris-4-methoxyphosphine, tetrabutylphosphonium bromide, tetraphenylphosphonium bromide, phenylphosphine, diphenylphosphine, triphenylphosphine, triphenylphosphine triphenylborane, triphenylphosphate And pin-1,4-benzoquinones adducts. The imidazoles include 2-phenyl-4methylimidazole, 2-methylimidazole, # 2-phenylimidazole, # 2-aminoimidazole, 2-methyl-1-vinylimidazole, and 2-ethyl-4. -Methylimidazole, 2-heptadecylimidazole, and the like, but are not limited thereto. Specific examples of the boron compound include tetraphenylphosphonium-tetraphenylborate, triphenylphosphine tetraphenylborate, tetraphenylboron salt, trifluoroborane-n-hexylamine, trifluoroborane monoethylamine, tetrafluoro Roboranetriethylamine, tetrafluoroboraneamine, and the like. In addition, 1, 5- diazabicyclo [4.3.0] non-5-ene (1, 5- diazabicyclo [4.3.0] non-5-ene: DBN), 1, 8- diazabicyclo [5.4. 0] undec-7-ene (1,8-diazabicyclo [5.4.0] undec-7-ene: DBU) and phenol novolak resin salts, and the like.
보다 구체적으로는, 상기 경화 촉진제로 유기인화합물, 붕소화합물, 아민계, 또는 이미다졸계 경화 촉진제를 단독 혹은 혼합하여 사용할 수 있다. 상기 경화 촉진제는 에폭시 수지 또는 경화제와 선반응하여 만든 부가물을 사용하는 것도 가능하다.More specifically, an organophosphorus compound, a boron compound, an amine type, or an imidazole series hardening accelerator can be used individually or in mixture as said hardening accelerator. The curing accelerator may also use an epoxy resin or an adduct made by preliminary reaction with a curing agent.
본 발명에서 경화 촉진제의 사용량은 에폭시 수지 조성물 총 중량에 대하여, 약 0.01 내지 약 2 중량%, 구체적으로 약 0.02 내지 약 1.5 중량%, 더욱 구체적으로 약 0.05 내지 약 1 중량%일 수 있다. 상기의 범위에서 에폭시 수지 조성물의 경화를 촉진하고 또한, 경화도도 좋은 장점이 있다.The amount of the curing accelerator used in the present invention may be about 0.01 to about 2% by weight, specifically about 0.02 to about 1.5% by weight, and more specifically about 0.05 to about 1% by weight, based on the total weight of the epoxy resin composition. In the above range, there is an advantage that the curing of the epoxy resin composition is promoted and the degree of curing is also good.
커플링제Coupling agent
상기 커플링제는 에폭시 수지와 무기 충전제 사이에서 반응하여 계면 강도를 향상시키기 위한 것으로, 예를 들면, 실란 커플링제일 수 있다. 상기 실란 커플링제는 에폭시 수지와 무기 충전제 사이에서 반응하여, 에폭시 수지와 무기 충전제의 계면 강도를 향상시키는 것이면 되고, 그 종류가 특별히 한정되지 않는다. 상기 실란 커플링제의 구체적인 예로는 에폭시실란, 아미노실란, 우레이도실란, 머캅토실란 등을 들 수 있다. 상기 커플링제는 단독으로 사용할 수 있으며 병용해서 사용할 수도 있다.The coupling agent is for improving the interfacial strength by reacting between the epoxy resin and the inorganic filler. For example, the coupling agent may be a silane coupling agent. The said silane coupling agent may react between an epoxy resin and an inorganic filler, and what is necessary is just to improve the interface strength of an epoxy resin and an inorganic filler, The kind is not specifically limited. Specific examples of the silane coupling agent include epoxysilane, aminosilane, ureidosilane, mercaptosilane, and the like. The coupling agents may be used alone or in combination.
상기 커플링제는 에폭시 수지 조성물 총 중량에 대해, 약 0.01 내지 약 5 중량%, 구체적으로 약 0.05 내지 약 3 중량%, 더욱 구체적으로 약 0.1 내지 약 2 중량%의 함량으로 포함될 수 있다. 상기 범위에서 에폭시 수지 조성물 경화물의 강도가 향상될 수 있다.The coupling agent may be included in an amount of about 0.01 to about 5 wt%, specifically about 0.05 to about 3 wt%, more specifically about 0.1 to about 2 wt%, based on the total weight of the epoxy resin composition. In the above range, the strength of the cured epoxy resin composition may be improved.
이형제Release agent
상기 이형제로는 파라핀계 왁스, 에스테르계 왁스, 고급 지방산, 고급 지방산 금속염, 천연 지방산 및 천연 지방산 금속염으로 이루어진 군으로부터 선택되는 1종 이상을 사용할 수 있다.The release agent may be used at least one selected from the group consisting of paraffin wax, ester wax, higher fatty acid, higher fatty acid metal salt, natural fatty acid and natural fatty acid metal salt.
상기 이형제는 에폭시수지 조성물 중 약 0.1 내지 약 1 중량%로 포함될 수 있다.The release agent may be included in about 0.1 to about 1% by weight of the epoxy resin composition.
착색제coloring agent
상기 착색제는 반도체 소자 밀봉재의 레이저 마킹을 위한 것으로, 당해 기술 분야에 잘 알려져 있는 착색제들이 사용될 수 있으며, 특별히 제한되지 않는다. 예를 들면, 상기 착색제는 카본 블랙, 티탄블랙, 티탄 질화물, 인산수산화구리(dicopper hydroxide phosphate), 철산화물, 운모 중 하나 이상을 포함할 수 있다. The colorant is for laser marking of the semiconductor device sealant, and colorants well known in the art may be used, and are not particularly limited. For example, the colorant may include one or more of carbon black, titanium black, titanium nitride, copper hydroxide phosphate, iron oxide, and mica.
상기 착색제는 에폭시 수지 조성물 총 중량에 대해, 약 0.01 내지 약 5 중량%, 구체적으로 약 0.05 내지 약 3 중량%, 더욱 구체적으로 약 0.1 내지 약 2 중량% 정도의 함량으로 포함될 수 있다.The colorant may be included in an amount of about 0.01 to about 5 wt%, specifically about 0.05 to about 3 wt%, more specifically about 0.1 to about 2 wt%, based on the total weight of the epoxy resin composition.
이외에도, 본 발명의 에폭시 수지 조성물은 본 발명의 목적을 해하지 않는 범위에서 변성 실리콘 오일, 실리콘 파우더, 및 실리콘 레진 등의 응력완화제; Tetrakis[methylene-3-(3,5-di-tertbutyl-4-hydroxyphenyl)propionate]methane 등의 산화방지제; 등을 필요에 따라 추가로 함유할 수 있다.In addition, the epoxy resin composition of the present invention may be selected from the group consisting of stress relieving agents such as modified silicone oil, silicone powder, and silicone resin within the scope of not impairing the object of the present invention; Antioxidants such as Tetrakis [methylene-3- (3,5-di-tertbutyl-4-hydroxyphenyl) propionate] methane; And the like may be further added as necessary.
한편, 상기 에폭시 수지 조성물은 상기와 같은 성분들을 헨셀 믹서(Hensel mixer)나 뢰디게 믹서(Lodige mixer)를 이용하여 소정의 배합비로 균일하게 충분히 혼합한 뒤, 롤밀(roll-mill)이나 니이더(kneader)로 용융 혼련한 후, 냉각, 분쇄 과정을 거쳐 고체 상태의 분말 형태로 제조될 수 있다.On the other hand, the epoxy resin composition is uniformly sufficiently mixed with the above components at a predetermined mixing ratio using a Henschel mixer or Lodige mixer, and then roll-mill or kneader ( After kneading with a kneader), it can be prepared in the form of a solid powder through cooling and grinding.
본 발명의 에폭시 수지 조성물은 고체 상태이기 때문에, 액상 에폭시 수지 조성물에 비해 저장 안정성이 높아 보관 및 이송이 용이하다. 또한, 숙성 후에 재보관이 가능하여 재료의 낭비를 방지할 수 있다. 또한, 액상 에폭시 수지에 비해 무기 충전제의 함량이 높아 내구성 및 신뢰성이 우수하다.Since the epoxy resin composition of the present invention is in a solid state, the storage stability is higher than that of the liquid epoxy resin composition, so that storage and transporting are easy. In addition, it is possible to re-storage after aging to prevent waste of material. In addition, the content of the inorganic filler is higher than the liquid epoxy resin, it is excellent in durability and reliability.
또한, 본 발명의 에폭시 수지 조성물은 에폭시 수지로 열팽창계수가 낮고, 유리전이온도가 높은 지환족 에폭시 수지를 사용하기 때문에, 반도체 패키지의 휨(warpage) 발생을 최소화할 수 있다.In addition, since the epoxy resin composition of the present invention uses an alicyclic epoxy resin having a low thermal expansion coefficient and a high glass transition temperature as the epoxy resin, warpage generation of the semiconductor package can be minimized.
봉지재Encapsulant
본 발명은 상기와 같은 본 발명의 반도체 소자 밀봉용 수지 조성물을 포함하는 봉지재를 제공한다. 본 발명의 봉지재는, 상기한 본 발명의 반도체 소자 밀봉용 수지 조성물을 포함하기만 하면 되고, 그 종류가 특별히 제한되지 않는다. 예를 들면, 상기 봉지재는 당해 기술 분야에서 일반적으로 사용되는 다양한 종류의 봉지재, 예를 들면, 그래뉼(granule)형 봉지재, 타블렛(tablet)형 봉지재, 필름(film)형 봉지재 또는 시트(sheet)형 봉지재일 수 있다. 이때 필름형 봉지재는 권취롤 등에 감길 수 있을 정도로 유연(flexible)한 필름 형태의 봉지재를 의미하며, 시트형 봉지재는 필름형 봉지재이 비해 상대적으로 딱딱하여 롤 등에 권취될 수 없는 형태의 봉지재를 의미한다.This invention provides the sealing material containing the resin composition for semiconductor element sealing of this invention as mentioned above. The sealing material of this invention only needs to contain the resin composition for semiconductor element sealing of above-mentioned this invention, and the kind in particular is not restrict | limited. For example, the encapsulant may be a variety of encapsulation materials commonly used in the art, such as granule encapsulation, tablet encapsulation, film encapsulation, or sheet. It may be a (sheet) -type encapsulant. In this case, the film encapsulant means a film-type encapsulant that is flexible enough to be wound on a winding roll, and the sheet encapsulant means an encapsulant that cannot be wound on a roll because it is relatively hard as compared to the film encapsulant. do.
본 발명의 봉지재는 종래에 사용되던 반도체 밀봉용 봉지재에 비해 휨 발생이 적어 웨이퍼 레벨 패키징 공정에 특히 유용하게 사용될 수 있다.The encapsulant of the present invention has less warpage than the encapsulant for semiconductor encapsulation, which can be used in the wafer level packaging process.
반도체 패키지Semiconductor package
다음으로, 본 발명에 따른 반도체 패키지에 대해 설명한다. 도 1 및 도 2에는 본 발명에 따른 반도체 패키지의 실시예들이 도시되어 있다.Next, a semiconductor package according to the present invention will be described. 1 and 2 illustrate embodiments of a semiconductor package according to the present invention.
도 1 및 도 2에 도시된 바와 같이, 본 발명의 반도체 패키지(100, 200)는 기판(110, 210), 반도체 소자(120, 220), 밀봉층(130, 230) 및 접속 단자(140, 240)를 포함한다. 1 and 2, the semiconductor packages 100 and 200 of the present invention may include the substrates 110 and 210, the semiconductor elements 120 and 220, the sealing layers 130 and 230, and the connection terminals 140. 240).
기판Board
상기 기판(110, 210)은 반도체 소자(120, 220)를 지지하고, 반도체 소자(120, 220)에 전기 신호를 부여하기 위한 것으로, 당해 기술 분야에서 일반적으로 사용되는 반도체 실장용 기판들이 제한 없이 사용될 수 있다. 예를 들면, 상기 기판(110, 210)은 회로 기판, 리드 프레임 기판 또는 재배선층(redistribution layer)을 포함하는 기판일 수 있다. The substrates 110 and 210 support the semiconductor devices 120 and 220 and provide electrical signals to the semiconductor devices 120 and 220, and the semiconductor mounting substrates generally used in the art are not limited. Can be used. For example, the substrates 110 and 210 may be a circuit board, a lead frame substrate, or a substrate including a redistribution layer.
상기 회로 기판은 절연성을 갖는 물질, 예를 들면 에폭시 수지나 폴리이미드와 같은 열 경화성 필름, 액정 폴리에스테르 필름이나 폴리아미드 필름과 같은 내열성 유기 필름이 부착된 평판으로 이루어질 수 있다. 상기 회로 기판에는 회로 패턴이 형성되며, 상기 회로 패턴은 전원 공급을 위한 전원 배선과 접지 배선 및 신호 전송을 위한 신호 배선 등을 포함한다. 상기 각 배선들은 층간 절연막에 의해 서로 구분되어 배치될 수 있다. 구체적으로는, 상기 회로 기판은 회로 패턴이 인쇄 공정에 의해 형성된 인쇄회로기판(Printed Circuit Board, PCB)일 수 있다.The circuit board may be made of an insulating material, for example, a flat plate to which a heat-curable film such as an epoxy resin or a polyimide is attached, or a heat-resistant organic film such as a liquid crystal polyester film or a polyamide film. A circuit pattern is formed on the circuit board, and the circuit pattern includes a power line for supplying power, a ground line, a signal line for signal transmission, and the like. Each of the wires may be separated from each other by an interlayer insulating layer. Specifically, the circuit board may be a printed circuit board (PCB) in which a circuit pattern is formed by a printing process.
상기 리드 프레임 기판은 니켈, 철, 구리, 니켈 합금, 철 합금, 동 합금 등과 같은 금속 재질로 이루어질 수 있다. 상기 리드 프레임 기판은, 반도체 칩을 탑재하기 위한 반도체 칩 탑재부와 반도체 칩의 전극부와 전기적으로 연결된 접속 단자부를 포함할 수 있으나, 이에 한정되는 것은 아니며, 당해 기술 분야에 알려진 다양한 구조 및 재질의 리드 프레임 기판이 제한 없이 사용될 수 있다.The lead frame substrate may be made of a metal material such as nickel, iron, copper, nickel alloy, iron alloy, copper alloy, or the like. The lead frame substrate may include a semiconductor chip mounting part for mounting a semiconductor chip and a connection terminal part electrically connected to an electrode part of the semiconductor chip. However, the lead frame substrate is not limited thereto, and leads of various structures and materials known in the art may be used. Frame substrates can be used without limitation.
상기 재배선층을 포함하는 기판은, 도 1에 도시된 바와 같이, 유전체층(111)과 금속층(112)이 교대로 적층된 적층체의 최외층에 재배선층(Re-Distribution Layer, RDL)(113)이 형성된 기판이다. 상기 유전체층(111)은 예를 들면 감광성 폴리이미드 등으로 이루어질 수 있고, 상기 금속층(112)은 예를 들면, 구리 등으로 이루어질 수 있으나. 이에 한정되는 것은 아니며, 당해 기술 분야에서 사용되는 다양한 재질의 유전체층 및 금속층들이 제한 없이 사용될 수 있다. 또한, 상기 재배선층(113)은, 예를 들면, 폴리벤조아졸과 같은 포토레지스트 등으로 이루어질 수 있으나 이에 한정되는 것은 아니며, 당해 기술 분야에서 사용되는 다양한 재배선층 형성 물질들이 제한 없이 사용될 수 있다. As shown in FIG. 1, the substrate including the redistribution layer may include a redistribution layer (RDL) 113 at an outermost layer of the laminate in which the dielectric layer 111 and the metal layer 112 are alternately stacked. This is a formed substrate. The dielectric layer 111 may be made of, for example, photosensitive polyimide, and the metal layer 112 may be made of, for example, copper. Without being limited thereto, dielectric layers and metal layers of various materials used in the art may be used without limitation. In addition, the redistribution layer 113 may include, for example, a photoresist such as polybenzoazole, but is not limited thereto. Various redistribution layer forming materials used in the art may be used without limitation.
반도체 소자Semiconductor device
상기 기판(110, 210) 상에는 반도체 소자(120, 220)가 실장된다. 이때, 상기 반도체 소자 실장 방법은, 특별히 한정되지 않으며, 당해 기술 분야에 알려진 반도체 칩 실장 기술이 제한 없이 사용될 수 있다. 예를 들면, 상기 반도체 소자는 플립 칩(flip chip) 또는 와이어 본딩(wire bonding) 등의 방법으로 기판에 실장될 수 있다. The semiconductor devices 120 and 220 are mounted on the substrates 110 and 210. In this case, the semiconductor device mounting method is not particularly limited, and semiconductor chip mounting techniques known in the art may be used without limitation. For example, the semiconductor device may be mounted on a substrate by a flip chip or a wire bonding method.
플립 칩 방식은 반도체 칩의 아랫면에 범프(bump)를 형성하고, 상기 범프를 이용하여 반도체 소자를 회로 기판에 융착시키는 방식이다. 플립 칩 방식으로 반도체 칩을 실장할 경우, 와이어와 같은 추가 연결 구조가 필요하지 않기 때문에 반도체 패키지의 소형화 및 경량화에 유리하고, 전극 간의 거리를 줄일 수 있어 고집적화가 가능하다는 장점이 있다.In the flip chip method, a bump is formed on a bottom surface of a semiconductor chip, and a semiconductor device is fused to a circuit board using the bump. When the semiconductor chip is mounted in a flip chip method, an additional connection structure such as a wire is not required, which is advantageous in miniaturization and light weight of the semiconductor package, and has a merit of high integration since the distance between electrodes can be reduced.
와이어 본딩 방식은 반도체 소자의 전극부와 기판을 금속 와이어로 전기적으로 연결시키는 방법이다. 와이어 본딩 방식으로 반도체 칩을 실장할 경우, 도 2에 도시된 바와 같이, 반도체 소자(220)와 기판(210) 사이에 다이 본딩 필름 등과 같은 접착 부재(250)가 개재될 수 있으며, 상기 접착 부재(250)에 의해 반도체 소자(220)가 기판(210) 상에 고정된다.The wire bonding method is a method of electrically connecting an electrode portion of a semiconductor device and a substrate with a metal wire. When the semiconductor chip is mounted by a wire bonding method, as illustrated in FIG. 2, an adhesive member 250, such as a die bonding film, may be interposed between the semiconductor device 220 and the substrate 210. The semiconductor device 220 is fixed on the substrate 210 by 250.
한편, 상기 반도체 소자는 하나의 반도체 칩으로 이루어질 수도 있고, 다수의 반도체 칩들을 포함할 수도 있다. 예를 들면, 상기 반도체 소자는, 도 2에 도시된 바와 같이, 다수의 반도체 칩(222)이 관통 실리콘 비아(Through silicon Via, TSV)(224)을 통해 통전 가능하게 적층되어 있는 적층형 반도체 소자일 수 있다.Meanwhile, the semiconductor device may be formed of one semiconductor chip or may include a plurality of semiconductor chips. For example, as illustrated in FIG. 2, the semiconductor device may be a stacked semiconductor device in which a plurality of semiconductor chips 222 are electrically stacked through a through silicon via (TSV) 224. Can be.
밀봉층Sealing layer
상기 밀봉층(130, 230)은 반도체 소자(120, 220)를 외부 환경으로부터 보호하기 위한 것으로, 상기한 본 발명에 따른 에폭시 수지 조성물을 포함한다. 에폭시 수지 조성물에 대해서는 상술하였으므로, 구체적인 설명은 생략한다.The sealing layers 130 and 230 are for protecting the semiconductor devices 120 and 220 from the external environment, and include the epoxy resin composition according to the present invention. Since the epoxy resin composition has been described above, a detailed description thereof will be omitted.
상기 밀봉층은 기판 상부에 반도체 소자의 적어도 일부를 봉지하도록 형성된다. 도 1 및 도 2에는 밀봉층이 반도체 소자의 측면을 봉지하는 형태로 도시되어 있으나, 이에 한정되는 것은 아니다. 즉, 상기 밀봉층은 반도체 소자의 측면 및 상면을 모두 봉지하도록 형성되어도 무방하다.The sealing layer is formed to encapsulate at least a portion of the semiconductor device on the substrate. 1 and 2, the sealing layer is illustrated as encapsulating the side surface of the semiconductor device, but is not limited thereto. That is, the sealing layer may be formed so as to seal both the side surface and the upper surface of the semiconductor device.
접속단자Connection terminal
상기 기판(110, 210)의 하면, 즉, 반도체 소자가 실장된 면의 반대면에는 기판(110, 210)과 외부 전원을 전기적으로 연결하기 위한 접속 단자(140, 240)가 형성된다. 상기 접속 단자는 당해 기술 분야에 잘 알려진 다양한 구조의 접속 단자들, 예를 들면, 리드(lead), 볼 그리드 어레이(Ball Grid Array) 등이 제한 없이 사용될 수 있다. Connection terminals 140 and 240 for electrically connecting the substrates 110 and 210 and an external power source are formed on the lower surfaces of the substrates 110 and 210, that is, opposite surfaces on which the semiconductor devices are mounted. The connection terminal may be any of various connection terminals well known in the art, for example, a lead, a ball grid array, and the like, without limitation.
일 구체예에 따르면, 본 발명에 따른 반도체 패키지는, 도 1에 도시된 바와 같이, 재배선층(Re-distribution layer)(113)을 포함하는 기판(110)과, 상기 재배선층(113) 상부에 배치되는 반도체 소자(120)와, 상기 재배선층(113) 상부에 형성되어 상기 반도체 소자(120)의 적어도 일부를 봉지하는 밀봉층(130)과, 상기 기판(110)의 하부에 형성되는 접속 단자(140)를 포함하는 것일 수 있다. 이때, 상기 밀봉층은 본 발명에 따른 에폭시 수지 조성물을 포함한다. According to one embodiment, the semiconductor package according to the present invention, as shown in Figure 1, the substrate 110 including a redistribution layer (113), and on the redistribution layer 113 A semiconductor device 120 disposed, a sealing layer 130 formed on the redistribution layer 113 and encapsulating at least a portion of the semiconductor device 120, and a connection terminal formed under the substrate 110. 140 may be included. At this time, the sealing layer comprises an epoxy resin composition according to the present invention.
다른 구체예에 따르면, 본 발명에 따른 반도체 패키지는, 도 2에 도시된 바와 같이, 기판(210)과, 상기 기판(210) 상에 접착 부재(250)를 통해 실장되며, 복수의 반도체 칩(222)이 관통 실리콘 비아(Through silicon Via, TSV)(224)을 통해 통전가능하게 적층되어 있는 반도체 소자(220)와, 상기 기판(210) 하부에 형성되는 접속단자(240)를 포함하는 것일 수 있다. 이때, 상기 밀봉층은 본 발명에 따른 에폭시 수지 조성물을 포함한다.According to another embodiment, the semiconductor package according to the present invention, as shown in Figure 2, is mounted on the substrate 210, the adhesive member 250 on the substrate 210, a plurality of semiconductor chips ( 222 may include a semiconductor device 220 that is electrically stacked through a through silicon via (TSV) 224, and a connection terminal 240 formed under the substrate 210. have. At this time, the sealing layer comprises an epoxy resin composition according to the present invention.
이하, 본 발명의 바람직한 실시예를 통해 본 발명의 구성 및 작용을 더욱 상세히 설명하기로 한다. 다만, 이는 본 발명의 바람직한 예시로 제시된 것이며 어떠한 의미로도 이에 의해 본 발명이 제한되는 것으로 해석될 수는 없다.Hereinafter, the configuration and operation of the present invention through the preferred embodiment of the present invention will be described in more detail. However, this is presented as a preferred example of the present invention and in no sense can be construed as limiting the present invention.
여기에 기재되지 않은 내용은 이 기술 분야에서 숙련된 자이면 충분히 기술적으로 유추할 수 있는 것이므로 그 설명을 생략하기로 한다.Details that are not described herein will be omitted since those skilled in the art can sufficiently infer technically.
하기 실시예 및 비교예에서 사용된 각 성분의 사양은 다음과 같다.Specifications of each component used in the following Examples and Comparative Examples are as follows.
(A) 에폭시 수지(A) epoxy resin
(a1) 하기 화학식 1a의 화합물을 사용하였다.(a1) The compound of Formula 1a was used.
[화학식 1a][Formula 1a]
Figure PCTKR2017003325-appb-I000015
Figure PCTKR2017003325-appb-I000015
(a2) 하기 화학식 1b의 화합물을 사용하였다.(a2) The compound of Formula 1b was used.
[화학식 1b] [Formula 1b]
Figure PCTKR2017003325-appb-I000016
Figure PCTKR2017003325-appb-I000016
(a3) 하기 화학식 1c의 화합물을 사용하였다.(a3) The compound of Formula 1c was used.
[화학식 1c][Formula 1c]
Figure PCTKR2017003325-appb-I000017
Figure PCTKR2017003325-appb-I000017
(a4) 하기 화학식 1d의 화합물을 사용하였다.(a4) The compound of Formula 1d was used.
[화학식 1d][Formula 1d]
Figure PCTKR2017003325-appb-I000018
Figure PCTKR2017003325-appb-I000018
(a5) 일본화약社의 NC-3000을 사용하였다.(a5) NC-3000 from Nippon Gunpowder was used.
(a6) 제팬에폭시레진社의 YX-4000를 사용하였다.(a6) Japan Epoxy Resin YX-4000 was used.
(B) 경화제(B) curing agent
(b1) Kolon 유화사의 KPH-F3065를 사용하였다.(b1) KPH-F3065 from Kolon Emulsifier was used.
(b2) 메이와사의 MEH-7851을 사용하였다.(b2) MEH-7851 from Maywa was used.
(C) 경화촉진제(C) curing accelerator
(C1) Hokko Chemical사의 TPP-k(트리페닐포스핀)를 사용하였다.(C1) TPP-k (triphenylphosphine) from Hokko Chemical was used.
(C2) 알드리치사의 1,4-벤조퀴논을 사용하였다.(C2) 1,4-benzoquinone of Aldrich Corporation was used.
(D) 무기 충전제(D) inorganic filler
평균입경 20㎛의 구상 용융실리카와 평균입경 0.5㎛의 구상 용융실리카의 9:1(중량비) 혼합물을 사용하였다.A 9: 1 (weight ratio) mixture of spherical molten silica having an average particle diameter of 20 µm and spherical molten silica having an average particle diameter of 0.5 µm was used.
(E) 커플링제(E) coupling agent
(e1) 다우 코닝사의 메틸트리메톡시 실란 커플링제인 SZ-6070을 사용하였다.(e1) SZ-6070, a methyltrimethoxy silane coupling agent from Dow Corning, was used.
(e2) 신에츠사의 N-페닐-3-아미노프로필트리메톡시 실란 커플링제인 KBM-573을 사용하였다.(e2) KBM-573, a Shin-Etsu N-phenyl-3-aminopropyltrimethoxy silane coupling agent, was used.
(F) 착색제(F) colorant
미쯔비시 케미칼사의 카본블랙 MA-600B를 사용하였다.Mitsubishi Chemical's carbon black MA-600B was used.
실시예Example 1 내지 5 및  1 to 5 and 비교예Comparative example 1 내지 2 1 to 2
하기 표 1의 조성에 따라. 헨셀 믹서(KEUM SUNG MACHINERY CO.LTD(KSM-22))를 이용하여 25~30℃에서 30분간 균일하게 혼합한 후, 연속 니이더(kneader)를 이용하여 Max. 110℃에서 30분간 용융 혼련 후, 10~15℃로 냉각하고 분쇄하여 반도체 소자 밀봉용 에폭시 수지 조성물을 제조하였다. 그런 다음, 상기 에폭시 수지 조성물을 4.5g을 취하여 타블렛(tablet) 제조설비에 투입 후 12톤의 무게로 가압하여 외경 Φ14(mm)인 타블렛형 봉지재를 제조하였다.According to the composition of Table 1 below. After mixing uniformly for 30 minutes at 25 ~ 30 ℃ using a Henschel mixer (KEUM SUNG MACHINERY CO.LTD (KSM-22)), the Max. After melt kneading at 110 ° C. for 30 minutes, the mixture was cooled and ground to 10 to 15 ° C. to prepare an epoxy resin composition for sealing semiconductor elements. Then, 4.5 g of the epoxy resin composition was taken and put into a tablet manufacturing facility, and then pressed under a weight of 12 tons to prepare a tablet-type encapsulant having an outer diameter of Φ14 (mm).
실시예 1Example 1 실시예 2Example 2 실시예 3Example 3 실시예 4Example 4 실시예 5Example 5 비교예 1Comparative Example 1 비교예 2Comparative Example 2
(A)(A) (a1)(a1) 88 -- -- -- 22 -- --
(a2)(a2) -- 88 -- -- 22 -- --
(a3)(a3) -- -- 88 -- 22 -- --
(a4)(a4) -- -- -- 88 22 -- --
(a5)(a5) -- -- -- -- -- 55 3.53.5
(a6)(a6) -- -- -- -- -- 1.51.5 33
(B)(B) (b1)(b1) 0.40.4 0.40.4 0.40.4 0.40.4 0.50.5 1One 0.50.5
(b2)(b2) 0.60.6 0.60.6 0.60.6 0.60.6 0.50.5 1.51.5 22
(C)(C) (c1)(c1) 0.20.2 0.20.2 0.20.2 0.20.2 0.10.1 0.20.2 0.10.1
(c2)(c2) -- -- -- -- 0.10.1 -- 0.10.1
(D)(D) 9090 9090 9090 9090 9090 9090 9090
(E)(E) (e1)(e1) 0.10.1 0.10.1 0.10.1 0.10.1 0.10.1 0.10.1 0.10.1
(e2)(e2) 0.20.2 0.20.2 0.20.2 0.20.2 0.20.2 0.20.2 0.20.2
(F)(F) 0.50.5 0.50.5 0.50.5 0.50.5 0.50.5 0.50.5 0.50.5
상기 실시예 1~5 및 비교예 1~2의 에폭시 수지 조성물에 대하여 하기의 방법으로 물성 평가를 하여 하기 표 2에 나타내었다.Physical properties of the epoxy resin compositions of Examples 1 to 5 and Comparative Examples 1 and 2 were evaluated by the following methods, and are shown in Table 2 below.
물성 평가방법Property evaluation method
(1) 유리전이온도(℃), 열팽창계수(ppm/℃):(1) Glass transition temperature (℃), thermal expansion coefficient (ppm / ℃):
실시예 및 비교예에 의해 제조된 봉지재 4.2g을 트랜스퍼 성형(성형 온도: 175℃, 경화 시간: 120초, 트랜서퍼 시간: 14초, 트랜스퍼 속도: 1.2mm/초, 클램프 압력: 40톤, 트랜스퍼 압력: 1톤)하여 시편을 제조한 후, TMA (美)TA사 Q400을 이용하여 측정 시편의 유리전이온도 및 열팽창계수(α1, α2)를 측정하였다. 유리전이온도 이전까지의 구간에서의 열팽창계수는α1, 유리전이온도부터 그 이후의 구간에서의 열팽창계수는 α2 라고 정의한다. 4.2 g of the encapsulant prepared by Examples and Comparative Examples were transferred to a transfer molding (molding temperature: 175 ° C., curing time: 120 seconds, transfer time: 14 seconds, transfer speed: 1.2 mm / sec, clamp pressure: 40 tons, Transfer pressure: 1 ton), the specimen was prepared, and then the glass transition temperature and the coefficient of thermal expansion (α1, α2) of the test specimen were measured using TMA (USA) Q400. The coefficient of thermal expansion in the section before the glass transition temperature is defined as α1, and the coefficient of thermal expansion in the section after the glass transition temperature is defined as α2.
(2) 휨(warpage)(㎛):(2) warpage (μm):
캐리어 웨이퍼(200mm_8inch or 300mm_12inch)에 점착 테이프(adhesive tape)를 부착한 후 pick-and-place 공정을 이용하여 단일 실리콘 칩을 점착 테이프가 붙어 있는 캐리어 웨이퍼 상단에 재배열(reconfiguration)시켰다. 칩을 재배열한 후 120℃로 프리-베이킹(pre-baking)을 진행하였다. 그런 다음, 120~170℃로 온도를 상승시킨 다음, 실시예 및 비교예에 의해 제조된 봉지재를 캐리어 웨이퍼 상에 도포한 후 상온으로 냉각시켜 웨이퍼 레벨에서 밀봉층을 형성하였다. 밀봉층 형성 후 (韓)레이저텍사의 WDM-300을 이용하여 웨이퍼의 높이, 단면을 레이저로 약 70,000 포인트를 측정하였으며, 측정된 값의 평균을 웨이퍼 레벨에서의 휨(warpage)로 나타내었다.After attaching an adhesive tape to a carrier wafer (200mm_8inch or 300mm_12inch), a single silicon chip was rearranged on top of a carrier wafer having an adhesive tape by using a pick-and-place process. The chips were rearranged and then pre-baked at 120 ° C. Then, after raising the temperature to 120 ~ 170 ℃, the sealing material prepared in Examples and Comparative Examples was applied on a carrier wafer and then cooled to room temperature to form a sealing layer at the wafer level. After the sealing layer was formed, (7) about 70,000 points of the height and cross section of the wafer were measured using a laser technology WDM-300, and the average of the measured values was expressed as warpage at the wafer level.
그런 다음, 캐리어 웨이퍼의 온도를 150~200℃로 상승시켜 캐리어 웨이퍼와 밀봉된 반도체 칩을 분리시켰다. 그런 다음, 성형 웨이퍼 상에 폴리벤조아졸 전구체 용액을 스핀 코팅하여 재배선층을 형성하고, 상기 재배선층 위에 분리된 반도체칩을 배치한 후, UV 경화시켰다. 그런 다음, 다이싱(dicing)하여 개별 반도체 패키지를 제조하였다. 상기와 같이 제조된 개별 반도체 패키지의 휨(warpage)을 Shadow moire(美)IPO사 AKRO MATRIX를 이용하여 JESD22-B112에 준하는 프로파일(profile)로 측정하였다.Then, the temperature of the carrier wafer was raised to 150-200 ° C. to separate the carrier wafer and the sealed semiconductor chip. Then, a spin coating of the polybenzoazole precursor solution was formed on the molded wafer to form a redistribution layer, and a semiconductor chip separated on the redistribution layer was disposed and then UV cured. Then, the individual semiconductor packages were manufactured by dicing. The warpage of the individual semiconductor packages manufactured as described above was measured using a profile according to JESD22-B112 using AKRO MATRIX of Shadow Moire (USA).
(3) 흡습율 (water absorption)(wt.%)(3) water absorption (wt.%)
실시예와 비교예에 의한 에폭시 수지 조성물을 이용하여 시험시편을 제작하였다. 시험시편은 30톤 프레스 성형기를 이용하여 지름 5cm, 깊이 5mm의 디스크 타입의 경화시편을 만들고, 175℃, 2시간 동안 건조오븐에서 후경화하여 제조하였다. 제조된 시험시편의 초기 무게를 0.001g 단위까지 측정한 다음, PCT (pressure cooking tester)(EHS-211MD, (美)ESPEC사)의 챔버 안에서 상기 시험 시편을 120℃, 2기압, 상대습도 100%에서 24시간 노출시킨 다음, 노출 후 무게를 0.001g 단위까지 측정하여 흡수율을 계산하였다. 3회 측정 후 평균값으로 나타내었다.Test specimens were prepared using the epoxy resin compositions according to Examples and Comparative Examples. Test specimens were prepared by making a disk-type hardened specimen of 5 cm in diameter and 5 mm in depth using a 30 ton press molding machine and post-curing at 175 ° C. for 2 hours in a dry oven. After measuring the initial weight of the prepared test specimen to 0.001g unit, the test specimen was placed in a chamber of a pressure cooking tester (PCT) (EHS-211MD, EPEC Co., Ltd.) at 120 ° C, 2 atmospheres, and a relative humidity of 100%. After 24 hours of exposure at, the weight was measured to 0.001g units after exposure to calculate the absorption. The mean value is shown after three measurements.
(4) 접착력 (adhesion)(kgf)(4) adhesion (kgf)
가로×세로×깊이가 각각 35×35×2 mm인 Ni 금속판을 플라즈마 처리한 후 PBO계 액상 타입 RDL을 15~20㎛ 두께로 스핀 코팅하고, 200℃에서 경화시켜 RDL층이 형성된 기판(Substrate)을 준비하였다. 상기 기판에 실시예와 비교예의 에폭시 수지 조성물을 금형 온도 175℃, 프랜스퍼 압력 9MPa, 이송속도 1mm/초, 경화 시간 90초의 조건으로 성형하여 경화시편을 얻은 후, 상기 경화시편을 175℃의 오븐에 넣어 4시간 동안 후경화(PMC; Post mold cure)시켰다.  이후, 60℃, 60% 상대습도 조건 하에서 120시간 동안 방치시킨 후, 260℃에서 30초간 IR-Reflow를 1회 통과시키는 것을 3회 반복하는 프리컨디션 조건 하에서 반도체 패키지 크랙 발생 유무를 C-SAM(scanning acoustic microscope: 음파로 박리유무를 판단하는 장비, Sonix社)으로 평가하고 인장력(kgf)을 측정하였다. 이때 기판에 닿는 에폭시 수지 조성물의 면적은 1×1cm이며 인장력 측정은 각 측정 공정 당 3개의 시편에 대하여 UTM(Universal Testing Machine)을 이용하여 수행되었으며 평균값을 계산하였다.Substrate with an RDL layer formed by performing a plasma treatment on a Ni metal plate having a width × length × depth of 35 × 35 × 2 mm, followed by spin coating a PBO-based liquid type RDL to a thickness of 15 to 20 μm and curing at 200 ° C. Was prepared. After the epoxy resin compositions of Examples and Comparative Examples were molded on the substrate under conditions of a mold temperature of 175 ° C., a transfer pressure of 9 MPa, a feed rate of 1 mm / sec, and a curing time of 90 seconds, a cured specimen was obtained, and then the cured specimen was ovened at 175 ° C. And post-cured (PMC) for 4 hours. Thereafter, the mixture was left for 60 hours at 60 ° C. and 60% relative humidity conditions, and then C-SAM (C) was used to detect the occurrence of semiconductor package cracks under pre-condition conditions, which was repeated three times at 260 ° C. for 30 seconds. Scanning Acoustic Microscope: Sonix Co., Ltd., a device for determining the presence or absence of peeling by sound waves, was measured for tensile strength (kgf). At this time, the area of the epoxy resin composition in contact with the substrate is 1 × 1cm and the tensile force measurement was carried out using a universal testing machine (UTM) for three specimens for each measurement process and the average value was calculated.
평가 항목Evaluation item 실시예 1Example 1 실시예 2Example 2 실시예 3Example 3 실시예 4Example 4 실시예 5Example 5 비교예 1Comparative Example 1 비교예 2Comparative Example 2
Tg(℃)Tg (℃) 188188 183183 179179 175175 175175 160160 175175
CTE(ppm/℃)CTE (ppm / ° C) α1α1 4.34.3 4.74.7 5.05.0 5.65.6 6.16.1 10.810.8 1111
α2α2 2828 3030 5252 3434 3838 3838 4242
Warpage(㎛)Warpage (μm) 웨이퍼 레벨 Wafer level 112112 129129 158158 193193 286286 842842 636636
개별 패키지Individual package 6363 7171 7676 7575 8686 128128 121121
흡습율 (%)Hygroscopicity (%) 0.120.12 0.150.15 0.160.16 0.180.18 0.200.20 0.970.97 0.830.83
접착력 (kgf)Adhesion (kgf) 6767 6565 6161 6363 6666 3232 3838
상기 표 2를 통해, 화학식 1의 화합물을 포함하는 에폭시 수지를 사용한 실시예 1~5의 경우, 종래의 일반적인 에폭시 수지를 사용한 비교예 1~2 보다 열팽창 계수가 낮고, 유리전이온도가 낮아 휨 특성이 우수함을 확인할 수 있다. 또한, 실시예 1~5의 경우, 흡습율 및 접착력 특성도 비교예 1~2보다 우수함을 확인할 수 있다.Through Table 2, in Examples 1 to 5 using an epoxy resin containing a compound of Formula 1, the thermal expansion coefficient is lower than that of Comparative Examples 1 to 2 using a conventional general epoxy resin, the glass transition temperature is lower, bending characteristics It can be confirmed that this excellent. In addition, in the case of Examples 1 to 5, it can be confirmed that the moisture absorption rate and the adhesive force characteristics are also superior to Comparative Examples 1 to 2.
[부호의 설명][Description of the code]
110, 210 : 기판110, 210: Substrate
120, 220 : 반도체 소자120, 220: semiconductor device
130, 230 : 밀봉층130, 230: sealing layer
140, 240 : 접속 단자140, 240: connection terminal
250 : 접착부재250: adhesive member

Claims (12)

  1. 하기 화학식 1로 표시되는 화합물을 포함하는 에폭시 수지;Epoxy resin containing a compound represented by the formula (1);
    경화제; 및Curing agent; And
    무기 충전제를 포함하는 고체상 반도체 소자 밀봉용 수지 조성물:Resin composition for sealing a solid-state semiconductor device containing an inorganic filler:
    [화학식 1][Formula 1]
    Figure PCTKR2017003325-appb-I000019
    Figure PCTKR2017003325-appb-I000019
    상기 화학식 1에서, R1 내지 R12는 각각 독립적으로 수소, 질소 원자를 함유하는 치환기, 치환 또는 비치환된 C1~C20 알킬기, 치환 또는 비치환된 C6~C30 아릴기, 치환 또는 비치환된 C3~C30의 헤테로아릴기, 치환 또는 비치환된 C3~C10의 헤테로시클로알킬기, 치환 또는 비치환된 C7~C30의 아릴알킬기, 또는 치환 또는 비치환된 C1~C30의 헤테로알킬기이며,In Formula 1, R1 to R12 are each independently hydrogen, a substituent containing a nitrogen atom, a substituted or unsubstituted C1-C20 alkyl group, a substituted or unsubstituted C6-C30 aryl group, a substituted or unsubstituted C3-C30 Heteroaryl group, substituted or unsubstituted C3-C10 heterocycloalkyl group, substituted or unsubstituted C7-C30 arylalkyl group, or substituted or unsubstituted C1-C30 heteroalkyl group,
    상기 R1 내지 R12 중 적어도 하나 이상이 치환 또는 비치환된 C6~C30 아릴기 또는 질소 원자를 함유하는 치환기임.At least one of R 1 to R 12 is a substituted or unsubstituted C 6 to C 30 aryl group or a substituent containing a nitrogen atom.
  2. 제1항에 있어서, 상기 질소 원자를 함유하는 치환기는 이소시아네이트기(-N=C=O), 시아노기, 니트로기, 아미노기, 아민기, 질소 원자를 포함하는 C3~C30의 헤테로아릴기 또는 질소 원자를 포함하는 C3~C10의 헤테로시클로알킬기인 고체상 반도체 소자 밀봉용 수지 조성물.The substituent containing a nitrogen atom according to claim 1, wherein the substituent containing an isocyanate group (-N = C = O), a cyano group, a nitro group, an amino group, an amine group, a C3-C30 heteroaryl group or nitrogen The resin composition for sealing a solid-state semiconductor element which is a C3-C10 heterocycloalkyl group containing an atom.
  3. 제1항에 있어서, 상기 C6~C30 아릴기는 페닐기, 비페닐기, 나프틸기, 나프톨기, 또는 안트라세닐기인 고체상 반도체 소자 밀봉용 수지 조성물.The resin composition for sealing a solid-state semiconductor element according to claim 1, wherein the C6 to C30 aryl group is a phenyl group, a biphenyl group, a naphthyl group, a naphthol group, or an anthracenyl group.
  4. 제1항에 있어서, 상기 에폭시 수지는 하기 화학식 1a 내지 1d로 표시되는 화합물들 중 적어도 하나 이상을 포함하는 것인 고체상 반도체 소자 밀봉용 수지 조성물.The resin composition of claim 1, wherein the epoxy resin comprises at least one or more of the compounds represented by the following Chemical Formulas 1a to 1d.
    [화학식 1a][Formula 1a]
    Figure PCTKR2017003325-appb-I000020
    Figure PCTKR2017003325-appb-I000020
    [화학식 1b][Formula 1b]
    Figure PCTKR2017003325-appb-I000021
    Figure PCTKR2017003325-appb-I000021
    [화학식 1c][Formula 1c]
    Figure PCTKR2017003325-appb-I000022
    Figure PCTKR2017003325-appb-I000022
    [화학식 1d][Formula 1d]
    Figure PCTKR2017003325-appb-I000023
    Figure PCTKR2017003325-appb-I000023
  5. 제1항에 있어서, 상기 조성물은 상기 에폭시 수지 약 0.1 내지 약 15 중량%, 경화제 약 0.1 내지 약 13 중량% 및 무기 충전제 약 70 내지 약 95 중량%를 포함하는 고체상 반도체 소자 밀봉용 수지 조성물.The resin composition of claim 1, wherein the composition comprises about 0.1 wt% to about 15 wt% of the epoxy resin, about 0.1 wt% to about 13 wt% of the curing agent, and about 70 wt% to about 95 wt% of the inorganic filler.
  6. 제1항 내지 제5항 중 어느 한 항의 고체상 반도체 소자 밀봉용 수지 조성물을 포함하는 봉지재.The sealing material containing the resin composition for sealing the solid-state semiconductor element of any one of Claims 1-5.
  7. 제6항에 있어서, 상기 봉지재는 타블렛형, 필름형 또는 시트형인 봉지재.The encapsulant of claim 6, wherein the encapsulant is a tablet, film, or sheet.
  8. 기판;Board;
    상기 기판 상부에 실장되는 반도체 소자;A semiconductor device mounted on the substrate;
    상기 기판 상부에 형성되어 상기 반도체 소자의 적어도 일부를 봉지하는 밀봉층; 및A sealing layer formed on the substrate to encapsulate at least a portion of the semiconductor device; And
    상기 기판 하부에 형성되는 접속단자를 포함하며,It includes a connection terminal formed under the substrate,
    상기 밀봉층은 제1항 내지 제5항 중 어느 한 항의 고체상 반도체 소자 밀봉용 수지 조성물을 포함하는 것인 반도체 패키지.The said sealing layer is a semiconductor package containing the resin composition for sealing the solid-state semiconductor element of any one of Claims 1-5.
  9. 제8항에 있어서, 상기 기판은 회로기판, 리드 프레임 기판 또는 재배선층(redistribution layer)을 포함하는 기판인 반도체 패키지.The semiconductor package of claim 8, wherein the substrate is a substrate including a circuit board, a lead frame substrate, or a redistribution layer.
  10. 제8항에 있어서, 반도체 소자는 다수의 반도체 칩이 관통 실리콘 비아(Through silicon Via, TSV)을 통해 통전 가능하게 적층되어 있는 것인 반도체 패키지.The semiconductor package of claim 8, wherein a plurality of semiconductor chips are electrically stacked through a through silicon via (TSV).
  11. 재배선층(redistribution layer)을 포함하는 기판;A substrate comprising a redistribution layer;
    상기 재배선층 상부에 배치되는 반도체 소자;A semiconductor device disposed on the redistribution layer;
    상기 재배선층 상부에 형성되어 상기 반도체 소자의 적어도 일부를 봉지하는 밀봉층; 및A sealing layer formed on the redistribution layer to seal at least a portion of the semiconductor device; And
    상기 기판의 하부에 형성되는 접속 단자를 포함하며,A connection terminal formed under the substrate,
    상기 밀봉층은 제1항 내지 제5항 중 어느 한 항의 고체상 반도체 소자 밀봉용 수지 조성물을 포함하는 것인 반도체 패키지.The said sealing layer is a semiconductor package containing the resin composition for sealing the solid-state semiconductor element of any one of Claims 1-5.
  12. 기판;Board;
    상기 기판 상에 접착 부재를 통해 실장되며, 복수의 반도체 칩이 관통 실리콘 비아(Through silicon Via, TSV)을 통해 통전가능하게 적층되어 있는 반도체 소자;A semiconductor device mounted on the substrate through an adhesive member, wherein a plurality of semiconductor chips are electrically stacked through a through silicon via (TSV);
    상기 기판 하부에 형성되는 접속단자를 포함하며,It includes a connection terminal formed under the substrate,
    상기 밀봉층은 제1항 내지 제5항 중 어느 한 항의 고체상 반도체 소자 밀봉용 수지 조성물을 포함하는 것인 반도체 패키지.The said sealing layer is a semiconductor package containing the resin composition for sealing the solid-state semiconductor element of any one of Claims 1-5.
PCT/KR2017/003325 2016-06-23 2017-03-28 Epoxy resin composition for sealing solid state semiconductor device, encapsulating material comprising same, and semiconductor package WO2017222151A1 (en)

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