WO2017221730A1 - Power semiconductor device and method for manufacturing power semiconductor device - Google Patents

Abstract

A semiconductor module for a power semiconductor device according to the present invention is provided with: a substrate; a semiconductor element having a back surface which is bonded to the substrate and a front surface which is provided with a main electrode; and a plate-like main terminal having an electrode-side bonding part which is electrically connected to the main electrode by being bonded to the front surface of the semiconductor element with a conductive bonding layer being interposed therebetween. The electrode-side bonding part of the first main terminal has a projection part and a through hole, which extend in the thickness direction thereof and face the front surface of the semiconductor element.

Description

Power semiconductor device and method for manufacturing power semiconductor device

The present invention relates to a power semiconductor device having a main terminal bonded to a main electrode of a semiconductor element through a conductive bonding layer, and a method for manufacturing the power semiconductor device.

In recent years, power semiconductor devices have been widely used not only for general industrial and electric railways but also for in-vehicle use. In automobiles, downsizing each component in a limited space directly affects the vehicle performance. Therefore, miniaturization is particularly demanded in power semiconductor devices for vehicles. In general, power semiconductor devices are required to have higher output density.

For example, in Patent Document 1, it is necessary to secure a clearance for bonding in order to prevent interference between a bonding tool and a bonding wire in a bonding process of connecting via a bonding wire. This has been made in view of the problem that miniaturization and high output density are hindered. In Patent Document 1, lead wires are soldered instead of wire bonding, and the need to provide the clearance is eliminated, thereby reducing the size and increasing the output density of the power semiconductor device.

JP 2014-11236 A

By using the technique described in Patent Document 1, there is a possibility that the power semiconductor device can be increased in output density. However, as the power semiconductor device has a higher output density, specifically, a higher current density of the semiconductor element, the temperature when the semiconductor element is energized also increases. When the temperature of the semiconductor element rises, for example, the thermal stress applied to the solder material at the joint between the semiconductor element and the lead also increases, so there is a possibility that reliability at the joint cannot be ensured. However, Patent Document 1 does not sufficiently study the reliability of a junction between a semiconductor element and a lead wire when the temperature at the time of energization of the semiconductor element becomes high. .

The present invention has been made to solve the above-described problems, and in a power semiconductor device including a main terminal bonded to a main electrode of a semiconductor element through a conductive bonding layer, It is an object to ensure reliability at the joint.

In order to achieve the above object, a power semiconductor device according to the present invention includes:
A substrate,
A semiconductor element having a back surface bonded to the substrate and a surface provided with a first main electrode;
A plate-like first main terminal having an electrode-side bonding portion bonded to the surface of the semiconductor element via a conductive bonding layer and electrically connected to the first main electrode;
The electrode-side joint portion of the first main terminal has a protrusion and a through hole that extend along the thickness direction and are provided to face the surface of the semiconductor element.

According to the present invention, the electrode-side joint portion of the first main terminal has the protrusion and the through hole, so that the joining area and thickness of the joining material can be secured, and thereby the reliability of the joint portion of the first main terminal Can be secured.

1 is a perspective view showing a power semiconductor device according to a first embodiment of the present invention. It is a perspective view which shows the power semiconductor device which concerns on Embodiment 1 of this invention in the state which excluded the frame member. It is a perspective view which shows the power semiconductor device which concerns on Embodiment 1 of this invention in the state which excluded the terminal block. It is the figure which looked at the power semiconductor device shown to FIG. 1C from the length direction. It is the elements on larger scale of FIG. 1B which show the semiconductor module of the power semiconductor device. FIG. 3 is a sectional view taken along line AA in FIG. 2. FIG. 3 is a sectional view taken along line BB in FIG. FIG. 3 is a cross-sectional view taken along the line CC of FIG. It is a figure which shows the inverter circuit which the power semiconductor device which concerns on embodiment of this invention comprises. 4 is a flowchart showing an exemplary manufacturing method of the power semiconductor device according to the embodiment of the present invention. It is a perspective view corresponding to FIG. 2 which shows the semiconductor module of the semiconductor device for electric power which concerns on Embodiment 2 of this invention. It is a perspective view corresponding to FIG. 2 which shows the semiconductor module of the semiconductor device for electric power which concerns on Embodiment 3 of this invention. It is a perspective view which shows the power semiconductor device which concerns on Embodiment 7 of this invention.

Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings. In the following description, terms indicating a specific direction (upper, lower, etc.) are used as necessary. These terms are used to facilitate understanding of the present invention. It should not be understood as limiting the scope of the invention. In the following description, the direction marked with “X” is called the width direction, the direction marked with “Y” is called the length direction, and the direction marked with “Z” is called the height direction. The X direction, the Y direction, and the Z direction are orthogonal to each other.

Embodiment 1. FIG.
1A, 1B, and 1C are perspective views showing a power semiconductor device 1000 according to Embodiment 1 of the present invention. The power semiconductor device 1000 includes six semiconductor modules 101, 102, 103, 104, 105, and 106. The semiconductor modules 101 to 106 are joined on the heat sink 110. A terminal block 120 extending in the length direction Y is fixed on the heat sink 110.

The six semiconductor modules 101 to 106 are arranged three by three across the terminal block 120. The semiconductor module sets 101 to 103 and the semiconductor module sets 104 to 106 are arranged side by side in the length direction Y, respectively.

As shown in FIG. 2, the semiconductor module 101 includes a substrate 10, semiconductor elements 21 and 22 disposed on the substrate 10, first main terminals 30 and second main terminals 40 that perform wiring of the semiconductor elements, Etc. The semiconductor module 101 includes a frame member 70 having a frame shape. The detailed shape of the frame member 70 will be described together with the description of the second embodiment.

Since the semiconductor modules 102 to 106 have substantially the same configuration as the semiconductor module 101 except for the first main terminal 30 and the second main terminal 40, the configuration of the semiconductor module 101 will be described below, and the semiconductor modules 102 to 106 will be described. Only parts different from the semiconductor module 101 will be described.

(Substrate 10)
The board | substrate 10 has the insulating layer 11, the surface conductor layer 12, and the back surface conductor layer 13 (refer FIG. 3). The back surface of the substrate 10 is bonded to the surface of the heat sink 110 via the first bonding layer 61. Specifically, the back surface of the back conductor layer 13 is bonded to the surface of the heat sink 110.

The insulating layer 11 is preferably made of a material having insulating properties and high thermal conductivity. Examples of the material constituting the insulating layer 11 include ceramic materials (such as AlN (aluminum nitride), Si ₃ N ₄ (silicon nitride), Al ₂ O ₃ (aluminum oxide)), and BN (boron nitride) filler. It is the contained epoxy resin insulating layer. An exemplary thickness of the insulating layer 11 is not less than about 0.3 mm and not more than about 1 mm.

Examples of the material constituting the front conductor layer 12 and the back conductor layer 13 are Cu (copper), Al (aluminum), and a laminate of Cu and Al. Exemplary thicknesses of the front conductor layer 12 and the back conductor layer 13 are about 0.2 mm or more and about 1 mm or less. The heat dissipation from the semiconductor elements 21 and 22 can be increased as the thickness of the front conductor layer 12 and the back conductor layer 13 is increased, and the thermal stress applied to the insulating layer 11 when the semiconductor elements 21 and 22 are energized as the thickness is decreased. Can be reduced. Therefore, in order to secure a margin for preventing the insulating layer 11 from being broken, the thickness may be, for example, about 0.3 to about 0.6 mm.

(Semiconductor elements 21, 22)
In the first embodiment, the semiconductor element 21 is an IGBT (insulated gate bipolar transistor), and the semiconductor element 22 is an FWD (free wheel diode). The semiconductor elements 21 and 22 may be other semiconductor elements such as a MOSFET (metal oxide semiconductor field effect transistor).

The semiconductor elements 21 and 22 are arranged side by side in the width direction X. The semiconductor elements 21 and 22 are each mounted on the surface of the surface conductor layer 12 of the substrate 10 via the second bonding layer 62.

The material of the semiconductor elements 21 and 22 may be Si (silicon), or may be a semiconductor material having a large band gap such as GaN (gallium nitride), SiC (silicon carbide), diamond, or the like. A semiconductor material having a large band gap has a high allowable current density and low power loss, so that the semiconductor elements 21 and 22 can be operated at a high temperature and the semiconductor module 101 can be downsized.

Although not shown in the figure, the front surface 21a of the semiconductor element 21 that is an IGBT is provided with an emitter that is a main electrode and a gate that is a control electrode, and the back surface (without reference numeral) of the semiconductor element 21 is the main electrode. A collector is provided. The gate receives a gate current from a control terminal (see FIG. 7). Although not shown, the semiconductor element 22 that is an FWD has electrodes provided on the front surface 22a and the back surface (no symbol). In this specification, the FWD electrode is also referred to as a main electrode. Hereinafter, the main electrodes provided on the front and back surfaces of the semiconductor elements 21 and 22 are referred to as a front main electrode and a back main electrode, respectively.

The main circuit of the power semiconductor device 1000 is constituted by the main electrodes of the semiconductor elements 21 and 22, the first main terminal 30, the second main terminal 40, and the main circuit wirings 51 to 55.

A metallized layer suitable for diffusion bonding with a conductive bonding material (hereinafter simply referred to as a bonding material) may be provided on the surfaces 21a and 22a of the semiconductor elements 21 and 22. For example, when a solder material is used as the bonding material, a metallized layer may be provided in the order of Au (gold) layer / Ni (nickel) layer from the outermost surface side. By providing the Au layer, oxidation of the outermost surface is prevented and wettability with respect to the solder material is improved. By providing the Ni layer, diffusion of the solder material from the Ni layer to the substrate side is prevented. The thickness of the Ni layer is determined in consideration of the heat application during solder bonding and the maximum temperature during operation. An exemplary thickness of the Ni layer is about 1.5 μm or more and about 5.0 μm or less. The Ni layer may be provided by sputtering in a vacuum, or may be provided by plating (which may be electrolytic plating or electroless plating).

(First main terminal 30)
The first main terminal 30 has a plate shape. The first main terminal 30 includes an electrode part 31 extending in the width direction X and a substantially L-shaped wiring part 32 extending from the electrode part 31 toward the main circuit wiring 51. The first main terminal 30 is bent between the electrode portion 31 and the wiring portion 32 and in the middle of the wiring portion 32 (L-shaped corner). An exemplary thickness of the first main terminal 30 is not less than about 0.2 mm and not more than about 1.0 mm. In view of the fact that the smaller the thickness of the first main terminal 30 is, the smaller the thermal stress applied to the semiconductor elements 21 and 22 during energization, the smaller the thickness of the first main terminal 30, the smaller the Joule heat generated during energization. Is set to an appropriate value.

The first main terminal 30 may be a single layer of Cu, or may be, for example, a laminate including a Cu layer / invar (Fe-36% Ni alloy) layer / Cu layer. By changing the thickness of each layer, the apparent linear expansion coefficient of the first main terminal 30 can be changed. The first main terminal 30 may be made of a Cu—Mo (copper-molybdenum) alloy or a Cu—W (copper-tungsten) alloy.

The electrode portion 31 of the first main terminal 30 has an electrode-side joint portion 33 joined to the surfaces 21 a and 22 a of the semiconductor elements 21 and 22 through the third joint layer 63. As a result, the electrode-side joint 33 and the entire first main terminal 30 are electrically connected to the surface main electrodes of the semiconductor elements 21 and 22. The electrode-side bonding portion 33 extends along the thickness direction (height direction Z) of the first main terminal 30 and is provided with a protrusion 34 and a through hole provided to face the surfaces 21 a and 22 a of the semiconductor elements 21 and 22. 35. The protrusion 34 protrudes along the height direction Z, and the through hole 35 penetrates along the height direction Z. The protrusion 34 is at least partially in contact with the third bonding layer 63. A bonding material constituting the third bonding layer 63 may exist in the through hole 35.

The protrusion 34 may be provided on the back surface of the first main terminal 30 as a separate body, or may be formed by press molding. When press molding is used, a recess corresponding to the protrusion 34 is formed on the surface of the first main terminal 30. The same applies to other joint portions provided in the first and second main terminals 30 and 40. Moreover, the height of the protrusion part 34 provided in each junction part may be the same.

In the drawings, a cylindrical protrusion 34 is shown, but the present invention is not limited to this, and the protrusion 34 may have any shape such as a prismatic shape, a cylindrical shape, or a plate shape. In the drawings, the through hole 35 having a circular shape in plan view is shown, but the present invention is not limited to this, and the through hole 35 may have an arbitrary shape such as a polygon in plan view. Furthermore, a cylindrical protrusion 34 may be provided at the position of the through hole 35 by press-fitting a cylindrical bush into the through hole 35. At this time, it is preferable that a hole is formed in the side surface of the protrusion 34. The modified examples of the shapes of the protrusions 34 and the through holes 35 described here can be similarly applied to other joints provided in the first and second main terminals 30 and 40.

By joining two semiconductor elements 21 and 22 arranged side by side in the width direction X with one first main terminal 30, the wiring inductance is reduced and the surge voltage applied to the semiconductor elements 21 and 22 is reduced. Can do. In addition, since the two electrode-side joints 33 provided between the first main terminal 30 and the semiconductor elements 21 and 22 can be joined at the same time in one joining process, the productivity of the power semiconductor device 1000 is improved. .

The wiring part 32 of the first main terminal 30 has a wiring side joining part 36 joined to the main circuit wiring 51 via the fourth joining layer 64. As a result, the wiring side joint 36 and the entire first main terminal 30 are electrically connected to the main circuit wiring 51. The wiring-side joint portion 36 includes a protrusion 37 and a through hole 38 that extend along the thickness direction (height direction Z) of the first main terminal 30 and are opposed to the main circuit wiring 51. The protruding portion 37 is at least partially in contact with the fourth bonding layer 64. A bonding material constituting the fourth bonding layer 64 may exist inside the through hole 38.

Note that the wiring side joints 36 of the semiconductor modules 102 and 103 are joined to the main circuit wiring 51 in the same manner as the semiconductor module 101, and the wiring side joints 36 of the semiconductor modules 104 to 106 are joined to the main circuit wiring 55. .

(Second main terminal 40)
The second main terminal 40 has a plate shape. The second main terminal 40 includes an electrode part 41 and a substantially L-shaped wiring part 42 extending from the electrode part 41 toward the main circuit wiring 54. The second main terminal 40 is bent between the electrode part 41 and the wiring part 42 and in the middle of the wiring part 42 (L-shaped corner). An exemplary thickness of the second main terminal 40 is not less than about 0.2 mm and not more than about 1.0 mm. Similar to the thickness of the first main terminal 30, the thermal stress applied to the semiconductor elements 21 and 22 during energization can be reduced as the thickness of the second main terminal 40 is smaller. In view of the fact that Joule heat can be reduced, an appropriate value is set.

Similar to the first main terminal 30, the second main terminal 40 may be a single layer of Cu, for example, a laminate composed of a Cu layer / invar (Fe-36% Ni alloy) layer / Cu layer. Alternatively, it may be made of a Cu—Mo (copper-molybdenum) alloy or a Cu—W (copper-tungsten) alloy.

The electrode part 41 of the second main terminal 40 has an electrode side joint part 43 joined to the surface conductor layer 12 of the substrate 10 via the fifth joint layer 65. As a result, the electrode-side joint 43 and the entire second main terminal 40 are electrically connected to the back main electrodes of the semiconductor elements 21 and 22. The electrode side joint 43 extends along the thickness direction (height direction Z) of the second main terminal 40 and includes a protrusion 44 and a through hole 45 provided to face the surface conductor layer 12 of the substrate 10. Have. The protrusion 44 is at least partially in contact with the fifth bonding layer 65. Inside the through hole 45, a bonding material constituting the fifth bonding layer 65 may exist.

The wiring part 42 of the second main terminal 40 has a wiring side joining part 36 joined to the main circuit wiring 54 via the fourth joining layer 64. As a result, the wiring side joint 46 and the entire second main terminal 40 are electrically connected to the main circuit wiring 54. The wiring side joint 46 includes a protrusion 47 and a through hole 48 that extend along the thickness direction (height direction Z) of the second main terminal 40 and that are opposed to the main circuit wiring 54. The protrusion 47 is at least partially in contact with the sixth bonding layer 66. A bonding material constituting the sixth bonding layer 66 may exist inside the through hole 48.

It should be noted that the wiring side joints 46 provided on the second main terminals 40 of the semiconductor modules 102, 103, 104, 105, 106 are joined to the main circuit wirings 53, 52, 54, 53, 52, respectively. The structure of the second main terminal 40 provided in each semiconductor module is changed depending on the height of the second main terminal 40 in the terminal block 120. For example, as shown in FIG. 2, the second main terminal 40 of the semiconductor module 102 has a flat shape.

(Main circuit wiring 51 to 55)
As shown in FIG. 5, the main circuit wirings 51 to 55 are fixed to the terminal block 120 and led out of the power semiconductor device 1000. As shown in FIGS. 1D and 5, the main circuit wires 51 to 55 each have a flat plate shape, and are arranged in parallel with a predetermined distance from each other. The main circuit wires 51 to 55 are exposed from the notches 121 and 122 provided on the terminal block 120. As described above, the first main terminals 30 of the semiconductor modules 101 to 103 are joined to the main circuit wiring 51. Second main terminals 40 of the semiconductor modules 103, 101, and 103 are joined to the main circuit wirings 52, 53, and 54, respectively. Although not shown, the second main terminals 40 of the semiconductor modules 106, 104, 105 are also joined to the main circuit wirings 52, 53, 54. First main terminals 30 of the semiconductor modules 104 to 106 are joined to the main circuit wiring 55.

The inverter circuit 600 shown in FIG. 6 is configured by the six semiconductor modules 101 to 106 wired using the main circuit wirings 51 to 55. Each semiconductor module constitutes one arm of the inverter circuit 600. The pair of semiconductor modules 101 and 104, the pair of semiconductor modules 102 and 105, and the pair of semiconductor modules 103 and 106 provided with the terminal block 120 interposed therebetween constitute a leg of the inverter circuit 600. The inverter circuit 600 is used as a drive circuit for driving a cage type three-phase induction motor, for example. At this time, one of the main circuit wires 51 and 55 is connected to the positive electrode of the external power supply, and the other is connected to the negative electrode of the external power supply. The main circuit wirings 52 to 54 are connected to the motor.

The main circuit wirings 51 and 52 have functions corresponding to the three-phase AC high voltage line (P) and the ground line (N) of the inverter circuit 600, respectively. As described above, each of the main circuit wirings 51 to 55 has a flat plate shape and is arranged in parallel with a predetermined distance from each other. Therefore, a magnetic field generated due to a current flowing through each main circuit wiring is a terminal. Canceled between. This minimizes the inductance component generated by the mutual magnetic field. By reducing the inductance component of the main circuit wiring, the surge voltage generated during the switching operation of the power semiconductor element 1000 is reduced, and as a result, the heat loss generated during the switching operation is reduced.

(Terminal block 120)
The terminal block 120 may be made of a resin such as PPS (polyphenylene sulfide), liquid crystal resin, or fluorine resin. The terminal block 120 may be bonded to the surface of the heat sink 110 with a silicone-based soft adhesive, or may be fixed to the heat sink 110 with a bolt by providing a screw hole in the heat sink 110.

(Heat sink 110)
Although not limited to this, the heat sink 110 has a rectangular parallelepiped shape. An exemplary size of the heat sink 110 is 350 mm × 200 mm × 50 mm. The heat sink 110 includes a top plate 111 bonded to the back surface of the substrate 10 via the first bonding layer 61, a plurality of heat radiation fins 112 attached to the top plate 111, and a coolant jacket 113 through which a coolant such as water flows. Have The refrigerant jacket 113 has an inlet portion 114 and an outlet portion 115 for circulating the refrigerant to an external radiator.

The refrigerant jacket 113 is fixed to the top plate 111 so that airtightness between the top plate 111 and the refrigerant jacket 113 is secured and leakage of the refrigerant to the outside of the heat sink is prevented. The fixing method is fixed to the top plate 111 using a method selected from 1) rubber O-ring and screwing, 2) application of sealing material and screwing, 3) brazing, and 4) friction stir welding. The

The heat sink 110 preferably has a high thermal conductivity and is easily available, and may be made of Cu or Al, for example. When the power semiconductor device 1000 is used for in-vehicle use, the heat sink 110 is preferably made of Al in order to reduce weight and improve fuel efficiency.

(First to sixth bonding layers 61 to 66)
The first bonding layer 61 is provided between the heat sink 110 and the substrate 10 of the semiconductor module 101. The bonding material constituting the first bonding layer 61 may be an Al—Si brazing material that enables direct bonding to the heat sink 110 made of Al, or may be an Sn-based solder material. Here, in the present specification, the Sn-based solder material is a solder material mainly composed of Sn (tin), for example, Ag (silver), Cu (copper), Bi (bismuth), In (indium), This refers to those to which Sb (antimony) or Pb (lead) is added. Hereinafter, for example, an Sn-based solder material in which Cu is added to Sn is shown as an Sn—Cu solder material.

If the bonding material forming the first bonding layer 61 is an Sn-based solder material and the material forming the heat sink 110 is Al, the Ni-based or Sn plating is applied to the heat sink 110 in advance, for example, to form the Sn-based solder material. By alloying with solder, it becomes easy to join both directly. It has been found that if the thickness of the plating layer is about 2 μm or more and about 10 μm or less, the wettability of the solder material and the reliability of the joint can be sufficiently satisfied.

Here, the material constituting the heat sink 110 is Al, the insulating layer 11 of the substrate 10 is Si ₃ N ₄ having a thickness of 0.32 mm, and the front conductor layer 12 and the back conductor layer 13 are Cu each having a thickness of 0.5 mm. Suppose that While the linear expansion coefficient of Al constituting the heat sink 110 is 23 ppm / K, the apparent linear expansion coefficient of the substrate 10 is about 7 ppm / K or more and about 8 ppm / K or less, and the difference between the two linear expansion coefficients is large. Become. As described above, when the difference in linear expansion coefficient between the material constituting the heat sink 110 and the material constituting the substrate 10 is large, the bonding material constituting the first bonding layer 61 is bonded with a large yield stress or 0.2% proof stress. By using a material, it is preferable to reduce the crack growth rate (crack growth amount per load cycle) of the first bonding layer 61.

The second bonding layer 62 is provided between the substrate 10 and the semiconductor elements 21 and 22. The third bonding layer 63 is provided between the surfaces 21 a and 22 a of the semiconductor elements 21 and 22 and the first main terminal 30. The fourth bonding layer 64 is provided between the main circuit wiring and the first main terminal 30. The fifth bonding layer 65 is provided between the surface conductor layer 12 of the substrate 10 and the second main terminal 40. The sixth bonding layer 66 is provided between the main circuit wiring and the second main terminal 40.

The bonding material constituting the second to sixth bonding layers 62 to 66 may be a solder material. The bonding material may be an epoxy resin adhesive mixed with a conductive filler (silver or graphite). A low-melting-point material such as a solder material has an advantage that it is easy to use because the heating temperature at the time of joining is low.

Further, the bonding materials constituting the second to sixth bonding layers 62 to 66 may be sinterable bonding materials such as an Ag-based sintering material, a Cu-based sintering material, and a CuSn (copper tin alloy) -based sintering material. . Here, the sinterable metal bonding material is a bonding material in which fine metal particles, which are aggregates, are dispersed in an organic component to form a paste, and the fine metal particles are sintered at a temperature lower than the melting point of the metal. This is a phenomenon. In the sinterable metal bonding material, the heat resistance temperature of the bonded portion can be increased by increasing the melting point of the bonding material after bonding to the original melting point as a metal.

Generally, when a metal is used at a temperature higher than the recrystallization temperature, the crystal grain boundary moves due to diffusion, and the crystal grain becomes coarse and weak against metal fatigue. Therefore, in particular, the bonding material constituting the second and third bonding layers 62 and 63 provided in the place in direct contact with the semiconductor elements 21 and 22 is a sinterable metal bonding material from the viewpoint of long-term reliability. It is preferable.

(Manufacturing method of power semiconductor device 1000)
As shown in FIG. 7, an exemplary manufacturing method of the power semiconductor device 1000 includes a step 1001 for preparing a substrate, a step 1002 for fixing the terminal block 120 to the surface of the heat sink 110, and a bonding material on the surface of the heat sink 110. Step 1003 for bonding the substrate 10 to form the first bonding layer 61; Step 1004 for bonding the semiconductor elements 21 and 22 to the surface of the substrate 10 using a bonding material to form the second bonding layer 62; Steps 1005 for bonding the first main terminals 30 to the surfaces 21a and 22a of the 21 and 22 and the main circuit wiring by using a bonding material to form the third and fourth bonding layers 63 and 64, and the surface conductor of the substrate 10 A step 1006 is formed in which the second main terminal 40 is bonded to the layer 12 and the main circuit wiring by using a bonding material to form fifth and sixth bonding layers 65 and 66.

In steps 1003 to 1006 using the bonding material, if the bonding material is a solder material, the bonding material is heated, melted, and cooled, and if the bonding material is a sinterable bonding material, the bonding material is heated. The first to sixth bonding layers 61 to 66 are formed by sintering. A solder material may be arranged at a plurality of joints, and a plurality of joint layers may be formed at a time by a known reflow process.

For example, in step 1005 for joining the first main terminal 30 to the surfaces 21a and 22a of the semiconductor elements 21 and 22 and the main circuit wiring 51, a bulk solder material is used as the joining material constituting the third and fourth joining layers 63 and 64. It is preferable to use (bar solder, plate solder, sheet solder, etc.). In the step 1005, first, a bulk solder material is disposed on each of the surfaces 21a, 22a and the main circuit wiring 51, and then the first main terminal 30 is pressed from above, so that the protrusions 34, 37 are placed in the bulk solder material. When the power semiconductor device 1000 is manufactured, the displacement of the first main terminal 30 is suppressed. In step 1006 for joining the second main terminal 40 to the surface conductor layer 12 and the main circuit wiring 54 of the substrate 10 using a joining material, similarly, as the joining materials constituting the fifth and sixth joining layers 65 and 66, By using the bulk solder material, the displacement of the second main terminal 40 is suppressed during the manufacture of the power semiconductor device 1000.

(effect)
The effect of the first embodiment will be specifically described. First, problems assumed in the power semiconductor device 1000 according to the first embodiment will be described.

For example, when the power semiconductor device 1000 is used as the inverter circuit 600 for a motor, a current of several hundred amperes normally flows through the main circuit of the power semiconductor device 1000. The third to sixth joining layers 63 to 66 of the first and second main terminals 30 and 40 constituting the main circuit join materials having different linear expansion coefficients. Therefore, when the thermal stress acting on the bonding layer increases due to the repeatedly applied temperature cycle, the crack progresses and the cross-sectional area of the bonded portion decreases. And the Joule heat which generate | occur | produces in a junction part at the time of electricity supply increases, and the thermal stress added to a junction part also becomes large. If a crack develops and a high potential difference is generated between the main surface electrodes of the semiconductor elements 21 and 22 and the main circuit wires 51 to 55, there is a problem that the electric power semiconductor device 1000 cannot operate properly due to arc discharge. .

In order to secure the reliability of the joint in consideration of the thermal stress acting on the joining layer, it is necessary to appropriately set the volume of the joining material after joining. For example, in the case of solder bonding, the bonding material is temporarily raised to the liquidus temperature and then liquefied to promote diffusion at the interface with the material to be joined, and then lowered to the solidus temperature and then solidified. The volume after bonding of the layers is determined. For example, in this way, the amount of the bonding material supplied to the bonding portion is determined.

However, even if the volume of the bonding layer is appropriate, 1) when the bonding area of the bonding layer is small (because the allowable crack range is small), or 2) when the thickness of the bonding layer is small, the bonding layer In this case, cracks tend to propagate.

When the first and second main terminals 30 and 40 are inclined from the horizontal state, the bonding area of the bonding layer is increased and decreased. The inclination of the first and second main terminals 30 and 40 is such that the tolerance of the member between the electrode side joints 33 and 43 and the wiring side joints 36 and 46 of the first and second main terminals 30 and 40, and This is caused by variations in the thickness of the bonding layer.

Consider the inclination of the first main terminal 30. The first main terminal 30 is supported by the electrode-side bonding portion 33 at a height equal to the sum of the thicknesses of the first bonding layer 61, the substrate 10, the second bonding layer 62, and the semiconductor elements 21 and 22. On the other hand, the 1st main terminal 30 is the wiring side junction part 36, and is equal to the height from the lower surface of the terminal block 120 to the notch part 121 (The terminal block 120 is joined to the top plate 111 of the heat sink 110 via a joining layer. In this case, it is supported by the sum of the height of the bonding layer. When the height of the first main terminal 30 at the electrode side joint 33 and the height at the wiring side joint 36 deviate from the ideal height, the first main terminal 30 is inclined.

In the first embodiment, the electrode side joint portion 33 and the wiring side joint portion 36 of the first main terminal 30 have the through holes 35 and 38, so that the electrode side joint portion 33 of the first main terminal 30 The deviation from the ideal height between the height and the height at the wiring side joint 36 is at least partially offset by the melted bonding material being absorbed by the through holes 35 and 38. The same effect can be obtained for the second main terminal 40. In this way, the bonding area of the third to sixth bonding layers 63 to 66 is ensured.

At this time, since the electrode side bonding portion 33 and the wiring side bonding portion 36 of the first main terminal 30 have the protrusions 34 and 37, the minimum thickness of the third to sixth bonding layers 63 to 66 is defined. Is done. The same effect can be obtained for the second main terminal 40. In this way, the thicknesses of the third to sixth bonding layers 63 to 66 are ensured.

In the first embodiment, since the two semiconductor elements 21 and 22 are joined by the one first main terminal 30, the first main terminal 30 and the semiconductor element 2122 are also formed at the same electrode-side joining portion 33. The first main terminal 30 may be inclined between the third bonding layer 63 between the first main terminal 30 and the third bonding layer 63 between the first main terminal 30 and the semiconductor element 22. Since the third bonding layer 63 and the third bonding layer 63 on the semiconductor element 22 side have the protrusions 34 and the through holes 35, the bonding area and thickness of the third bonding layer 63 can be secured.

As described above, the reliability of the electrode side joints 33 and 43 and the wiring side joints 36 and 46 of the first and second main terminals 30 and 40 is ensured.

In the first embodiment, the protrusions and the through holes are provided in all of the electrode side joints 33 and 43 and the wiring side joints 36 and 46 of the first and second main terminals 30 and 40. By providing the protrusion and the through hole in one joint, the above-described effects can be obtained at least partially.

Embodiment 2. FIG.
FIG. 8 is a perspective view showing a power semiconductor device according to the second embodiment of the present invention. In the description of the second embodiment and the drawings, the same or corresponding components as those of the first embodiment are denoted by the same reference numerals, and the description of the components is omitted.

The frame member 70 of the semiconductor module 201 of the power semiconductor device according to the second embodiment includes a housing portion 71 and a convex portion 72 that protrudes from the housing portion 71 in the length direction Y. The casing 71 of the frame member 70 is provided so as to surround the semiconductor elements 21 and 22. The terminal block side of the casing 71 in the width direction Y is cut away so as not to interfere with the wiring portions 32 and 42 of the first and second main terminals 30 and 40.

A protrusion 73 extending toward the heat sink 110 is provided on the outside of the wall surface of the frame member 70. The protrusion 73 is fitted in a recess 116 provided in the heat sink 110. By fitting the protrusion 73 into the recess 116, the positional deviation of the semiconductor module 101 during the manufacture of the power semiconductor device is suppressed.

The frame member 70 is made of, for example, a resin that can be injection-molded and has high heat resistance. The frame member 70 may be made of PPS (polyphenylene sulfide), liquid crystal resin, or fluorine resin. Although not shown, sealing resin is injected inside the frame member 70, and the semiconductor elements 21, 22, the electrode portions 31, 41 of the first and second main terminals 30, 40, and the like are sealed with resin. The frame member 70 is bonded to the front surface of the front surface conductor layer 12 of the substrate 10 via a back surface (no reference) through a seventh bonding layer (not shown). The bonding material constituting the seventh bonding layer may be a silicone-based soft adhesive.

A control terminal 80 protrudes from the frame member 70 in the height direction Z. The control terminal 80 is joined to a gate provided on the surface 21a of the semiconductor element 21 via a bonding wire 81 (or a bonding ribbon).

Although not shown, the joint between the frame member 70 and the surface conductor layer 12 of the substrate 10 is sealed and sealed with a sealing material so that the sealing resin does not flow out of the semiconductor module. Thereby, electrical insulation between the main electrodes of the semiconductor elements 21 and 22 and between the main electrodes and the heat sink 110 is ensured.

The electrode portion 31 of the first main terminal 30 has a concave portion 39 having a shape complementary to the convex portion 72 of the frame member 70. The recess 39 is formed by cutting out the vicinity of the center in the width direction X of the first main terminal 30. The concave portion 39 has a dimension substantially equal to the convex portion 72 of the frame member 70, and both are configured to engage with each other.

According to the second embodiment, the convex portion 72 of the frame member 70 fixed to the substrate 10 and the concave portion 39 of the first main terminal 30 are engaged, so that the main terminal is interposed via the third bonding layer 63. Misalignment of the main terminal 30 that occurs when 30 is bonded to the semiconductor elements 21 and 22 and the main circuit wiring 51 is suppressed.

In the above description, the convex portion 72 is provided in the casing portion 71 of the frame member 70 and the concave portion 39 is provided in the electrode portion 31 of the first main terminal 30. However, as a modification of the second embodiment, the frame member 70 is provided. Even if the housing portion 71 is provided with a recess and the electrode portion 31 of the first main terminal 30 is provided with a projection, the same effect as described above can be obtained.

Embodiment 3 FIG.
FIG. 9 is a perspective view showing a power semiconductor device according to the third embodiment of the present invention. In the description of the third embodiment and the drawings, the same or corresponding components as those of the first and second embodiments are denoted by the same reference numerals, and the description of the configuration is omitted.

In the third embodiment, a groove portion 238 extending through the first main terminal 30 in the thickness direction (the height direction Z) is formed in the wiring side joint portion 36 of the first main terminal 30. A groove portion 245 extending through the thickness direction (height direction Z) of the second main terminal 40 is formed in the electrode side bonding portion 43 of the second main terminal 40 and the wiring side bonding portion 46 of the second main terminal 40, respectively. , 248 are formed. These groove portions 238, 245, and 248 are open in the width direction X. That is, the groove portions 238, 245, and 248 are formed by opening the through holes 38, 45, and 48 shown in FIG. The grooves 238, 245, 248 may open in a direction inclined from the width direction X toward the length direction Y.

Next, effects obtained by the third embodiment will be described. In general, the appearance inspection of the bonding layer is performed before the shipment of the power semiconductor device. Specifically, 1) Is there a void or the like missing in the bonding layer, 2) Is the required amount of alloy layer formed at the interface between the bonding material and the material to be bonded, and 3) The bonding material is to be bonded? An inspection is performed to check whether the entire surface is wet and spread.

First, a transmission X-ray imaging apparatus is often used for the above-described inspection 1) to check whether a void or other missing portion has occurred in the bonding layer. However, when a transmission X-ray imaging apparatus is used, things other than the bonding layer to be confirmed, such as the heat radiation fin 112 of the heat sink 110, are reflected on the projection surface, and the missing portion in the bonding layer is detected with high accuracy. It becomes difficult. Although this problem may be solved by using an X-ray CT apparatus, since a long time is required for imaging using the X-ray CT apparatus, there arises a problem that the productivity of the power semiconductor device decreases.

Next, for the inspection to confirm whether the required amount of the alloy layer is formed at the interface between the bonding material and the material to be bonded, the determination of the unbonded region is performed by using ultrasonic flaw detection. Can do. However, since imaging using ultrasonic flaw detection takes a long time, there arises a problem that the productivity of the power semiconductor device decreases.

Here, as in the first and second bonding layers 61 and 62, in the bonding layer constituting the heat dissipation path from the semiconductor elements 21 and 22 to the heat sink 110, strict quality control may not be required for the void generation rate. In many cases, the generation rate of voids is generally managed under the process conditions in the solder bonding process. For example, in the case of a fluxless vacuum solder process, the void ratio can be indirectly managed based on a known correlation between the degree of vacuum and the void generation rate. As for the formation of the alloy layer, the formation amount of the alloy layer can be indirectly managed based on the correlation between the exposure time to the temperature above the liquidus and the formation amount of the alloy layer.

On the other hand, for the above-mentioned 3) inspection for confirming whether or not the bonding material spreads over the entire surface to be bonded, the fillet shape formed in the bonding layer at the ends of the first and second main terminals 30 and 40 is visually observed. By confirming with, it can carry out simply and effectively.

However, at or near the center of each bonding layer, the bonding material spreads over the entire surface to be bonded only by confirming the fillet shape formed in the bonding layers of the first and second main terminals 30 and 40. It is difficult to confirm that.

In the third embodiment, grooves 238, 245, and 248 are formed in the wiring side joint 36 of the first main terminal 30, the electrode side joint 43 of the second main terminal 40, and the wiring side joint 46 of the second main terminal 40, respectively. As a result, it is easier to visually recognize the fillet shape of the bonding layer while obtaining the effects described in the first and second embodiments, and confirmation of whether the bonding material spreads over the entire surface to be bonded. Accuracy is improved.

In the third embodiment, the groove portion is provided in the wiring side joint portion 36 of the first main terminal 30, the electrode side joint portion 43 of the second main terminal 40, and the wiring side joint portion 46 of the second main terminal 40. The present invention is not limited to this, and a groove portion may be provided in the electrode side joint portion 33 of the first main terminal 30. Moreover, the above-mentioned effect can be obtained at least partially by providing a groove in one or more of these four joints.

Embodiment 4 FIG.
In the description of the fourth embodiment, the same or corresponding components as those in the first to third embodiments are denoted by the same reference numerals, and the description of the configuration is omitted.

In the power semiconductor device according to the fourth embodiment, an Sn-based solder material is used as the bonding material forming the first, third to sixth bonding layers 61, 63 to 66, and the bonding material forming the second bonding layer 62 is used. As described above, a sinterable bonding material having a yield stress or 0.2% yield strength greater than that of the Sn-based solder material is used.

In the method for manufacturing a power semiconductor device according to the fourth embodiment, the first to third to sixth bonding layers 61 and 63 to 66 are collectively formed by a known reflow process as described in the first embodiment. .

Next, the effect of the fourth embodiment will be described. The second bonding layer 62 that bonds the surface conductor layer 12 of the substrate 10 and the semiconductor elements 21 and 22 is more sensitive to cracks than other bonding layers. Therefore, according to the fourth embodiment, the sinterable bonding material is used as the bonding material forming the second bonding layer 62, and the bonding forming the first to third to sixth bonding layers 61, 63 to 66 is performed. By forming these bonding layers in a lump using Sn-based solder material as a material, high reliability of each bonding portion can be ensured while improving productivity.

Embodiment 5 FIG.
In the description of the fifth embodiment, the same or corresponding components as those in the first to fourth embodiments are denoted by the same reference numerals, and the description of the configuration is omitted.

In the power semiconductor device according to the fifth embodiment, the yield stress or 0.2% proof stress is the third as the bonding material constituting the first, second, fourth, and sixth bonding layers 61, 62, 64, 66. In addition, a Sn—Sb solder material larger than the bonding material constituting the fifth bonding layers 63 and 65 is used. As a bonding material constituting the third and fifth bonding layers 63 and 65, for example, a Pb-free Sn—Cu solder material is used.

In the method for manufacturing a power semiconductor device according to the fifth embodiment, the first to sixth bonding layers 61 to 66 are collectively formed by a known reflow process as described in the first embodiment.

Next, the effect of the fifth embodiment will be described. In the first bonding layer 61, the difference in thickness between the bonding members (the heat sink 110 and the substrate 10) and the difference in linear expansion coefficient are increased. As described above, the second bonding layer 62 that bonds the substrate 10 and the semiconductor elements 21 and 22 has high sensitivity to cracks. The fourth and sixth bonding layers 64 and 66 that bond the first and second main terminals 30 and 40 and the main circuit wirings 51 and 55, respectively, preferably minimize the bonding area.

In the fifth embodiment, Sn—Sb solder material is used as the bonding material constituting the first, second, fourth, and sixth bonding layers 61, 62, 64, and 66, and the first to sixth bonding layers 61 are used. Forming these bonding layers in a lump using Sn-based solder materials as bonding materials constituting the components 66 to 66 can ensure high reliability of each bonding portion while improving productivity.

Embodiment 6 FIG.
In the description of the sixth embodiment, the same or corresponding components as those in the first to fifth embodiments are denoted by the same reference numerals, and the description of the configuration is omitted.

(Joining material)
Generally, as a solder material supply method, a method of printing cream solder obtained by impregnating fine solder balls in a flux having a reducing action, or a method of applying cream solder using a dispenser is known.

The heights of the first and second main terminals 30 and 40 are different between the electrode side joint and the wiring side joint. Therefore, when using cream solder, it is necessary to divide the printing into a plurality of times and to invert the first and second main terminals 30 and 40, which may reduce productivity.

On the other hand, when applying cream solder using a dispenser, it is possible to directly access the surfaces 21a and 22a of the semiconductor elements 21 and 22 and the main circuit wirings 51 and 52 to supply the solder material. The second main terminals 30 and 40 need not be inverted. However, it is conceivable that the solder material remains at the tip of the dispenser at the start of application, and the supply amount of the solder material varies due to the occurrence of liquid breakage when the dispenser is lifted after the application is completed.

Also, when cream solder is used, flux residues may be joined, causing a failure in long-term reliability. Therefore, in general, when cream solder is used, the flux residue is removed using an ultrasonic cleaning method. However, when this method is employed in the power semiconductor device according to the embodiment of the present invention, it is necessary to clean the whole together with the resin components such as the frame member 70 and the terminal block 120. As a result, it is necessary to provide a means for preventing the scattering of foreign matters from the resin component in addition to the means for removing the residue, and the manufacturing cost of the power semiconductor device 1000 increases.

In view of such problems, in the sixth embodiment, a fluxless solder material is used as the bonding material constituting the first to sixth bonding layers 61 to 66. This fluxless solder material is obtained, for example, by rolling minute solder balls containing no flux into a sheet. The fluxless solder material is punched with a blade type that is harder than Sn solder.

Since the fluxless solder material is in the form of a sheet, the amount of solder material supplied to each joint can be stabilized. Further, by using a fluxless solder material, it is basically unnecessary to perform cleaning after soldering.

(Bonding material heating method)
In general, as a heating method for fluxless solder materials, 1) an atmosphere heating method in which hot air is sent into a reflow bath, 2) a heat transfer method from a heating block to a workpiece, and 3) a radiant heat method using infrared rays such as a halogen lamp. There are mainly three methods.

Here, when using a fluxless solder material, it is common to use a reducing gas such as formic acid or hydrogen having reducing power instead of flux. In the case of atmospheric heating method, it is necessary to provide a reflow tank that efficiently sends hot air, but when formic acid and hydrogen gas are used, a reflow tank is used to prevent generation of off-flavors due to gas containing acidic formic acid, hydrogen explosion, etc. It is necessary to provide airtightness. However, it is difficult to efficiently send hot air while ensuring the airtightness of the reflow tank, or the manufacturing cost of the reflow tank is increased.

Next, in the case of the heat transfer method, when solder bonding is performed between the heat sink 110 and the substrate 10, which are larger than other components, as solder joint components, depending on the amount of warpage of the heat sink 110, air may be introduced into the heat transfer path. There will be intervening layers. Since air has a low thermal conductivity, it is considered that the temperature difference between the surfaces to be joined and the variation in temperature within each surface to be joined cannot be eliminated.

Next, in the case of the radiant heat method, heat transfer shortage and heat transfer distribution due to shape factors such as warpage of the heat sink 110 do not occur. Further, unlike the atmosphere heating method, it is not necessary to provide a reflow tank that is airtight and that can efficiently send hot air. However, where the emissivity varies greatly depending on the type of material constituting the heat receiving surface, the roughness of the surface, and the degree of oxidation of the material, there is a possibility that heat cannot be transferred efficiently depending on the size of the emissivity.

As a result of the test research by the present inventors, if the emissivity of the bonded object is 0.3 or more, the radiant heat method is used. If the emissivity of the bonded object is 0.3 or less, the heat transfer method is used. As a result, it was found that the heat transfer efficiency can be increased and soldering can be performed, which improves productivity. Therefore, in the sixth embodiment, a fluxless solder material is used as a bonding material in steps 1003 to 1006 shown in FIG. 7, and a radiant heat method or a heat transfer method is used to heat the fluxless solder material in accordance with the emissivity of the objects to be bonded. Adopt as a method.

Embodiment 7 FIG.
As described above, when a radiant heat method using an infrared light source (such as a halogen lamp) is used as a heating method for the fluxless solder material, the emissivity increases depending on the type of material constituting the heat receiving surface, the roughness of the surface, and the degree of oxidation of the material There are cases where heat transfer cannot be performed efficiently depending on the emissivity. In addition, as described above, the first and second main terminals 30 and 40 made of a material such as Cu and Al with the fourth and sixth bonding layers 64 and 66 sandwiched therebetween, PPS, liquid crystal resin, and fluorine resin. And a terminal block 120 made of a resin material.

Here, the wavelength of light emitted from the halogen lamp is typically about 1 μm or more and about 10 μm or less. The emissivity for light in this wavelength range is 0.1 or less for non-oxidized surfaces of Cu and Al, and 0.85 or more for resin materials such as PPS, liquid crystal resin, and fluorine resin. Therefore, the emissivity may be greatly different between the materials constituting the adjacent members.

In order to shorten the processing time at the time of soldering and increase productivity, when the energy of radiant heat is increased, the amount of energy transmitted to the resin material located in the vicinity of the fourth and sixth bonding layers 64 and 66 increases. Become. When this resin material reaches a temperature exceeding the softening temperature or decomposition temperature of the resin, part of the terminal block 120 may not function as a structural material.

Therefore, in the seventh embodiment, a fluxless solder material is used as a bonding material in steps 1005 and 1006 for forming the fourth and sixth bonding layers 64 and 66, and the terminal block 120 is fixed to the surface of the heat sink 110. The terminal block 120 (see FIG. 10) provided with a terminal block cover 121 is used.

The terminal block cover 121 is provided so as to cover the terminal block 120 as a whole. The terminal block cover 121 has the same emissivity as (or the same as) the material constituting the first and second main terminals 30 and 40. The terminal block cover 121 may be made of a metal material such as Cu or Al. The emissivity of the terminal block cover 121 may be adjusted not only by the type of material constituting the terminal block cover 121 but also by the roughness of the surface and the degree of oxidation of the material.

According to the seventh embodiment, when the terminal block 120 is covered with the terminal block cover 121, the fourth and sixth bonding layers 64 and 66 are formed by heating the flexless solder material using radiant heat. Even in such a case, it is possible to increase the energy of the radiant heat while suppressing the temperature rise of the terminal block 120 made of a resin material, thereby reducing the time required for soldering and improving the productivity.

Although the present invention has been described with reference to a plurality of embodiments, it should be understood that the present invention is not limited to the embodiments. The features described in each embodiment may be freely combined. Various improvements, design changes, and deletions may be added to the embodiments.

10 substrate, 11 insulating layer, 12 surface conductor layer, 13 back conductor layer, 21, 22 semiconductor element, 21a, 21b (semiconductor element) surface, 30 first main terminal, 31 (first main terminal) electrode part, 32 (first main terminal) wiring part, 33 electrode side joint part, 34 protrusion part, 35 through hole, 36 wiring side joint part, 37 protrusion part, 38 through hole, 39 concave part, 40 second main terminal, 41 ( Electrode part of second main terminal), 42 (second main terminal) wiring part, 43 electrode side joint part, 44 projection part, 45 through hole, 46 wiring side joint part, 47 projection part, 48 through hole, 51- 55, main circuit wiring, 61-66, first to sixth bonding layers, 70 frame members, 72 convex parts, 80 control terminals, 101-106, 201, 01 semiconductor module, 110 a heat sink, 120 terminal blocks 238 and 248 grooves, semiconductor device 1000 power

Claims (12)

1. A substrate,
   A semiconductor element having a back surface bonded to the substrate and a surface provided with a first main electrode;
   A plate-like first main terminal having an electrode-side bonding portion bonded to the surface of the semiconductor element via a conductive bonding layer and electrically connected to the first main electrode;
   The electrode-side joint portion of the first main terminal has a protrusion and a through-hole that extend along the thickness direction and is provided to face the surface of the semiconductor element.
   Power semiconductor device.
2. A first main circuit wiring led out of the power semiconductor device;
   The first main terminal has a wiring-side bonding portion bonded to the first main circuit wiring through a conductive bonding layer,
   The wiring side junction of the first main terminal has a protrusion and a through hole that extend along the thickness direction and is provided to face the first main circuit wiring.
   The power semiconductor device according to claim 1.
3. The substrate has a conductor layer;
   The semiconductor element has a plate-like second main electrode provided on the back surface of the semiconductor element and bonded to the conductor layer of the substrate;
   The power semiconductor device includes a second main terminal having an electrode-side joint portion joined to the conductor layer of the substrate via a conductive joint layer and electrically connected to the second main electrode of the semiconductor element. Is further provided,
   The electrode side joint portion of the second main terminal extends along its thickness direction and has a protrusion and a through hole facing the conductor layer.
   The power semiconductor device according to claim 1.
4. A second main circuit wiring led out of the power semiconductor device;
   The second main terminal has a wiring side bonding portion bonded to the second main circuit wiring through a conductive bonding layer,
   The wiring side junction of the second main terminal extends along its thickness direction and has a protrusion and a through hole facing the conductor layer.
   The power semiconductor device according to claim 3.
5. A frame member surrounding the semiconductor element;
   The frame member has an engagement portion with the first main terminal,
   The first main terminal has an engaged portion having a shape complementary to the engaging portion of the frame member.
   The power semiconductor device according to any one of claims 1 to 4.
6. Provided in at least one of the electrode side junction of the first main terminal, the wiring side junction of the first main terminal, the electrode side junction of the second main terminal, and the wiring side junction of the second main terminal The formed through hole is opened in a direction perpendicular to the thickness direction to form a groove,
   The power semiconductor device according to claim 4.
7. The semiconductor element is a first semiconductor element;
   The power semiconductor device includes a back surface provided with a third main electrode bonded to the conductor layer of the substrate, and a fourth main electrode bonded to an electrode side bonding portion of the first main electrode. A second semiconductor element having a surface,
   The power semiconductor device according to claim 1.
8. Preparing a substrate;
   Bonding a semiconductor element to the substrate;
   Arranging a plate-like main terminal on the semiconductor element via a bulk solder material;
   Heating the bulk solder material to join the semiconductor element and the main terminal,
   The main terminal has a protrusion and a through hole that extend along the thickness direction and is provided to face the surface of the semiconductor element.
   In the step of disposing the main terminal, the bulk solder material is fixed to the protrusion.
   A method of manufacturing a power semiconductor device.
9. In the step of bonding the semiconductor element, the semiconductor element is bonded to the substrate using a sinterable bonding material having a yield stress or 0.2% proof stress greater than that of the bulk solder material.
   A method for manufacturing a power semiconductor device according to claim 8.
10. In the step of bonding the semiconductor element, the semiconductor element is bonded to the substrate using a Sn—Sb solder material having a yield stress or 0.2% proof stress greater than that of the bulk solder material.
    A method for manufacturing a power semiconductor device according to claim 8.
11. The bulk solder material is a sheet-like fluxless solder material,
    The method for manufacturing a power semiconductor device according to claim 8.
12. The main terminal is joined to the main circuit wiring,
    Bonding the substrate onto a heat sink;
    A step of fixing a resin terminal block to which the main circuit wiring is fixed on the heat sink;
    The terminal block is covered with a metal terminal block cover,
    In the step of joining the semiconductor element and the main terminal, the bulk solder material is heated by radiant heat.
    The method for manufacturing a power semiconductor device according to claim 8.

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