WO2017203534A1

WO2017203534A1 - Simultaneous mimo communication system

Info

Publication number: WO2017203534A1
Application number: PCT/IN2016/050152
Authority: WO
Inventors: Lakshmi Mohan SARIPALLI; Balaji VENKATACHALAM
Original assignee: Thotaka Tekhnologies India Private Ltd
Priority date: 2016-05-24
Filing date: 2016-05-24
Publication date: 2017-11-30

Abstract

The present invention is a unique combining and a decoding system aided with a Multilevel Equalizer consisting of two equalizer units for a single carrier, Phase-Shift Keying (PSK) modulated MIMO system. The system is equipped with a unique aligning, combining and equalizing units performs an equalization operation before combining the multipath input data, obtained through various antennas. The multipath signals are aligned, combined and equalized to reduce the effect of Inter-Symbol Interference (ISI) introduced due to the increased data rates.

Description

SIMULTANEOUS MIMO COMMUNICATION SYSTEM FIELD OF THE INVENTION

This invention relates to a Multiple Input Multiple Output (MIMO) Communication System that can align, combine and equalize the multipath signals, thereby reducing the effect of Inter-Symbol Interference (ISI) introduced due to the increased data rates.

BACKGROUND OF THE INVENTION

The conventional telecommunication systems involving Multiple Input Multiple Output (MIMO) arrangements require the installation of several antennas for transmitting and receiving the signals in order to obtain the final output signal with improved Carrier-to-Noise ratio (C/N). Moreover, the multiple received signals undergo different time delay in the path which creates the need for a system which can time-align, phase align, combine and equalize the multipath signals to remedy the effects caused by the attenuation of the input stream. In addition, the data contained in the multiple input signals may be subjected to Inter-Symbol Interference (ISI), due to the overlapping of the symbols with the adjacent symbols because of increase in the data rate.

The MIMO system equipped with a unique aligning, combining and equalizing units can resolve the above-stated issues by performing an equalization operation before combining the multipath input data, obtained through various antennas. Another important factor that can affect the final signal information is the errors after the combination process, which can lower the accuracy of the decoded information. So, there is a need for an efficient equalization process after the combiner, that can offer a scope to use lower code rate Forward Error Correction (FEC) algorithms, leading to a higher bandwidth. DISCUSSION OF PRIOR ART

The systems involving Multiple Input Multiple Output (MEVIO), related to the telecommunication devices require various arrangements for processing the multiple input signals so as to render the final output to be free of errors that may have been induced due to the phenomenon such as multipath fading, Inter-symbol Interference, multipath dispersion, degraded Carrier-to-Noise Ratio. The arrangement includes units that deal with aligning, equalization or combination steps for processing these multipath signals.

CN102820934 A-l titled "Improved MRC (maximum ratio combining) detection method" discloses an improved method for maximum ratio combining (MRC) detection. The main characteristics being regulation of receiving signal amplitude in detection so as to facilitate the noise energy to be identical in every receiving diameter signal. The establishment of significant factors in a traditional MRC detection method to counterweigh unbalance of gain and noise of the radio frequency links among the receiving antennas such that the noise energy of the ultimate diversity diameters can be equal. Thus, obtains better performance over the original MRC detection method.

US007817748 B2 titled "Pragmatic Adaptive Maximum Ratio Combining (MRC) and Minimum Mean Square Error (MMSE) Multiple Input Multiple Output-Orthogonal Frequency Division Multiplexing (MIMO-OFDM) receiver algorithm''' discloses an adaptive receiver algorithm to be used in multiple-input- multiple-output orthogonal frequency division multiplexing systems. Based on the characteristics of the wireless environment, the adaptive receiver algorithm for optimum receiver performance carefully picks up either the maximum ratio combining technique or the minimum mean square error technique.

US007912142B2 titled "Double layer maximum ratio combining for an OFDM receiver with inter-carrier-interference cancelling" discloses an apparatus, method, and system to reduce Carrier-to-Noise Ratio (C/N) in an OFDM receiver applying diversity combining techniques in the existence of ICI. The apparatus consists of an encoded data estimator adapted to assess the data received in the OFDM receiver. For calculating an inter-carrier-interference term of the data, a tailored pair of ICI estimators is actively connected to the encoded data estimator. The balancing of multi-path interference of the data is done by a custom-made pair of diversity combining equalizers in which the first one of the diversity combining equalizers is operatively connected to the encoded data estimator and the second to the pair of ICI estimators. The diversity combining equalizer may include an MRC diversity combining equalizer. The encoded data estimator along with the pair of ICI estimators and diversity combining equalizers are implemented on a DVB-T/H diversity SoC preferably.

US007925234 B2 titled "Method for maximal ratio combining of spatially filtered signals and apparatus therefor" describes an apparatus and the method of maximum ratio combining of spatial-filtered received signals. The method for receiving signals by using a linear array antenna/multiple antennas, multiplying the several weight vectors by the received signals, adding the multiplication results for each weight vector and combining the results by using maximum ratio combining. The signals are separately received by applying spatial filtering in a receiving direction of each signal, and the performance can be improved by combining the received signals by using maximum ratio combining. The performance of an MRC-rake and a beam forming gain can be concurrently acquired in addition.

US008351534 B2 titled "Distributed maximal ratio combining receiver architecture" describes a wireless communication system that contains receivers configured independently in synchronization to the received waveform using its local received signal only. The frequency and/or phase error is eradicated by the local receiver based on the information encoded in the received waveform. The local receiver uses channel probe information that is embedded in the received waveform to provide channel estimates for the corresponding communication. Based on the estimates, the received signals are modified for phase shift and amplitude scaling produced by the channel. The partial demodulation and the signal acquisition are done independently for each channel. The system utilizes a maximal ratio combiner to merge the signals from each channel.

US20090296848 Al titled "Joint maximal ratio combining using time-domain based signal processing" discloses a communication device that transmits and receives communication signals through antennas, receive tapped delay-line filters, combiner/analyzer with multiple filters for signal processing and computation blocks all in multiples, with another communication device. The complex weights for the tapped delay-line filter to optimize the receiving signal- to-noise ratio and the range of communication is determined by the computational blocks.

US20140233625A1 titled "Maximal ratio combining of equalized symbols for MIMO systems with HARQ and/or repetition coding" discloses the systems and methods to decode the signal vectors in the multiple-input multiple out (MIMO) systems in which one or more signal vectors are received by the receiver based on the same transmitted vector. To linearize each received signal vector, one or more zero-forcing, MMSE or other suitable linear equalizers are applied. By combining components of the equalized signal vectors using maximum-ratio combining, the components of the combined equalized signal vector is derived, which are then decoded using a linear decoder individually. The above stated prior arts employ various techniques to improvise the carrier-to- noise ratio (CNR)/signal-to noise ratio (SNR) mainly involved in the Multiple- Input Multiple- Output (MIMO) system. One such method includes the use of a joint maximal ratio combining technique having a dual set of communication tools with several antennas that optimize the signal-to-noise ratio (SNR) in the transmission of data from one set of the communication device to the other. Another invention focuses on improving the MRC technique by adjusting the detection ability of the noise energy in varying receiver signals so as to equalize the difference so obtained. Although the CNR/SNR factors are enhanced by these processes, however, the system requires much iteration and also involves relative complexity in comparison to single MRC based system. Hence, it is important to have a system which reduces the factors like Inter-Symbol Interference (ISI) and Multipath dispersion by means of an effective equalization process prior to the application of the combining techniques so that the effects of fading of the signals is reduced, and the Carrier-to-Noise Ratio is enhanced even by using simple combining systems.

Another invention makes use of two diversity combining equalizer systems to improve the Carrier-to-Noise Ratio. However, this arrangement requires the estimation of the encoding data and the calculation of the Inter-Carrier Interference (ICI) for each channel of the system. Despite this method making use of dual equalization units, there is a no provision for storing the ICI estimations in the form of data history that may assist in reducing the iteration.

Another important factor that can affect the final signal information includes the errors induced during the combination process, which can lower the accuracy of the decoded information. Also, there is a need for an effective equalization process that can offer a scope to use lower code rate Forward Error Correction (FEC) systems, leading to higher bandwidth.

SUMMARY OF THE INVENTION

The present invention describes a Unique Combining and a Decoding system aided with a Multilevel Equalizer consisting of two equalizer units for a single carrier, Phase-Shift Keying (PSK) modulated MIMO system. The MIMO system comprises multiple hardware and software components. The system includes an Ethernet Communication Interface, which accepts user data that is to be transmitted. This data is handed over to an Application Processor that presents the payload to the Transmit side of the Baseband Processor. The Transmit Side of the Baseband Processor comprises a High-Level Data Link Control (HDLC) Encoder, Data Scrambler/Interleaver, Forward Error Correction Encoder with a User Selectable Code Rate and a Burst Modulator, which splits the data into I and Q samples and gives out of the Baseband Processor as parallel data. The parallel data is forwarded to a Digital to Analog Converter (DAC) through a Buffer and, an analog signal which is proportional to the digital value is generated. The Analog I and Q signals are forwarded to an IQ Modulator, which converts the I and Q signals into complex Intermediate Frequency (IF) signal. This signal is passed through a Transmit IF Frontend, which comprises a Surface Acoustic Wave (SAW) Filter, followed by a Low Noise Amplifier (LNA) that provides the necessary passband amplification and a Digital Step Attenuator (DSA). The output of the DSA is transmitted further using a power splitter.

On the receiving side, receive channel corresponds to the input signal given to the system through the connectors. Each of the receive channels are passed through IF Front End, IQ Demodulator, a signal conditioning circuit and an Analog to Digital Converter (ADC). The IF Frontend comprises a Low Noise Amplifier (LNA) to provide the required passband amplification, a User-Programmable Digital Step Attenuator (DSA) that provides required attenuation to prevent the subsequent modules from getting into saturation, and an SAW Filter network for bandwidth selection. The IQ Demodulators on each receive channel converts the complex IF signal into baseband I and Q signals. These I and Q signal are passed through a signal conditioning circuit which prepares the analog signal to be suitable for the Analog to Digital Converter for conversion of the analog signal to a proportional, multi-bit parallel digital value. The IQ Demodulators convert the Intermediate Frequency (IF) signal to a baseband signal.

The output of the Analog to Digital convertors is given to Multilevel Equalizer Aided Channel Combining and Demodulator 511, which is subsequently demodulated and converted to bits. The bit errors are corrected using Forward Error Correction Decoder with Code Rate same as that of Transmitter. Then this signal is descrambled using a Descrambler and is given to High-Level Data Link Control (HDLC) De-framer. The bits thus obtained are sent out through the Ethernet Communication Interface. The modular simultaneous MIMO communication system comprising a PC, a System Ethernet interface, a Receive block, a Transmit block, an Oven-Controlled Crystal Oscillator (OCXO) and a Clock Distribution. The PC is any computing device that can transmit and receive Ethernet data. The PC is connected through the System Ethernet interface to the Receive block R and the Transmit block T. The Clock Distribution refers to a circuit that performs distribution of Clock from the OCXO or an external Clock throughout the system. The OCXO provides an ultra-low jitter 10MHz clock and is powered independently, to eliminate any clock leakage on power supply lines. The system can also be clocked from a 10MHz external clock source instead of an internal OCXO.

In the present invention of the modular simultaneous MIMO communication system in which the System Ethernet Interface refers collectively to an Ethernet data processing system that includes an Ethernet Data Port, an Ethernet Control Port, an ETH2TXIPB application, a Baseband Logic, a Transmit Inter-Processor Bus, an IPB2MODEM Writer, a DPDCM, a HDLC encoder, a HDLC decoder, a XCLK domain, a MODEM2IPB writer, a Receive Side Inter-Processor Bus, a RXIPB2ETH application, a Baseband Processor and an Application Processor. Input Bits are transformed to analog stream and are transmitted over an Intermediate Frequency (IF) interface. In this invention, the Transmit block consists of a Scrambler, an FEC Encoder, a Modulator, a DAC driver, a Digital to Analog Converter (DAC), a DAC DATACLK Generator, a Low Pass Filter, an IQ-Modulator, an IQ-Modulator LO Generator, an IF Front-end, a Splitter and Transmission channels. The scrambler is used to enable accurate timing recovery on the receiver without resorting to redundant line coding and to disperse energy on the carrier. It disperses the data to meet the maximum power spectral density requirements. Scrambled Input Bits are those transmitted after scrambling and interleaving process. The FEC Encoder is a suitable standard forward error correction encoder used to encode the data. Encoded and Scrambled Input Bits are bits after Scrambling and FEC encoding processes. The Burst Modulator converts the data bits to In-phase (I) and Quadrature-Phase (Q) data with appropriate gain and further converts the stream of I and Q data to a user selected data rate without any drop in received input data. The DAC Driver runs on a user selected Clock Frequency, which is an operating frequency of the Digital to Analog Converter and converts the data into a format suited for the same. The Digital to Analog Converter produces an analog waveform proportional to digital value of transmit data, accepts a multi-bit parallel digital data from the DAC Driver and produces an analog voltage proportional to the digital value. The Digital to Analog Converter has dual channels, one for In-Phase (I) data and the other for Quadrature-phase (Q) data. The Low Pass Filter eliminates harmonics that are outside of passband from an output of the Digital to Analog Converter to conserve bandwidth. The IQ- Modulator combines the In-phase (I) and the Quadrature-phase (Q) outputs of the Low Pass Filter and upconverts to Intermediate Frequency (IF). The IF Front-end comprises an SAW Filter network, Attenuators and Low Noise Amplifiers of the Transmit side. The Splitters ends two copies of the signal to two different transmit ports. The Transmit Out-1 is the signal given to one transmit port and thereon to the associated transmit connector, whereas the Transmit Out-2 is the signal given to another transmit port and then to the associated transmit connector. The IQ- Modulator is clocked by the IQ-Modulator LO Generator, which in turn receives its input clock from the DAC Data Clock Generator. The DAC Data Clock Generator generates the clock required for the Digital to Analog Converter from the Clock Distribution.

The Receive block R consists of Receive Channel- 1, Receive Channel-2, Receive Channel-3 and Receive Channel-4,Intermediate Frequency (IF) Front-end- 1, Intermediate Frequency (IF) Front-end-2, Intermediate Frequency (IF) Front-end- 3and Intermediate Frequency (IF) Front-end-4,IQ Demodulators, Signal Conditioning, Analog to Digital Converters (ADC),a Multilevel Equalizer Aided Channel Combining and Demodulator, a Forward Error Correction (FEC) Decoder, a Descrambler, a 4x IQ DEMOD LO Generator and a 4xADC CLK Generator. The Descrambler organizes the data which is muddled by the Scrambler during the transmission. The Scrambled Bit Output corresponds to an input of the Descrambler. The FEC Decoder on the receive side is responsible for decoding of the data which is encoded by the FEC Encoder on the transmit side such that, if the FEC Encoder is disabled on the transmit side then the FEC Decoder will be evaded. Bit Error Rate (BER) corresponds to number of bit inaccuracies that are observed over a predefined data length. Encoded and Scrambled Bit output is bits before being sent to the FEC Decoder. The Multilevel Equalizer Aided Channel Combining and Demodulator acquires the data from the multiple Analog to Digital Converters (ADC), performs Co-Phasing, subsequently diversity combining, equalizes and demodulates the signal to obtain the data. The Analog to Digital Converters (ADC) converts the analog baseband signal to a proportional multi-bit parallel digital value. The Signal Conditioning prepares analog signal to be suitable for the Analog to Digital Converters (ADC). The IQ Demodulators convert the Intermediate Frequency (IF) signal to a baseband signal. The Intermediate Frequency (IF) Front-end comprises of Analog Filter networks, Attenuators and Low Noise Amplifiers for each receive channel. Multiple Receive Channels corresponds to the input signal given to the system through connectors of the enclosure. The 4x IQ DEMOD LO Generator generates the clock required for the respective IQ Demodulator and, 4 x ADC Clock Generator generate the clock necessary for the respective Analog to Digital Converter.

In the present invention of the modular simultaneous MIMO communication system, the Baseband processor and Application Processor in a chip with its embedded blocks comprising, an Ethernet Data Port, an ETH2TXIPB application, a Baseband Logic, a Transmit Inter- Processor Bus, an IPB2MODEM Writer, a DPDCM, a HDLC encoder, a HDLC decoder, a XCLK domain, a MODEM2IPB writer, a Receive Side Inter-Processor Bus, a RXIPB2ETH application, a Baseband Processor, an Application Processor, a Burst Modulator, a DPDCM Lossless, a DAC Driver, a Descrambler, an FEC Decoder, an FEC Encoder, a Scrambler, a Digital data to DAC via one or more interface connectors, Scrambled Bit output and Bit Error Rate (BER). The Ethernet Data Port obtains transmit data and sends out received data. The ETH2TXIPB Application is responsible for manipulating the user data such as providing compression and encryption of data received from the PC via the Ethernet Data Port. The Baseband Logic encapsulates all the processing involved in converting the Multilevel Equalizer Aided Channel Combining and Demodulator output to bits. This also encapsulates processing involved in converting the bits suitable for input to Digital to Analog Converter (DAC). The Transmit Inter-Processor Bus which is of any Standard Inter-Processor Communication Bus forwards the data obtained from the Application Processor to the Baseband Processor. The IPB2MODEM Writer is responsible for generating the flow control signal so as to match the data transmission speed of the Application Processor, which also acts as a buffer to match the speeds of the Application Processor to the Baseband Processor. The DPDCM converts the stream of In-phase (I) and Quadrature-Phase (Q) data to the user selected data rate. The HDLC Encoder is a standard High-Level Data Link Control (HDLC) and is a bit oriented code transparent synchronous data link layer protocol that converts the 8-Bit parallel data to 1-Bit serial data. Also, adds the header, footer and standard Cyclic Redundancy Check (CRC) and manipulates the data in order to eliminate the header occurrence in the data stream. The XCLK Domain converts the data on a User Clock into a standard clock which is used for further processing. The MODEM2IPB writer translates the flow control signal from the Baseband Processor and the Application Processor, also acts as the buffer to synchronize the Baseband Processor and Application Processor. The Receive Side Inter-Processor bus is responsible for handing over the data obtained from the Receive block R of the system to the RXIPB2ETH Application which aids in manipulating the user data such as providing decompression and decryption of the received data packets. The Baseband Processor modulates the data received from the Application processor and also decodes the data received from the Multilevel Equalizer Aided Channel Combining and Demodulator. The Application Processor and the Baseband Processor is realized as one or more Application Specific Integrated Circuits (ASIC) or Field Programmable Gate Arrays (FPGA's) or a combination of both. The FEC Encoder is a suitable standard forward error correction encoder used to encode the data. The Burst Modulator converts the data bits to In-phase (I) and Quadrature-Phase (Q) data with appropriate gain. The DPDCM Lossless converts the stream of In-phase (I) and Quadrature Phase (Q) data to the user selected data rate without skipping any input data received. The DAC Driver runs on a selected clock frequency, which is the operating frequency of the Digital to Analog Converter and converts the data into a format suited for the same. The FEC Decoder on receive signal processing side is responsible for decoding of the data that is encoded by the FEC Encoder on the transmit side and if the FEC Encoder is disabled on the transmit side, the FEC Decoder will be bypassed. The Scrambler is used for the following purposes, to enable accurate timing recovery on the receiver without resorting to redundant line coding and to disperse the energy on the carrier. It also disperses the data to meet the maximum power spectral density requirements. The Descrambler organizes the data which is muddled by the Scrambler during the transmission. The HDLC Decoder undoes the action done by the HDLC Encoder and converts the bit data into bytes and CRC is used to validate the byte data and subsequently removed. The Digital data to DAC via one or more interface connectors is the entry point for the TX CHAIN PCB assembly. The data from Transmit of the Baseband Processor will enter the TX CHAIN PCB Assembly via the Inter-board Connectors.

A modular apparatus for simultaneous MIMO communication having a Communication Modem whose components include an Ethernet Data Port, an Ethernet Control Port, an Application Processor, a Baseband Processor, a transmit PCB assembly, a receive PCB assembly, a Multilevel Equalizer Aided Channel Combining and Demodulator, an OCXO and a Clock Distribution. The transmit PCB assembly, TX Chain PCBA-Front-end includes transmit ports, a Digital to Analog Converter and forms a transmit analog signal conditioning part of the system and, one or more transmit ports to transmit Intermediate Frequency (IF) signal. The receive PCB assembly having a Front-end comprising, a RX Chain PCBA-Front-end-l,a RX Chain PCBA-Front-end-2,a RX Chain PCBA-Front- end-3and a RX Chain PCBA-Front-end-4, and one or more receive ports including, RX PORT-1, RX PORT-2, RX PORT-3and RX PORT-4, where the PCBA-Front-end provide signal conditioning to the IF received from receive ports. The Ethernet Data Port obtains transmit data and sends out received data while the Ethernet Control Port enables to control and configure the characteristics of modem sub-system running in the Baseband Processor.. The Application Processor facilitates the exchange of data between the Ethernet Data Port and the Baseband Processor and is realized as one or more Application Specific Integrated Circuits or Field Programmable Gate Arrays (FPGA's) or a combination of both. The Baseband Processor performs the function of modulating the data received from the Application Processor and also decodes the data received from the Multilevel Equalizer Aided Channel Combining and Demodulator and is realized as one or more Application Specific Integrated Circuits or Field Programmable Gate Arrays (FPGA's) or a combination of both.

In this invention, the modular apparatus of a wholly enclosed system in isometric view has the front panel comprising an Ethernet Data Connector, an Ethernet Control Connector, a RX Connector- 1, a RX Connector-2, a RX Connector-3,a RX Connector-4,aTX Connector- 1, a TX Connector-2andan external Clock Connector. The Ethernet Data Connector is connected by a cable to the Ethernet Data Port. The Ethernet Control Connector provides an interface to configure the Baseband Processor and the Application Processor, and is situated in an enclosure of the apparatus connected by a cable to the Ethernet Control Port. The RX Connector- 1, RX Connector-2, RX Connector-3, RX Connector-4are on a field space of the apparatus that are connected by a cable to the receive ports, RX Port- 1, RX Port-2, RX Port-3, RX Port-4. The TX Connector- land TX Connector-2are connected to TX Port-landTX Port-2by a cable. The external Clock Connector is a connector that carries an external 10 MHz stable reference to the system and can be used instead of the OCXO assembled into the system. The transmit PCB Assembly consists of a Digital to Analog Converter (DAC), an IQ-Modulator, a TX Low Pass Filter, a TX Saw Filter- 1, a TX Saw Filter-2,a TX Digital Step Attenuator, a TX Low Noise Amplifier, a Splitter, transmit ports, TX Port-1, TX Port-2,an IQ MOD LO Generator, a DAC DATACLK Generator and Digital data to DAC via one or more interface connectors. The Digital to Analog Converter (DAC) has dual channels, one for In-Phase (I) data and other for Quadrature-phase (Q) Data, accepts a multi-bit parallel digital data and produces an analog voltage proportional to the digital value. The TX Low Pass Filter that removes the harmonics that are outside of a passband from the output of the Digital to Analog Converter to conserve bandwidth, and the TX Low Noise Amplifier provides amplification to bandpass signal. The IQ-Modulator that combines the In-phase (I) and Quadrature-phase (Q) outputs of the TX Low Pass Filter and upconverts to Intermediate Frequency (IF). The TX Saw Filter- that removes the out-of-band noise in a spectrum of the Transmit signal, and the TX Digital Step Attenuator prevents subsequent components from getting into saturation, also aids to attenuate signal strength, if required. The TX Saw Filter- 2that is responsible for removing out-of-band noise in the spectrum of the Transmit signal which is introduced after the TX Low Noise Amplifier. The Splitter is applied to achieve transmit diversity by sending two copies of the same signal to two transmit ports. The transmit Intermediate Frequency (IF) signal that is given to the transmit ports TX Port-1 and TX Port-2, number of ports is any even number as determined during installation. The IQ MOD LO Generator generates clock required for the IQ-Modulator from the DAC DATACLK Generator, and the DAC DATACLK Generator generates the clock needed to the Digital to Analog Converter from the Clock Distribution. The Digital data to DAC via one or more interface connectors refers to a digital form of data that is given to the Digital to Analog Converter, the digital value corresponds to an analog voltage value which is the output of the Digital to Analog converter.

The receive PCB Assembly consists of an Analog to Digital converter, a ADC CLK Generator, an IQ DEMOD LO Generator, an IQ Demodulator, an Amplifier, a RX Saw Filter-2,a RX Saw Filter- 1, a RX Low Noise Amplifier, a RX Digital Step Attenuator, Receive-in and Digital data from ADC. The Receive-in that refers to the ports, RX Port-1, RX Port-2, RX Port-3 and RX Port-4. The RX Saw Filter- 1 that is a bandpass filter centered at an IF frequency is responsible for removing out-of-band noise from the signal. The RX Digital Step Attenuator that prevents the subsequent components from getting into saturation and also aids to attenuate the signal strength, if required, and the RX Low Noise Amplifier provides amplification to bandpass signal. The RX Saw Filter-2 that facilitates removal of the out-of-band noise in spectrum of its received input. The IQ Demodulator that converts filtered and conditioned IF signal to baseband at OHz and provides In-phase (I) and Quadrature-phase (Q) signals. The Amplifier that magnifies and shifts DC level of the baseband signal to levels appropriate for further signal processing. The Analog to Digital converter converts the analog baseband signal to a proportional, multi-bit parallel digital value. The ADC CLK Generator that generates clock required for the Analog to Digital Converter from the Clock Distribution, and the IQ DEMOD LO Generator generates the clock required for the IQ Demodulator. The Digital data from ADC that is a digital form of data which is an output of the Analog to Digital Converter and the digital value corresponds to an analog voltage value which is an input of the Analog to Digital Converter.

In the modular apparatus for simultaneous MEVIO communication, a top side view of the fully assembled un-enclosed system comprises an Ethernet Data Port, an Ethernet Control Port, a Carrier Card, a System Processor, a Clock Distribution, a Multilevel Equalizer Aided Channel Combining and Demodulator, an OCXO and PCB Assemblies, RX Chain PCBA-Front-end-1, RX Chain PCBA-Front-end-2, RX Chain PCBA-Front-end-3, RX Chain PCBA-Front-end-4 and a TX Chain PCBA-Front-end. The Ethernet Data Port is a port from which transmit data is obtained and to which received data is sent. The Ethernet Control Port enables to configure and control the characteristics of modem sub-system running in the Baseband Processor. The System Processor consists of the Application Processor and Baseband Process or realized in a single Field Programmable Gate Array (FPGA). The Multilevel Equalizer Aided Channel Combining and Demodulator is a unique equalizer realized as one or more Application Specific Integrated Circuits (ASIC) or Field Programmable Gate Arrays (FPGA's) or a combination of both and acts on digital data received at output of the front-end blocks. The OCXO provides an ultra-low jitter 10MHz clock and is powered independently to eliminate any clock leakage on power supply lines and the system can also be clocked from a 10MHz external clock source instead of the internal OCXO. The Clock Distribution refers to a circuit that performs distribution of clock from the OCXO or an external clock throughout the system. The Carrier Card is a PCB Assembly that holds all other discrete circuits onto itself. The TX Chain PCBA- Front-end is a PCB Assembly that forms analog signal conditioning section and consists of multiple components including a Digital to Analog Converter. The RX Chain PCBA-Front-end-1, RX Chain PCBA-Front-end-2,RX Chain PCBA-Front- end-3,RX Chain PCBA-Front-end-4are PCB assemblies that provide signal conditioning to IF received from receiving ports and also include an Analog to Digital Converter resulting in digital output analogous to the input of the Analog to Digital Converter.

In the modular apparatus for simultaneous MIMO communication, a bottom side view of a fully assembled unenclosed system comprises a Digital data to DAC via one or more interface connectors, a Digital to Analog Converter, DAC DATACLK Generator, a TX Low Pass Filter, an IQ MOD LO Generator, an IQ- Modulator, a TX Saw Filter- 1, TX Saw Filter-2, a TX Digital Step Attenuator, a TX Low Noise Amplifier, a Splitter, transmit ports, TX Port-Ι,ΤΧ Port-2, a TX Chain PCBA-Front-end, receive ports, RX PORT-1, RX PORT-2, RX PORT-3, RX PORT-4, receive Saw Filters, CH-1 RX Saw Filter- 1, CH-2 RX Saw Filter- 1, CH-3 RX Saw Filter- 1, CH-4 RX Saw Filter- 1, Digital Step Attenuators, CH-1 Digital Step Attenuator, CH-2 Digital Step Attenuator, CH-3 Digital Step Attenuator, CH-4 Digital Step Attenuator, Low Noise Amplifiers, CH-1 Low Noise Amplifier, CH-2 Low Noise Amplifier, CH-3 Low Noise Amplifier, CH-4 Low Noise Amplifier, receive Saw Filters, CH-1 RX Saw Filter-2, CH-2 RX Saw Filter-2, CH-3 RX Saw Filter-2, CH-4 RX Saw Filter-2, IQ Demodulators, CH-1 IQ Demodulator, CH-2 IQ Demodulator, CH-3 IQ Demodulator, CH-4 IQ Demodulator, IQ DEMOD Clock generators, CH-1 IQ DEMOD CLKGEN, CH -2 IQ DEMOD CLKGEN, CH-3 IQ DEMOD CLKGEN, CH-4 IQ DEMOD CLKGEN, Amplifiers, CH-1 Amplifier, CH-2 Amplifier, CH-3 Amplifier, CH-4 Amplifier, Analog to Digital Converters, a Clock Distribution, ADC Clock generators, CH-1 ADC CLKGEN, CH-2 ADC CLKGEN, CH-3 ADC CLKGEN, CH-4 ADC CLKGEN, a Digital Data from CH-1 ADC to Connector, a Digital Data from CH-2 ADC to Connector, a Digital Data from CH-3 ADC to Connector, a Digital Data from CH-4 ADC to Connector, RX Chain PCBA-Front- end, a Multilevel Equalizer Aided Channel Combining and Demodulator and a Carrier Card. The TX Chain PCBA-Front-end is a PCB assembly that forms transmit analog signal conditioning section of the system and consists of multiple components including the Digital to Analog Converter. The Digital data to DAC via one or more interface connectors is an entry point for the TX Chain PCB assembly, data from the Transmit side of the Baseband Processor will enter the TX Chain PCB assembly via Inter-board connectors. PCB trace length of the Digital to Analog Converter data clock is reduced, by placing the DAC DATACLK Generator adjacent to the Digital to Analog Converter, which is contiguous to the TX Low Pass Filter or minimizing the PCB trace length of the analog signal trace. The IQ MOD LO Generator is placed adjacent to the IQ- Modulator to lessen the PCB trace length, and this component derives its clock from the DAC DATACLK Generator, hence placed adjacent to it. The TX Low Pass Filter is placed after the Digital to Analog converter, the IQ-Modulator after the TX Low Pass Filter and the TX Saw Filter- 1 after the IQ-Modulator, the TX Digital Step Attenuator after the TX Saw Filter- 1, the TX Low Noise Amplifier after the TX Digital Step Attenuator, the TX Saw Filter-2 after the TX Low Noise Amplifier and the Splitter after the TX Saw Filter-2. The TX Port-2 is positioned after the Splitter, the TX Port-1 is also positioned after the Splitter and adjacent to the TX Port-2 whereas the RX PORT-1, RX PORT-2, RX PORT-3, and RX PORT-4 are placed at an edge of the respective Receive Front end PCBA. The CH-1 RX Saw Filter- 1, CH-2 RX Saw Filter- 1, CH-3 RX Saw Filter- 1, CH-4 RX Saw Filter- 1 removes out of the band noise in signal and are placed just after the respective RX Ports. The CH-1 Digital Step Attenuator, CH-2 Digital Step Attenuator, CH-3 Digital Step Attenuator, CH-4 Digital Step Attenuator prevent subsequent LNA from getting into saturation and also aids to attenuate signal strength if required, these are placed after respective RX Saw Filters, CH-1 RX Saw filter- 1, CH-2 RX Saw filter- 1, CH-3 RX Saw filter- 1, CH-4 RX Saw filter- 1. The CH-1 Low Noise Amplifier, CH-2 Low Noise Amplifier, CH-3 Low Noise Amplifier, and CH-4 Low Noise Amplifier are intended to provide amplification to bandpass signal and are positioned after respective Digital Step Attenuators. The CH-1 RX Saw Filter-2, CH-2 RX Saw Filter-2, CH-3 RX Saw Filter-2, CH-4 RX Saw Filter-2 are responsible for removing out-of-band noise in a spectrum of signal that is introduced after Low Noise Amplifier and is located after the Low Noise Amplifiers. The CH-1 IQ Demodulator, CH-2 IQ Demodulator, CH-3 IQ Demodulator, CH-4 IQ Demodulator convert Intermediate Frequency (IF) bandpass signal to a baseband signal and are placed after the respective RX Saw Filters. These also have respective IQ DEMOD CLKGEN adjacent to them in order to decrease the PCB trace length of Clock Signal input to these components., The CH-1 IQ DEMOD CLKGEN, CH -2 IQ DEMOD CLKGEN, CH-3 IQ DEMOD CLKGEN, CH -4 IQ DEMOD CLKGEN generate IQ demodulator clock from the respective ADC CLKGEN and are adjacent to respective IQ Demodulators on one side to reduce PCB trace length of the IQ Demodulator Clock signal and ADC CLKGEN to lessen reference clock signal trace length. The CH-1 Analog to Digital Converter, CH-2 Analog to Digital Converter, CH-3 Analog to Digital Converter, CH-4 Analog to Digital Converter convert the analog signal from respective Amplifiers to proportional digital values and are situated after the respective amplifiers and are also placed adjacent to the respective ADC CLKGEN to minimize the PCB trace length of ADC Clock Signal. The CH-1 ADC CLKGEN, CH-2 ADC CLKGEN, CH-3 ADC CLKGEN, CH-4 ADC CLKGEN provide clock signal to respective ADCs using input from the Clock Distribution and are placed immediately adjacent to the Analog to Digital Converter for reduced ADC Clock signal trace length, also positioned very adjacent to respective IQ DEMOD CLKGEN to lessen reference clock signal lengths. The Digital Data from CH-1 ADC to Connector, Digital Data from CH-2 ADC to Connector, Digital Data from CH-3 ADC to Connector, Digital Data from CH-4 ADC to Connector are the exit points of each of the respective RX Chain PCBA-Front-end. The Digital data from ADC are forwarded to Inter-Board Connectors and are taken to the Multilevel Equalizer Aided Channel Combining and Demodulator for further processing of data. The RX Chain PCBA-Front-end comprises a connector that carries the buffered digital ADC samples from the respective RX Chain PCBA-Front-end to the Carrier Card. The TX Chain PCBA- Front-end holds transmit side components of the apparatus, the RX Chain PCBA- Front-end- 1, RX Chain PCBA-Front-end-2, RX Chain PCBA-Front-end-3, RX Chain PCBA-Front-end-4hold receive side components of the Communication modem and are mounted on bottom side of the Carrier Card, connected electrically via inter-board connectors and mechanically using spacers.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 represents the overall block diagram for a modem system equipped with an encode transmission and decode unit. Figure 1 (a) shows the internal view of the Communication Modem.

Figure 2 (a) and 2 (b) shows the important components of the PCB assembly of the transmit side and receive side of the Communication Modem.

Figure 3 shows the Baseband processor and Application Processor in a chip with its embedded blocks. Figure 4 (a) shows the isometric view of the wholly enclosed system.

Figure 4 (b) shows the communication modem front panel connections of the MIMO system. Figure 5 shows the top view of the fully assembled unenclosed system. Figure 6 shows the bottom view of the fully assembled unenclosed system.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Figure 1 represents the overall block diagram of the present invention equipped with an encode transmission and decode unit. The system consists of a PC 500, a System Ethernet interface 501, a Receive block R, a Transmit block T, an Oven- Controlled Crystal Oscillator (OCXO) 522 and a Clock Distribution 524. The PC 500 is connected via the System Ethernet interface 501 to the Receive block R and the Transmit block T. The Transmit block T consists of a Scrambler 535, an FEC Encoder 534, a Modulator 533, a DAC driver 531, a Digital to Analog Converter (DAC) 528, a DAC DATACLK Generator 529, a Low Pass Filter 527, an IQ-Modulator 526, an IQ-Modulator LO Generator523, an IF Front-end 525, a Splitter 519 and Transmit signals 517, 518. The Receive block R consists of Receive Channel- 1 516a, Receive Channel-2 516b, Receive Channel-3 516c and Receive Channel-4 516d, Intermediate Frequency (IF)Front-end- 1 515a, Intermediate Frequency (IF) Front-end-2 515b, Intermediate Frequency (IF) Front-end-3 515c and Intermediate Frequency (IF) Front-end-4 515d, IQ Demodulators 514a, 514b, 514c, 514d, Signal Conditioning 513a, 513b, 513c, 513d, Analog to Digital Converters (ADC) 512a, 512b, 512c, 512d, a Multilevel Equalizer Aided Channel Combining and Demodulator 511, a Forward Error Correction (FEC) Decoder 508, a Descrambler 507, a 4x IQ DEMOD LO Generator 520 and a 4xADC CLK Generator 521.

The PC 500 is any computing device which is capable of transmitting and receiving Ethernet data. The System Ethernet Interface 501 refers collectively to an Ethernet data processing system that includes an Ethernet Data Port 501a, an Ethernet Control Port 501b, an ETH2TXIPB application 63, a Baseband Logic 66, a Transmit Inter-Processor Bus 55, an IPB2MODEM Writer 56, a DPDCM 57, a HDLC encoder58, a HDLC decoder70, a XCLK domain 69, a MODEM2IPB writer 68, a Receive Side Inter-Processor Bus 67, a RXIPB2ETH application 64, a Baseband Processor 32 and an Application Processor 40 as in Figure 3. Input Bits 501x are transformed to analog stream and transmitted over the Intermediate Frequency (IF) interface. The Bit Output 507x is the output of the Descrambler 507 and is the output of the Receive Portion R of the system. The Descrambler 507 is responsible for descrambling of data that is muddled by the scrambler during the transmission. The Scrambled Bit Output 508x corresponds to the input of the Descrambler 507. The FEC Decoder 508 on the receive side is responsible for decoding of data that is encoded by the FEC Encoder 534 on the transmit side. If the FEC Encoder 534 is disabled on the transmit side then the FEC Decoder 508 will be bypassed. Bit Error Rate (BER) 509 corresponds to the number of bit inaccuracies that are observed over a predefined data length. The Encoded and Scrambled Bit output 510 are the bits before being sent to the FEC Decoder 508. The Multilevel Equalizer Aided Channel Combining and Demodulator 511 acquire the data from the multiple Analog to Digital Converters (ADC) 512a.. d, then performs Co-Phasing, subsequently diversity combining, equalizes and demodulates the signal to obtain the data. The Analog to Digital Converters (ADC) 512a.. d converts the analog baseband signal to a proportional, multi-bit parallel digital value. The Signal Conditioning 513a..d prepares the analog signal to be suitable for the Analog to Digital Converters (ADC) 512a.. d. The IQ Demodulators 514a.. d converts the Intermediate Frequency (IF) signal to a baseband signal. The Intermediate Frequency (IF) Front-end 515a..d comprises of Analog Filter networks, Attenuators and Low Noise Amplifiers for each receive channel. Multiple Receive Channel 516a.. d corresponds to the input signal given to the system through the connectors of the enclosure. The Scrambler 535 is used to enable accurate timing recovery on the receiver without resorting to redundant line coding and to disperse the energy on the carrier. It disperses the data to meet the maximum power spectral density requirements. Scrambled Input Bits 535x are those transmitted after the scrambling and interleaving process. The FEC Encoder 534is a suitable standard forward error correction encoder used to encode the data. Encoded and Scrambled Input Bits 534x are the bits after Scrambling and FEC encoding processes. The Burst Modulator 533 converts the data bits to In-phase (I) and Quadrature-Phase (Q) data with appropriate gain and further converts the stream of I and Q data to the user selected data rate without losing any received input data. The DAC Driver 531 runs on a user selected Clock Frequency, which is the operating frequency of the Digital to Analog Converter 528 and converts the data into a format suited for the same. The Digital to Analog Converter 528 accepts a 14-bit parallel digital data from the DAC Driver 531and produces an analog voltage proportional to the digital value. The Digital to Analog Converter 528 has dual channels, one for In-Phase (I) data and the other for Quadrature-phase (Q) data. The Low Pass Filter 527 eliminates the harmonics that are outside of the passband from the output of the Digital to Analog Converter 528 to conserve the bandwidth. The IQ-Modulator 526 combines the In-phase (I) and the Quadrature -phase (Q) outputs of the Low Pass Filter 527 and upconverts to Intermediate Frequency. The IF Front-end 525 comprises a SAW Filter network, Attenuators and Low Noise Amplifiers of the Transmit side. The Splitter 519 sends two copies of the signal to two different transmit ports. The Transmit Out-1 517 is the signals given to one transmit port and thereon to the associated transmit connector, whereas the Transmit Out-2 518 is the signal given to another transmit port and then to the associated transmit connector.

The Clock Distribution 524 refers to a circuit that performs the distribution of the Clock from the OCXO 522 or an external Clock, throughout the system. The 4x IQ DEMOD LO Generator 520 generates the clock required for the respective IQ Demodulator 514a.. d and 4 x ADC Clock Generator 521 generates the clock necessary for the respective Analog to Digital Converter 512a..d. The IQ- Modulator 526 is clocked by the IQ-Modulator LO Generator 523, which in turn receives its input clock from the DAC Data Clock Generator 529. The OCXO 522 provides an ultra-low jitter 10MHz clock that is powered independently in order to eliminate any clock leakage on the power supply lines. The system can also be clocked from a 10MHz external clock source instead of the internal OCXO. The DAC Data Clock Generator 529 generates the clock required for the Digital to Analog Converter 528 from the Clock Distribution 524.

Figure la shows the Communication Modem internal components that includes an Ethernet Data Port 501a, an Ethernet Control Port 501b, an Application Processor 40, a Baseband Processor 32, a transmit PCBA assembly TX Chain PCBA-Front-end 525a, transmit ports, TX Port-1 39a, TX Port-239b, a RX Chain PCBA-Front-end-1 515h, a RX Chain PCBA-Front-end-2 515g, a RX Chain PCBA-Front-end-3 515f, a RX Chain PCBA-Front-end-4 515e, receive ports RX PORT-1 38d, RX PORT-2 38c, RX PORT-3 38b, RX PORT-4 38a, a Multilevel Equalizer Aided Channel Combining and Demodulator 511, an OCXO 522 and a Clock Distribution 524.

The Ethernet Data Port 501a obtains the transmit data and sends out the received data. The Ethernet Control Port 501b provides an interface to configure and control the characteristics of the logic running in the Baseband Processor 32 and the Application Processor 40. The Application Processor 40 and the Baseband Processor 32 are realized as one or more Application Specific Integrated Circuits or Field Programmable Gate Arrays (FPGA's) or a combination of both. The Application Processor 40 facilitates the exchange of data between the Ethernet Data Port 501a and the Baseband Processor 32. The Baseband Processor 32 performs the function of modulating the data received from the Application Processor 40 and also decodes the data received from the Multilevel Equalizer Aided Channel Combining and Demodulator 511. The TX Chain PCBA-Front- end 525a consists of multiple components including a Digital to Analog Converter 528a and, forms a transmit analog signal conditioning part of the system. The transmit ports 39a, 39b receive the transmit Intermediate Frequency (IF) signal and the receive ports 38a.. d obtains the IF signal at the Receive. The number of ports is for representation purpose only and can be any even number of ports as determined at the time of installation. The Receive PCB assemblies 515e..h provide signal conditioning to the IF received from the receive ports. Each front-end assembly includes an Analog to Digital converter resulting in digital output analogous to the input.

The Multilevel Equalizer Aided Channel Combining and Demodulator 511 is responsible for acquiring data from the four ADC channels, does Co-Phasing, subsequently diversity combining, equalizes and demodulates the signal to obtain the data. The Baseband Processor 32 does Forward Error Correction, Descrambling and De-Framing. The Multilevel Equalizer Aided Channel Combining and Demodulator 511 and the Baseband Processor 32 are realized as one or more Application Specific Integrated Circuits (ASIC) or Field Programmable Gate Arrays (FPGA's) or a combination of both. The OCXO 522 provides an ultra-low jitter 10MHz clock that is powered independently in order to eliminate any clock leakage on the power supply lines. The system can also be clocked from a 10MHz external clock source instead of internal OCXO. The Clock Distribution 524 refers to the circuit that performs the distribution of the clock from OCXO 522or an external clock, throughout the system. The input clock to TX Chain PCBA Front-end 525a is the clock to TX Chain 42 and that for RX Chain PCBA Front-end 515e..515h is the Clock to RX Chain 42b, both are the output from the Clock Distribution 524. The Digital data to DAC 41 is the digital form of the data fed to the Digital to Analog Converter 528a and the digital data from ADC 43 is again a digital form of data output from the Analog to Digital Converter 512. The digital value corresponds to an analog voltage value which is the output of the Digital to Analog Converter 528. The Digital Data from ADC 43 refers to the digital form of the data that is the output of the Analog to Digital Converter 512. This digital value relates to an analog voltage value which is the input of the Analog to Digital Converter512.

Figure 2(a) and 2 (b) shows the important components of the PCB assembly of the transmit side and receive side of the Communication Modem. A Digital to Analog Converter (DAC) 528a produces an analog waveform proportional to the digital value of the transmit data. The DAC 528a accepts a multi-bit parallel digital data and produces an analog voltage proportional to the digital value. The DAC 528a has a dual channel, one for In-Phase (I) data and other for Quadrature- phase (Q) Data. The TX Low Pass Filter 527removes the harmonics that are outside of the pass band from the output of the Digital to Analog Converter 528a to conserve the bandwidth. The IQ-Modulator 526 combines the In-phase (I) and Quadrature-phase (Q) outputs of the TX Low Pass Filter 527 and upconverts to Intermediate Frequency (IF). The TX Saw Filter- 146a removes the out-of-band noise in the spectrum of the Transmit signal. A TX Digital Step Attenuator 47 prevents the subsequent components from getting into saturation and also aids to attenuate the signal strength if required. The TX Low Noise Amplifier 48 is intended to provide amplification to the band pass signal. The TX Saw Filter-2 46b is responsible for removing the out-of-band noise in the spectrum of the Transmit signal that is introduced after the TX Low Noise Amplifier 48. The Splitter 519 sends two copies of the same signal to two transmit ports. The TX Port-1 39a and TX Port-2 39b, are the transmit ports to which transmit Intermediate Frequency (IF) signal is given. The IQ MOD LO Generator 520a generates the clock required for the IQ-Modulator 526 from DAC DATACLK Generator 529a. The DAC DATACLK Generator 529a generates the clock needed to the Digital to Analog Converter 528a from the Clock Distribution 524. The Receive-in 516 refers to the ports, RX Port-138d, RX Port-238c, RX Port-3 38b and RX Port-4 38a. The RX Saw Filter- 1 52b is a band pass filter centred at the IF frequency and is responsible for removing the out-of-band noise in the signal. The RX Digital Step Attenuator 54 prevents the subsequent components from getting into saturation and also aids to attenuate the signal strength. The RX Low Noise Amplifier 53 is intended to provide amplification to the band pass signal. The RX Saw Filter-2 52a facilitates removal of the out-of-band noise in the spectrum of its received input. The IQ Demodulator 514 converts the filtered and conditioned IF signal to baseband at OHz and provides the In-phase (I) and Quadrature-phase (Q) signals. The Amplifier 51magnifies and shifts the DC level of the baseband signal to the levels appropriate for further signal processing. The Analog to Digital converter 512 converts the analog baseband signal to a proportional, multi-bit parallel digital value. The ADC CLK Generator 521a generates the clock required for the Analog to Digital Converter512 from the Clock Distribution 524.

The IQ DEMOD LO Generator 50 generates the clock required for the IQ Demodulator 514 from the4xADC CLK Generator 521. The Digital data from ADC 43 is the digital form of the data which is the output of the Analog to Digital Converter 512. This digital value corresponds to an analog voltage value that is the input of the Analog to Digital Converter 512. The Digital data to DAC 41via one or more interface connectors refers to the digital form of the data that is given to the Digital to Analog Converter 528a. This digital value corresponds to an analog voltage value that is the output of the Digital to Analog converter 528a.

Figure 3 shows the Baseband processor and Application Processor in a chip with its embedded blocks. The transmit data is obtained, and the received data is sent through the Ethernet Data Port 501a. An ETH2TXIPB Application 63 is responsible for manipulating the user data such as providing compression and encryption of data received from the PC 500 via the Ethernet Data Port 501a.Baseband Logic 66 encapsulates all the processing involved in converting the Multilevel Equalizer Aided Channel Combining and Demodulator 511 output to bits and converting the bits suitable for input to Digital to Analog Converter (DAC) 528a. The Transmit Inter-Processor Bus 55 which is of any Standard Inter- Processor Communication Bus forwards the data obtained from the Application Processor 40to the Baseband Processor 32. The IPB2MODEM Writer 56 is responsible for generating the flow control signal so as to match the data transmission speed of the Application Processor 40, the IPB2MODEMalso acts as a buffer to match the speeds of the Application Processor 40 to the Baseband Processor 32. The DPDCM 57 converts the stream of In-phase (I) and Quadrature-Phase (Q) data to the user selected data rate. For example, the input side is at 100MHz, and the output is at 80MHz. Since the input is faster than the output, there is a flow control signal that runs all the way from this point to ETH2TXIPB Application63 that prohibits the input data flow, if any of the logical blocks is still processing the previously received data, and is not ready to process a newer input. The HDLC Encoder 58 is a standard High-Level Data Link Control (HDLC) and is a bit oriented code transparent synchronous data link layer protocol that converts the 8-Bit parallel data to 1-Bit serial data. Also, adds the header, footer and standard Cyclic Redundancy Check (CRC) and manipulates the data in order to eliminate the header occurrence in the data stream. The Scrambler 535 is used to enable accurate timing recovery on the receiver without resorting to redundant line coding and to disperse the energy on the carrier. It disperses the data to meet the maximum power spectral density requirements.

The FEC Encoder 534 is a suitable standard forward error correction encoder used to encode the data. The Modulator 59 converts the data bits to In-phase (I) and Quadrature-Phase (Q) data with appropriate gain. The DPDCM Lossless 60converts the stream of In-phase (I) and Quadrature Phase (Q) data to the user selected data rate without skipping any input data received. The DAC Driver 531a runs on a selected clock frequency, which is the operating frequency of the Digital to Analog Converter 528a and converts the data into a format suited for the same. The FEC Decoder 508 on receive signal processing side is responsible for decoding of the data that is encoded by the FEC Encoder 534 on the transmit side. If the FEC Encoder 534 is disabled on the transmit side, the FEC Decoder 508 will be bypassed. The Descrambler 507 is responsible for descrambling of the data that is scrambled by the Scrambler 535 while transmission. The HDLC Decoder 70 undoes the action done by the HDLC Encoder 58 and converts the bit data into bytes. CRC is used to validate the byte data and subsequently removed. The XCLK Domain 69 converts the data on a User Clock into a suitable clock used for further processing. An example is when the input side operates at 80MHz and output side operates at 100MHz. Since the input is slower than the output, no flow control is required. An MODEM2IPB writer 68 translates the flow control signals from the Baseband Processor 32 and the Application Processor 40. The MODEM2IPB writer 68 also acts as the buffer to synchronize the Baseband Processor 32 and Application Processor 40. The Receive Side Inter-Processor bus 67 is responsible for handing over the data obtained from the Receive block R of the system to an RXIPB2ETH Application 64. The RXIPB2ETH Application 64 aids in manipulating the user data such as providing decompression and decryption of the received data packets. The Baseband Processor 32 modulates the data received from the Application processor 40 and also decodes the data received from the Multilevel Equalizer Aided Channel Combining and Demodulator 511. The Baseband Processor 32 and the Application Processor 40 is realized as one or more Application Specific Integrated Circuits (ASIC) or Field Programmable Gate Arrays (FPGA's) or a combination of both. The Digital data to DAC 41 is the entry point for the TX CHAIN PCB assembly. The data from Transmit of the Baseband Processor 32 will enter the TX CHAIN PCB Assembly via the Inter-board Connectors.

Figure 4(a) is the wholly enclosed system in isometric view showing the front panel. The front panel consists of exit points and entry points. The points are placed adjacent to each other. Figure 4(b) is the Communication Modem front panel connections of the MIMO system with an Ethernet Data Connector 501c and an Ethernet Control Connector 501d. The Ethernet Data Connector 501c is in the area of the apparatus that is connected by a cable to the Ethernet Data Port 501a. The Ethernet Control Connector 501d provides an interface to configure the Baseband Processor 32 and the Application Processor 40, and is situated in the enclosure of the apparatus connected by a cable to the Ethernet Control Port 501b. The RX Connector- 1 38e, RX Connector-2 38f, RX Connector-3 38g, RX Connector-4 38h are on the field space of the apparatus that are connected by a cable to the receive ports, RX Port-1 38d, RX Port-238c, RX Port-338b, RX Port- 438a. The TX Connector- 1 39c and TX Connector- 239don the area of the apparatus are connected to TX Port-1 39a and TX Port-2 39b by a cable.

Figure 5 shows the top side view of the fully assembled unenclosed system. The Ethernet Data Port 501a is the port from which the transmit data is obtained and to which the received data is sent. The Ethernet Control Port 501b enables to configure and control the characteristics of the modem sub-system running in the Baseband Processor 32 and the Application Processor 40. The System Processor 466 consists of the Application Processor 40 and Baseband Processor 32 realized in a single Field Programmable Gate Array(FPGA).The TX Chain PCBA-Front- end 525a is a PCB Assembly that forms the analog signal conditioning section of the system and consists of multiple components including a Digital to Analog Converter 528a.The RX Chain PCBA-Front-end-1515h,RX Chain PCBA-Front- end-2 515g, RX Chain PCBA-Front-end-3 515f, RX Chain PCBA-Front-end-4 515e are the PCB assemblies that provide signal conditioning to the IF received from the receiving ports. These front-end assemblies also include an Analog to Digital Converter 512 resulting in digital output analogous to the input. The Multilevel Equalizer Aided Channel Combining and Demodulator 511 is a unique equalizer realized as one or more Application Specific Integrated Circuits (ASIC) or Field Programmable Gate Arrays (FPGA's) or a combination of both. The Multilevel Equalizer Aided Channel Combining and Demodulator 511 acts on the digital data received at the output of the front-end blocks.

The OCXO 522 provides an ultra-low jitter 10MHz clock and is powered independently to eliminate any clock leakage on the power supply lines. The system can also be clocked from a 10MHz external clock source instead of the internal OCXO. The Clock Distribution 524 refers to the circuit that performs the distribution of the clock from the OCXO 522 or an external clock throughout the system. The Carrier Card 465 is the PCB Assembly that holds all the other discrete circuits onto itself.

Figure 6 is the bottom side view of the fully assembled unenclosed system. The Digital data to DAC 41 via one or more interface connectors is the entry point for the TX Chain PCB assembly. Data from the Transmit side of the Baseband Processor 32 will enter the TX Chain PCB assembly via the Inter-board connectors. In order to reduce the PCB trace length of the Digital to Analog Converter 528a data clock, the DAC DATACLK Generator 529a is placed adjacent to the Digital to Analog Converter 528a, which is contiguous to the TX Low Pass Filter 527 for minimizing the PCB trace length of the analog signal trace. The IQ MOD LO Generator 520a is placed adjacent to the IQ-Modulator 526 to lessen the PCB trace length. This component derives its clock from the DAC DATACLK Generator 529a and hence placed adjacent to it. The TX Low Pass Filter 527 is placed after the Digital to Analog converter 528a, the IQ- Modulator 526 after the TX Low Pass Filter 527 and the TX Saw Filter- 146a after the IQ-Modulator 526,the TX Digital Step Attenuator 47 after the TX Saw Filter- 1 46a, the TX Low Noise Amplifier 48 after the TX Digital Step Attenuator47, the TX Saw Filter-246b after the TX Low Noise Amplifier 48 andthe splitter 519 after the TX Saw Filter-2 46b. Further, the TX Port-2 39b is positioned after the Splitter 519, the TX Port-139ais also positioned after the Splitter 519 and adjacent to the TX Port-2 39b. The TX Chain PCBA-Front-end 525ais a PCB assembly that forms transmit analog signal conditioning section of the system and consists of multiple components including the Digital to Analog Converter 528a.TheRX PORT-1 38d, RX PORT-2 38c, RX PORT-3 38b, RX PORT-4 38a are placed at the edge of the Receive Front PCBA.

The CH-1 RX Saw Filter- 1 413, CH-2 RX Saw Filter- 1 424, CH-3 RX Saw Filter- 1 433, CH-4 RX Saw Filter- 1 442removes the out of the band noise in the signal and are placed just after the respective RX Ports 38d, 38c, 38b, 38a respectively. TheCH-1 Digital Step Attenuator 414, CH-2 Digital Step Attenuator 425, CH-3 Digital Step Attenuator 434, CH-4 Digital Step Attenuator 443 prevent the subsequent LNA from getting into the saturation and also aids to attenuate the signal strength if required. These are placed after the respective RX SAW Filters. The CH-1 Low Noise Amplifier 415, CH-2 Low Noise Amplifier 426, CH-3 Low Noise Amplifier 435, CH-4 Low Noise Amplifier 444 are intended to provide amplification to the band pass signal and are positioned after the respective Digital Step Attenuators 414, 425, 434, 443.

TheCH-1 RX Saw Filter-2416, CH-2 RX Saw Filter-2 427,CH-3 RX Saw Filter-2 436,CH-4 RX Saw Filter-2 445 are responsible for removing the out-of-band noise in the spectrum of the signal that is introduced after the Low Noise Amplifier and are located after the Low Noise Amplifiers 415,426,435,444. The CH-1 IQ Demodulator 514a,CH-2 IQ Demodulator 514b, CH-3 IQ Demodulator514c, CH-4 IQ Demodulator 514d convert the Intermediate Frequency band pass Signal to a baseband signal. These are placed after the respective RX Saw Filter-2. They also have respective IQ DEMOD CLKGEN 419,429,438,447 adjacent to them in order to decrease the PCB trace length of the Clock Signal input to these components. The CH-1 Amplifier 418, CH-2 Amplifier 451, CH-3 Amplifier 452, CH-4 Amplifier 453 amplify and perform DC level shift of the analog signal to the levels appropriate to the respective Analog to Digital Converters 512a,512b,512c,512d. These are positioned after the respective IQ Demodulators. TheCH-1 IQ DEMOD CLKGEN 419, CH-2 IQ DEMOD CLKGEN 429, CH-3 IQ DEMOD CLKGEN 438, and CH-4 IQ DEMOD CLKGEN 447 generate the IQ demodulator clock from ADC CLKGEN 421,430,439,448. They are adjacent to the respective IQ Demodulators on one side to reduce the PCB trace length of the IQ Demodulator Clock signal and ADC CLKGEN to lessen the reference clock signal trace length. The CH-1 Analog to Digital Converter512a, CH-2 Analog to Digital Converter512b, CH-3 Analog to Digital Converter512c, CH-4 Analog to Digital Converter512d convert the analog signal from the respective Amplifiers 418,451,452,453 to proportional digital values and are situated after the respective Amplifiers. They are also placed adjacent to the respective ADC CLKGEN 421,430,439,448to minimize the PCB trace length of the ADC Clock Signal. The CH-1 ADC CLKGEN421, CH-2 ADC CLKGEN430, CH-3 ADC CLKGEN 439, CH-4 ADC CLKGEN448provide the clock signal to the respective ADCs 512a,512b,512c,512d using the input from the Clock Distribution 524. They are placed immediate adjacent to the Analog to Digital Converter for reduced ADC Clock signal trace length. They are also positioned very adjacent to the respective IQ DEMOD CLKGEN 419,429,438,447 to lessen the reference clock signal lengths. The Digital Data from CH-1 ADC to Connector 422, Digital Data from CH-2 ADC to Connector431, Digital Data from CH-3 ADC to Connector 440, Digital Data from CH-4 ADC to Connector 449 are the exit points of each of the respective RX Chain PCBA-Front-end 515h, 515g, 515f, 515e. The Digital data from ADC 43 are forwarded to the Inter-Board Connectors and are taken to the Multilevel Equalizer Aided Channel Combining and Demodulator 511 for further processing of the data. The RX Chain PCBA-Front-end comprises a connector that carries the buffered digital ADC samples from the respective RX Chain PCBA-Front-end 515h, 515g, 515f, 515e to the Carrier Card 465.

The TX Chain PCBA-Front-end 525a holds the transmit side components of the device. The RX Chain PCBA-Front-end- 1515h, RX Chain PCBA-Front-end- 2515g, RX Chain PCBA-Front-end- 3 515f,RX Chain PCBA-Front-end-4 515e hold the receive side components of the Communication modem and are mounted on the bottom side of the Carrier Card 465 and are connected electrically via inter- board connectors and mechanically using spacers.

Claims

A modular simultaneous MIMO communication system comprising (a) a PC 500, (b) a System Ethernet interface 501, (c) a Receive block R, (d) a Transmit block T, (e) an Oven-Controlled Crystal Oscillator (OCXO) 522 and (f) a Clock Distribution 524 wherein:

a. The PC 500 is any computing device that can transmit and receive Ethernet data;

b. The PC 500 is connected through the System Ethernet interface

501 to the Receive block R and the Transmit block T; c. The Clock Distribution 524 refers to a circuit that performs distribution of Clock from the OCXO 522 or an external Clock throughout the system;

d. The OCXO 522 provides an ultra-low jitter 10MHz clock and is powered independently, to eliminate any clock leakage on power supply lines; and

e. The system can also be clocked from a 10MHz external clock source instead of an internal OCXO.

The modular simultaneous MIMO communication system of Claim 1 where the System Ethernet Interface 501 refers collectively to an Ethernet data processing system that includes (a) an Ethernet Data Port 501a, (b) an Ethernet Control Port 501b, (c) an ETH2TXIPB application 63, (d) a Baseband Logic 66, (e) a Transmit Inter-Processor Bus 55, (f) an IPB2MODEM Writer 56, (g) a DPDCM 57, (h) a HDLC encoder 58, (i) a HDLC decoder 70, (j) a XCLK domain 69, (k) a MODEM2IPB writer 68, (1) a Receive Side Inter- Processor Bus 67, (m) a RXIPB2ETH application 64, (n) a Baseband Processor 32 and (o) an Application Processor 40 wherein, Input Bits 501x are transformed to analog stream and transmitted over an Intermediate Frequency (IF) interface. The modular simultaneous MEVIO communication system of Claim 1 where the Transmit block T consists of (a) a Scrambler 535, (b) an FEC Encoder 534, (c)a Burst Modulator 533, (d) a DAC driver 531, (e) a Digital to Analog Converter (DAQ528, (f) a DAC DATACLK Generator 529, (g) a Low Pass Filter 527, (h) an IQ-Modulator 526, (i) an IQ- Modulator LO Generator 523, (j) an IF Front-end 525, (k) a Splitter 519 and (1) Transmit signals 517, 518, wherein:

a. The scrambler 535 is used to enable accurate timing recovery on the receiver without resorting to redundant line coding and to disperse the energy on the carrier, it disperses the data to meet the maximum power spectral density requirements;

b. Scrambled Input Bits 535x are those transmitted after scrambling and interleaving process;

c. The FEC Encoder 534 is a suitable standard forward error correction encoder used to encode the data;

d. Encoded and Scrambled Input Bits 534x are bits after Scrambling and FEC encoding processes;

e. The Burst Modulator 533 converts the data bits to In-phase (I) and Quadrature-Phase (Q) data with appropriate gain and further converts the stream of I and Q data to a user selected data rate without any drop in received input data;

f. The DAC Driver 531 runs on a user selected Clock Frequency, which is an operating frequency of the Digital to Analog Converter 528 and converts the data into a format suited for the same;

g. The Digital to Analog Converter 528,accepts a multi-bit parallel digital data from the DAC Driver531and produces an analog voltage proportional to the digital value; h. The Digital to Analog Converter 528 has dual channels, one for In- Phase (I) data and the other for Quadrature-phase(Q) data; i. The Low Pass Filter 527 eliminates harmonics that are outside of passband from an output of the Digital to Analog Converter 528 to conserve bandwidth;

j. The IQ-Modulator 526 combines the In -phase (I) and the Quadrature-phase (Q) outputs of the Low Pass Filter 527 and upconverts to Intermediate Frequency (IF);

k. The IF Front-end 525 comprises an SAW Filter network, Attenuators and Low Noise Amplifiers of the Transmit side;

1. The Splitter 519 sends two copies of the signal to two different transmit ports;

m. The Transmit Out-1 517 is the signal given to one transmit port and thereon to the associated transmit connector, whereas the Transmit Out-2 518 is the signal given to another transmit port and then to the associated transmit connector;

n. The IQ-Modulator 526 is clocked by the IQ- 523, which in turn receives its input clock from the DAC Data Clock Generator 529; and

o. The DAC Data Clock Generator 529 generates the clock required for the Digital to Analog Converter 528 from the Clock Distribution 524.

4. The modular simultaneous MEVIO communication system of Claim 1 where the Receive block R consists of (a) Receive Channel- 1 516a,

Receive Channel-2 516b, Receive Channel-3 516c and Receive Channel-4 516d, (b) Intermediate Frequency (IF) Front-end- 1 515a, Intermediate Frequency (IF) Front-end-2 515b, Intermediate Frequency (IF) Front-end- 3 515c and Intermediate Frequency (IF) Front-end-4 515d, (c) IQ Demodulators 514a, 514b, 514c, 514d, (d)Signal Conditioning 513a,

513b, 513c, 513d, (e) Analog to Digital Converters (ADC) 512a, 512b, 512c, 512d, (f) a Multilevel Equalizer Aided Channel Combining and Demodulator 511, (g) a Forward Error Correction (FEC) Decoder 508, (h)a Descrambler 507, (i) a 4x IQ DEMOD LO Generator 520 and (j) a 4xADC CLK Generator 521, wherein:

a. The Descrambler 507 organizes the data which is muddled by the Scrambler 535 during the transmission;

b. The Scrambled Bit Output 508x corresponds to an input of the Descrambler 507;

c. The FEC Decoder 508 on the receive side is responsible for decoding of the data which is encoded by the FEC Encoder 534 on the transmit side such that, if the FEC Encoder 534 is disabled on the transmit side then the FEC Decoder 508 will be evaded;

d. Bit Error Rate (BER) 509corresponds to number of bit inaccuracies that are observed over a predefined data length;

e. Encoded and Scrambled Bit output 510 are bits before being sent to the FEC Decoder 508;

f. The Multilevel Equalizer Aided Channel Combining and Demodulator 511 acquire the data from the multiple Analog to Digital Converters (ADC) 512a.. d, performs Co-Phasing, subsequently diversity combining, equalizes and demodulates the signal to obtain the data;

g. The Analog to Digital Converters (ADC) 512a.. d converts the analog baseband signal to a proportional multi-bit parallel digital value;

h. The Signal Conditioning 513a..d prepares analog signal to be suitable for the Analog to Digital Converters (ADC) 512a.. d;

i. The IQ Demodulators 514a.. d convert the Intermediate Frequency (IF) signal to a baseband signal;

j. The Intermediate Frequency (IF) Front-end515a..d comprises of Analog Filter networks, Attenuators and Low Noise Amplifiers for each receive channel; k. Multiple Receive Channels 516a.. d corresponds to the input signal given to the system through connectors of the enclosure;

1. The 4x IQ DEMOD LO Generator 520 generates the clock required for the respective IQ Demodulator 514a..d; and m. The4 x ADC Clock Generator 521 generates the clock necessary for the respective Analog to Digital Converter 512a..d and provide the input clock to the4x IQ DEMOD LO Generator 520, the4 x ADC Clock Generator 521 inputs are generated from the Clock Distribution 524.

The modular simultaneous MEVIO communication system of Claim 1, the Baseband processor and Application Processor in a chip with its embedded blocks comprising (a) an Ethernet Data Port 501a, (b) an ETH2TXIPB application 63, (c) a Baseband Logic 66, (d) a Transmit Inter-Processor Bus 55, (e) an IPB2MODEM Writer 56, (f) a DPDCM 57, (g) a HDLC encoder 58, (h) a HDLC decoder 70, (i) a XCLK domain 69, (j) a MODEM2IPB writer 68, (k) a Receive Side Inter-Processor Bus 67, (1) a RXIPB2ETH application 64, (m) a Baseband Processor 32, (n) an Application Processor 40, (o) a Burst Modulator 59, (p) a DPDCM Lossless 60, (q) a DAC Driver 531, (r) a Descrambler 507, (s) an FEC Decoder 508, (t) an FEC Encoder 534, (u) a Scrambler 535, (v)a Digital data to DAC 41via one or more interface connectors, (w) Scrambled Bit output 510 and (x) Bit Error Rate (BER) 509 wherein:

a. The Ethernet Data Port 501a obtains transmit data and sends out received data;

b. The ETH2TXIPB Application 63 is responsible for manipulating the user data such as providing compression and encryption of data received from PC 500 via the Ethernet Data Port 501a; The Baseband Logic 66 encapsulates all the processing involved in converting the Multilevel Equalizer Aided Channel Combining and Demodulator 511 output to bits, this also encapsulates processing involved in converting the bits suitable for input to Digital to Analog Converter (DAC) 528a;

The Transmit Inter-Processor Bus 55 which is of any Standard Inter-Processor Communication Bus forwards the data obtained from the Application Processor 40 to the Baseband Processor 32; The IPB2MODEM Writer 56 is responsible for generating the flow control signal so as to match the data transmission speed of the Application Processor 40, which also acts as a buffer to match the speeds of the Application Processor 40 to the Baseband Processor 32;

The DPDCM 57 converts the stream of In-phase (I) and

Quadrature-Phase (Q) data to the user selected data rate;

The HDLC Encoder58is a standard High-Level Data Link Control

(HDLC) and is a bit oriented code transparent synchronous data link layer protocol that converts the 8-Bit parallel data to 1-Bit serial data, also adds the header, footer and standard Cyclic

Redundancy Check (CRC) and manipulates the data in order to eliminate the header occurrence in the data stream;

The XCLK Domain 69 converts the data on a User Clock into a standard clock which is used for further processing;

The MODEM2IPB writer 68 translates the flow control signal from the Baseband Processor 32 and the Application Processor 40, also acts as the buffer to synchronize the Baseband Processor 32 and Application Processor 40; j. The Receive Side Inter- Processor bus 67 is responsible for handing over the data obtained from the Receive block R of the system to the RXIPB2ETH Application 64 which aids in manipulating the user data such as providing decompression and decryption of the received data packets;

k. The Baseband Processor 32 modulates the data received from the Application processor 40 and also decodes the data received from the Multilevel Equalizer Aided Channel Combining and Demodulator 511;

1. The Application Processor 40 and the Baseband Processor 32 is realized as one or more Application Specific Integrated Circuits (ASIC) or Field Programmable Gate Arrays (FPGA's) or a combination of both;

m. The FEC Encoder 534 is a suitable standard forward error correction encoder used to encode the data;

n. The Burst Modulator 59 converts the data bits to In-phase (I) and

Quadrature-Phase (Q) data with appropriate gain;

o. The DPDCM Lossless 60 converts the stream of In-phase (I) and Quadrature Phase (Q) data to the user selected data rate without skipping any input data received;

p. The DAC Driver 531a runs on a selected clock frequency, which is the operating frequency of the Digital to Analog Converter 528a and converts the data into a format suited for the same;

q. The FEC Decoder 508 on receive signal processing side is responsible for decoding of the data that is encoded by the FEC

Encoder 534 on the transmit side and if the FEC Encoder 534 is disabled on the transmit side, the FEC Decoder 508 will be bypassed; r. The scrambler 535 is used to enable accurate timing recovery on the receiver without resorting to redundant line coding and to disperse the energy on the carrier, it disperses the data to meet the maximum power spectral density requirements;

s. The Descrambler 507 organizes the data which is muddled by the

Scrambler 535 during the transmission;

t. The HDLC Decoder 70 undoes the action done by the HDLC Encoder 58 and converts the bit data into bytes and CRC is used to validate the byte data and subsequently removed;

u. The Digital data to DAC 41 via one or more interface connectors is the entry point for the TX CHAIN PCB assembly; and

v. The data from Transmit of the Baseband Processor 32 will enter the TX CHAIN PCB Assembly via the Inter-board Connectors. A modular apparatus for simultaneous MIMO communication having a Communication Modem whose components include (a) an Ethernet Data Port 501a, (b) an Ethernet Control Port 501b, (c) an Application Processor 40, (d) a Baseband Processor 32, (e)a transmit PCB assembly,(f)a receive PCB assembly,(g) a Multilevel Equalizer Aided Channel Combining and Demodulator 511, (h) an OCX0522 and (i) a Clock Distribution 524, wherein:

a. The transmit PCB assembly, TX Chain PCBA-Front-end 525a includes transmit ports, a Digital to Analog Converter 528a and forms a transmit analog signal conditioning part of the system and, one or more transmit ports TX Port- 139a and TX Port-239b to transmit Intermediate Frequency (IF) signal;

b. The receive PCB assembly having a Front-end comprising, a RX Chain PCBA-Front-end- 1 515h, a RX Chain PCBA-Front-end-2 515g, a RX Chain PCBA-Front-end-3 515f and a RX Chain PCBA-Front-end-4 515e, and one or more receive ports including, RX PORT-1 38d, RX PORT-2 38c, RX PORT-3 38b and RX PORT-4 38a, where the PCBA-Front-end 515e..h provide signal conditioning to the IF received from receive ports;

c. The Ethernet Data Port 501a obtains transmit data and sends out received data while the Ethernet Control Port enables to configure and control the characteristics of the modem sub-system running in the Baseband Processor 32 and the Application Processor 40;

d. The Application Processor 40 facilitates the exchange of data between the Ethernet Data Port 501a and the Baseband Processor 32 and is realized as one or more Application Specific Integrated Circuits or Field Programmable Gate Arrays (FPGA's) or a combination of both; and

e. The Baseband Processor 32 performs the function of modulating the data received from the Application Processor 40 and also decodes the data received from the Multilevel Equalizer Aided Channel Combining and Demodulator 511 and is realized as one or more Application Specific Integrated Circuits or Field Programmable Gate Arrays (FPGA's) or a combination of both.

The modular apparatus for simultaneous MIMO communication of Claim 6, wherein a wholly enclosed system in isometric view has the front panel comprising (a) an Ethernet Data Connector 501c, (b)an Ethernet Control Connector 501d, (c) a RX Connector- 1 38e,(d) a RX Connector-2 38f,(e) a RX Connector-3 38g, (f) a RX Connector-4 38h, (g) a TX Connector- 1 39c, (h) a TX Connector-2 39d and (i) an external Clock Connector 411, comprising:

a. The Ethernet Data Connector 501cis connected by a cable to the Ethernet Data Port 501a;

b. The Ethernet Control Connector 501d provides interface to the configuration of the Baseband Processor 32 and the Application Processor 40, and is situated in an enclosure of the apparatus connected by a cable to the Ethernet Control Port 501b; c. The RX Connector- 1 38e, RX Connector-2 38f, RX Connector-3 38g, RX Connector-4 38h are on a field space of the apparatus that are connected by a cable to the receive ports, RX Port-1 38d, RX Port-2 38c, RX Port-3 38b, RX Port-4 38a;

d. The TX Connector- 1 39c and TX Connector-2 39d are connected to TX Port-1 39a and TX Port-2 39b by a cable; and

e. The external Clock Connector 411 is a connector that carries an external 10 MHz stable reference to the system and can be used instead of the OCXO 522assembled into the system.

The modular apparatus for simultaneous MIMO communication of Claim 6, where the important components in transmit PCB Assembly consists of (a) a Digital to Analog Converter (DAC) 528a,(b) an IQ-Modulator 526, (c) a TX Low Pass Filter 527, (d) a TX Saw Filter- 1 46a, a TX Saw Filter- 2 46b, (e) a TX Digital Step Attenuator 47, (f) a TX Low Noise Amplifier 48, (g) a Splitter 519, (h) transmit ports, TX Port-1 39a,TX Port-2 39b, (i) an IQ MOD LO Generator 520a, (j) a DAC DATACLK Generator 529a and (k) Digital data to DAC41via one or more interface connectors comprising:

a. The Digital to Analog Converter (DAC) 528a has dual channels, one for In-Phase (I) data and other for Quadrature-phase (Q) Data accepts a multi-bit parallel digital data;

b. The TX Low Pass Filter 527 that removes harmonics that are outside of the passband from the output of the Digital to Analog Converter 528a to conserve bandwidth, and the TX Low Noise Amplifier 48 provides amplification to bandpass signal;

c. The IQ-Modulator 526that combines the In-phase (I) and Quadrature-phase (Q) outputs of the TX Low Pass Filter 527 and upconverts to Intermediate Frequency; d. The TX Saw Filter- 146athat removes the out-of-band noise in a spectrum of the Transmit signal, and the TX Digital Step Attenuator 47 prevents subsequent components from getting into saturation, also aids to attenuate signal strength, if required;

e. The TX Saw Filter-2 46bthat is responsible for removing out-of- band noise in the spectrum of the Transmit signal which is introduced after the TX Low Noise Amplifier48;

f. The Splitter 519 is applied to achieve transmit diversity by sending two copies of the same signal to two transmit ports;

g. The transmit Intermediate Frequency (IF) signal that is given to the transmit ports TX Port- 139a and TX Port-2 39b, the number of ports is any even number as determined during installation;

h. The IQ MOD LO Generator 520a generates clock required for the IQ-Modulator 526 from the DAC DATACLK Generator 529a, and the DAC DATACLK Generator 529a generates the clock needed to the Digital to Analog Converter 528a from the Clock Distribution 524; and

i. The Digital data to DAC 41via one or more interface connectors refers to a digital form of data that is given to the Digital to Analog Converter 528a, the digital value corresponds to an analog voltage value which is the output of the Digital to Analog converter 528.

The modular apparatus for simultaneous MIMO communication of Claim 6 where the receive PCB Assembly consists of (a) an Analog to Digital converter 512, (b)an ADC CLK Generator 521a, (c) an IQ DEMOD LO Generator 50, (d) an IQ Demodulator 514, (e) an Amplifier 51, (f)a RX Saw Filter-2 52a, (g) a RX Saw Filter- 1 52b, (h) a RX Low Noise Amplifier 53, (i)a RX Digital Step Attenuator 54, j)Receive-in 516 and (k) Digital data from ADC 43 further comprising:

a. The Receive-in 516 that refers to the ports, RX Port-1 38d, RX Port-2 38c, RX Port-3 38b and RX Port-4 38a; b. The RX Saw Filter- 1 52bt hat is a bandpass filter centered at an IF frequency is responsible for removing out-of-band noise from the signal;

c. The RX Digital Step Attenuator 54thatprevents the subsequent components from getting into saturation and also aids to attenuate the signal strength if required, and the RX Low Noise Amplifier 53 provides amplification to bandpass signal;

d. The RX Saw Filter-2 52athatfacilitates removal of the out-of-band noise in spectrum of its received input;

e. The IQ Demodulator 514thatconverts filtered and conditioned IF signal to baseband at OHz and provides In-phase (I) and

Quadrature-phase (Q) signals;

f. The Amplifier 51thatmagnifies and shifts DC level of the baseband signal to levels appropriate for further signal processing;

g. The Analog to Digital converter 512thatconverts the analog baseband signal to a proportional, multi-bit parallel digital value; h. The ADC CLK Generator 521a that generates clock required for the Analog to Digital Converter 512 from the Clock Distribution 524, and the IQ DEMOD LO Generator 50 generates the clock required for the IQ Demodulator 514 from the 4xADC CLK

Generator 521; and

i. The Digital data from ADC 43thatis a digital form of data which is an output of the Analog to Digital Converter 512and the digital value corresponds to an analog voltage value which is an input of the Analog to Digital Converter 512.

10. The modular apparatus for simultaneous MIMO communication of Claim 6 wherea top side view of the fully assembled unenclosed system comprises(a) an Ethernet Data Port 501a, (b) an Ethernet Control Port 501b, (c) a Carrier Card 465, (d) a System Processor 466, (e) a Clock Distribution 524, (f) a Multilevel Equalizer Aided Channel Combining and Demodulator 511, (g) an OCXO 522and (h) PCB Assemblies, RX Chain PCBA-Front-end-1 515h, RX Chain PCBA-Front-end-2 515g, RX Chain PCBA-Front-end-3 515f, RX Chain PCBA-Front-end-4 515e and (i) a TX Chain PCBA-Front-end 525a, wherein:

a. The Ethernet Data Port 501a is a port from which transmit data is obtained and to which received data is sent;

b. The Ethernet Control Port 501benables to configure and control the characteristics of the modem sub-system running in the Baseband Processor32 and the Application Processor40; c. The System Processor 466 consists of the Application Processor 40 and Baseband Processor 32 realized in a single Field Programmable Gate Array (FPGA);

d. The Multilevel Equalizer Aided Channel Combining and Demodulator 511 is a unique equalizer realized as one or more Application Specific Integrated Circuits (ASIC) or Field Programmable Gate Arrays (FPGA's) or a combination of both and acts on digital data received at output of the Receive front-end blocks;

e. The OCXO 522 provides an ultra-low jitter 10MHz clock and is powered independently to eliminate any clock leakage on power supply lines and the system can also be clocked from a 10MHz external clock source instead of an internal OCXO;

f. The Clock Distribution 524 refers to a circuit that performs distribution of clock from the OCXO 522 or an external clock throughout the system; The Carrier Card 465 is a PCB Assembly that holds all other discrete circuits onto itself;

The TX Chain PCBA-Front-end 525a is a PCB Assembly that forms analog signal conditioning section and consists of multiple components including a Digital to Analog Converter 528a; and The RX Chain PCBA-Front-end- 1 515h, RX Chain PCBA-Front- end-2 515g, RX Chain PCBA-Front-end-3 515f, RX Chain PCBA- Front-end-4 515e are PCB assemblies that provide signal conditioning to IF received from receiving ports and are front-end assemblies, also include an Analog to Digital Converter 512 resulting in digital output analogous to the input.

11. The modular apparatus for simultaneous MIMO communication of Claim 6, wherein a bottom side view of a fully assembled unenclosed system comprises(a) a Digital data to DAC 41via one or more interface connectors, (b) a Digital to Analog Converter 528a, (c) DAC DATACLK Generator 529a, (d) a TX Low Pass Filter 527, (e) an IQ MOD LO Generator 520a, (f) an IQ-Modulator 526, (g) a TX Saw Filter- 1 46a, TX Saw Filter-2 46b, (h)a TX Digital Step Attenuator 47, (i) a TX Low Noise Amplifier 48, (j) a Splitter 519, (k) transmit ports, TX Port-1 39a,TX Port- 2 39b, (1) a TX Chain PCBA-Front-end 525a, (m)receive ports, RX PORT-1 38d, RX PORT-2 38c, RX PORT-3 38b, RX PORT-4 38a, (n) receive Saw Filters, CH-1 RX Saw Filter- 1 413, CH-2 RX Saw Filter- 1 424, CH-3 RX Saw Filter- 1 433, CH-4 RX Saw Filter- 1 442, (o) Digital Step Attenuators, CH-1 Digital Step Attenuator 414, CH-2 Digital Step Attenuator 425, CH-3 Digital Step Attenuator 434, CH-4 Digital Step Attenuator 443, (p) Low Noise Amplifiers, CH-1 Low Noise Amplifier 415, CH-2 Low Noise Amplifier 426, CH-3 Low Noise Amplifier 435, CH-4 Low Noise Amplifier 444, (q) receive Saw Filters, CH-1 RX Saw Filter-2 416, CH-2 RX Saw Filter-2 427, CH-3 RX Saw Filter-2 436, CH- 4 RX Saw Filter-2 445, (r) IQ Demodulators, CH-1 IQ Demodulator 514a, CH-2 IQ Demodulator 514b, CH-3 IQ Demodulator 514c, CH-4 IQ Demodulator 514d, (s) IQ DEMOD Clock generators, CH-1 IQ DEMOD CLKGEN 419, CH -2 IQ DEMOD CLKGEN 429, CH-3 IQ DEMOD CLKGEN 438, CH -4 IQ DEMOD CLKGEN 447, (t) Amplifiers, CH-1 Amplifier 418, CH-2 Amplifier 451, CH-3 Amplifier 452, CH-4 Amplifier 453, (u) Analog to Digital Converters 512a,512b,512c,512d, (v) a Clock Distribution 524, (w) ADC Clock generators, CH-1 ADC CLKGEN 421, CH-2 ADC CLKGEN 430, CH-3 ADC CLKGEN 439, CH-4 ADC CLKGEN 448, (x) a Digital Data from CH-1 ADC to Connector 422, (y) a Digital Data from CH-2 ADC to Connector 431, (z) a Digital Data from CH-3 ADC to Connector 440, (aa) a Digital Data from CH-4 ADC to Connector 449, (bb) RX Chain PCBA-Front-end 515h, 515g, 515f, 515e, (cc) a Multilevel Equalizer Aided Channel Combining and Demodulator 511 and (dd) a Carrier Card 465, wherein:

a. The TX Chain PCBA-Front-end 525a is a PCB assembly that forms transmit analog signal conditioning section of the system and consists of multiple components including the Digital to Analog Converter 528a;

b. The Digital data to DAC 41 via one or more interface connectors is an entry point for the TX Chain PCB assembly, data from the Transmit side of the Baseband Processor 32will enter the TX Chain PCB assembly via Inter-board connectors;

c. PCB trace length of the Digital to Analog Converter 528adata clock is reduced, by placing the DAC DATACLK Generator 529aadjacent to the Digital to Analog Converter 528a,which is contiguous to the TX Low Pass Filter 527for minimizing the PCB trace length of the analog signal trace;

d. The IQ MOD LO Generator 520ais placed adjacent to the IQ- Modulator 526 to lessen the PCB trace length, and this component derives its clock from the DAC DATACLK Generator 529a,hence placed adjacent to it; The TX Low Pass Filter 527 is placed after the Digital to Analog converter528a, the IQ-Modulator 526after the TX Low Pass Filter 527 and the TX Saw Filter- 146a after the IQ-Modulator526,the TX Digital Step Attenuator47 after the TX Saw Filter- 1 46a, the TX Low Noise Amplifier 48 after the TX Digital Step Attenuator47, the TX Saw Filter-246b after the TX Low Noise Amplifier 48andthe Splitter 519 after the TX Saw Filter-2 46b;

The TX Port-2 39bis positioned after the Splitter 519, the TX Port- 139a is also positioned after the Splitter519 and adjacent to the TX Port-239b whereas the RX PORT-1 38d, RX PORT-2 38c, RX PORT-3 38b, RX PORT-4 38a are placed at an edge of the Receive Front PCBA;

The CH-1 RX Saw Filter- 1 413, CH-2 RX Saw Filter- 1 424, CH-3 RX Saw Filter- 1 433, CH-4 RX Saw Filter- 1 442 removes out of the band noise in signal and are placed just after the respective RX Ports 38d, 38c, 38b, 38a;

The CH-1 Digital Step Attenuator 414, CH-2 Digital Step Attenuator 425, CH-3 Digital Step Attenuator 434, CH-4 Digital Step Attenuator 443 prevent subsequent LNA from getting into saturation and also aids to attenuate signal strength if required, these are placed after respective RX Saw Filters, CH-1 RX Saw filter- 1413, CH-2 RX Saw filter- 1424,CH- 3 RX Saw filter- 1433,CH-4 RX Saw filter- 1442;

The CH-1 Low Noise Amplifier 415, CH-2 Low Noise Amplifier 426, CH-3 Low Noise Amplifier 435, CH-4 Low Noise Amplifier 444 are intended to provide amplification to bandpass signal and are positioned after respective Digital Step Attenuators 414, 425, 434, 443;

The CH-1 RX Saw Filter-2 416, CH-2 RX Saw Filter-2 427, CH-3 RX Saw Filter-2 436, CH-4 RX Saw Filter-2 445 are responsible for removing out-of-band noise in a spectrum of signal that is introduced after Low Noise Amplifier and is located after the Low Noise Amplifiers 415,426,435,444;

k. The CH-1 IQ Demodulator 514a, CH-2 IQ Demodulator 514b, CH-3 IQ Demodulator 514c, CH-4 IQ Demodulator 514d convert Intermediate Frequency bandpass signal to a baseband signal and are placed after the respective RX Saw Filter- 2416,427,436,445, also, have respective IQ DEMOD CLKGEN 419,429,438,447 adjacent to them in order to decrease the PCB trace length of Clock Signal input to these components;

1. The CH-1 Amplifier 418, CH-2 Amplifier 451, CH-3 Amplifier 452, CH-4 Amplifier 453, amplify and perform DC level shift of analog signal to levels appropriate to respective Analog to Digital Converters 512a,512b,512c,512d, are positioned after the respective IQ Demodulators514a, 514b, 514c,514d;

m. The CH-1 IQ DEMOD CLKGEN 419, CH -2 IQ DEMOD CLKGEN 429, CH-3 IQ DEMOD CLKGEN 438, CH -4 IQ DEMOD CLKGEN 447generate IQ demodulator clock from ADC CLKGEN and are adjacent to respective IQ Demodulators on one side to reduce PCB trace length of the IQ Demodulator Clock signal and ADC CLKGEN to lessen reference clock signal trace length;

n. The CH-1 Analog to Digital Converter 512a, CH-2 Analog to Digital Converter 512b, CH-3 Analog to Digital Converter 512c, CH-4 Analog to Digital Converter 512d convert analog signal from respective Amplifiers 418,451,452,453 to proportional digital values and are situated after the respective amplifiers and are also placed adjacent to the respective ADC CLKGEN 421,430,439,448 to minimize the PCB trace length of ADC Clock Signal; The CH-1 ADC CLKGEN 421, CH-2 ADC CLKGEN 430, CH-3 ADC CLKGEN 439, CH-4 ADC CLKGEN 448 provide clock signal to respective ADCs 512a, 512b, 512c, 512d using input from the Clock Distribution 524 and are placed immediately adjacent to the Analog to Digital Converter for reduced ADC Clock signal trace length, also positioned very adjacent to respective IQ DEMOD CLKGEN 419,429,438,447 to lessen reference clock signal lengths;

The Digital Data from CH-1 ADC to Connector 422, Digital Data from CH-2 ADC to Connector 431, Digital Data from CH-3 ADC to Connector 440, Digital Data from CH-4 ADC to Connector 449 are the exit points of each of the respective RX Chain PCBA- Front-end 515h, 515g, 515f, 515e;

The Digital data from ADC 43 are forwarded to Inter-Board Connectors and are taken to the Multilevel Equalizer Aided Channel Combining and Demodulator 511 for further processing of data;

The RX Chain PCBA-Front-end comprises a connector that carries the buffered digital ADC samples from the respective RX Chain PCBA-Front-end 515h, 515g, 515f, 515e to the Carrier Card 465; and

The TX Chain PCBA-Front-end 525a holds transmit side components of the apparatus, the RX Chain PCBA-Front-end- 1 515h, RX Chain PCBA-Front-end-2 515g, RX Chain PCBA-Front- end-3 515f, RX Chain PCBA-Front-end-4 515e hold receive side components of the Communication modem and are mounted on bottom side of the Carrier Card 465, connected electrically via inter-board connectors and mechanically using spacers.