CN114124278A - Digital synchronization circuit and method for digital simultaneous multi-beam transmission - Google Patents
Digital synchronization circuit and method for digital simultaneous multi-beam transmission Download PDFInfo
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Abstract
The invention has proposed a digital synchronous circuit and method used for that the digital multi-beam sends at the same time, the clock circuit passes the clock that the external or on-board crystal oscillator provides through the frequency multiplication, supply ADC, DAC, FPGA's working clock and SYSREF signal that the synchronism needs; the ADC circuit collects the intermediate frequency signal into a digital signal and transmits the digital signal to the FPAG for processing through a JESD204B protocol; the FPGA receives digital signals sent by the ADC to carry out phase measurement, calculates the phase difference among the ADC channels, and returns the phase difference to the clock circuit to carry out clock phase adjustment; meanwhile, a digital channel equalization filter is constructed in the FPGA for amplitude-phase error correction, and the DAC circuit finishes data playback of stored waveforms to generate intermediate frequency signals. The invention improves the synchronization precision of the circuit.
Description
Technical Field
The invention relates to a digital circuit synchronization technology, in particular to a digital synchronization circuit and a method for digital simultaneous multi-beam transmission.
Background
The digital simultaneous transmission multi-beam is a new technology applied to an array system electronic countermeasure system, and can simultaneously transmit a plurality of interference signals to interfere a target. The technology has high requirements on digital board synchronization, and the delay jitter requirement of a multi-path signal finally output by a DAC (digital-to-analog converter) at the digital board end is less than or equal to 10 ps. The existing digital circuit mainly comprises an ADC (analog-to-digital converter), an FPGA (programmable logic gate array), a DAC (digital-to-analog converter) and a clock circuit, wherein the clock circuit provides working clocks for the ADC, the FPGA and the DAC, an ADC chip synchronously acquires intermediate-frequency signals, and sampled data are subjected to algorithm processing such as digital extraction and digital filtering in the FPGA. The multi-path high-speed DAC chip receives data sent by the FPGA to generate single-tone signals, modulation signals, communication signals and the like, the existing circuit synchronization mainly adopts the deterministic delay relation in the JESD204B protocol and the interval taking a sampling clock as a unit to adjust the synchronization error, and the synchronization method is difficult to meet the synchronization precision within 10 ps.
Disclosure of Invention
The invention aims to provide a digital synchronization circuit and a method for digital simultaneous multi-beam transmission.
The technical solution for realizing the purpose of the invention is as follows: a digital synchronization circuit for digital simultaneous multi-beam transmission comprises a clock circuit, an ADC circuit, a DAC circuit and an FPGA, wherein the ADC circuit and the FPGA, and the DAC circuit and the FPGA adopt a JESD204B protocol with deterministic delay to construct a link; the clock circuit supplies a clock provided by an external or on-board crystal oscillator to working clocks of an ADC (analog to digital converter), a DAC (digital to analog converter) and an FPGA (field programmable gate array) and SYSREF (synchronous error frequency ef) signals required by synchronization through frequency multiplication; the ADC circuit collects the intermediate frequency signal into a digital signal and transmits the digital signal to the FPAG for processing through a JESD204B protocol; the FPGA receives digital signals sent by the ADC to carry out phase measurement, calculates the phase difference among the ADC channels, and returns the phase difference to the clock circuit to carry out clock phase adjustment; meanwhile, a digital channel equalization filter is constructed in the FPGA for amplitude-phase error correction, and the DAC circuit finishes data playback of stored waveforms to generate intermediate frequency signals.
Furthermore, the clock circuit is composed of two stages, the first stage adopts an HMC7044 chip, after an external reference clock is input, the frequency is multiplied by the HMC7044 to be a working clock of an ADC (analog to digital converter), a DAC (digital to analog converter) and an FPGA (field programmable gate array), and a SYSREF reference signal is provided to be used as a JESD204B protocol for synchronization, so that the synchronous acquisition and the synchronous transmission of signals are realized; the LTM2954 is adopted as the second-stage clock, the low-jitter clock given by the first-stage clock circuit is subjected to phase adjustment through an internal PLL, and then a clock signal with a fixed phase relation and a SYSREF signal are output.
Furthermore, the ADC circuit performs balance-unbalance conversion on the radio frequency input signal at the front end of an ADC chip by adopting a balun transformer TCM1-63AX +, and realizes impedance matching of the input end while performing single-ended and differential conversion functions.
Furthermore, the DAC circuit converts the complementary current signals output by the DAC chip into intermediate-frequency analog signals at the back end of the DAC chip by adopting a balun transformer TCM1-63AX +.
Further, the digital channel equalization filter connects the DAC signals output by multiple channels back to the same ADC through an analog switch to acquire and store data, calculates the phase acquired by each channel through the FPGA, selects 1 of the channels as a reference channel, calculates the equalization filter coefficients of the other channels and the reference channel, and adjusts the phase and amplitude error through the equalization filter.
A digital synchronization method is based on the digital synchronization circuit for digital simultaneous multi-beam transmission to realize digital synchronization.
Compared with the prior art, the invention has the following remarkable advantages: 1) a secondary clock circuit is added, and the clock phase delay is adjusted; 2) and a channel equalization filter is designed in the FPGA, so that the output synchronization performance is improved.
Drawings
Fig. 1 is a block diagram of a digital synchronization circuit for digital simultaneous multi-beam transmission of the present invention.
Fig. 2 is a block diagram of the clock circuit of the present invention.
Fig. 3 is a synchronous timing diagram of the HMC7044 output of the present invention.
Fig. 4 is a block diagram of an ADC circuit of the present invention.
Fig. 5 is a circuit diagram of the ADC radio frequency input circuit of the present invention.
Fig. 6 is a circuit diagram of a DAC output matching circuit of the present invention.
Fig. 7 is a diagram of an ADC synchronization example of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
As shown in FIG. 1, the digital synchronization circuit for digital simultaneous multi-beam transmission of the present invention comprises a secondary clock circuit, an ADC circuit, a DAC circuit and an FPGA, wherein the ADC and the FPGA, and the DAC and the FPGA all adopt a JESD204B protocol with deterministic delay to construct a link. The clock circuit supplies a clock provided by an external or on-board crystal oscillator to working clocks of an ADC (analog to digital converter), a DAC (digital to analog converter) and an FPGA (field programmable gate array) and SYSREF (synchronous error frequency ef) signals required by synchronization through frequency multiplication; the ADC circuit collects the intermediate frequency signals into digital signals, the digital signals are transmitted to the FPAG to be processed through a JESD204B protocol, the FPGA receives the digital signals sent by the ADC to carry out phase measurement, phase difference among ADC channels is calculated, and the digital signals are returned to the clock circuit to carry out clock phase adjustment; meanwhile, a digital channel equalization filter is constructed in the FPGA for amplitude-phase error correction, and the DAC circuit finishes data playback of stored waveforms to generate intermediate frequency signals. The specific design is described below.
Clock circuit
As shown in fig. 2, the clock design needs to consider the following indexes of the clock: clock phase noise or clock jitter; broadband noise of the clock; synchronization of clocks and lane-to-lane skew. The clock circuit mainly comprises two stages, wherein a first stage adopts an HMC7044 chip, after an external reference clock is input, the frequency is multiplied by the HMC7044 to be working clocks of an ADC (analog-to-digital converter), a DAC (digital-to-analog converter) and an FPGA (field programmable gate array), and a SYSREF reference signal is provided for synchronization of a JESD204B protocol, so that synchronous acquisition and synchronous emission of signals are realized. And the clock jitter brought by a clock source, a transmission path and the like is purified by using the jitter removing function of the HMC7044 chip. The second-stage clock adopts LTM2954, and low-jitter clocks given by the first-stage clock circuit are adjusted in phase (phase values are calculated by FPGA) through an internal high-precision PLL, and then clock signals of an ADC and a DAC and SYSREF signals are provided. The final output device clock and SYSREF have a fixed phase relationship. In addition, in order to avoid the influence of different delays caused by the transmission paths, the clock circuit and the wirings of the ADC and DAC are processed with equal length.
The synchronous relation between the input reference clock (100MHz) and the output clock signal of the HMC7044 and the SYSREF signal is simulated by adopting ADIsimCLK _ setup simulation software of an ADI official network, and a simulation timing diagram is shown in FIG. 3. As can be seen, the HMC7044 output clock has a fixed phase relationship, as does the device clock and SYSREF.
(II) ADC circuit
The ADC is designed and realized by a high-performance ADC chip ADC12DJ3200 of TI company. According to the requirement, the bandwidth of the radio frequency input signal is 1.4 GHz-2.4 GHz, and the ADC performs high-medium frequency sampling in the frequency band. As shown in fig. 4, the ADC circuit performs balun conversion on the rf input signal by using a high-bandwidth 1:1 balun transformer TCM1-63AX + at the front end of the ADC chip, and performs single-ended and differential conversion, and at the same time, the input impedance is 50 Ω, which can better implement impedance matching at the input end. The radio frequency input coupling mode is alternating current coupling. The TCM1-63AX + is a large-bandwidth high-performance balun transformer, the input bandwidth of the balun transformer is 10 MHz-6 GHz, the insertion loss is 1.5dB, the two-stage insertion loss is 3dB, and the balun transformer has low phase and amplitude imbalance degree.
(III) DAC circuit
The DAC adopts a chip AD9164 of ADI company, and the AD9164 is a high-performance single-channel 16-bit digital-to-analog converter and supports the DAC sampling rate of 12.6 GSPS. As shown in fig. 6, the DAC circuit converts the complementary current signal output by the DAC into an intermediate-frequency analog signal at the back end of the DAC by using a balun. TCM1-63AX + balun with lower phase and amplitude imbalance are also sampled.
(IV) JESD204B protocol transport
As shown in fig. 3, JESD204B is designed to transmit a fixed delay, which satisfies the following key synchronization points: synchronizing sampling clocks; JESD204B link synchronization; and (5) baseband synchronous control. In the sampling clock synchronization process, the clock output by the HMC7044 has a fixed phase relationship, the clock phases of each ADC and DAC can be aligned by adjusting the device clock and the SYSREF signal, the timing requirements for establishing a holding relationship and a synchronization signal are met, and meanwhile, an elastic buffer release point is arranged at the receiving end of the JESD204B protocol. The synchronization performance of the JESD204B link is then utilized to align the data of multiple serial channel links or multiple ADCs, DACs to SYSREF using the system reference event signal (SYSREF) in order to synchronize the internal frame clocks of the transmitter and receiver. The base band time sequence synchronization is a trigger signal for the internal work synchronization of the FPGA. The base band time sequence synchronous signal adopts an external clock board card to provide PPS second pulse signals, the provided PPS second pulse signals are required to have a fixed phase relation with a clock, and the second pulse which can be normally acquired by the FPGA is ensured.
The following description will take the example of 2 ADCs synchronized using JESD204B protocol. 2 ADC12DJ3200 devices are synchronous with the same host (namely FPGA), the FPGA samples data under the same SYNC signal, and if deviations of process, voltage, temperature and the like exist in the same clock domain of each ADC, the data are sampled by using a clock which is twice as large as the SYNC signal through data multi-stage cache, so that the error of a data clock can be ensured to be less than 1 clock period. The hardware schematic block diagram is shown in fig. 7: the board card adopts an ADC12DJ3200 chip with a JESD204B interface, and the chip supports JESD204B subclass 1. In a subclass 1 system, the accuracy of the deterministic delay depends on the timing relationship between the device clock and SYSREF, and the skew of the distribution of these signals in the system. In addition to the set-time and hold-time requirements (TSU and THOLD) of SYSREF, the degree to which an application is tolerant of deterministic delay uncertainty is critical to defining the application distribution skew requirements of SYSREF and device clocks. In the subclass 1 system, a "receive buffer" is defined, whose release time is referenced to the external SYSREF signal. Therefore, it is not affected by power cycling in the JESD204B system. Therefore, to achieve data alignment of the outputs of a multi-chip ADC, the DLU time is guaranteed to meet the requirements of the system in the design. The synchronization among a plurality of devices is realized through LMFC frame synchronization in JESD204B and a receiving buffer is arranged at the receiving end.
(V) FPGA
The design of the channel equalization filter in the FPGA is that DAC signals output by multiple channels are connected back to the same ADC through an analog switch to acquire and store data, phases acquired by the channels are calculated through the FPGA, 1 channel is selected as a reference channel, equalization filter coefficients of other channels and the reference channel are calculated, and phase and amplitude errors are adjusted through the equalization filter. The specific operation is as follows:
(1) 1 channel in 2 DACs is selected as a reference channel, and a DDS is used for producing a test signal, such as a linear frequency modulation signal, in the FPGA. After the DAC outputs, the digital signal processor sequentially enters the ADC for collection, collected signals are cached, and obtained data are respectively recorded as: h isref(m) and h1(m)。
(2) Sending the stored data to a main control for processing; to href(m)、h1(m) FFT of corresponding points respectively to obtain Href(m)、H1(m)。
(3) To find
The filter coefficient is h ═ A+H。
(4) These coefficients are used to design an equalization filter.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (6)
1. A digital synchronization circuit for digital simultaneous multi-beam transmission is characterized by comprising a clock circuit, an ADC circuit, a DAC circuit and an FPGA, wherein the ADC circuit and the FPGA, and the DAC circuit and the FPGA adopt a JESD204B protocol with deterministic delay to construct a link; the clock circuit supplies a clock provided by an external or on-board crystal oscillator to working clocks of an ADC (analog to digital converter), a DAC (digital to analog converter) and an FPGA (field programmable gate array) and SYSREF (synchronous error frequency ef) signals required by synchronization through frequency multiplication; the ADC circuit collects the intermediate frequency signal into a digital signal and transmits the digital signal to the FPAG for processing through a JESD204B protocol; the FPGA receives digital signals sent by the ADC to carry out phase measurement, calculates the phase difference among the ADC channels, and returns the phase difference to the clock circuit to carry out clock phase adjustment; meanwhile, a digital channel equalization filter is constructed in the FPGA for amplitude-phase error correction, and the DAC circuit finishes data playback of stored waveforms to generate intermediate frequency signals.
2. The digital synchronization circuit for digital simultaneous multi-beam transmission according to claim 1, wherein the clock circuit is composed of two stages, the first stage adopts an HMC7044 chip, after an external reference clock is input, the HMC7044 is used for frequency multiplication to be used as working clocks of an ADC, a DAC and an FPGA, and simultaneously a SYSREF reference signal is provided for JESD204B protocol synchronization, so as to realize synchronous acquisition and synchronous transmission of signals; the LTM2954 is adopted as the second-stage clock, the low-jitter clock given by the first-stage clock circuit is subjected to phase adjustment through an internal PLL, and then a clock signal with a fixed phase relation and a SYSREF signal are output.
3. The digital synchronization circuit for digital simultaneous multi-beam transmission according to claim 1, wherein the ADC circuit performs balun transformation on the rf input signal at the front end of the ADC chip using balun transformers TCM1-63AX +, thereby performing impedance matching at the input end while performing single-ended and differential transformation functions.
4. The digital synchronization circuit for digital simultaneous multi-beam transmission of claim 1, wherein the DAC circuit converts the complementary current signals output by the DAC chip into intermediate frequency analog signals at the DAC chip back end using balun transformers TCM1-63AX +.
5. The digital synchronization circuit for digital simultaneous multi-beam transmission according to claim 1, wherein the digital channel equalization filter connects the DAC signal outputted by multiple channels back to the same ADC through an analog switch for data acquisition and storage, calculates the phase after each channel is acquired through the FPGA, selects 1 channel as a reference channel, calculates the equalization filter coefficients of other channels and the reference channel, and adjusts the phase and amplitude error through the equalization filter.
6. A digital synchronization method, characterized in that digital synchronization is realized based on the digital synchronization circuit for digital simultaneous multi-beam transmission of any one of claims 1-5.
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| CN116455394A (en) * | 2023-06-16 | 2023-07-18 | 成都铭科思微电子技术有限责任公司 | Multichannel ADC synchronization device and automatic synchronization method |
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