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WO2016002305A1 - Thermistor element and electronic component - Google Patents

Thermistor element and electronic component Download PDF

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Publication number
WO2016002305A1
WO2016002305A1 PCT/JP2015/061755 JP2015061755W WO2016002305A1 WO 2016002305 A1 WO2016002305 A1 WO 2016002305A1 JP 2015061755 W JP2015061755 W JP 2015061755W WO 2016002305 A1 WO2016002305 A1 WO 2016002305A1
Authority
WO
WIPO (PCT)
Prior art keywords
external electrode
land portion
thermistor element
thermistor
element body
Prior art date
Application number
PCT/JP2015/061755
Other languages
French (fr)
Japanese (ja)
Inventor
洋 井原木
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to JP2016531156A priority Critical patent/JP6252679B2/en
Priority to CN201580035880.9A priority patent/CN106663509B/en
Publication of WO2016002305A1 publication Critical patent/WO2016002305A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/02—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material having positive temperature coefficient
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/04—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material having negative temperature coefficient
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering

Definitions

  • the present invention relates to a thermistor element and an electronic component.
  • the thermistor element includes an element body made of ceramics, an internal electrode provided in the element body, and an external electrode that is electrically connected to the internal electrode and covers a part of the outer surface of the element body.
  • the wettability of the solder is good on the outer surface of the external electrode of the thermistor element.
  • the thermistor element becomes small, the problem of mounting defects such as tombstones becomes prominent.
  • an object of the present invention is to provide a thermistor element and an electronic component that can be favorably mounted on a land portion of an external electrode.
  • the thermistor element of the present invention is An element body including first and second end surfaces located on opposite sides, first to fourth side surfaces disposed between the first end surface and the second end surface, and made of ceramics.
  • a first external electrode having a first surface to a fourth surface; Covering the second end surface of the element body and the second end surface side of the fourth side surface from the first side surface of the element body, and facing the fourth side surface from the first side surface of the element body.
  • a second external electrode having a first surface to a fourth surface;
  • the first side surface and the second side surface are located on opposite sides, and the surface roughness of the first side surface and the surface roughness of the second side surface are equal, and Ra1.
  • the third side surface and the fourth side surface are located on opposite sides, and the surface roughness of the third side surface and the surface roughness of the fourth side surface are equal, and Ra2.
  • the surface roughness of the first side surface and the surface roughness of the second side surface are Ra1
  • the surface roughness of the third side surface and the surface roughness of the fourth side surface are Ra2, and Ra1.
  • the first external electrode of the thermistor element is bonded to the first land portion of the mounting substrate, and the second external electrode of the thermistor element is bonded to the second land portion of the mounting substrate.
  • the relationship between the first external electrode and the first land portion will be described. The same applies to the relationship between the second external electrode and the second land portion.
  • the first surface or the second surface of the first external electrode is used as the surface of the first land portion.
  • the third and fourth surfaces of the first external electrode are bonded to the surface of the first land portion via solder.
  • the first and second surfaces of the first external electrode are substantially flat, and the entire opposing surface facing the first land portion of the first external electrode is The surface of the first land portion can be approached. Thereby, the thermal conductivity between the first external electrode and the first land portion (mounting substrate) is improved. Further, since 0.4 ⁇ m ⁇ Ra2, the third surface and the fourth surface of the first external electrode are rough, and the wettability of the solder is good on the third surface and the fourth surface of the first external electrode. Become. Thereby, the mounting of the first external electrode on the first land portion becomes favorable.
  • the third surface or the fourth surface of the first external electrode is defined as the first land portion.
  • the surface of the first land portion is joined to the surface of the first land portion with solder.
  • the third surface and the fourth surface of the first external electrode are rough, and the third surface and the fourth surface of the first external electrode have good solder wettability. It becomes. Thereby, the mounting of the first external electrode on the first land portion becomes favorable.
  • the thermistor element can be satisfactorily mounted on the mounting board by changing the facing surface facing the first and second land parts of the thermistor element according to the size of the first and second land parts of the mounting board. .
  • the surface roughness of the third and fourth side surfaces of the element body does not become too large, and when selecting the appearance defect of the thermistor element, It is not determined that the appearance is poor.
  • the size of the thermistor element is JIS standard 0603 size.
  • the size of the thermistor element is JIS standard 0603 size. Thereby, the size of the thermistor element is reduced.
  • the first and second external electrodes are remarkably mounted on the first and second land portions, and mounting defects such as tombstones are poor. There is no problem.
  • the thermistor element In the electronic component of one embodiment, The thermistor element; A mounting substrate having a first land portion to which the first external electrode of the thermistor element is bonded; and a second land portion to which the second external electrode of the thermistor element is bonded.
  • the quality of the electronic component is improved.
  • the surface area of the first land portion is larger than the areas of the first and second surfaces of the first external electrode, and the surface area of the second land portion is the first surface of the second external electrode.
  • the first surface or the second surface of the first external electrode faces the surface of the first land portion, and the third surface and the third surface of the first external electrode Four surfaces are joined to the surface of the first land portion via solder, and the first surface or the second surface of the second external electrode is opposed to the surface of the second land portion, and the second external electrode
  • the third surface and the fourth surface are joined to the surface of the second land portion via solder,
  • the area of the surface of the first land portion is smaller than the areas of the first and second surfaces of the first external electrode, and the surface area of the second land portion is the first area of the second external electrode.
  • the third surface or the fourth surface of the first external electrode faces the surface of the first land portion while soldering the surface of the first land portion. And the third surface or the fourth surface of the second external electrode is bonded to the surface of the second land portion through solder while facing the surface of the second land portion.
  • the thermistor element is satisfactorily mounted on the mounting substrate, so that the quality of the electronic component is improved.
  • the surface roughness of the first side surface and the surface roughness of the second side surface are Ra1
  • the surface roughness of the third side surface and the surface roughness of the fourth side surface are Ra2, and Ra1.
  • the quality of the electronic component is improved.
  • FIG. 1 is a perspective view showing a thermistor element 1 and an electronic component according to a first embodiment of the present invention.
  • the electronic component includes a mounting substrate 50 and a thermistor element 1 bonded to the mounting substrate 50.
  • Electronic components are used in devices such as personal computers, mobile phones, printers, digital cameras, projectors, LEDs, and car electronics.
  • FIG. 2 is a sectional view of the thermistor element 1.
  • the thermistor element 1 includes an element body 10 made of ceramics, and first and second external electrodes 41 and 42 that cover a part of the outer surface of the element body 10.
  • the element body 10 is made of, for example, ceramics having a positive resistance temperature characteristic.
  • the ceramic is, for example, a barium titanate semiconductor ceramic. That is, the thermistor element 1 is a PTC (Positive Temperature Coefficient) thermistor and has a characteristic that the electrical resistance rapidly increases at the Curie temperature.
  • PTC Positive Temperature Coefficient
  • the element body 10 is formed in a substantially rectangular parallelepiped shape.
  • the element body 10 includes a first end surface 15 and a second end surface 16 that are located on opposite sides, and a first side surface 11 to a fourth side surface 14 that are disposed between the first end surface 15 and the second end surface 16.
  • the first side surface 11 and the second side surface 12 are located on the opposite sides.
  • the third side surface 13 and the fourth side surface 14 are located on the opposite sides.
  • the surface roughness of the first side surface 11 is equal to the surface roughness of the second side surface 12 and is Ra1.
  • the surface roughness of the third side surface 13 and the surface roughness of the fourth side surface 14 are equal and are Ra2.
  • Ra1 and Ra2 are arithmetic mean roughnesses. Ra1 ⁇ Ra2 and 0.1 ⁇ m ⁇ Ra1 ⁇ 0.4 ⁇ m and 0.4 ⁇ m ⁇ Ra2.
  • the first and second external electrodes 41 and 42 are made of Ag, for example.
  • the first and second external electrodes 41 and 42 are formed by sputtering, for example.
  • the first external electrode 41 covers the first end surface 15 of the element body 10 and the first end surface 15 side of the fourth side surface 14 from the first side surface 11 of the element body 10.
  • the first external electrode 41 has a first surface 141 to a fourth surface 144 that sequentially face the first side surface 11 to the fourth side surface 14 of the element body 10.
  • the first surface 141 and the second surface 142 are located on opposite sides of each other.
  • the third side surface 13 and the fourth side surface 14 are located on the opposite sides.
  • the surface roughness of the first surface 141 to the fourth surface 144 of the first external electrode 41 corresponds to the surface roughness of the first side surface 11 to the fourth side surface 14 of the element body 10. That is, the roughness of the surface from the first side surface 11 to the fourth side surface 14 is transferred from the first surface 141 to the surface of the fourth surface 144.
  • the second external electrode 42 covers the second end face 16 of the element body 10 and the first end face 11 to the second end face 16 side of the fourth side face 14 of the element body 10.
  • the second external electrode 42 has a first surface 141 to a fourth surface 144 that sequentially face the first side surface 11 to the fourth side surface 14 of the element body 10.
  • the first surface 141 and the second surface 142 are located on opposite sides of each other.
  • the third side surface 13 and the fourth side surface 14 are located on the opposite sides.
  • the surface roughness of the first surface 141 to the fourth surface 144 of the second external electrode 42 corresponds to the surface roughness of the first side surface 11 to the fourth side surface 14 of the element body 10. That is, the roughness of the surface from the first side surface 11 to the fourth side surface 14 is transferred from the first surface 141 to the surface of the fourth surface 144.
  • the surface roughness of the first side surface 11 and the surface roughness of the second side surface 12 are Ra1
  • the surface roughness of the third side surface 13 and the surface roughness of the fourth side surface 14 are Ra2, Ra1 ⁇ Ra2, 0.1 ⁇ m ⁇ Ra1 ⁇ 0.4 ⁇ m, and 0.4 ⁇ m ⁇ Ra2.
  • the surface roughness of the first and second surfaces 141 and 142 of the first external electrode 41 and the surface roughness of the first and second surfaces 141 and 142 of the second external electrode 42 are uneven, corresponding to Ra1. Get smaller.
  • the surface roughness of the third and fourth surfaces 143 and 144 of the first external electrode 41 and the surface roughness of the third and fourth surfaces 133 and 144 of the second external electrode 42 have large irregularities corresponding to Ra2. Become.
  • first external electrode 41 of the thermistor element 1 is bonded to the first land portion 51 of the mounting substrate 50 and the second external electrode 42 of the thermistor element 1 is bonded to the second land portion 52 of the mounting substrate 50.
  • first external electrode 41 and the first land portion 51 will be described.
  • second external electrode 42 and the second land portion 52 is the same, the description thereof is omitted.
  • the second surface 142 of the first external electrode 41 is opposed to the surface of the first land portion 51, and the third surface 143 and the fourth surface 144 of the first external electrode 41 are disposed on the surface of the first land portion 51. It joins via the solder 60. That is, the second surface 142 of the first external electrode 41 is a surface facing the first land portion 51 of the thermistor element 1.
  • the first and second surfaces 141 and 142 of the first external electrode 41 are substantially flat and face the first land portion 51 of the first external electrode 41.
  • the entire second surface 142 can approach the surface of the first land portion 51.
  • the thermal conductivity between the first external electrode 41 and the first land portion 51 (mounting substrate 50) is improved.
  • Ra1 is larger than 0.4 ⁇ m
  • the unevenness of the second surface 142 becomes large, and a part (concave portion) of the second surface 142 is far from the surface of the first land portion 51.
  • the thermal conductivity between the first external electrode 41 and the first land portion 51 is lowered.
  • the thermal conductivity from the mounting substrate 50 is improved, when the thermistor element 1 is an overheat detection element, the response to the temperature of the overheat detection element is improved.
  • the heat dissipation to the mounting substrate 50 is improved, when the thermistor element 1 is an overcurrent protection element, a large amount of current can flow through the overcurrent protection element, and the withstand voltage level of the overcurrent protection element is high. improves.
  • the first surface 141 that is the upper surface of the first external electrode 41 is substantially flat, it is possible to prevent moisture from remaining on the first surface 141 at the time of dew condensation and to reduce the risk of Ag and Sn migration. .
  • the lower limit value of Ra1 is set to 0.1 ⁇ m, it is possible to suppress the influence of mounting failure (tombstone) of the thermistor element 1 on the mounting substrate 50.
  • Ra1 is smaller than 0.1 ⁇ m, the thermistor element 1 may be mounted poorly. The cause of this is that the solder 60 existing between the second surface 142 of the first external electrode 41 and the surface of the first land portion 51 causes a buoyancy and a repulsive force is generated in the first external electrode 41. It is considered that a tombstone is generated in the element 1.
  • the third and fourth surfaces 143 and 144 of the first external electrode 41 become rough, and the third and fourth surfaces 143 and 144 of the first external electrode 41 have solder 60.
  • the wettability of is improved.
  • the third and fourth surfaces 143 and 144 and the surface of the first land portion 51 are firmly joined by the solder 60, and the first external electrode 41 can be mounted on the first land portion 51 well.
  • Ra2 is smaller than 0.4 ⁇ m, the unevenness of the third and fourth surfaces 143 and 144 is reduced, and the wettability of the solder 60 on the third and fourth surfaces 143 and 144 is reduced. As a result, the mounting of the first external electrode 41 on the first land portion 51 becomes defective.
  • the thermistor element 1 is an overcurrent protection element, a large amount of current can flow through the overcurrent protection element, and the withstand voltage level of the overcurrent protection element is improved.
  • the second surface 142 of the first external electrode 41 is opposed to the surface of the first land portion 51.
  • the first surface 141 and the second surface 142 have the same surface roughness, the first external electrode
  • the first surface 141 of 41 may be opposed to the surface of the first land portion 51.
  • the first surface 141 and the second surface 142 do not cause a problem even if the first surface 141 and the second surface 142 are reversed, and no extra alignment work is required.
  • the third surface 143 of the first external electrode 41 is opposed to the surface of the first land portion 51 and joined to the surface of the first land portion 51 via the solder 60. That is, the third surface 143 of the first external electrode 41 is a surface facing the first land portion 51 of the thermistor element 1.
  • the second surface 142 When the second surface 142 is opposed to the first land portion 51, the surface of the first land portion 51 is covered with the second surface 142, and the surface of the first land portion 51 has third, There is no region for joining the fourth surfaces 143 and 144. For this reason, the first external electrode 41 cannot be bonded to the first land portion 51.
  • the third surface 143 is connected to the first land portion 51 via the solder 60 regardless of whether the width W2 of the third and fourth surfaces 143 and 144 is larger or smaller than the width S of the first land portion 51. Can be joined together.
  • the third and fourth surfaces 143 and 144 of the first external electrode 41 are rough, and the third and fourth surfaces 143 and 144 of the first external electrode 41 are soldered.
  • a wettability of 60 is good.
  • the third surface 143 and the surface of the first land portion 51 are firmly joined by the solder 60, and the mounting of the first external electrode 41 on the first land portion 51 is improved.
  • Ra2 is smaller than 0.4 ⁇ m, the unevenness of the third surface 143 is reduced, and the wettability of the solder 60 on the third surface 143 is lowered. As a result, the first outer electrode 41 of the first external electrode 41 is reduced. Mounting on one land portion 51 becomes defective.
  • the 3rd surface 143 of the 1st external electrode 41 was made to oppose the surface of the 1st land part 51, since the 3rd surface 143 and the 4th surface 144 have the same surface roughness, the 1st external electrode The fourth surface 144 of 41 may be opposed to the surface of the first land portion 51.
  • the third surface 143 and the fourth surface 144 have a structure that does not cause a problem even if the third surface 143 and the fourth surface 144 are reversed, and no extra alignment work is required.
  • the thermistor element is changed by changing the facing surfaces of the thermistor element 1 facing the first and second land parts 51 and 52 according to the sizes of the first and second land parts 51 and 52 of the mounting substrate 50. 1 can be satisfactorily mounted on the mounting substrate 50.
  • the standard size of the first and second land portions 51 and 52 is approximately larger than the outer surfaces 141 to 144 of the first and second external electrodes 41 and 42. Therefore, as shown in FIG. 3, the thermistor element 1 is mounted on the mounting substrate 50 so that the second surface 142 of the first external electrode 41 faces the first land portion 51 of the thermistor element 1.
  • electronic devices such as smartphones have been downsized. In such an electronic device, since it is necessary to densely mount electronic components on the mounting substrate, the size of the land portion is reduced.
  • the thermistor element 1 is arranged so that the third surface 143 of the first external electrode 41 faces the first land portion 51 of the thermistor element 1 as shown in FIG. Mounted on the mounting substrate 50. Therefore, the thermistor element 1 can be satisfactorily mounted on the mounting substrate 50 regardless of the size of the first and second land portions 51 and 52.
  • the surface roughness of the third and fourth side surfaces 13 and 14 of the element body 10 does not become too large, and is not determined to be an appearance defect when the appearance defect of the thermistor element 1 is selected.
  • the size of the thermistor element 1 is JIS standard 0603 size.
  • the JIS standard 0603 size is length (0.6 ⁇ 0.03) mm ⁇ width (0.3 ⁇ 0.03) mm, for example, length 0.6 mm ⁇ width 0.3 mm ⁇
  • the thickness is 0.3 mm.
  • the first and second external electrodes 41 and 42 are mounted on the first and second land portions 51 and 52 to be remarkably good. Therefore, there is no problem of mounting defects such as Tombstone.
  • the area of the surface of the first land portion 51 is larger than the areas of the first and second surfaces 141 and 142 of the first external electrode 41, as shown in FIG.
  • the first land 141 or the first surface of the first external electrode 41 is large.
  • the second surface 142 faces the surface of the first land portion 51, the third surface 143 and the fourth surface 144 of the first external electrode 41 are joined to the surface of the first land portion 51 via the solder 60, and 2
  • the first surface 141 or the second surface 142 of the external electrode 42 faces the surface of the second land portion 52, and the third surface 143 and the fourth surface 144 of the second external electrode 42 are on the surface of the second land portion 52. Bonding is performed via solder 60.
  • the area of the surface of the first land portion 51 is smaller than the areas of the first and second surfaces 141 and 142 of the first external electrode 41, and the surface of the second land portion 52.
  • the third surface 143 or the fourth surface 144 of the first external electrode 41 has the first land portion.
  • the third surface 143 or the fourth surface 144 of the second external electrode 42 is joined to the surface of the second land portion 52 while being bonded to the surface of the first land portion 51 via the solder 60 while facing the surface of the first land portion 51. It is joined to the surface of the second land portion 52 via the solder 60 while facing each other.
  • Example 1 of the thermistor element 1 will be described.
  • thermistor element 1 a chip type PTC thermistor of JIS standard 0603 size (0.6 mm ⁇ 0.3 mm ⁇ 0.3 mm) was prepared.
  • the chip-type PTC thermistor is a ceramic PTC thermistor mainly composed of BaTiO 3 , and has a Curie temperature of 100 ° C. and a room temperature resistance value (25 ° C.) of 2.2 k ⁇ (specific resistance is 34 ⁇ ⁇ cm).
  • the dimensions of the first and second external electrodes 41 and 42 are 0.15 mm.
  • the first and second external electrodes 41 and 42 were formed by applying Ni / Sn plating (surface layer is Sn 100%, matte plating, plating thickness: 3 ⁇ m) on the surface of the element body 10.
  • the element body 10 is not particularly subjected to pretreatment (such as steam aging).
  • the surface roughness Ra2 of the third and fourth side surfaces 13 and 14 of the element body 10 is fixed to 0.2 ⁇ m, and the surface roughness of the first and second side surfaces 11 and 12 of the element body 10 is fixed.
  • Ra1 was changed by barrel polishing or sandblasting. 10,000 samples of the thermistor element 1 with different Ra1 were prepared, and an experiment for mounting the substrate on the mounter was conducted. That is, as shown in FIGS. 1 and 3, the first and second external electrodes 41 and 42 are opposed to the first and second land portions 51 and 52 so that the second surfaces 142 of the first and second external electrodes 41 and 42 are opposed to each other.
  • the third and fourth surfaces 143 and 144 of the electrodes 41 and 42 are joined to the first and second land portions 51 and 52 by solder 60.
  • Table 1 shows the number of failures when Ra1 is changed.
  • an element was prepared in which Ra1 was changed from 0.1 ⁇ m to 0.8 ⁇ m and Ra2 was changed from 0.1 ⁇ m to 0.8 ⁇ m. These elements were reflow mounted and the element strength after mounting evaluation was confirmed. At this time, the size of the land used in the mounting evaluation is 0.3 mm ⁇ 0.3 mm.
  • the solder paste M705-GRN360-K2-V made by Senju Metal Co., Ltd. was used, and the solder coating thickness was 80 ⁇ m.
  • Table 2 shows the test results for this strength.
  • the number of measurements is 50 under each condition, and the minimum value of intensity [N] is shown under each condition.
  • Example 2 of the thermistor element 1 will be described.
  • thermistor element 1 a chip type PTC thermistor of JIS standard 0603 size (0.6 mm ⁇ 0.3 mm ⁇ 0.3 mm) was prepared.
  • the chip-type PTC thermistor is a ceramic PTC thermistor mainly composed of BaTiO 3 , and has a Curie temperature of 120 ° C. and a room temperature resistance value (25 ° C.) of 470 ⁇ (specific resistance is 7.7 ⁇ ⁇ cm).
  • the dimensions of the first and second external electrodes 41 and 42 are 0.15 mm.
  • the first and second external electrodes 41 and 42 were formed by applying Ni / Sn plating (surface layer is Sn 100%, matte plating, plating thickness: 3 ⁇ m) on the surface of the element body 10.
  • the element body 10 is not particularly subjected to pretreatment (such as steam aging).
  • Table 3 shows the withstand voltage test results. Table 3 shows the minimum value of the voltage [V] that the product withstood under each condition with the number of measurements being 50 under each condition.
  • FIG. 5 is a sectional view showing a thermistor element according to the second embodiment of the present invention.
  • the second embodiment is different from the first embodiment only in the configuration of the internal electrodes. Only this different configuration will be described below. Note that in the second embodiment, the same reference numerals as those in the first embodiment have the same configurations as those in the first embodiment, and a description thereof will be omitted.
  • the thermistor element 1 ⁇ / b> A includes internal electrodes 21 and 22 that are provided in the element body 10 and end portions 21 a and 22 a are exposed from the outer surface of the element body 10.
  • the external electrodes 41 and 42 are electrically connected to the end portions 21 a and 22 a of the internal electrodes 21 and 22.
  • the internal electrodes 21 and 22 are formed in a substantially flat plate shape.
  • the internal electrodes 21 and 22 include, for example, at least one element of Ni, Cu, Fe, Co, W, Ta, Ti, and Mo.
  • the plurality of internal electrodes 21 and 22 are arranged substantially in parallel with a space therebetween. In two adjacent internal electrodes 21 and 22, the end 21 a of the first internal electrode 21 is exposed from the first end surface 15 of the element body 10, and the end 22 a of the second internal electrode 22 is exposed to the first end of the element body 10. The two end faces 16 are exposed.
  • the first external electrode 41 is in contact with and electrically connected to the end 21a of the first internal electrode 21.
  • the second external electrode 42 is in contact with and electrically connected to the end 22 a of the second internal electrode 22.
  • the first and second side surfaces 11 and 12 of the element body 10 are positioned in the stacking direction of the plurality of internal electrodes 21 and 22.
  • the surface roughness of the first side surface 11 and the surface roughness of the second side surface 12 are Ra1
  • the surface roughness of the third side surface 13 and the surface roughness of the fourth side surface 14 are Ra2, Ra1 ⁇ Ra2, 0.1 ⁇ m ⁇ Ra1 ⁇ 0.4 ⁇ m, and 0.4 ⁇ m ⁇ Ra2. Therefore, in the thermistor element 1A of the second embodiment, the mounting of the external electrodes 41 and 42 on the land portion is good as in the first embodiment.
  • the thermistor element is a PTC (Positive Temperature Coefficient) thermistor, but may be an NTC (Negative Temperature Temperature Coefficient) thermistor made of ceramics having negative resistance temperature characteristics.
  • the thermistor element may include an internal electrode or may not include an internal electrode.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thermistors And Varistors (AREA)
  • Details Of Resistors (AREA)

Abstract

This thermistor element comprises: an element body; and first and second external electrodes, each of which covers a part of the outer surface of the element body. The element body has first to fourth lateral surfaces. The first lateral surface and the second lateral surface are positioned opposite to each other. The third lateral surface and the fourth lateral surface are positioned opposite to each other. The surface roughness of the first lateral surface and the surface roughness of the second lateral surface are equal to each other and represented by Ra1. The surface roughness of the third lateral surface and the surface roughness of the fourth lateral surface are equal to each other and represented by Ra2. The surface roughnesses satisfy Ra1 < Ra2, 0.1 μm ≤ Ra1 ≤ 0.4 μm and 0.4 μm ≤ Ra2.

Description

サーミスタ素子および電子部品Thermistor element and electronic component
　本発明は、サーミスタ素子および電子部品に関する。 The present invention relates to a thermistor element and an electronic component.
　従来、サーミスタ素子としては、特開２００７－２４６３２８号公報（特許文献１）に記載されたものがある。このサーミスタ素子は、セラミックスから構成される素体と、素体内に設けられた内部電極と、内部電極に電気的に接続され素体の外面の一部を覆う外部電極とを有する。 Conventionally, as a thermistor element, there is one described in Japanese Patent Application Laid-Open No. 2007-246328 (Patent Document 1). The thermistor element includes an element body made of ceramics, an internal electrode provided in the element body, and an external electrode that is electrically connected to the internal electrode and covers a part of the outer surface of the element body.
特開２００７－２４６３２８号公報JP 2007-246328 A
　ところで、前記従来のサーミスタ素子では、実際に、サーミスタ素子の外部電極を、半田を介して、実装基板のランド部に接合しようとすると、サーミスタ素子の外部電極の外面では、半田の濡れ性が良くなく、外部電極とランド部とを半田により接合し難くい問題があった。特に、サーミスタ素子が小さくなると、ツームストン等の実装不良の問題が顕著となった。 By the way, in the conventional thermistor element, when the external electrode of the thermistor element is actually joined to the land portion of the mounting substrate via solder, the wettability of the solder is good on the outer surface of the external electrode of the thermistor element. However, there is a problem that it is difficult to join the external electrode and the land portion with solder. In particular, when the thermistor element becomes small, the problem of mounting defects such as tombstones becomes prominent.
　そこで、本発明の課題は、外部電極のランド部への実装が良好となるサーミスタ素子および電子部品を提供することにある。 Therefore, an object of the present invention is to provide a thermistor element and an electronic component that can be favorably mounted on a land portion of an external electrode.
　前記課題を解決するため、本発明のサーミスタ素子は、
　互いに反対側に位置する第１端面および第２端面と、前記第１端面と前記第２端面との間に配置される第１側面から第４側面とを有すると共に、セラミックスから構成される素体と、
　前記素体の前記第１端面と、前記素体の前記第１側面から前記第４側面の前記第１端面側とを覆うと共に、前記素体の前記第１側面から前記第４側面に対向する第１面から第４面を有する第１外部電極と、
　前記素体の前記第２端面と、前記素体の前記第１側面から前記第４側面の前記第２端面側とを覆うと共に、前記素体の前記第１側面から前記第４側面に対向する第１面から第４面を有する第２外部電極と
を備え、
　前記第１側面と前記第２側面とは、互いに反対側に位置し、前記第１側面の表面粗さと前記第２側面の表面粗さとは、等しく、Ｒａ１であり、
　前記第３側面と前記第４側面とは、互いに反対側に位置し、前記第３側面の表面粗さと前記第４側面の表面粗さとは、等しく、Ｒａ２であり、
　Ｒａ１＜Ｒａ２であり、かつ、
　０．１μｍ≦Ｒａ１≦０．４μｍであり、かつ、
　０．４μｍ≦Ｒａ２であることを特徴としている。 In order to solve the above problems, the thermistor element of the present invention is
An element body including first and second end surfaces located on opposite sides, first to fourth side surfaces disposed between the first end surface and the second end surface, and made of ceramics. When,
Covering the first end surface of the element body and the first end surface side of the fourth side surface from the first side surface of the element body, and facing the fourth side surface from the first side surface of the element body. A first external electrode having a first surface to a fourth surface;
Covering the second end surface of the element body and the second end surface side of the fourth side surface from the first side surface of the element body, and facing the fourth side surface from the first side surface of the element body. A second external electrode having a first surface to a fourth surface;
The first side surface and the second side surface are located on opposite sides, and the surface roughness of the first side surface and the surface roughness of the second side surface are equal, and Ra1.
The third side surface and the fourth side surface are located on opposite sides, and the surface roughness of the third side surface and the surface roughness of the fourth side surface are equal, and Ra2.
Ra1 <Ra2 and
0.1 μm ≦ Ra1 ≦ 0.4 μm, and
It is characterized by 0.4 μm ≦ Ra2.
　本発明のサーミスタ素子によれば、第１側面の表面粗さと第２側面の表面粗さとは、Ｒａ１であり、第３側面の表面粗さと第４側面の表面粗さとは、Ｒａ２であり、Ｒａ１＜Ｒａ２であり、かつ、０．１μｍ≦Ｒａ１≦０．４μｍであり、かつ、０．４μｍ≦Ｒａ２である。これにより、第１外部電極の第１、第２面の表面粗さと第２外部電極の第１、第２面の表面粗さとは、Ｒａ１に対応して凹凸が小さくなり、一方、第１外部電極の第３、第４面の表面粗さと第２外部電極の第３、第４面の表面粗さとは、Ｒａ２に対応して凹凸が大きくなる。 According to the thermistor element of the present invention, the surface roughness of the first side surface and the surface roughness of the second side surface are Ra1, the surface roughness of the third side surface and the surface roughness of the fourth side surface are Ra2, and Ra1. <Ra2, 0.1 μm ≦ Ra1 ≦ 0.4 μm, and 0.4 μm ≦ Ra2. Thereby, the surface roughness of the first and second surfaces of the first external electrode and the surface roughness of the first and second surfaces of the second external electrode are reduced in unevenness corresponding to Ra1, while the first external electrode The surface roughness of the third and fourth surfaces of the electrode and the surface roughness of the third and fourth surfaces of the second external electrode increase in unevenness corresponding to Ra2.
　ここで、サーミスタ素子の第１外部電極を実装基板の第１ランド部に接合し、サーミスタ素子の第２外部電極を実装基板の第２ランド部に接合する。以下、第１外部電極と第１ランド部との関係について説明するが、第２外部電極と第２ランド部との関係についても同様である。 Here, the first external electrode of the thermistor element is bonded to the first land portion of the mounting substrate, and the second external electrode of the thermistor element is bonded to the second land portion of the mounting substrate. Hereinafter, the relationship between the first external electrode and the first land portion will be described. The same applies to the relationship between the second external electrode and the second land portion.
　第１ランド部の表面の面積が、第１外部電極の第１、第２面の面積に比べて、大きい場合、第１外部電極の第１面または第２面を第１ランド部の表面に対向させ、第１外部電極の第３面と第４面を第１ランド部の表面に半田を介して接合する。 When the area of the surface of the first land portion is larger than the areas of the first and second surfaces of the first external electrode, the first surface or the second surface of the first external electrode is used as the surface of the first land portion. The third and fourth surfaces of the first external electrode are bonded to the surface of the first land portion via solder.
　このとき、０．１μｍ≦Ｒａ１≦０．４μｍであるため、第１外部電極の第１、第２面は、略平坦となり、第１外部電極の第１ランド部に対向する対向面の全体が、第１ランド部の表面に近づくことができる。これにより、第１外部電極と第１ランド部（実装基板）との熱伝導性が、向上する。また、０．４μｍ≦Ｒａ２であるため、第１外部電極の第３面と第４面は、粗くなり、第１外部電極の第３面と第４面では、半田の濡れ性が、良好となる。これにより、第１外部電極の第１ランド部への実装が、良好となる。 At this time, since 0.1 μm ≦ Ra1 ≦ 0.4 μm, the first and second surfaces of the first external electrode are substantially flat, and the entire opposing surface facing the first land portion of the first external electrode is The surface of the first land portion can be approached. Thereby, the thermal conductivity between the first external electrode and the first land portion (mounting substrate) is improved. Further, since 0.4 μm ≦ Ra2, the third surface and the fourth surface of the first external electrode are rough, and the wettability of the solder is good on the third surface and the fourth surface of the first external electrode. Become. Thereby, the mounting of the first external electrode on the first land portion becomes favorable.
　一方、第１ランド部の表面の面積が、第１外部電極の第１、第２面の面積に比べて、小さい場合、第１外部電極の第３面または第４面を、第１ランド部の表面に対向させつつ、第１ランド部の表面に半田を介して接合する。 On the other hand, when the area of the surface of the first land portion is smaller than the areas of the first and second surfaces of the first external electrode, the third surface or the fourth surface of the first external electrode is defined as the first land portion. The surface of the first land portion is joined to the surface of the first land portion with solder.
　このとき、０．４μｍ≦Ｒａ２であるため、第１外部電極の第３面と第４面は、粗くなり、第１外部電極の第３面と第４面では、半田の濡れ性が、良好となる。これにより、第１外部電極の第１ランド部への実装が、良好となる。 At this time, since 0.4 μm ≦ Ra2, the third surface and the fourth surface of the first external electrode are rough, and the third surface and the fourth surface of the first external electrode have good solder wettability. It becomes. Thereby, the mounting of the first external electrode on the first land portion becomes favorable.
　したがって、実装基板の第１、第２ランド部の大きさに応じて、サーミスタ素子の第１、第２ランド部に対向する対向面を変更することで、サーミスタ素子を実装基板に良好に実装できる。 Therefore, the thermistor element can be satisfactorily mounted on the mounting board by changing the facing surface facing the first and second land parts of the thermistor element according to the size of the first and second land parts of the mounting board. .
　また、一実施形態のサーミスタ素子では、Ｒａ２≦０．８μｍである。 In the thermistor element of one embodiment, Ra2 ≦ 0.8 μm.
　前記実施形態のサーミスタ素子によれば、Ｒａ２≦０．８μｍであるので、素体の第３、第４側面の表面粗さは、大きくなりすぎず、サーミスタ素子の外観不良を選別する際に、外観不良と判定されない。 According to the thermistor element of the embodiment, since Ra2 ≦ 0.8 μm, the surface roughness of the third and fourth side surfaces of the element body does not become too large, and when selecting the appearance defect of the thermistor element, It is not determined that the appearance is poor.
　また、一実施形態のサーミスタ素子では、前記サーミスタ素子のサイズは、ＪＩＳ規格０６０３サイズである。 Also, in the thermistor element of one embodiment, the size of the thermistor element is JIS standard 0603 size.
　前記実施形態のサーミスタ素子によれば、前記サーミスタ素子のサイズは、ＪＩＳ規格０６０３サイズである。これにより、サーミスタ素子のサイズが小さくなるが、本発明のサーミスタ素子では、第１、第２外部電極の第１、第２ランド部への実装が顕著に良好となって、ツームストン等の実装不良の問題がない。 According to the thermistor element of the embodiment, the size of the thermistor element is JIS standard 0603 size. Thereby, the size of the thermistor element is reduced. However, in the thermistor element of the present invention, the first and second external electrodes are remarkably mounted on the first and second land portions, and mounting defects such as tombstones are poor. There is no problem.
　また、一実施形態の電子部品では、
　前記サーミスタ素子と、
　前記サーミスタ素子の前記第１外部電極が接合される第１ランド部と、前記サーミスタ素子の前記第２外部電極が接合される第２ランド部とを有する実装基板と
を備える。 In the electronic component of one embodiment,
The thermistor element;
A mounting substrate having a first land portion to which the first external electrode of the thermistor element is bonded; and a second land portion to which the second external electrode of the thermistor element is bonded.
　前記実施形態の電子部品によれば、実装基板に良好に実装できるサーミスタ素子を有するので、電子部品の品質が良好となる。 According to the electronic component of the above-described embodiment, since the thermistor element that can be satisfactorily mounted on the mounting substrate is provided, the quality of the electronic component is improved.
　また、一実施形態の電子部品では、
　前記第１ランド部の表面の面積が、前記第１外部電極の第１、第２面の面積に比べて、大きく、前記第２ランド部の表面の面積が、前記第２外部電極の第１、第２面の面積に比べて、大きい状態では、前記第１外部電極の第１面または第２面が前記第１ランド部の表面に対向し、前記第１外部電極の第３面と第４面が前記第１ランド部の表面に半田を介して接合されると共に、前記第２外部電極の第１面または第２面が前記第２ランド部の表面に対向し、前記第２外部電極の第３面と第４面が前記第２ランド部の表面に半田を介して接合され、
　前記第１ランド部の表面の面積が、前記第１外部電極の第１、第２面の面積に比べて、小さく、前記第２ランド部の表面の面積が、前記第２外部電極の第１、第２面の面積に比べて、小さい状態では、前記第１外部電極の第３面または第４面が、前記第１ランド部の表面に対向しつつ前記第１ランド部の表面に半田を介して接合されると共に、前記第２外部電極の第３面または第４面が、前記第２ランド部の表面に対向しつつ前記第２ランド部の表面に半田を介して接合される。 In the electronic component of one embodiment,
The surface area of the first land portion is larger than the areas of the first and second surfaces of the first external electrode, and the surface area of the second land portion is the first surface of the second external electrode. In a state larger than the area of the second surface, the first surface or the second surface of the first external electrode faces the surface of the first land portion, and the third surface and the third surface of the first external electrode Four surfaces are joined to the surface of the first land portion via solder, and the first surface or the second surface of the second external electrode is opposed to the surface of the second land portion, and the second external electrode The third surface and the fourth surface are joined to the surface of the second land portion via solder,
The area of the surface of the first land portion is smaller than the areas of the first and second surfaces of the first external electrode, and the surface area of the second land portion is the first area of the second external electrode. In a state smaller than the area of the second surface, the third surface or the fourth surface of the first external electrode faces the surface of the first land portion while soldering the surface of the first land portion. And the third surface or the fourth surface of the second external electrode is bonded to the surface of the second land portion through solder while facing the surface of the second land portion.
　前記実施形態の電子部品によれば、サーミスタ素子が実装基板に良好に実装されているので、電子部品の品質が向上する。 According to the electronic component of the above embodiment, the thermistor element is satisfactorily mounted on the mounting substrate, so that the quality of the electronic component is improved.
　本発明のサーミスタ素子によれば、第１側面の表面粗さと第２側面の表面粗さとは、Ｒａ１であり、第３側面の表面粗さと第４側面の表面粗さとは、Ｒａ２であり、Ｒａ１＜Ｒａ２であり、かつ、０．１μｍ≦Ｒａ１≦０．４μｍであり、かつ、０．４μｍ≦Ｒａ２である。これにより、外部電極のランド部への実装が良好となる。 According to the thermistor element of the present invention, the surface roughness of the first side surface and the surface roughness of the second side surface are Ra1, the surface roughness of the third side surface and the surface roughness of the fourth side surface are Ra2, and Ra1. <Ra2, 0.1 μm ≦ Ra1 ≦ 0.4 μm, and 0.4 μm ≦ Ra2. Thereby, the mounting of the external electrode on the land portion becomes good.
　また、本発明の電子部品によれば、実装基板に良好に実装できるサーミスタ素子を有するので、電子部品の品質が良好となる。 In addition, according to the electronic component of the present invention, since the thermistor element that can be satisfactorily mounted on the mounting substrate is provided, the quality of the electronic component is improved.
本発明の第１実施形態のサーミスタ素子および電子部品を示す斜視図である。It is a perspective view which shows the thermistor element and electronic component of 1st Embodiment of this invention. サーミスタ素子の断面図である。It is sectional drawing of a thermistor element. サーミスタ素子を標準サイズのランド部に接合した状態を示す説明図である。It is explanatory drawing which shows the state which joined the thermistor element to the land part of standard size. サーミスタ素子を小サイズのランド部に接合した状態を示す説明図である。It is explanatory drawing which shows the state which joined the thermistor element to the small-sized land part. 本発明の第２実施形態のサーミスタ素子を示す断面図である。It is sectional drawing which shows the thermistor element of 2nd Embodiment of this invention.
　以下、本発明を図示の実施の形態により詳細に説明する。 Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
　（第１の実施形態）
　図１は、本発明の第１実施形態のサーミスタ素子１および電子部品を示す斜視図である。図１に示すように、電子部品は、実装基板５０と、実装基板５０に接合されるサーミスタ素子１とを有する。電子部品は、例えば、パソコン、携帯電話、プリンタ、デジカメ、プロジェクタ、ＬＥＤ、カーエレクトロニクスなどの機器に用いられる。 (First embodiment)
FIG. 1 is a perspective view showing a thermistor element 1 and an electronic component according to a first embodiment of the present invention. As shown in FIG. 1, the electronic component includes a mounting substrate 50 and a thermistor element 1 bonded to the mounting substrate 50. Electronic components are used in devices such as personal computers, mobile phones, printers, digital cameras, projectors, LEDs, and car electronics.
　図２は、サーミスタ素子１の断面図である。図１と図２に示すように、サーミスタ素子１は、セラミックスから構成される素体１０と、素体１０の外面の一部を覆う第１、第２外部電極４１，４２とを有する。 FIG. 2 is a sectional view of the thermistor element 1. As shown in FIGS. 1 and 2, the thermistor element 1 includes an element body 10 made of ceramics, and first and second external electrodes 41 and 42 that cover a part of the outer surface of the element body 10.
　素体１０は、例えば、正の抵抗温度特性を有するセラミックスからなる。セラミックスは、例えば、チタン酸バリウム系半導体セラミックスである。つまり、サーミスタ素子１は、ＰＴＣ（Positive Temperature Coefficient）サーミスタであり、キュリー温度で電気抵抗が急上昇するという特性を有する。 The element body 10 is made of, for example, ceramics having a positive resistance temperature characteristic. The ceramic is, for example, a barium titanate semiconductor ceramic. That is, the thermistor element 1 is a PTC (Positive Temperature Coefficient) thermistor and has a characteristic that the electrical resistance rapidly increases at the Curie temperature.
　素体１０は、略直方体状に形成されている。素体１０は、互いに反対側に位置する第１端面１５および第２端面１６と、第１端面１５と第２端面１６との間に配置される第１側面１１から第４側面１４とを有する。第１側面１１と第２側面１２とは、互いに反対側に位置する。第３側面１３と第４側面１４とは、互いに反対側に位置する。 The element body 10 is formed in a substantially rectangular parallelepiped shape. The element body 10 includes a first end surface 15 and a second end surface 16 that are located on opposite sides, and a first side surface 11 to a fourth side surface 14 that are disposed between the first end surface 15 and the second end surface 16. . The first side surface 11 and the second side surface 12 are located on the opposite sides. The third side surface 13 and the fourth side surface 14 are located on the opposite sides.
　第１側面１１の表面粗さと第２側面１２の表面粗さとは、等しく、Ｒａ１である。第３側面１３の表面粗さと第４側面１４の表面粗さとは、等しく、Ｒａ２である。Ｒａ１とＲａ２は、算術平均粗さである。Ｒａ１＜Ｒａ２であり、かつ、０．１μｍ≦Ｒａ１≦０．４μｍであり、かつ、０．４μｍ≦Ｒａ２である。 The surface roughness of the first side surface 11 is equal to the surface roughness of the second side surface 12 and is Ra1. The surface roughness of the third side surface 13 and the surface roughness of the fourth side surface 14 are equal and are Ra2. Ra1 and Ra2 are arithmetic mean roughnesses. Ra1 <Ra2 and 0.1 μm ≦ Ra1 ≦ 0.4 μm and 0.4 μm ≦ Ra2.
　第１、第２外部電極４１，４２は、例えば、Ａｇから構成される。第１、第２外部電極４１，４２は、例えば、スパッタリングによって、形成される。 The first and second external electrodes 41 and 42 are made of Ag, for example. The first and second external electrodes 41 and 42 are formed by sputtering, for example.
　第１外部電極４１は、素体１０の第１端面１５と、素体１０の第１側面１１から第４側面１４の第１端面１５側とを覆う。第１外部電極４１は、素体１０の第１側面１１から第４側面１４に順に対向する第１面１４１から第４面１４４を有する。第１面１４１と第２面１４２とは、互いに反対側に位置する。第３側面１３と第４側面１４とは、互いに反対側に位置する。 The first external electrode 41 covers the first end surface 15 of the element body 10 and the first end surface 15 side of the fourth side surface 14 from the first side surface 11 of the element body 10. The first external electrode 41 has a first surface 141 to a fourth surface 144 that sequentially face the first side surface 11 to the fourth side surface 14 of the element body 10. The first surface 141 and the second surface 142 are located on opposite sides of each other. The third side surface 13 and the fourth side surface 14 are located on the opposite sides.
　第１外部電極４１の第１面１４１から第４面１４４の表面粗さは、素体１０の第１側面１１から第４側面１４の表面粗さに、対応する。つまり、第１側面１１から第４側面１４の表面の粗さは、第１面１４１から第４面１４４の表面に、転写される。 The surface roughness of the first surface 141 to the fourth surface 144 of the first external electrode 41 corresponds to the surface roughness of the first side surface 11 to the fourth side surface 14 of the element body 10. That is, the roughness of the surface from the first side surface 11 to the fourth side surface 14 is transferred from the first surface 141 to the surface of the fourth surface 144.
　第２外部電極４２は、素体１０の第２端面１６と、素体１０の第１側面１１から第４側面１４の第２端面１６側とを覆う。第２外部電極４２は、素体１０の第１側面１１から第４側面１４に順に対向する第１面１４１から第４面１４４を有する。第１面１４１と第２面１４２とは、互いに反対側に位置する。第３側面１３と第４側面１４とは、互いに反対側に位置する。 The second external electrode 42 covers the second end face 16 of the element body 10 and the first end face 11 to the second end face 16 side of the fourth side face 14 of the element body 10. The second external electrode 42 has a first surface 141 to a fourth surface 144 that sequentially face the first side surface 11 to the fourth side surface 14 of the element body 10. The first surface 141 and the second surface 142 are located on opposite sides of each other. The third side surface 13 and the fourth side surface 14 are located on the opposite sides.
　第２外部電極４２の第１面１４１から第４面１４４の表面粗さは、素体１０の第１側面１１から第４側面１４の表面粗さに、対応する。つまり、第１側面１１から第４側面１４の表面の粗さは、第１面１４１から第４面１４４の表面に、転写される。 The surface roughness of the first surface 141 to the fourth surface 144 of the second external electrode 42 corresponds to the surface roughness of the first side surface 11 to the fourth side surface 14 of the element body 10. That is, the roughness of the surface from the first side surface 11 to the fourth side surface 14 is transferred from the first surface 141 to the surface of the fourth surface 144.
　前記実施形態のサーミスタ素子１によれば、第１側面１１の表面粗さと第２側面１２の表面粗さとは、Ｒａ１であり、第３側面１３の表面粗さと第４側面１４の表面粗さとは、Ｒａ２であり、Ｒａ１＜Ｒａ２であり、かつ、０．１μｍ≦Ｒａ１≦０．４μｍであり、かつ、０．４μｍ≦Ｒａ２である。 According to the thermistor element 1 of the embodiment, the surface roughness of the first side surface 11 and the surface roughness of the second side surface 12 are Ra1, and the surface roughness of the third side surface 13 and the surface roughness of the fourth side surface 14 are Ra2, Ra1 <Ra2, 0.1 μm ≦ Ra1 ≦ 0.4 μm, and 0.4 μm ≦ Ra2.
　これにより、第１外部電極４１の第１、第２面１４１，１４２の表面粗さと第２外部電極４２の第１、第２面１４１，１４２の表面粗さとは、Ｒａ１に対応して凹凸が小さくなる。一方、第１外部電極４１の第３、第４面１４３，１４４の表面粗さと第２外部電極４２の第３、第４面１３３，１４４の表面粗さとは、Ｒａ２に対応して凹凸が大きくなる。 Thereby, the surface roughness of the first and second surfaces 141 and 142 of the first external electrode 41 and the surface roughness of the first and second surfaces 141 and 142 of the second external electrode 42 are uneven, corresponding to Ra1. Get smaller. On the other hand, the surface roughness of the third and fourth surfaces 143 and 144 of the first external electrode 41 and the surface roughness of the third and fourth surfaces 133 and 144 of the second external electrode 42 have large irregularities corresponding to Ra2. Become.
　ここで、サーミスタ素子１の第１外部電極４１を実装基板５０の第１ランド部５１に接合し、サーミスタ素子１の第２外部電極４２を実装基板５０の第２ランド部５２に接合するときを考える。つまり、電子部品を組み立てるときを考える。以下、第１外部電極４１と第１ランド部５１との関係について説明する。なお、第２外部電極４２と第２ランド部５２との関係について同様であるため、説明を省略する。 Here, when the first external electrode 41 of the thermistor element 1 is bonded to the first land portion 51 of the mounting substrate 50 and the second external electrode 42 of the thermistor element 1 is bonded to the second land portion 52 of the mounting substrate 50. Think. In other words, consider when assembling electronic components. Hereinafter, the relationship between the first external electrode 41 and the first land portion 51 will be described. Since the relationship between the second external electrode 42 and the second land portion 52 is the same, the description thereof is omitted.
　図３に示すように、第１ランド部５１の表面の面積が、第１外部電極４１の第１、第２面１４１，１４２の面積に比べて、大きい場合、つまり、第１外部電極４１における素体１０の第１端面１５と対向する面に直交する方向からみて、第１ランド部５１の幅Ｓが、第１外部電極４１の第１、第２面１４１，１４２の幅Ｗ１に比べて、大きい場合、第１外部電極４１の第２面１４２を第１ランド部５１の表面に対向させ、第１外部電極４１の第３面１４３と第４面１４４を第１ランド部５１の表面に半田６０を介して接合する。つまり、第１外部電極４１の第２面１４２が、サーミスタ素子１の第１ランド部５１への対向面となる。 As shown in FIG. 3, when the surface area of the first land portion 51 is larger than the areas of the first and second surfaces 141 and 142 of the first external electrode 41, that is, in the first external electrode 41. The width S of the first land portion 51 is larger than the width W1 of the first and second surfaces 141 and 142 of the first external electrode 41 when viewed from the direction orthogonal to the surface facing the first end surface 15 of the element body 10. If large, the second surface 142 of the first external electrode 41 is opposed to the surface of the first land portion 51, and the third surface 143 and the fourth surface 144 of the first external electrode 41 are disposed on the surface of the first land portion 51. It joins via the solder 60. That is, the second surface 142 of the first external electrode 41 is a surface facing the first land portion 51 of the thermistor element 1.
　このとき、０．１μｍ≦Ｒａ１≦０．４μｍであるため、第１外部電極４１の第１、第２面１４１，１４２は、略平坦となり、第１外部電極４１の第１ランド部５１に対向する第２面１４２の全体が、第１ランド部５１の表面に近づくことができる。これにより、第１外部電極４１と第１ランド部５１（実装基板５０）との熱伝導性が、向上する。これに対して、Ｒａ１が０．４μｍよりも大きいと、第２面１４２の凹凸が大きくなり、第２面１４２の一部（凹部）は、第１ランド部５１の表面から遠くなる。この結果、第１外部電極４１と第１ランド部５１との熱伝導性が、低下する。 At this time, since 0.1 μm ≦ Ra1 ≦ 0.4 μm, the first and second surfaces 141 and 142 of the first external electrode 41 are substantially flat and face the first land portion 51 of the first external electrode 41. The entire second surface 142 can approach the surface of the first land portion 51. Thereby, the thermal conductivity between the first external electrode 41 and the first land portion 51 (mounting substrate 50) is improved. On the other hand, when Ra1 is larger than 0.4 μm, the unevenness of the second surface 142 becomes large, and a part (concave portion) of the second surface 142 is far from the surface of the first land portion 51. As a result, the thermal conductivity between the first external electrode 41 and the first land portion 51 is lowered.
　また、実装基板５０からの熱伝導性が良くなるので、サーミスタ素子１を過熱検知素子としたとき、過熱検知素子の温度に対するレスポンスが良くなる。また、実装基板５０への熱放散性が良くなるので、サーミスタ素子１を過電流保護素子としたとき、過電流保護素子に多くの電流を流すことができ、過電流保護素子の耐電圧レベルが向上する。 In addition, since the thermal conductivity from the mounting substrate 50 is improved, when the thermistor element 1 is an overheat detection element, the response to the temperature of the overheat detection element is improved. In addition, since the heat dissipation to the mounting substrate 50 is improved, when the thermistor element 1 is an overcurrent protection element, a large amount of current can flow through the overcurrent protection element, and the withstand voltage level of the overcurrent protection element is high. improves.
　また、第１外部電極４１の上面となる第１面１４１が略平坦になることで、結露時に、第１面１４１に水分が残留することを抑制し、ＡｇやＳｎマイグレーションの危険性が低下する。 In addition, since the first surface 141 that is the upper surface of the first external electrode 41 is substantially flat, it is possible to prevent moisture from remaining on the first surface 141 at the time of dew condensation and to reduce the risk of Ag and Sn migration. .
　また、Ｒａ１の下限値を０．１μｍとしているため、サーミスタ素子１の実装基板５０への実装不良（ツームストン）の影響を抑制できる。これに対して、Ｒａ１が０．１μｍよりも小さいと、サーミスタ素子１の実装不良が発生するおそれがある。この原因として、第１外部電極４１の第２面１４２と第１ランド部５１の表面との間に存在する半田６０により、第１外部電極４１に、浮力が働き反発力が発生して、サーミスタ素子１にツームストンが発生すると考えられる。 In addition, since the lower limit value of Ra1 is set to 0.1 μm, it is possible to suppress the influence of mounting failure (tombstone) of the thermistor element 1 on the mounting substrate 50. On the other hand, if Ra1 is smaller than 0.1 μm, the thermistor element 1 may be mounted poorly. The cause of this is that the solder 60 existing between the second surface 142 of the first external electrode 41 and the surface of the first land portion 51 causes a buoyancy and a repulsive force is generated in the first external electrode 41. It is considered that a tombstone is generated in the element 1.
　一方、０．４μｍ≦Ｒａ２であるため、第１外部電極４１の第３、第４面１４３，１４４は、粗くなり、第１外部電極４１の第３、第４面１４３，１４４では、半田６０の濡れ性が、良好となる。これにより、第３、第４面１４３，１４４と第１ランド部５１の表面とが、半田６０により、強固に接合され、第１外部電極４１の第１ランド部５１への実装が、良好となる。これに対して、Ｒａ２が０．４μｍよりも小さいと、第３、第４面１４３，１４４の凹凸が小さくなり、第３、第４面１４３，１４４の半田６０の濡れ性が低下して、この結果、第１外部電極４１の第１ランド部５１への実装が不良となる。 On the other hand, since 0.4 μm ≦ Ra2, the third and fourth surfaces 143 and 144 of the first external electrode 41 become rough, and the third and fourth surfaces 143 and 144 of the first external electrode 41 have solder 60. The wettability of is improved. As a result, the third and fourth surfaces 143 and 144 and the surface of the first land portion 51 are firmly joined by the solder 60, and the first external electrode 41 can be mounted on the first land portion 51 well. Become. On the other hand, when Ra2 is smaller than 0.4 μm, the unevenness of the third and fourth surfaces 143 and 144 is reduced, and the wettability of the solder 60 on the third and fourth surfaces 143 and 144 is reduced. As a result, the mounting of the first external electrode 41 on the first land portion 51 becomes defective.
　また、第１外部電極４１の第３、第４面１４３，１４４の半田６０の濡れ性が良好となるので、第３、第４面１４３，１４４に対する半田６０の接触面積が増加して、サーミスタ素子１から実装基板５０への熱放散性が良くなる。これにより、サーミスタ素子１を過電流保護素子としたとき、過電流保護素子に多くの電流を流すことができ、過電流保護素子の耐電圧レベルが向上する。 Further, since the wettability of the solder 60 on the third and fourth surfaces 143 and 144 of the first external electrode 41 is improved, the contact area of the solder 60 with respect to the third and fourth surfaces 143 and 144 is increased, and the thermistor is increased. The heat dissipation from the element 1 to the mounting substrate 50 is improved. Thereby, when the thermistor element 1 is an overcurrent protection element, a large amount of current can flow through the overcurrent protection element, and the withstand voltage level of the overcurrent protection element is improved.
　なお、第１外部電極４１の第２面１４２を第１ランド部５１の表面に対向させたが、第１面１４１と第２面１４２とが、同じ表面粗さを有するため、第１外部電極４１の第１面１４１を第１ランド部５１の表面に対向させるようにしてもよい。このように、本発明では、第１面１４１と第２面１４２とが逆になっても問題とならない構造としており、余計な整列作業を必要としていない。 The second surface 142 of the first external electrode 41 is opposed to the surface of the first land portion 51. However, since the first surface 141 and the second surface 142 have the same surface roughness, the first external electrode The first surface 141 of 41 may be opposed to the surface of the first land portion 51. As described above, in the present invention, the first surface 141 and the second surface 142 do not cause a problem even if the first surface 141 and the second surface 142 are reversed, and no extra alignment work is required.
　一方、図４に示すように、第１ランド部５１の表面の面積が、第１外部電極４１の第１、第２面１４２の面積に比べて、小さい場合、つまり、第１外部電極４１における素体１０の第１端面１５と対向する面に直交する方向からみて、第１ランド部５１の幅Ｓが、第１外部電極４１の第１、第２面１４１，１４２の幅Ｗ１に比べて、小さい場合、第１外部電極４１の第３面１４３を、第１ランド部５１の表面に対向させ、第１ランド部５１の表面に半田６０を介して接合する。つまり、第１外部電極４１の第３面１４３が、サーミスタ素子１の第１ランド部５１への対向面となる。 On the other hand, as shown in FIG. 4, when the area of the surface of the first land portion 51 is smaller than the areas of the first and second surfaces 142 of the first external electrode 41, that is, in the first external electrode 41. The width S of the first land portion 51 is larger than the width W1 of the first and second surfaces 141 and 142 of the first external electrode 41 when viewed from the direction orthogonal to the surface facing the first end surface 15 of the element body 10. In the case of being small, the third surface 143 of the first external electrode 41 is opposed to the surface of the first land portion 51 and joined to the surface of the first land portion 51 via the solder 60. That is, the third surface 143 of the first external electrode 41 is a surface facing the first land portion 51 of the thermistor element 1.
　なお、第２面１４２を第１ランド部５１へ対向させると、第１ランド部５１の表面が、第２面１４２に覆われることになり、第１ランド部５１の表面には、第３、第４面１４３，１４４を接合する領域が存在しない。このため、第１外部電極４１を第１ランド部５１に接合することができない。また、第３、第４面１４３，１４４の幅Ｗ２が、第１ランド部５１の幅Ｓに比べて、大きくても小さくても、第３面１４３を第１ランド部５１に半田６０を介して接合することができる。 When the second surface 142 is opposed to the first land portion 51, the surface of the first land portion 51 is covered with the second surface 142, and the surface of the first land portion 51 has third, There is no region for joining the fourth surfaces 143 and 144. For this reason, the first external electrode 41 cannot be bonded to the first land portion 51. The third surface 143 is connected to the first land portion 51 via the solder 60 regardless of whether the width W2 of the third and fourth surfaces 143 and 144 is larger or smaller than the width S of the first land portion 51. Can be joined together.
　このとき、０．４μｍ≦Ｒａ２であるため、第１外部電極４１の第３、第４面１４３，１４４は、粗くなり、第１外部電極４１の第３、第４面１４３，１４４では、半田６０の濡れ性が、良好となる。これにより、第３面１４３と第１ランド部５１の表面とが、半田６０により、強固に接合され、第１外部電極４１の第１ランド部５１への実装が、良好となる。これに対して、Ｒａ２が０．４μｍよりも小さいと、第３面１４３の凹凸が小さくなり、第３面１４３の半田６０の濡れ性が低下して、この結果、第１外部電極４１の第１ランド部５１への実装が不良となる。 At this time, since 0.4 μm ≦ Ra2, the third and fourth surfaces 143 and 144 of the first external electrode 41 are rough, and the third and fourth surfaces 143 and 144 of the first external electrode 41 are soldered. A wettability of 60 is good. As a result, the third surface 143 and the surface of the first land portion 51 are firmly joined by the solder 60, and the mounting of the first external electrode 41 on the first land portion 51 is improved. On the other hand, when Ra2 is smaller than 0.4 μm, the unevenness of the third surface 143 is reduced, and the wettability of the solder 60 on the third surface 143 is lowered. As a result, the first outer electrode 41 of the first external electrode 41 is reduced. Mounting on one land portion 51 becomes defective.
　なお、第１外部電極４１の第３面１４３を第１ランド部５１の表面に対向させたが、第３面１４３と第４面１４４とが、同じ表面粗さを有するため、第１外部電極４１の第４面１４４を第１ランド部５１の表面に対向させるようにしてもよい。このように、本発明では、第３面１４３と第４面１４４とが逆になっても問題とならない構造としており、余計な整列作業を必要としていない。 In addition, although the 3rd surface 143 of the 1st external electrode 41 was made to oppose the surface of the 1st land part 51, since the 3rd surface 143 and the 4th surface 144 have the same surface roughness, the 1st external electrode The fourth surface 144 of 41 may be opposed to the surface of the first land portion 51. Thus, in the present invention, the third surface 143 and the fourth surface 144 have a structure that does not cause a problem even if the third surface 143 and the fourth surface 144 are reversed, and no extra alignment work is required.
　したがって、実装基板５０の第１、第２ランド部５１，５２の大きさに応じて、サーミスタ素子１の第１、第２ランド部５１，５２に対向する対向面を変更することで、サーミスタ素子１を実装基板５０に良好に実装できる。 Therefore, the thermistor element is changed by changing the facing surfaces of the thermistor element 1 facing the first and second land parts 51 and 52 according to the sizes of the first and second land parts 51 and 52 of the mounting substrate 50. 1 can be satisfactorily mounted on the mounting substrate 50.
　第１、第２ランド部５１，５２の標準サイズは、おおよそ、第１、第２外部電極４１，４２の外面１４１～１４４よりも、大きい。このため、図３に示すように、第１外部電極４１の第２面１４２を、サーミスタ素子１の第１ランド部５１に対向させるように、サーミスタ素子１を実装基板５０に実装する。ところが、近年、スマートフォンなど電子機器の小型化が進んでいる。このような電子機器において、電子部品を実装基板に密に搭載する必要があるため、ランド部のサイズを小さくしている。このように、ランド部のサイズが小さいと、図４に示すように、第１外部電極４１の第３面１４３を、サーミスタ素子１の第１ランド部５１に対向させるように、サーミスタ素子１を実装基板５０に実装する。したがって、第１、第２ランド部５１，５２の大きさに関わらず、サーミスタ素子１を実装基板５０に良好に実装できる。 The standard size of the first and second land portions 51 and 52 is approximately larger than the outer surfaces 141 to 144 of the first and second external electrodes 41 and 42. Therefore, as shown in FIG. 3, the thermistor element 1 is mounted on the mounting substrate 50 so that the second surface 142 of the first external electrode 41 faces the first land portion 51 of the thermistor element 1. However, in recent years, electronic devices such as smartphones have been downsized. In such an electronic device, since it is necessary to densely mount electronic components on the mounting substrate, the size of the land portion is reduced. As described above, when the size of the land portion is small, the thermistor element 1 is arranged so that the third surface 143 of the first external electrode 41 faces the first land portion 51 of the thermistor element 1 as shown in FIG. Mounted on the mounting substrate 50. Therefore, the thermistor element 1 can be satisfactorily mounted on the mounting substrate 50 regardless of the size of the first and second land portions 51 and 52.
　好ましくは、Ｒａ２≦２．０μｍであり、さらに好ましくは、Ｒａ２≦０．８μｍである。これにより、素体１０の第３、第４側面１３，１４の表面粗さは、大きくなりすぎず、サーミスタ素子１の外観不良を選別する際に、外観不良と判定されない。 Preferably, Ra2 ≦ 2.0 μm, and more preferably Ra2 ≦ 0.8 μm. Thereby, the surface roughness of the third and fourth side surfaces 13 and 14 of the element body 10 does not become too large, and is not determined to be an appearance defect when the appearance defect of the thermistor element 1 is selected.
　好ましくは、サーミスタ素子１のサイズは、ＪＩＳ規格０６０３サイズである。ここで、ＪＩＳ規格０６０３サイズとは、長さ（０．６±０．０３）ｍｍ×幅（０．３±０．０３）ｍｍであり、例えば、長さ０．６ｍｍ×幅０．３ｍｍ×厚み０．３ｍｍである。これにより、サーミスタ素子１のサイズが小さくなるが、本発明のサーミスタ素子１では、第１、第２外部電極４１，４２の第１、第２ランド部５１，５２への実装が顕著に良好となって、ツームストン等の実装不良の問題がない。 Preferably, the size of the thermistor element 1 is JIS standard 0603 size. Here, the JIS standard 0603 size is length (0.6 ± 0.03) mm × width (0.3 ± 0.03) mm, for example, length 0.6 mm × width 0.3 mm × The thickness is 0.3 mm. As a result, the size of the thermistor element 1 is reduced. However, in the thermistor element 1 of the present invention, the first and second external electrodes 41 and 42 are mounted on the first and second land portions 51 and 52 to be remarkably good. Therefore, there is no problem of mounting defects such as Tombstone.
　上述のように組み立てられた電子部品では、図３に示すように、第１ランド部５１の表面の面積が、第１外部電極４１の第１、第２面１４１，１４２の面積に比べて、大きく、第２ランド部５２の表面の面積が、第２外部電極４２の第１、第２面１４１，１４２の面積に比べて、大きい状態では、第１外部電極４１の第１面１４１または第２面１４２が第１ランド部５１の表面に対向し、第１外部電極４１の第３面１４３と第４面１４４が第１ランド部５１の表面に半田６０を介して接合されると共に、第２外部電極４２の第１面１４１または第２面１４２が第２ランド部５２の表面に対向し、第２外部電極４２の第３面１４３と第４面１４４が第２ランド部５２の表面に半田６０を介して接合される。 In the electronic component assembled as described above, the area of the surface of the first land portion 51 is larger than the areas of the first and second surfaces 141 and 142 of the first external electrode 41, as shown in FIG. In a state where the surface area of the second land portion 52 is larger than the areas of the first and second surfaces 141 and 142 of the second external electrode 42, the first land 141 or the first surface of the first external electrode 41 is large. The second surface 142 faces the surface of the first land portion 51, the third surface 143 and the fourth surface 144 of the first external electrode 41 are joined to the surface of the first land portion 51 via the solder 60, and 2 The first surface 141 or the second surface 142 of the external electrode 42 faces the surface of the second land portion 52, and the third surface 143 and the fourth surface 144 of the second external electrode 42 are on the surface of the second land portion 52. Bonding is performed via solder 60.
　一方、図４に示すように、第１ランド部５１の表面の面積が、第１外部電極４１の第１、第２面１４１，１４２の面積に比べて、小さく、第２ランド部５２の表面の面積が、第２外部電極４２の第１、第２面１４１，１４２の面積に比べて、小さい状態では、第１外部電極４１の第３面１４３または第４面１４４が、第１ランド部５１の表面に対向しつつ第１ランド部５１の表面に半田６０を介して接合されると共に、第２外部電極４２の第３面１４３または第４面１４４が、第２ランド部５２の表面に対向しつつ第２ランド部５２の表面に半田６０を介して接合される。 On the other hand, as shown in FIG. 4, the area of the surface of the first land portion 51 is smaller than the areas of the first and second surfaces 141 and 142 of the first external electrode 41, and the surface of the second land portion 52. Is smaller than the areas of the first and second surfaces 141 and 142 of the second external electrode 42, the third surface 143 or the fourth surface 144 of the first external electrode 41 has the first land portion. The third surface 143 or the fourth surface 144 of the second external electrode 42 is joined to the surface of the second land portion 52 while being bonded to the surface of the first land portion 51 via the solder 60 while facing the surface of the first land portion 51. It is joined to the surface of the second land portion 52 via the solder 60 while facing each other.
　したがって、上述の電子部品では、サーミスタ素子１が実装基板５０に良好に実装されているので、電子部品の品質が向上する。 Therefore, in the above-described electronic component, since the thermistor element 1 is well mounted on the mounting substrate 50, the quality of the electronic component is improved.
　（実施例１）
　次に、サーミスタ素子１の実施例１について説明する。 (Example 1)
Next, Example 1 of the thermistor element 1 will be described.
　サーミスタ素子１として、ＪＩＳ規格０６０３サイズ（０．６ｍｍ×０．３ｍｍ×０．３ｍｍ）のチップ型ＰＴＣサーミスタを準備した。チップ型ＰＴＣサーミスタは、ＢａＴｉＯ３を主成分としたセラミックスＰＴＣサーミスタで、キュリー温度は、１００℃であり、室温抵抗値（２５℃）は、２．２ｋΩ（比抵抗は３４Ω・ｃｍ）である。 As the thermistor element 1, a chip type PTC thermistor of JIS standard 0603 size (0.6 mm × 0.3 mm × 0.3 mm) was prepared. The chip-type PTC thermistor is a ceramic PTC thermistor mainly composed of BaTiO 3 , and has a Curie temperature of 100 ° C. and a room temperature resistance value (25 ° C.) of 2.2 kΩ (specific resistance is 34 Ω · cm).
　第１、第２外部電極４１，４２の寸法は、０．１５ｍｍである。第１、第２外部電極４１，４２は、素体１０の表面に、Ｎｉ／Ｓｎめっき（表層はＳｎ１００％，非光沢めっき，めっき厚：３μｍ）を施すことにより、形成した。素体１０には、特に前処理（スチームエージングなど）を実施していない。 The dimensions of the first and second external electrodes 41 and 42 are 0.15 mm. The first and second external electrodes 41 and 42 were formed by applying Ni / Sn plating (surface layer is Sn 100%, matte plating, plating thickness: 3 μm) on the surface of the element body 10. The element body 10 is not particularly subjected to pretreatment (such as steam aging).
　複数のサーミスタ素子１において、素体１０の第３、第４側面１３，１４の表面粗さＲａ２を０．２μｍに固定し、素体１０の第１、第２側面１１，１２の表面粗さＲａ１を、バレル研磨やサンドブラストにより、変化させた。Ｒａ１を変えたサーミスタ素子１のサンプルを各１０，０００個準備し、マウンターでの基板搭載の実験を実施した。つまり、図１と図３に示すように、第１、第２外部電極４１，４２の第２面１４２を、第１、第２ランド部５１，５２に対向させて、第１、第２外部電極４１，４２の第３、第４面１４３，１４４を、第１、第２ランド部５１，５２に半田６０により接合した。 In the plurality of thermistor elements 1, the surface roughness Ra2 of the third and fourth side surfaces 13 and 14 of the element body 10 is fixed to 0.2 μm, and the surface roughness of the first and second side surfaces 11 and 12 of the element body 10 is fixed. Ra1 was changed by barrel polishing or sandblasting. 10,000 samples of the thermistor element 1 with different Ra1 were prepared, and an experiment for mounting the substrate on the mounter was conducted. That is, as shown in FIGS. 1 and 3, the first and second external electrodes 41 and 42 are opposed to the first and second land portions 51 and 52 so that the second surfaces 142 of the first and second external electrodes 41 and 42 are opposed to each other. The third and fourth surfaces 143 and 144 of the electrodes 41 and 42 are joined to the first and second land portions 51 and 52 by solder 60.
　このマウンター搭載実験の結果を表１に示す。表１では、Ｒａ１を変化させたときの不具合発生の個数を示す。 The results of this mounter mounting experiment are shown in Table 1. Table 1 shows the number of failures when Ra1 is changed.
Figure JPOXMLDOC01-appb-T000001
 　表１に示すように、実装不良が５個以下（認識成功率：９９．９５％以上）を合格とした場合、Ｒａ１が０．１μｍ以上であるときに、実装が合格となる。表１では、合格となったものを「ＯＫ」と示している。
Figure JPOXMLDOC01-appb-T000001
 As shown in Table 1, when the mounting failure is 5 or less (recognition success rate: 99.95% or more), the mounting is passed when Ra1 is 0.1 μm or more. In Table 1, what passed is shown as “OK”.
　次に、Ｒａ１を０．１μｍ～０．８μｍで変化させ、Ｒａ２を０．１μｍ～０．８μｍで変化させた素子を準備した。これらの素子をリフロー実装し、実装評価後の素子強度を確認した。なお、この時に実装評価で使用したランド部の寸法は、０．３ｍｍ×０．３ｍｍである。半田ペーストは、千住金属製Ｍ７０５－ＧＲＮ３６０－Ｋ２－Ｖを用い、半田の塗布厚は、８０μｍとした。 Next, an element was prepared in which Ra1 was changed from 0.1 μm to 0.8 μm and Ra2 was changed from 0.1 μm to 0.8 μm. These elements were reflow mounted and the element strength after mounting evaluation was confirmed. At this time, the size of the land used in the mounting evaluation is 0.3 mm × 0.3 mm. As the solder paste, M705-GRN360-K2-V made by Senju Metal Co., Ltd. was used, and the solder coating thickness was 80 μm.
　この強度の試験結果を表２に示す。表２では、各条件で測定数を５０個とし、各条件で強度［Ｎ］の最小値を示す。 Table 2 shows the test results for this strength. In Table 2, the number of measurements is 50 under each condition, and the minimum value of intensity [N] is shown under each condition.
Figure JPOXMLDOC01-appb-T000002
 　表２に示すように、強度の目標値を２．０Ｎ以上とした場合、以下の条件が必要であることが分かった。表２では、強度の目標値をクリアしたものを「ＯＫ」と示している。条件としては、Ｒａ１＜Ｒａ２であり、かつ、Ｒａ１は、０．１μｍ～０．４μｍであり、かつ、Ｒａ２は、０．４μｍ～０．８μｍである。
Figure JPOXMLDOC01-appb-T000002
 As shown in Table 2, it was found that the following conditions were necessary when the target strength value was 2.0 N or more. In Table 2, “OK” indicates that the target value of the strength is cleared. The conditions are Ra1 <Ra2, Ra1 is 0.1 μm to 0.4 μm, and Ra2 is 0.4 μm to 0.8 μm.
　したがって、表１と表２に示すように、以下の条件を満たすことで、実装不良が無く、かつ、実装強度の高いチップ型ＰＴＣサーミスタを得ることができる。条件としては、Ｒａ１＜Ｒａ２であり、かつ、Ｒａ１は、０．１μｍ～０．４μｍであり、かつ、Ｒａ２は、０．４μｍ～０．８μｍである。 Therefore, as shown in Tables 1 and 2, by satisfying the following conditions, a chip type PTC thermistor having no mounting failure and high mounting strength can be obtained. The conditions are Ra1 <Ra2, Ra1 is 0.1 μm to 0.4 μm, and Ra2 is 0.4 μm to 0.8 μm.
　（実施例２）
　次に、サーミスタ素子１の実施例２について説明する。 (Example 2)
Next, Example 2 of the thermistor element 1 will be described.
　サーミスタ素子１として、ＪＩＳ規格０６０３サイズ（０．６ｍｍ×０．３ｍｍ×０．３ｍｍ）のチップ型ＰＴＣサーミスタを準備した。チップ型ＰＴＣサーミスタは、ＢａＴｉＯ３を主成分としたセラミックスＰＴＣサーミスタで、キュリー温度は、１２０℃であり、室温抵抗値（２５℃）は、４７０Ω（比抵抗は７．７Ω・ｃｍ）である。 As the thermistor element 1, a chip type PTC thermistor of JIS standard 0603 size (0.6 mm × 0.3 mm × 0.3 mm) was prepared. The chip-type PTC thermistor is a ceramic PTC thermistor mainly composed of BaTiO 3 , and has a Curie temperature of 120 ° C. and a room temperature resistance value (25 ° C.) of 470Ω (specific resistance is 7.7Ω · cm).
　第１、第２外部電極４１，４２の寸法は、０．１５ｍｍである。第１、第２外部電極４１，４２は、素体１０の表面に、Ｎｉ／Ｓｎめっき（表層はＳｎ１００％，非光沢めっき，めっき厚：３μｍ）を施すことにより、形成した。素体１０には、特に前処理（スチームエージングなど）を実施していない。 The dimensions of the first and second external electrodes 41 and 42 are 0.15 mm. The first and second external electrodes 41 and 42 were formed by applying Ni / Sn plating (surface layer is Sn 100%, matte plating, plating thickness: 3 μm) on the surface of the element body 10. The element body 10 is not particularly subjected to pretreatment (such as steam aging).
　そして、Ｒａ１を０．１μｍ～０．８μｍで変化させ、Ｒａ２を０．１μｍ～０．８μｍで変化させた素子を準備した。これらの素子をリフロー実装し、実装評価後の耐電圧を確認した。つまり、図１と図３に示すように、第１、第２外部電極４１，４２の第２面１４２を、第１、第２ランド部５１，５２に対向させて、第１、第２外部電極４１，４２の第３、第４面１４３，１４４を、第１、第２ランド部５１，５２に半田６０により接合した。なお、この時に実装評価で使用したランド部の寸法は、０．３ｍｍ×０．３ｍｍである。半田ペーストは、千住金属製Ｍ７０５－ＧＲＮ３６０－Ｋ２－Ｖを用い、半田の塗布厚は、８０μｍとした。 Then, an element was prepared in which Ra1 was changed from 0.1 μm to 0.8 μm and Ra2 was changed from 0.1 μm to 0.8 μm. These devices were reflow mounted, and the withstand voltage after mounting evaluation was confirmed. That is, as shown in FIGS. 1 and 3, the first and second external electrodes 41 and 42 are opposed to the first and second land portions 51 and 52 so that the second surfaces 142 of the first and second external electrodes 41 and 42 are opposed to each other. The third and fourth surfaces 143 and 144 of the electrodes 41 and 42 are joined to the first and second land portions 51 and 52 by solder 60. At this time, the size of the land used in the mounting evaluation is 0.3 mm × 0.3 mm. As the solder paste, M705-GRN360-K2-V made by Senju Metal Co., Ltd. was used, and the solder coating thickness was 80 μm.
　この耐電圧の試験結果を表３に示す。表３では、各条件で測定数を５０個とし、各条件で製品が耐えた電圧［Ｖ］の最小値を示す。 Table 3 shows the withstand voltage test results. Table 3 shows the minimum value of the voltage [V] that the product withstood under each condition with the number of measurements being 50 under each condition.
Figure JPOXMLDOC01-appb-T000003
 　表３に示すように、耐電圧の目標値を３２Ｖ以上とした場合、以下の条件が必要であることが分かった。表３では、耐電圧の目標値をクリアしたものを「ＯＫ」と示している。条件としては、Ｒａ１＜Ｒａ２であり、かつ、Ｒａ１は、０．１μｍ～０．４μｍであり、かつ、Ｒａ２は、０．４μｍ～０．８μｍである。
Figure JPOXMLDOC01-appb-T000003
 As shown in Table 3, it was found that the following conditions were necessary when the withstand voltage target value was set to 32 V or more. In Table 3, “OK” indicates that the target value of withstand voltage has been cleared. The conditions are Ra1 <Ra2, Ra1 is 0.1 μm to 0.4 μm, and Ra2 is 0.4 μm to 0.8 μm.
　（第２の実施形態）
　図５は、本発明の第２実施形態のサーミスタ素子を示す断面図である。第２実施形態は、前記第１実施形態とは、内部電極の構成のみが相違する。この相違する構成のみを以下に説明する。なお、第２実施形態において、第１実施形態と同一の符号は、第１実施形態と同じ構成であるため、その説明を省略する。 (Second Embodiment)
FIG. 5 is a sectional view showing a thermistor element according to the second embodiment of the present invention. The second embodiment is different from the first embodiment only in the configuration of the internal electrodes. Only this different configuration will be described below. Note that in the second embodiment, the same reference numerals as those in the first embodiment have the same configurations as those in the first embodiment, and a description thereof will be omitted.
　図５に示すように、サーミスタ素子１Ａは、素体１０内に設けられ素体１０の外面から端部２１ａ，２２ａが露出する内部電極２１，２２を有する。外部電極４１，４２は、内部電極２１，２２の端部２１ａ，２２ａに電気的に接続される。 As shown in FIG. 5, the thermistor element 1 </ b> A includes internal electrodes 21 and 22 that are provided in the element body 10 and end portions 21 a and 22 a are exposed from the outer surface of the element body 10. The external electrodes 41 and 42 are electrically connected to the end portions 21 a and 22 a of the internal electrodes 21 and 22.
　前記内部電極２１，２２は、略平板状に形成されている。内部電極２１，２２は、例えば、Ｎｉ、Ｃｕ、Ｆｅ、Ｃｏ、Ｗ、Ｔａ、Ｔｉ、Ｍｏのうちの少なくとも一つの元素を含んでいる。 The internal electrodes 21 and 22 are formed in a substantially flat plate shape. The internal electrodes 21 and 22 include, for example, at least one element of Ni, Cu, Fe, Co, W, Ta, Ti, and Mo.
　前記複数の内部電極２１，２２は、互いに間隔をあけて、略平行に配列されている。隣り合う２つの内部電極２１，２２において、第１内部電極２１の端部２１ａは、素体１０の第１端面１５から露出し、第２内部電極２２の端部２２ａは、素体１０の第２端面１６から露出している。 The plurality of internal electrodes 21 and 22 are arranged substantially in parallel with a space therebetween. In two adjacent internal electrodes 21 and 22, the end 21 a of the first internal electrode 21 is exposed from the first end surface 15 of the element body 10, and the end 22 a of the second internal electrode 22 is exposed to the first end of the element body 10. The two end faces 16 are exposed.
　前記第１外部電極４１は、第１内部電極２１の端部２１ａに接触して電気的に接続される。前記第２外部電極４２は、第２内部電極２２の端部２２ａに接触して電気的に接続される。 The first external electrode 41 is in contact with and electrically connected to the end 21a of the first internal electrode 21. The second external electrode 42 is in contact with and electrically connected to the end 22 a of the second internal electrode 22.
　前記素体１０の第１、第２側面１１，１２は、複数の内部電極２１，２２の積層方向に位置する。前記第１実施形態と同じように、第１側面１１の表面粗さと第２側面１２の表面粗さとは、Ｒａ１であり、第３側面１３の表面粗さと第４側面１４の表面粗さとは、Ｒａ２であり、Ｒａ１＜Ｒａ２であり、かつ、０．１μｍ≦Ｒａ１≦０．４μｍであり、かつ、０．４μｍ≦Ｒａ２である。したがって、第２実施形態のサーミスタ素子１Ａでは、第１実施形態と同じように、外部電極４１，４２のランド部への実装が良好となる。 The first and second side surfaces 11 and 12 of the element body 10 are positioned in the stacking direction of the plurality of internal electrodes 21 and 22. As in the first embodiment, the surface roughness of the first side surface 11 and the surface roughness of the second side surface 12 are Ra1, and the surface roughness of the third side surface 13 and the surface roughness of the fourth side surface 14 are Ra2, Ra1 <Ra2, 0.1 μm ≦ Ra1 ≦ 0.4 μm, and 0.4 μm ≦ Ra2. Therefore, in the thermistor element 1A of the second embodiment, the mounting of the external electrodes 41 and 42 on the land portion is good as in the first embodiment.
　なお、本発明は上述の実施形態に限定されず、本発明の要旨を逸脱しない範囲で設計変更可能である。 It should be noted that the present invention is not limited to the above-described embodiment, and the design can be changed without departing from the gist of the present invention.
　前期実施形態では、サーミスタ素子は、ＰＴＣ（Positive Temperature Coefficient）サーミスタとしたが、負の抵抗温度特性を有するセラミックスからなるＮＴＣ（Negative Temperature Coefficient）サーミスタとしてもよい。このとき、サーミスタ素子は、内部電極を含んでいてもよく、または、内部電極を含んでいなくてもよい。 In the previous embodiment, the thermistor element is a PTC (Positive Temperature Coefficient) thermistor, but may be an NTC (Negative Temperature Temperature Coefficient) thermistor made of ceramics having negative resistance temperature characteristics. At this time, the thermistor element may include an internal electrode or may not include an internal electrode.
　１，１Ａ　サーミスタ素子
　１０　素体
　１１　第１側面
　１２　第２側面
　１３　第３側面
　１４　第４側面
　１５　第１端面
　１６　第２端面
　１７　周面
　２１　第１内部電極
　２１ａ　端部
　２２　第２内部電極
　２２ａ　端部
　４１　第１外部電極
　４２　第２外部電極
　５０　実装基板
　５１　第１ランド部
　５２　第２ランド部
　６０　半田
　１４１　第１面
　１４２　第２面
　１４３　第３面
　１４４　第４面
　Ｓ　第１、第２ランド部の幅
　Ｗ１　第１、第２面の幅
　Ｗ２　第３、第４面の幅 DESCRIPTION OF SYMBOLS 1,1A Thermistor element 10 Element body 11 1st side surface 12 2nd side surface 13 3rd side surface 14 4th side surface 15 1st end surface 16 2nd end surface 17 Peripheral surface 21 1st internal electrode 21a End part 22 2nd internal electrode 22a end Part 41 First external electrode 42 Second external electrode 50 Mounting substrate 51 First land part 52 Second land part 60 Solder 141 First surface 142 Second surface 143 Third surface 144 Fourth surface S First and second land portions Width W1 width of the first and second surfaces W2 width of the third and fourth surfaces

Claims (5)

  1. 　互いに反対側に位置する第１端面および第２端面と、前記第１端面と前記第２端面との間に配置される第１側面から第４側面とを有すると共に、セラミックスから構成される素体と、
    　前記素体の前記第１端面と、前記素体の前記第１側面から前記第４側面の前記第１端面側とを覆うと共に、前記素体の前記第１側面から前記第４側面に対向する第１面から第４面を有する第１外部電極と、
    　前記素体の前記第２端面と、前記素体の前記第１側面から前記第４側面の前記第２端面側とを覆うと共に、前記素体の前記第１側面から前記第４側面に対向する第１面から第４面を有する第２外部電極と
    を備え、
    　前記第１側面と前記第２側面とは、互いに反対側に位置し、前記第１側面の表面粗さと前記第２側面の表面粗さとは、等しく、Ｒａ１であり、
    　前記第３側面と前記第４側面とは、互いに反対側に位置し、前記第３側面の表面粗さと前記第４側面の表面粗さとは、等しく、Ｒａ２であり、
    　Ｒａ１＜Ｒａ２であり、かつ、
    　０．１μｍ≦Ｒａ１≦０．４μｍであり、かつ、
    　０．４μｍ≦Ｒａ２であることを特徴とするサーミスタ素子。     An element body including first and second end surfaces located on opposite sides, first to fourth side surfaces disposed between the first end surface and the second end surface, and made of ceramics. When,
    Covering the first end surface of the element body and the first end surface side of the fourth side surface from the first side surface of the element body, and facing the fourth side surface from the first side surface of the element body. A first external electrode having a first surface to a fourth surface;
    Covering the second end surface of the element body and the second end surface side of the fourth side surface from the first side surface of the element body, and facing the fourth side surface from the first side surface of the element body. A second external electrode having a first surface to a fourth surface;
    The first side surface and the second side surface are located on opposite sides, and the surface roughness of the first side surface and the surface roughness of the second side surface are equal, and Ra1.
    The third side surface and the fourth side surface are located on opposite sides, and the surface roughness of the third side surface and the surface roughness of the fourth side surface are equal, and Ra2.
    Ra1 <Ra2 and
    0.1 μm ≦ Ra1 ≦ 0.4 μm, and
    A thermistor element, wherein 0.4 μm ≦ Ra2.
  2. 　請求項１に記載のサーミスタ素子において、
    　Ｒａ２≦０．８μｍであることを特徴とするサーミスタ素子。     The thermistor element according to claim 1,
    A thermistor element, wherein Ra2 ≦ 0.8 μm.
  3. 　請求項１または２に記載のサーミスタ素子において、
    　前記サーミスタ素子のサイズは、ＪＩＳ規格０６０３サイズであることを特徴とするサーミスタ素子。     The thermistor element according to claim 1 or 2,
    The thermistor element has a JIS standard 0603 size.
  4. 　請求項１から３の何れか一つに記載のサーミスタ素子と、
    　前記サーミスタ素子の前記第１外部電極が接合される第１ランド部と、前記サーミスタ素子の前記第２外部電極が接合される第２ランド部とを有する実装基板と
    を備えることを特徴とする電子部品。     The thermistor element according to any one of claims 1 to 3,
    An electronic device comprising: a mounting substrate having a first land portion to which the first external electrode of the thermistor element is bonded and a second land portion to which the second external electrode of the thermistor element is bonded. parts.
  5. 　請求項４に記載の電子部品において、
    　前記第１ランド部の表面の面積が、前記第１外部電極の第１、第２面の面積に比べて、大きく、前記第２ランド部の表面の面積が、前記第２外部電極の第１、第２面の面積に比べて、大きい状態では、前記第１外部電極の第１面または第２面が前記第１ランド部の表面に対向し、前記第１外部電極の第３面と第４面が前記第１ランド部の表面に半田を介して接合されると共に、前記第２外部電極の第１面または第２面が前記第２ランド部の表面に対向し、前記第２外部電極の第３面と第４面が前記第２ランド部の表面に半田を介して接合され、
    　前記第１ランド部の表面の面積が、前記第１外部電極の第１、第２面の面積に比べて、小さく、前記第２ランド部の表面の面積が、前記第２外部電極の第１、第２面の面積に比べて、小さい状態では、前記第１外部電極の第３面または第４面が、前記第１ランド部の表面に対向しつつ前記第１ランド部の表面に半田を介して接合されると共に、前記第２外部電極の第３面または第４面が、前記第２ランド部の表面に対向しつつ前記第２ランド部の表面に半田を介して接合されることを特徴とする電子部品。     The electronic component according to claim 4,
    The surface area of the first land portion is larger than the areas of the first and second surfaces of the first external electrode, and the surface area of the second land portion is the first surface of the second external electrode. In a state larger than the area of the second surface, the first surface or the second surface of the first external electrode faces the surface of the first land portion, and the third surface and the third surface of the first external electrode Four surfaces are joined to the surface of the first land portion via solder, and the first surface or the second surface of the second external electrode is opposed to the surface of the second land portion, and the second external electrode The third surface and the fourth surface are joined to the surface of the second land portion via solder,
    The area of the surface of the first land portion is smaller than the areas of the first and second surfaces of the first external electrode, and the surface area of the second land portion is the first area of the second external electrode. In a state smaller than the area of the second surface, the third surface or the fourth surface of the first external electrode faces the surface of the first land portion while soldering the surface of the first land portion. And the third surface or the fourth surface of the second external electrode is bonded to the surface of the second land portion via solder while facing the surface of the second land portion. Features electronic components.
PCT/JP2015/061755 2014-07-04 2015-04-16 Thermistor element and electronic component WO2016002305A1 (en)

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