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WO2015184963A1 - 一种锁相环频率校正方法及系统 - Google Patents

一种锁相环频率校正方法及系统 Download PDF

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Publication number
WO2015184963A1
WO2015184963A1 PCT/CN2015/080447 CN2015080447W WO2015184963A1 WO 2015184963 A1 WO2015184963 A1 WO 2015184963A1 CN 2015080447 W CN2015080447 W CN 2015080447W WO 2015184963 A1 WO2015184963 A1 WO 2015184963A1
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Prior art keywords
frequency
band
sub
target
value
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PCT/CN2015/080447
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English (en)
French (fr)
Inventor
高鹏
朱年勇
梁建
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华为技术有限公司
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Publication of WO2015184963A1 publication Critical patent/WO2015184963A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/14—Demodulator circuits; Receiver circuits
    • H04L27/144—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements
    • H04L27/152—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements using controlled oscillators, e.g. PLL arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/10—Monitoring; Testing of transmitters
    • H04B17/11—Monitoring; Testing of transmitters for calibration
    • H04B17/14—Monitoring; Testing of transmitters for calibration of the whole transmission and reception path, e.g. self-test loop-back
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/20—Monitoring; Testing of receivers
    • H04B17/21—Monitoring; Testing of receivers for calibration; for correcting measurements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a phase locked loop frequency correction method and system.
  • a frequency synthesizer based on a phase-locked loop (PLL) structure is widely used to generate a local oscillation signal, which is referred to as a local oscillator (LO), to complete the frequency shift of the signal.
  • PLL phase-locked loop
  • LO local oscillator
  • RF transceivers are required to operate in multiple frequency bands, and therefore, the output signal of the phase locked loop is required to cover a sufficiently wide frequency range.
  • the core device Voltage-Controlled Oscillator (VCO) in the phase-locked loop also needs to operate over a wide enough frequency range. Since the voltage controlled oscillator is limited by noise requirements, process conditions, etc., a multi-band design structure is generally adopted, that is, multiple sub-bands are used to cover a sufficiently wide frequency range, but each sub-frequency only needs to cover a relatively narrow frequency. The sub-frequency is controlled by means of digital codes.
  • VCO Voltage-Controlled Oscillator
  • the system will require the phase-locked loop to output a specific frequency.
  • the phase-locked loop For multi-band voltage-controlled oscillators, it is necessary to set a suitable sub-band to meet the system's requirements for the output frequency and to meet the phase-locked loop circuit. The need to stabilize work.
  • the output frequency of each sub-band of the wideband voltage controlled oscillator is not stable. That is, it is difficult to directly obtain the voltage-controlled oscillator sub-band setting value according to the target frequency value that the voltage-controlled oscillator that is set by the system needs to be output.
  • the following describes a method for obtaining a voltage-controlled oscillator sub-band using the target frequency value given by the system in the prior art.
  • FIG. 1 there is shown a schematic diagram of a binary search method in the prior art.
  • the 16-band is taken as an example, 4-bit control, and the nodes in the figure are represented by binary control words.
  • up represents the path of the uplink search
  • dn represents the path of the downlink search
  • the binary algorithm starts from the middle sub-band of the voltage-controlled oscillator, and measures the output frequency of the voltage-controlled oscillator through the frequency counter.
  • the obtained information is compared with the target frequency value set by the system, and the search path is selected according to the comparison result.
  • one search path in Figure 1 is: 1000 -> 1100 -> 1110 -> 1101.
  • 1101 is the target sub-band of the search.
  • 1000 is an intermediate sub-band of 16 bands.
  • the count time of the frequency counter is R ⁇ T REF
  • f RES is the target precision.
  • R can be derived from f REF and f RES .
  • R is the count time reference parameter.
  • NCT NCT ⁇ R ⁇ T REF .
  • the main problem with the prior art shown in Fig. 1 is that the correction takes a long time.
  • the calibration time for this technique is estimated below using parameters commonly used in the design of radio frequency transceivers.
  • the calibration time is generally close to 50us.
  • the calibration time is too long, which will bring time pressure to other operations of the system.
  • Embodiments of the present invention provide a phase-locked loop frequency correction method and system, which can shorten the frequency correction time of a phase-locked loop.
  • a phase locked loop frequency correction method is applied to subband selection of a multi-band voltage controlled oscillator
  • the frequency signal outputted by the voltage controlled oscillator in the current working sub-band is frequency-counted to obtain a frequency count value FCNT[k], wherein the current working sub-band corresponds to a binary search tree.
  • the dynamically adjusting the T CNT [k] within a range of values of T CNT [k] according to a comparison result, and determining the The target sub-band of the voltage controlled oscillator works, specifically:
  • the current sub-band is used as the target sub-band of the voltage controlled oscillator operation
  • the increase count time reference T CNT [k] continues to read the frequency count value of the frequency control signal output by the voltage controlled oscillator in the current sub-band, and calculates a new read.
  • the error of the frequency count value and the FCNT TARGET [k] if the error is 0, the current sub-band is used as the target sub-band of the voltage-controlled oscillator operation, and if the error is not 0, the error is continued.
  • the counting of the output frequency of the voltage controlled oscillator corresponding to the current subband is stopped, and the next subband of the binary search is entered.
  • the entering the next sub-band of the binary search is specifically:
  • the sub-band whose binary value of the node is smaller than the current working sub-band is selected as the next sub-band on the binary search path;
  • T REF is the period of the reference clock signal input to the phase-locked loop
  • R[k] is the count time parameter, which is a positive integer that varies with the current time k, and k is a positive integer
  • the FCW is the frequency control of the phase-locked loop
  • the word signal is a known quantity.
  • the R[k] 2 k-1 ;
  • FCNT TARGET [k] 2 k-1 ⁇ FCW;
  • R max The maximum value of R[k] is R max .
  • f REF 1/T REF ;
  • f RES is the target precision of the phase-locked loop and is a known amount.
  • a second method provides a phase locked loop frequency correction system, including: a phase locked loop, a frequency counter, and a controller, wherein the phase locked loop includes a multi-band voltage controlled oscillator;
  • the phase locked loop is configured to control the voltage controlled oscillator output frequency signal according to the input reference clock signal
  • the frequency counter is configured to perform frequency counting on the frequency signal output by the voltage controlled oscillator in a current working sub-band during a counting time T CNT [k] to obtain a frequency counting value FCNT[k], wherein
  • the current working subband corresponds to a binary value of the current node in the binary search tree;
  • the controller is configured to calculate an error of the FCNT[k] and the target frequency count value FCNT TARGET [k], and compare the absolute value of the error with a predetermined value, according to the comparison result, at T CNT [k]
  • the T CNT [k] is dynamically adjusted within a range of values, and combined with a binary search algorithm, determines a target sub-band for operation of the voltage controlled oscillator.
  • the controller dynamically adjusts the T CNT [k] within a range of values of T CNT [k] according to the comparison result, and determines the binary search algorithm to determine
  • the target sub-band of the voltage controlled oscillator operates, specifically:
  • the current sub-band is used as the target of the voltage-controlled oscillator Subband
  • the increase count time reference T CNT [k] continues to read the frequency count value of the frequency control signal output by the voltage controlled oscillator in the current sub-band, and calculates a new read.
  • the error of the frequency count value and the FCNT TARGET [k] if the error is 0, the current sub-band is used as the target sub-band of the voltage-controlled oscillator operation, and if the error is not 0, the error is continued.
  • the counting of the output frequency of the voltage controlled oscillator corresponding to the current subband is stopped, and the next subband of the binary search is entered.
  • the controller is configured to enter a next sub-band of the binary search, specifically:
  • the sub-band whose binary value of the node is smaller than the current working sub-band is selected as the next sub-band on the binary search path;
  • the sub-band whose binary value of the node is larger than the current working sub-band is selected as the next sub-band on the binary search path.
  • T REF is the period of the reference clock signal input to the phase-locked loop
  • R[k] is the count time parameter, which is a positive integer that varies with the current time k, and k is a positive integer
  • the FCW is the frequency control of the phase-locked loop
  • the word signal is a known quantity.
  • the R[k] 2 k-1 ;
  • FCNT TARGET [k] 2 k-1 ⁇ FCW;
  • R max The maximum value of R[k] is R max .
  • f REF 1/T REF ;
  • f RES is the target precision of the phase-locked loop and is a known amount.
  • the phase-locked loop includes: an analog integer phase-locked loop, an analog fractional phase-locked loop, a digital integer phase-locked loop, and Digital fractional phase-locked loop.
  • the set count time reference and the target frequency count value are both variable, and the count time reference and the target frequency count value are fixed in the prior art. Since the correction time and correction accuracy of the frequency are contradictory, and there are many sub-bands that differ greatly from the target frequency value, some sub-bands do not have to take a long time to improve the accuracy of the measurement, but are closer to the target frequency value. The sub-band takes a long time to increase the accuracy of the measurement so that the corrected exact frequency can be obtained.
  • the measured error is compared with a preset value, thereby controlling whether to increase the counting time reference, and making a correct trade-off between the correction time and the correction accuracy, thereby effectively controlling the correction time.
  • This dynamic correction method as a whole The correction time can be effectively shortened.
  • FIG. 1 is a schematic diagram of a binary search method in the prior art
  • 2a is a schematic diagram of a frequency control structure of a voltage controlled oscillator provided by the present invention
  • FIG. 3 is a schematic diagram of a control curve of a voltage controlled oscillator frequency provided by the present invention.
  • Embodiment 4a is a flowchart of Embodiment 1 of a phase-locked loop frequency correction method provided by the present invention
  • Embodiment 4 is a flow chart of Embodiment 2 of a phase-locked loop frequency correction method provided by the present invention.
  • FIG. 5 is a schematic diagram showing the working principle of a frequency counter in the prior art
  • Embodiment 6 is a flowchart of Embodiment 3 of a phase-locked loop frequency correction method provided by the present invention.
  • FIG. 7 is a schematic diagram of a binary search algorithm provided by the present invention.
  • FIG. 9 is a schematic diagram showing the working principle of the frequency counter provided by the present invention.
  • Embodiment 1 of a phase-locked loop frequency correcting apparatus provided by the present invention
  • Embodiment 11 is a schematic diagram of Embodiment 2 of a phase-locked loop frequency correction device provided by the present invention.
  • Embodiment 1 is a schematic diagram of Embodiment 1 of a phase-locked loop frequency correction system provided by the present invention.
  • Embodiment 12 is a schematic diagram of Embodiment 2 of a phase-locked loop frequency correction system provided by the present invention.
  • 12a is a schematic diagram of a phase locked loop frequency correction system provided by the present invention when simulating a fractional phase locked loop;
  • 12b is a schematic diagram of the phase locked loop frequency correction system provided by the present invention when it is a digital fractional phase locked loop;
  • 12c is a schematic diagram of the phase locked loop frequency correction system provided by the present invention when another digital fractional phase locked loop is provided;
  • 12d is a schematic diagram of the phase locked loop frequency correction system provided by the present invention when it is a digital integer phase locked loop.
  • this figure is a structural diagram of a phase locked loop in the prior art.
  • the phase-locked loop consists of four basic components: phase detector A, loop filter B, voltage controlled oscillator C and feedback divider D. Among them, the voltage controlled oscillator C serves as a frequency source output frequency.
  • the output signal of the voltage controlled oscillator through the acquisition and distribution of C and the input frequency f REF of the reference clock is input together with the A phase detector, the phase detector comparing a difference A by f REF and VCO output frequency f VCO output An error voltage proportional to the frequency difference, and then filtering the high-frequency component of the error voltage through the loop filter B, and outputting a control voltage to control the voltage-controlled oscillator C, so that the frequency of the output signal of the voltage-controlled oscillator C is stabilized at The target frequency value, the output frequency f VCO of the voltage controlled oscillator C is divided by the feedback frequency divider D and the feedback signal f DIV is supplied to the phase detector A as a sampling signal of the output frequency.
  • the voltage controlled oscillator C in the phase-locked loop is usually implemented by a multi-subband structure. Specifically, a group of switchable capacitor arrays can be connected in parallel in the voltage controlled oscillator C to control the switch through digital signals. Therefore, the capacitance value of the capacitor array is externally changed, and the frequency range of the voltage controlled oscillator C is switched. Wherein each digital signal corresponds to one sub-band.
  • the output frequency of the voltage controlled oscillator C can be controlled in two ways, the coarse control and the fine control.
  • Coarse Tuning Select the sub-band of the voltage-controlled oscillator, determine the approximate range of the voltage-controlled oscillator, and control the selection of the sub-band of the voltage-controlled oscillator by digital signals, which are represented by CT. That is, the value of each CT corresponds to a sub-band of the voltage controlled oscillator.
  • Fine Tuning Controls the voltage controlled oscillator to accurately output the target frequency value set by the system through the phase-locked loop feedback mechanism.
  • CT and FT are usually executed sequentially after the system sets the target frequency value.
  • FIG. 2a the figure is a schematic diagram of a frequency control structure of a broadband voltage controlled oscillator provided by the present invention.
  • the voltage controlled oscillator C in the figure is a multi-subband voltage controlled oscillator whose band selection is realized by a coarse control signal (CT), and the value of the CT signal is obtained by the automatic frequency correction method provided by the present invention.
  • CT coarse control signal
  • FT fine-tuned control signal
  • phase detector A loop filter B
  • voltage controlled oscillator C feedback divider D
  • the signal output by the loop filter B is LPF.
  • the CLK_REF signal is an input reference clock signal of the phase locked loop.
  • CLK_REF is a frequency stable periodic signal. Let its signal frequency be f REF and its signal period is
  • the F_VCO signal is the phase-locked loop output signal, that is, the output signal of the voltage-controlled oscillator, its signal frequency f VCO , and its signal period is
  • FCW is the frequency control word signal of the phase-locked loop.
  • the system sets the output target frequency value of the phase-locked loop by setting the value of FCW.
  • FCW is a known amount.
  • FCW is different from CT, and FCW is the feedback divider D in the phase-locked loop.
  • the CT is used to control the selection of the sub-band of the voltage controlled oscillator C, which is a digital signal.
  • the frequency counter E and the algorithm logic module F are used to perform phase-locked loop frequency correction, and E and F are combined to form a frequency correcting device.
  • the correction biasing module G is used for initialization.
  • the control switch SW_CT controls the signal FT_BIAS outputted by the correction biasing module G to the FT, and outputs it to the voltage controlled oscillator C, and sets the initial value of the CT to the intermediate subband.
  • the intermediate sub-band is 1000.
  • this figure is a schematic diagram of a control curve of a voltage controlled oscillator frequency provided by the present invention.
  • the set target frequency value is f TARGET .
  • FT FT 0 .
  • the relationship between the target frequency value and its corresponding sub-band is not fixed.
  • a device needs to be specially designed to automatically select an optimal voltage-controlled oscillator sub-band through the device according to the target frequency value set by the system, that is, The most suitable coarse control signal is selected, which is called the frequency correction of the wideband phase locked loop.
  • the sub-band is selected by CT, and the value of CT is realized by automatic frequency correction.
  • the FT signal is obtained through a feedback mechanism of the phase locked loop, which will not be specifically described in the present invention.
  • the method provided by the invention can shorten the time of automatic frequency correction, and is described in detail below with reference to the accompanying drawings.
  • FIG. 4a the figure is a flowchart of Embodiment 1 of a phase-locked loop frequency correction method provided by the present invention.
  • phase-locked loop frequency correction method provided in this embodiment is applied to sub-band selection of a multi-band voltage controlled oscillator
  • the frequency technology of the frequency signal outputted by the voltage controlled oscillator in the current working sub-band is performed by the frequency counter.
  • the current working sub-band refers to a binary value corresponding to the current node in the binary search tree.
  • S402a calculating an error of the FCNT[k] and the target frequency count value FCNT TARGET [k], and comparing the absolute value of the error with a predetermined value, according to the comparison result, the value range of T CNT [k]
  • the T CNT [k] is dynamically adjusted internally and combined with a binary search algorithm to determine a target sub-band for operation of the voltage controlled oscillator.
  • the measurement accuracy can be reduced in the sub-band only for determining the relationship between the frequencies, so that the measurement time in these sub-bands can be shortened.
  • the sub-frequency which requires high measurement accuracy, ensures measurement accuracy to lengthen the measurement time. Therefore, in the embodiment, the method of dynamically adjusting the frequency measurement accuracy can improve the effect of frequency correction without loss of accuracy of correction.
  • the set count time and the target frequency count value are both variable, and the count time and the target frequency count value are fixed in the prior art. Since the correction accuracy of the frequency correction time is contradictory, and there are many sub-bands that differ greatly from the target frequency value, some sub-bands do not have to take a long time to improve the accuracy of the measurement, but are closer to the target frequency value. The sub-band takes a long time to increase the accuracy of the measurement, thereby obtaining a corrected accurate frequency.
  • the measured error is compared with a preset value, thereby controlling whether or not the counting time is adjusted, thereby effectively controlling the correction time. This dynamic correction method can effectively shorten the correction time as a whole.
  • FIG. 4b the figure is a flowchart of Embodiment 2 of a phase-locked loop frequency correction method provided by the present invention.
  • T REF is the period of the phase-locked loop input reference clock
  • R[k] is the count time parameter, which is a positive integer that varies with the current time k, and k is a positive integer
  • the FCW is a frequency control word signal, which is known the amount
  • the count time and the target frequency count value are both related to R, Therefore, the two quantities are not fixed as in the prior art, but vary; in the prior art, the counting time is fixed, and the target frequency count value is also fixed.
  • the function of the frequency counter is to count the output signal of the voltage controlled oscillator within the counting time. If the counting time is stable, the count value output by the frequency counter can represent the output frequency of the voltage controlled oscillator.
  • FIG. 5 it is a schematic diagram of the working principle of the frequency counter in the prior art.
  • FIG. 5 is a working principle diagram of a frequency counter in the prior art.
  • the counting time T CNT is fixed.
  • the counting time of the frequency counter is changed, that is, becomes T CNT [k].
  • the output signal of the voltage controlled oscillator is F_VCO, and the frequency of F_VCO is f VCO ;
  • frequency counter CNT counts time T, T in the count signal CNT on F_VCO, i.e. F_VCO calculate how many cycles, over FCNT output value of the frequency counter CNT can be obtained in the time range T ':
  • a corresponding counter value FCNT' can be obtained by the frequency counter. That is, in the case that the counting time T CNT is stable, the output frequency f VCO of the voltage controlled oscillator can be characterized by the counting value FCNT' of the frequency counter, that is, the output frequency of the voltage controlled oscillator is measured by the frequency counter:
  • the ROUND function represents a rounding operation.
  • FCNT' FCNT+E QUAT (5)
  • ABS function indicates an absolute value operation.
  • the voltage-controlled oscillator frequency measurement error introduced by the frequency counter quantization error is related to the frequency counter count time. It can be known from equation (7) that the longer the counting time of the frequency counter is, the smaller the error of the voltage controlled oscillator frequency measurement is, that is, the closer the voltage controlled oscillator output frequency reflected by the FCNT of the frequency counter is to the actual output of the voltage controlled oscillator. frequency.
  • the frequency counter typically uses CLK_REF to generate the count time.
  • T CNT R ⁇ T REF (R ⁇ positive integer) (8)
  • the counting time of the frequency counter is usually an integer multiple of the reference clock period.
  • R in the formulas (8) and (9) is a counting time parameter in the prior art.
  • R is fixed, and in the embodiment of the present invention, R is changed, that is, changed. Is R[k].
  • the broadband phase-locked loop frequency correction mechanism Due to the quantization characteristics of the frequency counter, the broadband phase-locked loop frequency correction mechanism has an insurmountable contradiction in accuracy and efficiency.
  • the method adopted in this embodiment is to shorten the correction time by using a shorter counting time in a sub-band having a larger difference from the target frequency value; however, in a sub-band having a smaller distance from the target frequency, a longer counting is used. Time to ensure correction accuracy.
  • the predetermined value is a preset threshold. If the error between the current count value and the current target frequency count value is less than the predetermined value, the current sub-band is closer to the target frequency value, and the need to obtain more Accurate frequency count values increase accuracy by increasing the count time, at which point the measurement time is sacrificed.
  • step of how to enter the next sub-band belongs to the prior art, and specifically:
  • the sub-band whose binary value of the node is smaller than the current working sub-band is selected as the next sub-band on the binary search path;
  • the sub-band whose binary value of the node is larger than the current working sub-band is selected as the next sub-frequency on the binary search path. band.
  • end of the binary search means that the search path ends, for example, in Figure 1, the bottom layer of the search path is searched.
  • the set count time and the target frequency count value are both variable, and the count time and the target frequency count value are fixed in the prior art. Since the correction accuracy of the frequency correction time is contradictory, and there are many sub-bands that differ greatly from the target frequency value, some sub-bands do not have to take a long time to improve the accuracy of the measurement, but are closer to the target frequency value. The sub-band takes a long time to increase the accuracy of the measurement, thereby obtaining a corrected accurate frequency.
  • the measured error is compared with a preset value, thereby controlling whether or not the counting time is increased, thereby effectively controlling the correction time. This dynamic correction method can effectively shorten the correction time as a whole.
  • FIG. 6 is a flowchart of Embodiment 3 of a phase-locked loop frequency correction method provided by the present invention.
  • This embodiment introduces one of the most complete calibration procedures.
  • R[k] has been introduced as a positive integer. Since in practice, for the convenience of implementation, R[k] can be set to an integer power of 2, because in the logic circuit, only the logic circuit needs to be performed. By shifting the operation, the calculation of the integer power of 2 can be realized, which can greatly reduce the consumption of the chip resources. Therefore, in the present embodiment, R[k] is realized by an integer power of two.
  • S606 Determine whether the R[k] has reached the maximum value, and if yes, forcibly enter the next sub-band of the binary search, that is, execute S607.
  • f REF 1/T REF ;
  • f RES is the target precision of the phase-locked loop and is a known amount.
  • End of binary search refers to searching to the bottom of the binary search tree, the bottom layer.
  • S610 Update the CT value according to the binary search algorithm, that is, switch to the next sub-band to perform frequency measurement.
  • the following description will be made with reference to a specific example, and the description will be continued by taking the NCT as 4, that is, the 16-band.
  • FIG. 7 the figure is a schematic diagram of a binary search algorithm provided by the present invention.
  • Design a certain margin, that is, CT 0 design redundancy, not within the system requirements, can not be measured to save calibration time.
  • the frequency of the voltage-controlled oscillator in the corresponding sub-band is measured by the frequency counter, and the difference between the corresponding count value and the target frequency count value is stored, and finally the difference is measured.
  • the smallest sub-band will be used as the selected sub-band.
  • the target frequency value f TARGET of the phase locked loop corresponds to the count value FCNT TARGET of a frequency counter, which can be obtained according to formula (2) and formula (8):
  • the target frequency count value of the frequency counter can be directly obtained by the frequency control word signal FCW of the phase locked loop.
  • CT 13
  • Figure 8 is a sub-band search diagram.
  • the measured frequency is relatively close to the target frequency value, so it is necessary to measure the frequency more accurately, and select the final correction result according to the measurement result.
  • the 16 frequency band is taken as an example for explanation, which can be understood. Yes, the more the number of sub-bands, the more advantageous the method provided by the embodiment of the present invention is, that is, the relatively shortened correction time will be longer.
  • the counting time in the dynamic frequency correction provided by the present invention is dynamically adjusted as described below with reference to FIG.
  • a frequency counter can be applied to perform counting measurement of frequencies at a plurality of different counting times, and multiple frequency counters are not required, and multiple measurements are not required.
  • T CNT [1] T REF ;
  • T CNT [2] 2 * T REF ;
  • T CNT [3] 4 * T REF ;
  • the method provided by the foregoing embodiment of the present invention is applicable to an analog integer phase locked loop, an analog fractional phase locked loop, a digital integer phase locked loop, and a digital fractional phase locked loop.
  • the counting time of the frequency counter corresponding to each sub-band is dynamically variable, and a short counting time is adopted for a sub-band having a large difference from the target frequency value, so that a fast judgment can be realized.
  • a longer counting time is used to ensure the correction accuracy. Since the count time parameter takes the form of an integer power of 2, this is easy to implement without additional consumption on the hardware.
  • the embodiment of the present invention further provides a frequency correction device for the phase-locked loop, which will be described in detail below with reference to the accompanying drawings.
  • FIG. 10 it is a schematic diagram of Embodiment 1 of a phase-locked loop frequency correcting apparatus provided by the present invention.
  • the broadband phase-locked loop frequency correction device includes: a first judging module 100, a counting time updating module 200, a sub-band updating module 300, and a second judging module 100a;
  • the first determining module 100 is configured to determine, under the current counting time T CNT [k], whether the error of the current counter value FCNT[k] output by the frequency counter and the corresponding current target frequency counter value FCNT TARGET [k] is less than a predetermined value.
  • the frequency counter counts an output frequency of the voltage controlled oscillator; the voltage controlled oscillator is a multi-band voltage controlled oscillator; and the sub-band selection in the multi-band voltage controlled oscillator is controlled by a digital signal;
  • T REF is the period of the phase-locked loop input reference clock
  • R[k] is the count time parameter, which is a positive integer that varies with the current time k, and k is a positive integer
  • the FCW is the frequency control word signal of the phase-locked loop , is a known amount
  • both the count time and the target frequency count value are related to R, so the two quantities are not fixed as in the prior art, but are changed;
  • the counting time is fixed and the target frequency count value is also fixed.
  • the set count time and the target frequency count value can be changed because for the broadband voltage controlled oscillator, most of the sub-bands in the binary search path only need to judge the count value and target read by the frequency counter.
  • the relative magnitude of the frequency does not require the accurate output frequency of the voltage controlled oscillator. For a few sub-bands close to the target frequency value, it is necessary to know the exact output frequency.
  • the difference between the count value read by the frequency counter and the target frequency value will be used as the basis for the sub-frequency selection, that is, the measurement accuracy will affect the final. The result of the frequency correction.
  • the measurement accuracy can be reduced in the sub-band only for determining the relationship between the frequencies, so that the measurement time in these sub-bands can be shortened.
  • the sub-frequency which requires high measurement accuracy, ensures measurement accuracy to lengthen the measurement time. Therefore, in the embodiment, the method of dynamically adjusting the frequency measurement accuracy can improve the effect of frequency correction without loss of accuracy of correction.
  • the function of the frequency counter is to count the output signal of the voltage controlled oscillator within the counting time. If the counting time is stable, the count value output by the frequency counter can represent the output frequency of the voltage controlled oscillator.
  • the counting time update module 200 is configured to: when the first determining module 100 determines that the error is less than a predetermined value, increase the counting time to continue reading the count value output by the frequency counter;
  • the predetermined value is a preset threshold. If the error between the current count value and the current target frequency count value is less than the predetermined value, the current sub-band is closer to the target frequency value, and the need to obtain more Accurate frequency count values increase accuracy by increasing the count time, at which point the measurement time is sacrificed.
  • the sub-band update module 300 is configured to stop the output of the voltage-controlled oscillator corresponding to the current sub-band by the frequency counter when the first determining module 100 determines that the error is greater than or equal to a predetermined value. The count of frequencies enters the next subband of the binary search.
  • the second determining module 100a is configured to determine that the binary search ends, and the sub-band corresponding to the minimum value of the error is used as a sub-band of the voltage controlled oscillator.
  • end of the binary search refers to the completion of the sub-band search on the search path, such as the bottom layer in FIG.
  • the set count time and the target frequency count value are both variable, and the count time and the target frequency count value are fixed in the prior art. Since the correction accuracy of the frequency correction time is contradictory, and there are many sub-bands that differ greatly from the target frequency value, some sub-bands do not have to take a long time to improve the accuracy of the measurement, but are closer to the target frequency value. The sub-band takes a long time to increase the accuracy of the measurement, thereby obtaining a corrected accurate frequency.
  • the measured error is compared with a preset value, thereby controlling whether or not the counting time is increased, thereby effectively controlling the correction time. This dynamic correction method can effectively shorten the correction time as a whole.
  • FIG. 11 is a schematic diagram of Embodiment 2 of a broadband phase-locked loop frequency correction apparatus provided by the present invention.
  • R[k] is a positive integer. Since in practice, for the convenience of implementation, R[k] can be set to the form of an integer power of 2, because in the logic circuit, only the shift operation is required, and 2 can be realized. The calculation of the integer power, which can greatly reduce the consumption of chip resources. Therefore, in the present embodiment, R[k] is realized by an integer power of two.
  • the broadband phase-locked loop frequency correction device may further include: a maximum value determining module 400;
  • the maximum value judging module 400 is configured to determine whether the R[k] has reached a maximum value, and if so, the sub-band update module 300 forcibly enters a next sub-band of the binary search.
  • the counting time of the frequency counter corresponding to each sub-band is dynamically variable, and a short counting time is adopted for a sub-band having a large difference from the target frequency value, so that a fast judgment can be realized.
  • a longer counting time is used to ensure the correction accuracy. Since the count time parameter takes the form of an integer power of 2, this is easy to implement without additional consumption on the hardware.
  • the embodiment of the present invention further provides a phase-locked loop frequency correction system, which will be described in detail below with reference to the accompanying drawings.
  • FIG. 11a the figure is a schematic diagram of Embodiment 1 of a phase-locked loop frequency correction system provided by the present invention.
  • the phase-locked loop frequency correction system includes: a phase-locked loop 1000, a frequency counter E, and a controller 1200, and the phase-locked loop 1000 includes a multi-band voltage-controlled oscillator;
  • the phase locked loop 1000 is configured to control the voltage controlled oscillator output frequency signal according to the input reference clock signal
  • the frequency counter E is configured to perform frequency counting on the frequency signal output by the voltage controlled oscillator in the current working sub-band during the counting time T CNT [k] to obtain a frequency count value FCNT[k],
  • the current working subband corresponds to a binary value of a current node in the binary search tree;
  • the current working sub-band refers to a binary value corresponding to the current node in the binary search tree.
  • the controller 1200 is configured to calculate an error of the FCNT[k] and the target frequency count value FCNT TARGET [k], and compare the absolute value of the error with a predetermined value, according to the comparison result, at T CNT [
  • the T CNT [k] is dynamically adjusted within a range of k], and combined with a binary search algorithm, determines a target sub-band for operation of the voltage controlled oscillator.
  • the set count time and the target frequency count value can be changed because for the broadband voltage controlled oscillator, most of the sub-bands in the binary search path only need to judge the count value and target read by the frequency counter.
  • the relative magnitude of the frequency does not require the accurate output frequency of the voltage controlled oscillator. For a few sub-bands close to the target frequency value, it is necessary to know the exact output frequency.
  • the difference between the count value read by the frequency counter and the target frequency value will be used as the basis for the sub-frequency selection, that is, the measurement accuracy will affect the final. The result of the frequency correction.
  • the measurement accuracy can be reduced in the sub-band only for determining the relationship between the frequencies, so that the measurement time in these sub-bands can be shortened.
  • the sub-frequency which requires high measurement accuracy, ensures measurement accuracy to lengthen the measurement time. Therefore, in the embodiment, the method of dynamically adjusting the frequency measurement accuracy can improve the effect of frequency correction without loss of accuracy of correction.
  • the set count time and the target frequency count value are both variable, and the count time and the target frequency count value are fixed in the prior art. Since the correction accuracy of the frequency correction time is contradictory, and there are many sub-bands that differ greatly from the target frequency value, some sub-bands do not have to take a long time to improve the accuracy of the measurement, but are closer to the target frequency value. The sub-band takes a long time to increase the accuracy of the measurement, thereby obtaining a corrected accurate frequency.
  • the measured error is compared with a preset value, thereby controlling whether or not the counting time is adjusted, thereby effectively controlling the correction time. This dynamic correction method can effectively shorten the correction time as a whole.
  • FIG. 12 it is a schematic diagram of Embodiment 2 of a phase-locked loop frequency correction system provided by the present invention.
  • phase locked loop in the phase locked loop frequency correction system includes: phase detector A, loop filter B, voltage controlled oscillator C, and feedback frequency divider D;
  • the voltage controlled oscillator C is a multi-band voltage controlled oscillator, and the sub-band selection in the multi-band voltage controlled oscillator is controlled by digital signals;
  • the sub-band corresponds to a binary value corresponding to a node in the binary search tree.
  • the phase detector A is configured to compare the target frequency value with the output frequency of the acquired voltage controlled oscillator C, obtain a frequency error, output an error voltage proportional to the frequency error, and output the error voltage to The loop filter B;
  • the loop filter B is configured to filter out the high frequency signal in the error voltage, and output control power Pressing the voltage controlled oscillator C;
  • the voltage controlled oscillator C is configured to output a target frequency value under the control voltage
  • the frequency counter E is used to count the output frequency of the voltage controlled oscillator C under the current counting time T CNT [k], and output the current count value FCNT[k] to the controller 1200;
  • T REF is the period of the reference clock signal input to the phase-locked loop
  • R[k] is the count time parameter, which is a positive integer that varies with the current time k, and k is a positive integer
  • the FCW is the frequency control of the phase-locked loop
  • the word signal is a known quantity.
  • both the count time and the target frequency count value are related to R, so the two quantities are not fixed as in the prior art, but are changed;
  • the counting time is fixed and the target frequency count value is also fixed.
  • the set count time and the target frequency count value can be changed because for the broadband voltage controlled oscillator, most of the sub-bands in the binary search path only need to judge the count value and target read by the frequency counter.
  • the relative magnitude of the frequency does not require the accurate output frequency of the voltage controlled oscillator. For a few sub-bands close to the target frequency value, it is necessary to know the exact output frequency.
  • the difference between the count value read by the frequency counter and the target frequency value will be used as the basis for the sub-frequency selection, that is, the measurement accuracy will affect the final. The result of the frequency correction.
  • the measurement accuracy can be reduced in the sub-band only for determining the relationship between the frequencies, so that the measurement time in these sub-bands can be shortened.
  • the sub-frequency which requires high measurement accuracy, ensures measurement accuracy to lengthen the measurement time. Therefore, in the embodiment, the method of dynamically adjusting the frequency measurement accuracy can improve the effect of frequency correction without loss of accuracy of correction.
  • the function of the frequency counter is to count the output signal of the voltage controlled oscillator within the counting time. If the counting time is stable, the count value output by the frequency counter can represent the output frequency of the voltage controlled oscillator.
  • the controller 1200 is configured to dynamically adjust the T CNT [k] in a range of values of T CNT [k] according to a comparison result, and determine the voltage controlled oscillator in combination with a binary search algorithm.
  • the target sub-band of the work specifically:
  • the current sub-band is used as the target sub-band of the voltage controlled oscillator operation
  • the increase count time reference T CNT [k] continues to read the frequency count value of the frequency control signal output by the voltage controlled oscillator in the current sub-band, and calculates a new read.
  • the error of the frequency count value and the FCNT TARGET [k] if the error is 0, the current sub-band is used as the target sub-band of the voltage-controlled oscillator operation, and if the error is not 0, the error is continued.
  • FCNT TARGET [k] R[k] ⁇ FCW;
  • T CNT [k] and the FCNT TARGET [k] in the expression are as k is varied, not fixed.
  • the counting of the output frequency of the voltage controlled oscillator corresponding to the current subband is stopped, and the next subband of the binary search is entered.
  • step of how to enter the next sub-band belongs to the prior art, and specifically:
  • the controller is configured to enter a next sub-band of the binary search, specifically:
  • the sub-band whose binary value of the node is smaller than the current working sub-band is selected as the next sub-band on the binary search path;
  • the sub-band whose binary value of the node is larger than the current working sub-band is selected as the next sub-band on the binary search path.
  • end of the binary search refers to the end of the search path, that is, the last sub-band of the search path, such as the lowest layer in FIG.
  • the predetermined value is a preset threshold, if the current count value is If the error between the previous target frequency count values is less than the predetermined value, it indicates that the current sub-band is close to the target frequency value, and it is necessary to obtain a more accurate frequency count value, and the accuracy can be improved by increasing the counting time. Sacrifice measurement time.
  • the set count time and the target frequency count value are both variable, and the count time and the target frequency count value are fixed in the prior art. Since the correction accuracy of the frequency correction time is contradictory, and there are many sub-bands that differ greatly from the target frequency value, some sub-bands do not have to take a long time to improve the accuracy of the measurement, but are closer to the target frequency value. The sub-band takes a long time to increase the accuracy of the measurement, thereby obtaining a corrected accurate frequency.
  • the measured error is compared with a preset value, thereby controlling whether or not the counting time is increased, thereby effectively controlling the correction time. This dynamic correction method can effectively shorten the correction time as a whole.
  • R[k] is a positive integer. Since in practice, for the convenience of implementation, R[k] can be set to the form of an integer power of 2, because in the logic circuit, only the shift operation is required, and 2 can be realized. The calculation of the integer power, which can greatly reduce the consumption of chip resources. Therefore, in the present embodiment, R[k] is realized by an integer power of two.
  • the R[k] 2 k-1 ;
  • FCNT TARGET [k] 2 k-1 ⁇ FCW;
  • R max The maximum value of R[k] is R max .
  • f REF 1/T REF ;
  • f RES is the target precision of the phase-locked loop and is a known amount.
  • phase-locked loops provided by the foregoing embodiments of the present invention may be of various types, such as an analog integer phase-locked loop, an analog fractional phase-locked loop, a digital integer phase-locked loop, and a digital fractional phase-locked loop.
  • FIG. 12 shows an analog integer phase-locked loop, that is, phase detector A, loop filter B, voltage-controlled oscillator C, and feedback divider D all operate in an analog signal domain, and the phase-locked loop
  • the FCW is a positive integer.
  • phase-locked loop in the present invention may also be an analog fractional phase-locked loop (Fractional-N PLL), see FIG. 12a, that is, phase detector A, loop filter B, voltage controlled oscillator C, and feedback divider. D works in the analog signal domain, and the FCW of the phase-locked loop is a positive number rational number.
  • Fractional-N PLL analog fractional phase-locked loop
  • the Sigma-Delta modulator M is added in Fig. 12a compared to Fig. 12.
  • phase-locked loop in the present invention may also be a digital integer phase-locked loop (Digital Fractional-N PLL).
  • the phase-to-phase loop time-to-digital converter A1 converts phase information into a digital signal and passes the digital
  • the filter B1 processes the digitized phase error information, and controls the numerically controlled oscillator C1 to output a desired frequency signal through the digital signal.
  • the frequency control word FCW of the phase locked loop is a positive number rational number.
  • the Sigma-Delta modulator M is also added in Fig. 12b as in Fig. 12.
  • phase locked loop of the present invention may also be another form of digital fractional phase locked loop, which is different from the phase locked loop of Fig. 12b, which is suitable for high frequency applications. That is, the high frequency digital fractional phase locked loop using the prescaler.
  • the other parts are the same as those of FIG. 12b, and are not described herein again.
  • the output frequency of the numerically controlled oscillator C1 is relatively high, and the frequency counter E cannot directly count the frequency of the output frequency of the numerically controlled oscillator C1.
  • the present invention also provides a digital integer phase locked loop, see Figure 12d.
  • the difference between Figure 12d and Figure 12a is that the Sigma-Delta modulator is omitted and the factor is a digital integer phase-locked loop, so a sigma-delta modulator is not required.
  • the frequency correction method, apparatus and system provided by the above embodiments of the present invention can significantly shorten the correction time without affecting the requirements of the correction accuracy.

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Abstract

一种锁相环频率校正方法及系统，应用于对多频带压控振荡器的子频带选择；包括：在计数时间TCNT［k］内，对压控振荡器在当前工作子频带下输出的所述频率信号进行频率计数，得到频率计数值FCNT［k］，其中，当前工作子频带对应二进制搜索树中的当前节点的二进制数值（S401a）；计算所述FCNT［k］与目标频率计数值FCNTTARGET［k］的误差，并将所述误差的绝对值与预定值进行比较，根据比较结果，在TCNT［k］的取值范围内动态调整所述TCNT［k］，并结合二进制搜索算法，确定所述压控振荡器工作的目标子频带（S402a）。将测量的误差与预设值进行比较，从而控制是否增加计数时间基准，在校正时间和校正精度之间做出正确的取舍，从而有效控制校正时间，这种动态地校正方法整体上可以有效地缩短校正时间。

Description

一种锁相环频率校正方法及系统
本申请要求于2014年6月3日提交中国专利局、申请号为201410242385.2、发明名称为“一种锁相环频率校正方法及系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及通信技术领域，特别涉及一种锁相环频率校正方法及系统。
背景技术
无线射频收发信机中，广泛采用基于锁相环(PLL，Phase-Locked Loop)结构的频率综合器，用来产生本地振荡信号，简称本振(LO，Local Oscillator)，完成信号的频率搬移。
在现代无线通信中，要求射频收发信机能够工作在多个频段，因此，需要锁相环的输出信号能够覆盖足够宽的频率范围。
实现宽带锁相环，则锁相环中的核心器件压控振荡器(VCO，Voltage-Controlled Oscillator)也需要工作在足够宽的频率范围。由于压控振荡器受到噪声要求、工艺条件等限制，一般采用多频带设计结构，即采用多个子频带来覆盖足够宽的频率范围，但每个子频率仅需要覆盖相对较窄的频率。子频率通过数字码的方式实现控制。
在实际应用中，系统会要求锁相环输出一个特定的频率，对于多频带压控振荡器来说，则需要设置一个合适的子频带，满足系统对输出频率的要求，同时满足锁相环电路稳定工作的需要。
由于芯片制造工艺的波动，以及应用环境的不确定性，宽带压控振荡器各个子频带的输出频率并不是稳定不变的。即，很难根据系统设定的压控振荡器需要输出的目标频率值，直接得到压控振荡器子频带设置值。
下面介绍现有技术中利用系统给出的目标频率值得到压控振荡器子频带的方法。
参见图1，该图为现有技术中二进制搜索法示意图。
图1中是以16频带为例，4位(bit)控制，图中节点用二进制控制字表示。
图1中的up表示上行搜索的路径，dn表示下行搜索的路径。
二进制算法是从压控振荡器的中间子频带出发，通过频率计数器对压控振荡器的输出频率进行测量，获得的信息与系统设定的目标频率值进行比较，根据比较结果，选择搜索路径。
例如，图1中的一条搜索路径是：1000–>1100->1110->1101。1101即为搜索的目标子频带。1000为16频带的中间子频带。
在路径上的每个节点，频率计数器的计数时间长度都是R×TREF，理论上可获得的频率计数精度为fRES＝fREF/R，其中，fREF是计数的基准频率，该基准频率就是锁相环输入参考时钟的频率。fRES是目标精度。由fREF和fRES便可以得出R。
R为计数时间基准参数。
因此，如果不计入其他开销，总校正时间长度为tCAL＝NCT×R×TREF。其中，NCT为压控振荡器子频带控制字的位宽。在图1中，NCT＝4。
图1所示的现有技术存在的主要问题是校正的时间较长。下面以无线射频收发机设计中常用的参数估算一下该技术的校正时间。
fREF＝20MHz即
Figure PCTCN2015080447-appb-000001
fRES＝200kHz；
则
Figure PCTCN2015080447-appb-000002
通常设计压控振荡器子频带控制字为NCT＝8，则不计入其他开销前提下，校正所需要的时间为：
tCAL＝NCT×R×TREF＝40us；
加上其他开销，校正时间一般会接近50us，对于无线射频收发信机来讲，校正时间太长，对系统的其他操作会带来时间压力。
因此，本领域技术人员需要提供一种锁相环频率校正方法，能够缩短校正时间。
发明内容
本发明实施例提供一种锁相环频率校正方法及系统，能够缩短锁相环的频率校正时间。
本发明公开了以下技术方案：
第一方面，一种锁相环频率校正方法，应用于对多频带压控振荡器的子频带选择；包括：
在计数时间TCNT[k]内，对压控振荡器在当前工作子频带下输出的所述频率信号进行频率计数，得到频率计数值FCNT[k]，其中，当前工作子频带对应二进制搜索树中的当前节点的二进制数值；
计算所述FCNT[k]与目标频率计数值FCNTTARGET[k]的误差，并将所述误差的绝对值与预定值进行比较，根据比较结果，在TCNT[k]的取值范围内动态调整所述TCNT[k]，并结合二进制搜索算法，确定所述压控振荡器工作的目标子频带。
在第一方面的第一种可能的实现方式中，所述根据比较结果，在TCNT[k]的取值范围内动态调整所述TCNT[k]，并结合二进制搜索算法，确定所述压控振荡器工作的目标子频带，具体为：
如果判断所述误差为0，将当前子频带作为所述压控振荡器工作的目标子频带；
如果判断所述误差大于0且小于预定值，则增大计数时间基准TCNT[k]继续读取压控振荡器在当前子频带输出的频率信号进行频率计数的频率计数值，计算新读取的所述频率计数值与所述FCNTTARGET[k]的误差，如果误差为0，则将当前子频带作为压控振荡器工作的目标子频带，如果误差不为0，继续进行所述误差与所述预定值的比较，一直增大TCNT[k]到TCNT[k]的取值范围内的最大值时，强制进入二进制搜索的下一个子频带；二进制搜索结束时，将所述误差最小值对应的子频带作为所述压控振荡器工作的目标子频带；
如果判断所述误差大于或等于预定值，则停止对当前子频带对应的压控振荡器的输出频率的计数，进入二进制搜索的下一个子频带。
结合第一方面及上述任一种可能的实现方式中，在第二种可能的实现方式中，所述进入二进制搜索的下一个子频带，具体为：
当所述频率计数值大于所述目标频率计数值时，则在二进制搜索路径上选择节点的二进制数值比当前工作子频带小的子频带作为下一个子频带；
当所述频率计数值小于所述目标频率计数值时，则在二进制搜索路径 上选择节点的二进制数值比当前工作子频带大的子频带作为下一个子频带。
结合第一方面及上述任一种可能的实现方式中，在第三种可能的实现方式中，所述TCNT[k]＝TREF*R[k]；所述FCNTTARGET[k]＝R[k]×FCW；
其中，TREF为输入锁相环的参考时钟信号的周期；R[k]为计数时间参数，是随当前时间k变化的正整数，k为正整数；所述FCW是锁相环的频率控制字信号，为已知量。
结合第一方面及上述任一种可能的实现方式中，在第四种可能的实现方式中，所述R[k]＝2k-1；
所述TCNT[k]＝TREF*R[k]＝TREF*2k-1；
所述FCNTTARGET[k]＝2k-1×FCW；
所述R[k]的最大取值为Rmax，当A＝fREF/fRES为2的整数次幂时，则Rmax＝A；当A不为2的整数次幂时，Rmax取大于A的2的整数次幂中的最小值；
其中，fREF＝1/TREF；fRES为锁相环的目标精度，为已知量。
第二方法，提供一种锁相环频率校正系统，包括：锁相环、频率计数器、控制器，所述锁相环包括多频带的压控振荡器；
所述锁相环，用于根据输入的参考时钟信号，控制所述压控振荡器输出频率信号；
所述频率计数器，用于在计数时间TCNT[k]内，对所述压控振荡器在当前工作子频带下输出的所述频率信号进行频率计数，得到频率计数值FCNT[k]，其中，当前工作子频带对应二进制搜索树中的当前节点的二进制数值；
所述控制器，用于计算所述FCNT[k]与目标频率计数值FCNTTARGET[k]的误差，并将所述误差的绝对值与预定值进行比较，根据比较结果，在TCNT[k]的取值范围内动态调整所述TCNT[k]，并结合二进制搜索算法，确定所述压控振荡器工作的目标子频带。
在第二方面的第一种可能的实现方式中，所述控制器根据比较结果，在TCNT[k]的取值范围内动态调整所述TCNT[k]，并结合二进制搜索算法，确定所述压控振荡器工作的目标子频带，具体为：
如果判断所述误差为0，将当前子频带作为所述压控振荡器工作的目标 子频带；
如果判断所述误差大于0且小于预定值，则增大计数时间基准TCNT[k]继续读取压控振荡器在当前子频带输出的频率信号进行频率计数的频率计数值，计算新读取的所述频率计数值与所述FCNTTARGET[k]的误差，如果误差为0，则将当前子频带作为压控振荡器工作的目标子频带，如果误差不为0，继续进行所述误差与所述预定值的比较，一直增大TCNT[k]到TCNT[k]的取值范围内的最大值时，强制进入二进制搜索的下一个子频带；二进制搜索结束时，将所述误差最小值对应的子频带作为所述压控振荡器工作的目标子频带；
如果判断所述误差大于或等于预定值，则停止对当前子频带对应的压控振荡器的输出频率的计数，进入二进制搜索的下一个子频带。
结合第二方面及上述任一种可能的实现方式中，在第二种可能的实现方式中，所述控制器用于进入二进制搜索的下一个子频带，具体为：
当所述频率计数值大于所述目标频率计数值时，则在二进制搜索路径上选择节点的二进制数值比当前工作子频带小的子频带作为下一个子频带；
当所述频率计数值小于所述目标频率计数值时，则在二进制搜索路径上选择节点的二进制数值比当前工作子频带大的子频带作为下一个子频带。
结合第二方面及上述任一种可能的实现方式中，在第三种可能的实现方式中，所述TCNT[k]＝TREF*R[k]；所述FCNTTARGET[k]＝R[k]×FCW；
其中，TREF为输入锁相环的参考时钟信号的周期；R[k]为计数时间参数，是随当前时间k变化的正整数，k为正整数；所述FCW是锁相环的频率控制字信号，为已知量。
结合第二方面及上述任一种可能的实现方式中，在第四种可能的实现方式中，所述R[k]＝2k-1；
所述TCNT[k]＝TREF*R[k]＝TREF*2k-1；
所述FCNTTARGET[k]＝2k-1×FCW；
所述R[k]的最大取值为Rmax，当A＝fREF/fRES为2的整数次幂时，则Rmax＝A；当A不为2的整数次幂时，Rmax取大于A的2的整数次幂中的最小值；
其中，fREF＝1/TREF；fRES为锁相环的目标精度，为已知量。
结合第二方面及上述任一种可能的实现方式中，在第五种可能的实现方式中，所述锁相环包括：模拟整数锁相环、模拟小数锁相环、数字整数锁相环和数字小数锁相环。
以上技术方案，设置计数时间基准和目标频率计数值均是可变的，而现有技术中计数时间基准和目标频率计数值是固定不变的。由于频率的校正时间和校正精度是互相矛盾的，并且有很多子频带与目标频率值相差较大，因此，有些子频带不必花费很长时间来提高测量的精度，而在与目标频率值较近的子频带花费较长时间来提高测量的精度，从而可以获得校正后的精确频率。本实施例将测量的误差与预设值进行比较，从而控制是否增加计数时间基准，在校正时间和校正精度之间做出正确的取舍，从而有效控制校正时间，这种动态地校正方法整体上可以有效地缩短校正时间。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中二进制搜索法示意图；
图2是现有技术中的锁相环结构图；
图2a本发明提供的压控振荡器频率控制结构示意图；
图3是本发明提供的压控振荡器频率的控制曲线示意图；
图4a是本发明提供的锁相环频率校正方法实施例一流程图；
图4是本发明提供的锁相环频率校正方法实施例二流程图；
图5是现有技术中的频率计数器的工作原理示意图；
图6是本发明提供的锁相环频率校正方法实施例三流程图；
图7是本发明提供的二进制搜索算法示意图；
图8是本发明提供的子频带搜索示意图；
图9是本发明提供的频率计数器的工作原理示意图；
图10是本发明提供的锁相环频率校正设备实施例一示意图；
图11是本发明提供的锁相环频率校正设备实施例二示意图；
图11a是本发明提供的锁相环频率校正系统实施例一示意图；
图12是本发明提供的锁相环频率校正系统实施例二示意图；
图12a是本发明提供的锁相环频率校正系统为模拟小数锁相环时的示意图；
图12b是本发明提供的锁相环频率校正系统为数字小数锁相环时的示意图；
图12c是本发明提供的锁相环频率校正系统为另一种数字小数锁相环时的示意图；
图12d是本发明提供的锁相环频率校正系统为数字整数锁相环时的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
首先，为了本领域技术人员能够更好地理解本发明的工作原来，下面首先介绍锁相环的基本组成部分。
参见图2，该图为现有技术中的锁相环结构图。
锁相环包括四个基本组成部分：鉴相器A、环路滤波器B、压控振荡器C和反馈分频器D。其中，压控振荡器C作为频率源输出频率。
压控振荡器C的输出信号经过采集并分配和输入参考时钟的频率fREF一起被输入鉴相器A，鉴相器A通过比较fREF和压控振荡器的输出频率fVCO的差，输出一个与频率差成正比的误差电压，再经过环路滤波器B滤去误 差电压中的高频成分，输出一个控制电压控制压控振荡器C，使压控振荡器C输出信号的频率稳定在目标频率值，压控振荡器C的输出频率fVCO经过反馈分频器D分频后反馈信号fDIV给鉴相器A，作为输出频率的采样信号。
在射频收发信机中，锁相环中的压控振荡器C通常采用多子频带结构来实现，具体可以通过在压控振荡器C中并联一组可以开关的电容阵列，通过数字信号控制开关，从而改变电容阵列对外呈现的电容值，实现压控振荡器C频率范围的切换。其中，每个数字信号对应一个子频带。
这样可以通过粗调控制和精调控制两种方式控制压控振荡器C的输出频率。
粗调控制(CT，Coarse Tuning)：选择压控振荡器的子频带，确定压控振荡器的大致范围，通过数字信号来控制压控振荡器的子频带的选择，该数字信号用CT表示，即每个CT的取值对应压控振荡器的一个子频带。
精调控制(FT，Fine Tuning)：通过锁相环反馈机制，控制压控振荡器精确输出系统设定的目标频率值。
CT和FT通常在系统设定了目标频率值以后顺序执行。
参见图2a，该图为本发明提供的宽带压控振荡器频率控制结构示意图。
图中压控振荡器C为多子频带压控振荡器，其频带选择通过粗调控制信号(CT)实现，CT信号的取值通过本发明提供的自动频率校正方法获得。压控振荡器的精调控制信号(FT)则通过锁相环的反馈机制获得。
在图2中已经介绍了鉴相器A、环路滤波器B、压控振荡器C和反馈分频器D的工作原理，在此不再具体介绍。
其中，环路滤波器B输出的信号为LPF。
其中，CLK_REF信号为锁相环的输入参考时钟信号，在无线通信应用中，CLK_REF为一频率稳定的周期性信号。设其信号频率为fREF，其信号周期为
Figure PCTCN2015080447-appb-000003
F_VCO信号为锁相环输出信号，即压控振荡器的输出信号，其信号频率fVCO，其信号周期为
Figure PCTCN2015080447-appb-000004
FCW为锁相环的频率控制字信号(Frequency Control Word)，系统通过设定FCW的值来设置锁相环的输出目标频率值。
根据锁相环的工作原理，当锁相环稳定工作时，输出频率就是目标频率值fVCO＝fTARGET，存在以下关系：
fVCO＝fTARGET＝FCW×fREF  (1)
可以理解的是，FCW为已知量。
FCW区别于CT，FCW是锁相环中给反馈分频器D的。
CT是用来控制压控振荡器C的子频带的选择，CT是数字信号。
频率计数器E和算法逻辑模块F是用来进行锁相环频率校正的，E和F综合在一起为频率校正装置。
而校正偏置模块G是用来初始化的，初始化时，控制开关SW_CT控制校正偏置模块G输出的信号FT_BIAS给了FT，输出给压控振荡器C，设置CT初始值为中间子频带。例如，对于二进制搜索中的4位控制，中间子频带为1000。
需要说明的是，本发明实施例提供的方法是通过所述算法逻辑模块F来实现的。
参见图3，该图为本发明提供的压控振荡器频率的控制曲线示意图。
如图3所示，设定的目标频率值为fTARGET。
首先，选择合适的CT控制信号，如图中CT＝CT0；
然后，通过锁相环反馈机制获得合适的FT控制信号，如图3中FT＝FT0。
从图3可见，对于同一目标频率fTARGET，可以存在多个子频带能够同时覆盖，但是选择不同的子频带意味着精调控制FT值选择也会相应改变。如图3所示，CT＝CT0与CT＝CT1均能覆盖fTARGET，当选择CT＝CT0时，相应FT＝FT0；而当选择CT＝CT1时，相应FT＝FT1。
对于锁相环系统，为了系统稳定运行，通常需要将精调控制信号FT限制在一定的范围内，这个限制条件也给粗调控制信号CT的选择设置了约束条件。
如图3所示，假设系统设定的FT值目标范围区间如图3中斜线覆盖的范围，为了满足这个约束条件，系统只能选择CT＝CT0，而不能选择CT＝CT1。
由于芯片制造工艺存在波动，以及芯片的应用环境不确定，因此目标频率值与其对应的子频带的关系并不是固定不变的。
例如，对于相同的目标频率值fTARGET，在芯片样本A中，应该选择子频 带CT＝CT0，而在芯片样本B中，由于芯片制造工艺的波动，可能选择CT＝CT1最合适。
由于存在上述不确定的因素，因此在宽带锁相环中，需要专门设计一个装置，能够根据系统设定的目标频率值，通过该装置可以自动选择一个最佳的压控振荡器子频带，即选择最合适的粗调控制信号，该选择过程称为宽带锁相环的频率校正。
本发明中主要介绍通过CT来选择子频带，而CT的取值通过自动频率校正来实现。而FT信号通过锁相环的反馈机制来获得，在本发明中将不具体介绍。
本发明提供的方法可以缩短频率自动校正的时间，下面结合附图进行详细介绍。
方法实施例一：
参见图4a，该图为本发明提供的锁相环频率校正方法实施例一流程图。
本实施例提供的锁相环频率校正方法，应用于对多频带压控振荡器的子频带选择；包括：
S401a：在计数时间TCNT[k]内，对压控振荡器在当前工作子频带下输出的所述频率信号进行频率计数，得到频率计数值FCNT[k]，其中，当前工作子频带对应二进制搜索树中的当前节点的二进制数值；
需要说明的是，对压控振荡器在当前工作子频带下输出的所述频率信号进行频率技术是由频率计数器来完成的。
可以理解的是，对于多频带压控振荡器，其当前工作子频带指的是二进制搜索树中的当前节点对应的二进制数值，例如，对于16频带的压控振荡器，其节点CT＝12对应的二进制数值为1100。
需要说明的是，对于二进制搜索树，初始搜索的节点是从中间子频带对应的节点开始进行搜索，例如16频带的压控振荡器，初始搜索的节点是CT＝8(对应的二进制数值为1000)。
S402a：计算所述FCNT[k]与目标频率计数值FCNTTARGET[k]的误差，并将所述误差的绝对值与预定值进行比较，根据比较结果，在TCNT[k]的取值范围内动态调整所述TCNT[k]，并结合二进制搜索算法，确定所述压控振荡器工作的目标子频带。
本实施例中只所以设置计数时间和目标频率计数值是可以变化的，是 因为对于宽带压控振荡器，二进制搜索路径中大部分的子频带，仅仅需要判断频率计数器读取的计数值与目标频率的相对大小关系，而无需得到压控振荡器精确的输出频率。而对于少数与目标频率值接近的子频带，需要知道其精确的输出频率，频率计数器读取的计数值与目标频率值的差值将被作为子频率选择的依据，即测量精度将会影响最终的频率校正的结果。
由于频率测量精度和测量时间之间存在折中关系，因此，为了缩短频率校正时间可以在仅需要判断频率高低关系的子频带降低测量精度的要求，这样可以缩短在这些子频带的测量时间。而在测量精度要求高的子频率确保测量精度，来加长测量时间。因此，本实施例中这种动态调节频率测量精度的方法，既可以提高频率校正的效果，又没有损失校正的精度。
本实施例提供的锁相环频率校正方法，设置计数时间和目标频率计数值均是可变的，而现有技术中计数时间和目标频率计数值是固定不变的。由于频率的校正时间的校正精度是互相矛盾，并且有很多子频带与目标频率值相差较大，因此，有些子频带不必花费很长时间来提高测量的精度，而在与目标频率值较近的子频带花费较长时间来提高测量的精度，从而获得校正后的精确频率。本实施例将测量的误差与预设值进行比较，从而控制是否调整计数时间，从而有效控制校正时间，这种动态地校正方法整体上可以有效地缩短校正时间。
方法实施例二：
参见图4b，该图为本发明提供的锁相环频率校正方法实施例二流程图。
本实施例提供的宽带锁相环频率校正方法，包括：
S401：在当前计数时间TCNT[k]下，判断频率计数器输出的当前计数值FCNT[k]与对应的当前目标频率计数值FCNTTARGET[k]的误差是否小于预定值；所述频率计数器对压控振荡器的输出频率进行计数；所述TCNT[k]＝TREF*R[k]；所述FCNTTARGET[k]＝R[k]×FCW；所述压控振荡器为多频带压控振荡器；所述多频带压控振荡器中的子频带选择采用数字信号控制；即CT为数字信号。
其中，TREF为锁相环输入参考时钟的周期；R[k]为计数时间参数，是随当前时间k变化的正整数，k为正整数；所述FCW是频率控制字信号，为已知量；
需要说明的是，本实施例中计数时间和目标频率计数值均与R有关系， 因此这两个量并不是像现有技术中是固定不变的，而是变化的；而现有技术中计数时间是固定不变的，目标频率计数值也是固定不变的。
下面介绍频率计数器的工作原理。
频率计数器的功能是在计数时间内对压控振荡器的输出信号进行计数，如果计数时间是稳定的，则频率计数器输出的计数值可以表征压控振荡器的输出频率。
参见图5，该图为现有技术中的频率计数器的工作原理示意图。
需要说明的是，图5为现有技术中频率计数器的工作原理图，现有技术中计数时间TCNT为固定不变的。而本发明实施例中频率计数器的计数时间是变化的，即变为TCNT[k]。
压控振荡器的输出信号为F_VCO，F_VCO的频率为fVCO；
假设频率计数器的计数时间为TCNT，在TCNT内对F_VCO信号进行计数，也就是计算在TCNT时间范围内有多少个F_VCO周期，则可获得频率计数器的理想输出值FCNT'：
Figure PCTCN2015080447-appb-000005
从式(2)中可知，对于任意压控振荡器输出频率fVCO，都可以通过频率计数器得到一个与之相对应的计数值FCNT'。即在计数时间TCNT稳定的情况下，可用频率计数器的计数值FCNT'表征压控振荡器的输出频率fVCO，即通过频率计数器实现压控振荡器输出频率的测量：
Figure PCTCN2015080447-appb-000006
从图4所示的频率计数器工作原理可知，频率计数器输出的计数值FCNT仅能取整数，因此频率计数器输出的计数值存在量化误差。为获得频率计数器的输出值，式(2)需修正为：
Figure PCTCN2015080447-appb-000007
上式(4)中，ROUND函数表示四舍五入操作。
设频率计数器输出量化误差为EQUAT，则
FCNT'＝FCNT+EQUAT  (5)
从图4及式(4)可知，频率计数器输出量化误差的范围为：
ABS(EQUAT)≤1  (6)
上式(6)中，ABS函数表示取绝对值操作。
根据式(3)、(5)和(6)，可得到由于频率计数器量化误差引入的压控振荡器频率测量误差为：
fRES＝ABS((FCNT-FCNT')×fCNT)
＝ABS(EQUAT×fCNT)  (7)
≤fCNT
即由频率计数器量化误差引入的压控振荡器频率测量误差与频率计数器计数时间相关。从式(7)可知，频率计数器的计数时间越长，压控振荡器频率测量的误差越小，即频率计数器输出的FCNT所反映的压控振荡器输出频率越接近压控振荡器的实际输出频率。
由于在锁相环系统中，通常仅有输入参考时钟CLK_REF为稳定频率信号。因此，频率计数器通常采用CLK_REF来产生计数时间。即：
TCNT＝R×TREF(R∈正整数)  (8)
即频率计数器的计数时间通常为参考时钟周期的整数倍。根据式(7)和(8)可得：
Figure PCTCN2015080447-appb-000008
(R∈正整数)  (9)
需要说明的是，公式(8)和(9)中的R是现有技术中的计数时间参数，在现有技术中，R是固定的，而本发明实施例中R是变化的，即变为R[k]。
显然，式(8)中R值取值越大，得到的频率计数器输出的计数值越能精确的反映压控振荡器的实际频率，即频率测量越精确。从整个校正过程来看，压控振荡器频率测量越精确，则最终获得的校正精度越高。但是R值取值越大，也意味着频率测量的时间越长。从整个校正过程来看，单次频率测量的时间越长，意味着整个校正过程消耗的时间越长，或者说校正效率越低。
由于频率计数器存在量化特性，导致宽带锁相环频率校正机制在精度和效率上存在难以克服的矛盾关系。而本实施例采用的方法，是在距离目标频率值差值较大的子频带，采用较短的计数时间来缩短校正时间；但在距离目标频率值较小的子频带，采用较长的计数时间来确保校正精度。
S402：如果判断所述误差为0，将当前子频带作为所述压控振荡器工作的目标子频带；
S403：如果判断所述误差大于0且小于预定值，则增大计数时间基准TCNT[k]继续读取压控振荡器在当前子频带输出的频率信号进行频率计数的频率计数值，计算新读取的所述频率计数值与所述FCNTTARGET[k]的误差，如果误差为0，则将当前子频带作为压控振荡器工作的目标子频带，如果误差不为0，继续进行所述误差与所述预定值的比较，一直增大TCNT[k]到TCNT[k]的取值范围内的最大值时，强制进入二进制搜索的下一个子频带；二进制搜索结束时，将所述误差最小值对应的子频带作为所述压控振荡器工作的目标子频带；
可以理解的是，当所述误差为零时，说明已经达到目标子频带，可以不必再往下进一步进行子频带的搜索，直接将当前子频带作为目标子频带即可。
需要说明的是，预定值为预先设定的一个阈值，如果当前计数值与当前的目标频率计数值之间的误差小于预定值，则说明当前的子频带与目标频率值比较接近，需要获得更精确的频率计数值，通过增大计数时间则能提高精度，此时就要牺牲测量时间。
S404：如果判断所述误差大于或等于预定值，则停止频率计数器对当前子频带对应的压控振荡器的输出频率的计数，进入二进制搜索的下一个子频带。
如果判断当前计数值与当前的目标频率计数值之间的误差大于或等于预定值，则说明当前的子频带与目标频率值较远，不需要在该子频率浪费太多的时间继续进行测量，因此，可以直接进入下一个子频带的测量。这样可以大大地缩短校正时间。
需要说明的是，如何进入下一个子频带的步骤本身属于现有技术，具体为：
当所述频率计数值大于所述目标频率计数值时，则在二进制搜索路径上选择节点的二进制数值比当前工作子频带小的子频带作为下一个子频带；
当所述频率计数值小于所述目标频率计数值时，则在二进制搜索路径上选择节点的二进制数值比当前工作子频带大的子频带作为下一个子频 带。
图7中中可以看出，在二进制搜索树上有除了数值为0的节点，15个节点。在二进制搜索路径中，下一个节点对应的二进制数值可能大于前一个节点，也可能小于前一个节点，例如，当前节点是CT＝12，那么当前节点的下一个节点有2个，分别是CT＝10和CT＝14。如果频率计数值大于目标频率计数值，则选择CT＝10作为下一个子频带；如果频率计数值小于目标频率计数值，则选择CT＝14作为下一个子频带。
可以理解的是，二进制搜索结束指的是，搜索路径结束，例如图1中的，搜索到路径的最底层。
本实施例提供的宽带锁相环频率校正方法，设置计数时间和目标频率计数值均是可变的，而现有技术中计数时间和目标频率计数值是固定不变的。由于频率的校正时间的校正精度是互相矛盾，并且有很多子频带与目标频率值相差较大，因此，有些子频带不必花费很长时间来提高测量的精度，而在与目标频率值较近的子频带花费较长时间来提高测量的精度，从而获得校正后的精确频率。本实施例将测量的误差与预设值进行比较，从而控制是否增加计数时间，从而有效控制校正时间，这种动态地校正方法整体上可以有效地缩短校正时间。
方法实施例三：
参见图6，该图为本发明提供的锁相环频率校正方法实施例三流程图。
本实施例介绍一个最完整的校正过程。
在方法实施例一中已经介绍R[k]为正整数，由于在实际应用中，为了实现方便，可以设置R[k]为2的整数次幂的形式，因为在逻辑电路中，仅仅需要进行移位操作，便可以实现2的整数次幂的计算，这样可以大大降低对芯片资源的消耗。因此，本实施例中，R[k]以2的整数次幂来实现。
S601：在当前计数时间TCNT[k]下，读取频率计数器的当前计数值FCNT[k]；
S602：计算当前目标频率计数值FCNTTARGET[k]；S603：由FCNT[k]和FCNTTARGET[k]获得两者的误差FCNTERR＝FCNT[k]-FCNTTARGET[k]；
S604：判断所述误差FCNTERR是否小于预定值，如果是，则执行S605，如果否则执行S607：
S605：增大计数时间，即k加1，TCNT[k]变为TCNT[k+1]；
需要说明的是，此时，与k有关的数值均跟随变化。
S606：判断所述R[k]是否已经到达最大值，如果是，则强制进入二进制搜索的下一个子频带，即执行S607。
由于k变化时，R[k]也跟随变化，并且R[k]＝2k-1；所述R[k]的最大取值为Rmax，当A＝fREF/fRES为2的整数次幂时，则Rmax＝A；当A不为2的整数次幂时，Rmax取大于A的2的整数次幂中的最小值；
其中，fREF＝1/TREF；fRES为锁相环的目标精度，为已知量。
S607：结束对当前子频带的测量；
S608：判断二进制搜索是否结束，如果是，则执行S609，如果否，则执行S610；
二进制搜索结束指的是搜索到二进制搜索树的最底层，即最下边一层。
S609：选择误差FCNTERR最小值对应的子频带，通过控制开关SW_CT将FT＝LPF。
S610：根据二进制搜索算法更新CT值，即切换到下一个子频带进行频率的测量。
S611：如果所述二进制搜索结束，则将所述误差的最小值对应的子频带作为所述压控振荡器工作的子频带。
为了更好地理解本实施例提供的方法，下面结合一个具体实例来说明，继续以NCT为4，即16频带为例来说明。
参见图7，该图为本发明提供的二进制搜索算法示意图。
从中间子频带(CT＝1000)开始，即从CT＝8开始。
频率计数器对该子频带下压控振荡器的输出频率进行计数，得到计数值(FCNT)CT＝8，假设fTARGET对应的计数值为FCNTTARGET，如果
(FCNT)CT＝8＜FCNTTARGET  (10)
通过公式(10)可知当前计数值低于目标频率值。
因此，按照二进制搜索算法，即图7中上行搜索(up)路径，将待测量子频带调整为CT＝12。
在CT＝12的子频带上，将重复上述测量、比较、搜索过程，直至搜索到图7中的最底一层，即奇数层。
在此搜索过程中，CT＝0子频带没有测量。通常压控振荡器设计中，会 设计一定的裕量，即CT＝0设计冗余，不在系统需求范围内，可以不测量，以节省校正时间。
在二进制搜索路径的每个节点，即每个子频带，都会通过频率计数器测量压控振荡器在相应子频带的频率，对应的计数值与目标频率计数值的差值被储存，最终测得差值最小的子频带将被作为选定的子频带。
对于图7所示的4位，即16子频带的压控振荡器，共要进行4次测量。子频带越多，所需要的测量时间越长。
锁相环的目标频率值fTARGET对应一个频率计数器的计数值FCNTTARGET，根据公式(2)与公式(8)可得：
Figure PCTCN2015080447-appb-000009
即通过锁相环的频率控制字信号FCW，可以直接获得频率计数器的目标频率计数值。
图7中对应的理论上最优的子频带为CT＝13，参见图8，该图为子频带搜索示意图。
图中用弧线给出了二进制搜索的路径，即CT＝8→CT＝12→CT＝14→CT＝13。在上述路径中的每个子频带，都会通过频率计数器对该子频带对应的压控振荡器的输出频率进行技术，并将计数值与目标计数值进行比较，并对搜索路径进行判断。
从图8中可以看出，各子频带对应的计数值与目标计数值的差值并不相同。在图8示例中，(Δf)CT＝0,1,2,...表示各个子频带(CT＝0，1，2，…)对应的压控振荡器输出频率与目标频率值的差值。
从图8可以看出，存在：
(Δf)CT＝8＞(Δf)CT＝12＞(Δf)CT＝13＞(Δf)CT＝14  (12)
在子频带CT＝8、CT＝12，测得频率距离目标频率值较远，即(Δf)CT＝8、(Δf)CT＝12相对较大，因此仅仅需要判断其与目标频率值的相对大小关系，不需要精确测量频率。
而在子频带CT＝13，CT＝14，其测得频率与目标频率值相对接近，因此需要比较精确的对频率进行测量，并根据测量结果选择最终的校正结果。
需要说明的是，本实施例中是以16频带为例进行说明的，可以理解的 是，当子频带数目越多时，本发明实施例提供的方法的优点将更加明显，即相对缩短的校正时间将更长。
即，所述多频带压控振荡器的子频带数目NCT＝2m，m为正整数。即子频带的数目可以为2的整数次幂。
可以理解的是，由于k为正整数，在R[k]＝2k-1中，k最小的取值为1，即R[1]＝20＝1。k的取值越大，则频率计数器的频率测量精度越高，但对应的时间会越长；k的取值越小，则频率计数器的频率测量精度越低，但对应的时间越短。
下面结合图9说明本发明提供的动态频率校正中的计数时间是动态调节的。
由于k值变化的，因此，本实施例中可以应用一个频率计数器完成多个不同计数时间下的频率的计数测量，并不需要多个频率计数器，也不需要进行多次的测量。
从图9中可以看出，TCNT[1]＝TREF；TCNT[2]＝2*TREF；TCNT[3]＝4*TREF；
需要说明的是，本发明以上实施例提供的方法适用于模拟整数锁相环、模拟小数锁相环、数字整数锁相环和数字小数锁相环。
本实施例提供的频率校正方法，各个子频带对应的频率计数器的计数时间是动态可变的，对于距离目标频率值的差值较大的子频带，采用较短的计数时间这样可以实现快速判断，对于距离目标频率值的差值较小的子频带，采用较长的计数时间这样可以确保校正精度。由于计数时间参数采用2的整数次幂的形式，这样对于硬件上没有额外的消耗，容易实现。
基于以上实施例提供的一种锁相环的频率校正方法，本发明实施例还提供一种锁相环的频率校正设备，下面结合附图来进行详细的说明。
参见图10，该图为本发明提供的锁相环频率校正设备实施例一示意图。
本实施例提供的宽带锁相环频率校正设备，包括：第一判断模块100、计数时间更新模块200、子频带更新模块300和第二判断模块100a；
第一判断模块100，用于在当前计数时间TCNT[k]下，判断频率计数器输出的当前计数值FCNT[k]与对应的当前目标频率计数值FCNTTARGET[k]的误差是否小于预定值；所述频率计数器对压控振荡器的输出频率进行计数；所述压控振荡器为多频带压控振荡器；所述多频带压控振荡器中的子频带选 择采用数字信号控制；
所述TCNT[k]＝TREF*R[k]；所述FCNTTARGET[k]＝R[k]×FCW；
其中，TREF为锁相环输入参考时钟的周期；R[k]为计数时间参数，是随当前时间k变化的正整数，k为正整数；所述FCW是锁相环的频率控制字信号，为已知量；
需要说明的是，本实施例中计数时间和目标频率计数值均与R有关系，因此这两个量并不是像现有技术中是固定不变的，而是变化的；而现有技术中计数时间是固定不变的，目标频率计数值也是固定不变的。
本实施例中只所以设置计数时间和目标频率计数值是可以变化的，是因为对于宽带压控振荡器，二进制搜索路径中大部分的子频带，仅仅需要判断频率计数器读取的计数值与目标频率的相对大小关系，而无需得到压控振荡器精确的输出频率。而对于少数与目标频率值接近的子频带，需要知道其精确的输出频率，频率计数器读取的计数值与目标频率值的差值将被作为子频率选择的依据，即测量精度将会影响最终的频率校正的结果。
由于频率测量精度和测量时间之间存在折中关系，因此，为了缩短频率校正时间可以在仅需要判断频率高低关系的子频带降低测量精度的要求，这样可以缩短在这些子频带的测量时间。而在测量精度要求高的子频率确保测量精度，来加长测量时间。因此，本实施例中这种动态调节频率测量精度的方法，既可以提高频率校正的效果，又没有损失校正的精度。
下面介绍频率计数器的工作原理。
频率计数器的功能是在计数时间内对压控振荡器的输出信号进行计数，如果计数时间是稳定的，则频率计数器输出的计数值可以表征压控振荡器的输出频率。
计数时间更新模块200，用于在所述第一判断模块100判断所述误差小于预定值时，增大计数时间继续读取频率计数器输出的计数值；
需要说明的是，预定值为预先设定的一个阈值，如果当前计数值与当前的目标频率计数值之间的误差小于预定值，则说明当前的子频带与目标频率值比较接近，需要获得更精确的频率计数值，通过增大计数时间则能提高精度，此时就要牺牲测量时间。
子频带更新模块300，用于在所述第一判断模块100判断所述误差大于或等于预定值时，停止频率计数器对当前子频带对应的压控振荡器的输出 频率的计数，进入二进制搜索的下一个子频带。
如果判断当前计数值与当前的目标频率计数值之间的误差大于或等于预定值，则说明当前的子频带与目标频率值较远，不需要在该子频率浪费太多的时间继续进行测量，因此，可以直接进入下一个子频带的测量。这样可以大大地缩短校正时间。
所述第二判断模块100a，用于判断所述二进制搜索结束，则将所述误差的最小值对应的子频带作为所述压控振荡器工作的子频带。
需要说明的是，二进制搜索结束指的是搜索路径上的子频带搜索完了，例如图1中的对底层。
本实施例提供的宽带锁相环频率校正设备，设置计数时间和目标频率计数值均是可变的，而现有技术中计数时间和目标频率计数值是固定不变的。由于频率的校正时间的校正精度是互相矛盾，并且有很多子频带与目标频率值相差较大，因此，有些子频带不必花费很长时间来提高测量的精度，而在与目标频率值较近的子频带花费较长时间来提高测量的精度，从而获得校正后的精确频率。本实施例将测量的误差与预设值进行比较，从而控制是否增加计数时间，从而有效控制校正时间，这种动态地校正方法整体上可以有效地缩短校正时间。
设备实施例二：
参见图11，该图为本发明提供的宽带锁相环频率校正设备实施例二示意图。
R[k]为正整数，由于在实际应用中，为了实现方便，可以设置R[k]为2的整数次幂的形式，因为在逻辑电路中，仅仅需要进行移位操作，便可以实现2的整数次幂的计算，这样可以大大降低对芯片资源的消耗。因此，本实施例中，R[k]以2的整数次幂来实现。
即所述R[k]＝2k-1；所述TCNT[k]＝TREF*2k-1；所述FCNTTARGET[k]＝2k-1×FCW；所述R[k]的最大取值为：Rmax＝2k-1≥fREF/fRES；
其中，fREF锁相环输入参考时钟的频率fREF＝1/TREF；fRES为锁相环的目标精度，为已知量。
本实施例提供的宽带锁相环频率校正设备，还可以包括：最大值判断模块400；
所述最大值判断模块400，用于判断所述R[k]是否已经到达最大值，如果是，则所述子频带更新模块300强制进入二进制搜索的下一个子频带。
本实施例提供的频率校正设备，各个子频带对应的频率计数器的计数时间是动态可变的，对于距离目标频率值的差值较大的子频带，采用较短的计数时间这样可以实现快速判断，对于距离目标频率值的差值较小的子频带，采用较长的计数时间这样可以确保校正精度。由于计数时间参数采用2的整数次幂的形式，这样对于硬件上没有额外的消耗，容易实现。
基于以上实施例提供的一种锁相环的频率校正方法，本发明实施例还提供一种锁相环频率校正系统，下面结合附图来进行详细的说明。
系统实施例一：
参见图11a，该图为本发明提供的锁相环频率校正系统实施例一示意图。
本实施例提供的锁相环频率校正系统，包括：锁相环1000、频率计数器E、控制器1200，所述锁相环1000包括多频带的压控振荡器；
所述锁相环1000，用于根据输入的参考时钟信号，控制所述压控振荡器输出频率信号；
所述频率计数器E，用于在计数时间TCNT[k]内，对所述压控振荡器在当前工作子频带下输出的所述频率信号进行频率计数，得到频率计数值FCNT[k]，其中，当前工作子频带对应二进制搜索树中的当前节点的二进制数值；
可以理解的是，对于多频带压控振荡器，其当前工作子频带指的是二进制搜索树中的当前节点对应的二进制数值，例如，对于16频带的压控振荡器，其节点CT＝12对应的二进制数值为1100。
需要说明的是，对于二进制搜索树，初始搜索的节点是从中间子频带对应的节点开始进行搜索，例如16频带的压控振荡器，初始搜索的节点是CT＝8(对应的二进制数值为1000)。
所述控制器1200，用于计算所述FCNT[k]与目标频率计数值FCNTTARGET[k]的误差，并将所述误差的绝对值与预定值进行比较，根据比较结果，在TCNT[k]的取值范围内动态调整所述TCNT[k]，并结合二进制搜索算法，确定所述压控振荡器工作的目标子频带。
本实施例中只所以设置计数时间和目标频率计数值是可以变化的，是因为对于宽带压控振荡器，二进制搜索路径中大部分的子频带，仅仅需要判断频率计数器读取的计数值与目标频率的相对大小关系，而无需得到压控振荡器精确的输出频率。而对于少数与目标频率值接近的子频带，需要知道其精确的输出频率，频率计数器读取的计数值与目标频率值的差值将被作为子频率选择的依据，即测量精度将会影响最终的频率校正的结果。
由于频率测量精度和测量时间之间存在折中关系，因此，为了缩短频率校正时间可以在仅需要判断频率高低关系的子频带降低测量精度的要求，这样可以缩短在这些子频带的测量时间。而在测量精度要求高的子频率确保测量精度，来加长测量时间。因此，本实施例中这种动态调节频率测量精度的方法，既可以提高频率校正的效果，又没有损失校正的精度。
本实施例提供的锁相环频率校正系统，设置计数时间和目标频率计数值均是可变的，而现有技术中计数时间和目标频率计数值是固定不变的。由于频率的校正时间的校正精度是互相矛盾，并且有很多子频带与目标频率值相差较大，因此，有些子频带不必花费很长时间来提高测量的精度，而在与目标频率值较近的子频带花费较长时间来提高测量的精度，从而获得校正后的精确频率。本实施例将测量的误差与预设值进行比较，从而控制是否调整计数时间，从而有效控制校正时间，这种动态地校正方法整体上可以有效地缩短校正时间。
系统实施例二：
参见图12，该图为本发明提供的锁相环频率校正系统实施例二示意图。
本实施例提供的锁相环频率校正系统中的锁相环包括：鉴相器A、环路滤波器B、压控振荡器C、反馈分频器D；
所述压控振荡器C为多频带压控振荡器，所述多频带压控振荡器中的子频带选择采用数字信号控制；
所述子频带对应的是二进制搜索树中节点对应的二进制数值。
所述鉴相器A，用于将目标频率值与采集的压控振荡器C的输出频率进行比较，获得频率误差，输出与所述频率误差成正比的误差电压，将所述误差电压输出给所述环路滤波器B；
所述环路滤波器B，用于滤除所述误差电压中的高频信号，输出控制电 压给所述压控振荡器C；
所述压控振荡器C，用于在所述控制电压下输出目标频率值；
所述频率计数器E，用于在当前计数时间TCNT[k]下，对压控振荡器C的输出频率进行计数，输出当前计数值FCNT[k]给所述控制器1200；
所述TCNT[k]＝TREF*R[k]；
其中，TREF为输入锁相环的参考时钟信号的周期；R[k]为计数时间参数，是随当前时间k变化的正整数，k为正整数；所述FCW是锁相环的频率控制字信号，为已知量。
需要说明的是，本实施例中计数时间和目标频率计数值均与R有关系，因此这两个量并不是像现有技术中是固定不变的，而是变化的；而现有技术中计数时间是固定不变的，目标频率计数值也是固定不变的。
本实施例中只所以设置计数时间和目标频率计数值是可以变化的，是因为对于宽带压控振荡器，二进制搜索路径中大部分的子频带，仅仅需要判断频率计数器读取的计数值与目标频率的相对大小关系，而无需得到压控振荡器精确的输出频率。而对于少数与目标频率值接近的子频带，需要知道其精确的输出频率，频率计数器读取的计数值与目标频率值的差值将被作为子频率选择的依据，即测量精度将会影响最终的频率校正的结果。
由于频率测量精度和测量时间之间存在折中关系，因此，为了缩短频率校正时间可以在仅需要判断频率高低关系的子频带降低测量精度的要求，这样可以缩短在这些子频带的测量时间。而在测量精度要求高的子频率确保测量精度，来加长测量时间。因此，本实施例中这种动态调节频率测量精度的方法，既可以提高频率校正的效果，又没有损失校正的精度。
下面介绍频率计数器的工作原理。
频率计数器的功能是在计数时间内对压控振荡器的输出信号进行计数，如果计数时间是稳定的，则频率计数器输出的计数值可以表征压控振荡器的输出频率。
所述控制器1200，用于所述控制器根据比较结果，在TCNT[k]的取值范围内动态调整所述TCNT[k]，并结合二进制搜索算法，确定所述压控振荡器工作的目标子频带，具体为：
如果判断所述误差为0，将当前子频带作为所述压控振荡器工作的目标子频带；
如果判断所述误差大于0且小于预定值，则增大计数时间基准TCNT[k]继续读取压控振荡器在当前子频带输出的频率信号进行频率计数的频率计数值，计算新读取的所述频率计数值与所述FCNTTARGET[k]的误差，如果误差为0，则将当前子频带作为压控振荡器工作的目标子频带，如果误差不为0，继续进行所述误差与所述预定值的比较，一直增大TCNT[k]到TCNT[k]的取值范围内的最大值时，强制进入二进制搜索的下一个子频带；二进制搜索结束时，将所述误差最小值对应的子频带作为所述压控振荡器工作的目标子频带；
所述FCNTTARGET[k]＝R[k]×FCW；
从TCNT[k]和FCNTTARGET[k]的表达式中可以看出，TCNT[k]和FCNTTARGET[k]均是随着k来变化的，不是固定不变的。
如果判断所述误差大于或等于预定值，则停止对当前子频带对应的压控振荡器的输出频率的计数，进入二进制搜索的下一个子频带。
需要说明的是，如何进入下一个子频带的步骤本身属于现有技术，具体为：
所述控制器用于进入二进制搜索的下一个子频带，具体为：
当所述频率计数值大于所述目标频率计数值时，则在二进制搜索路径上选择节点的二进制数值比当前工作子频带小的子频带作为下一个子频带；
当所述频率计数值小于所述目标频率计数值时，则在二进制搜索路径上选择节点的二进制数值比当前工作子频带大的子频带作为下一个子频带。
图7中中可以看出，在二进制搜索树上有除了数值为0的节点，15个节点。在二进制搜索路径中，下一个节点对应的二进制数值可能大于前一个节点，也可能小于前一个节点，例如，当前节点是CT＝12，那么当前节点的下一个节点有2个，分别是CT＝10和CT＝14。如果频率计数值大于目标频率计数值，则选择CT＝10作为下一个子频带；如果频率计数值小于目标频率计数值，则选择CT＝14作为下一个子频带。
需要说明的是，所述二进制搜索结束指的是搜索路径结束，即搜索到路径的最后一个子频带，例如图1中的最底层。
需要说明的是，预定值为预先设定的一个阈值，如果当前计数值与当 前的目标频率计数值之间的误差小于预定值，则说明当前的子频带与目标频率值比较接近，需要获得更精确的频率计数值，通过增大计数时间则能提高精度，此时就要牺牲测量时间。
如果判断当前计数值与当前的目标频率计数值之间的误差大于或等于预定值，则说明当前的子频带与目标频率值较远，不需要在该子频率浪费太多的时间继续进行测量，因此，可以直接进入下一个子频带的测量。这样可以大大地缩短校正时间。
图12中校正偏置模块是现有技术，用于在初始化时，控制FT＝FT_BIAS，设置CT到二进制搜索树中的中间子频带。对于16频带时，初始搜索节点就是CT＝8(对应的二进制数值为1000)。
本实施例提供的锁相环频率校正系统，设置计数时间和目标频率计数值均是可变的，而现有技术中计数时间和目标频率计数值是固定不变的。由于频率的校正时间的校正精度是互相矛盾，并且有很多子频带与目标频率值相差较大，因此，有些子频带不必花费很长时间来提高测量的精度，而在与目标频率值较近的子频带花费较长时间来提高测量的精度，从而获得校正后的精确频率。本实施例将测量的误差与预设值进行比较，从而控制是否增加计数时间，从而有效控制校正时间，这种动态地校正方法整体上可以有效地缩短校正时间。
系统实施例三：
R[k]为正整数，由于在实际应用中，为了实现方便，可以设置R[k]为2的整数次幂的形式，因为在逻辑电路中，仅仅需要进行移位操作，便可以实现2的整数次幂的计算，这样可以大大降低对芯片资源的消耗。因此，本实施例中，R[k]以2的整数次幂来实现。
所述R[k]＝2k-1；
所述TCNT[k]＝TREF*R[k]＝TREF*2k-1；
所述FCNTTARGET[k]＝2k-1×FCW；
所述R[k]的最大取值为Rmax，当A＝fREF/fRES为2的整数次幂时，则Rmax＝A；当A不为2的整数次幂时，Rmax取大于A的2的整数次幂中的最小值；
其中，fREF＝1/TREF；fRES为锁相环的目标精度，为已知量。
需要说明的是，本发明以上实施例提供的锁相环可以为多种类型，例如：模拟整数锁相环、模拟小数锁相环、数字整数锁相环和数字小数锁相环。
例如，图12所示的便是模拟整数锁相环，即鉴相器A、环路滤波器B、压控振荡器C和反馈分频器D都工作在模拟信号域，且该锁相环的FCW为正整数。
另外，本发明中的锁相环还可以为模拟小数锁相环(Fractional-N PLL)，参见图12a，即鉴相器A、环路滤波器B、压控振荡器C和反馈分频器D都工作在模拟信号域，且该锁相环的FCW为正数有理数。
图12a中比图12中多了Sigma-Delta调制器M。
另外，本发明中的锁相环还可以为数字整数锁相环(Digital Fractional-N PLL)，参见图12b，即锁相环内时间数字转换器A1将相位信息转换为数字信号，并通过数字滤波器B1处理数字化后的相位误差信息，并通过数字信号控制数控振荡器C1输出期望的频率信号。该锁相环的频率控制字FCW为一正数有理数。
图12b中也比图12中多了Sigma-Delta调制器M。
另外，本发明中的锁相环还可以为另外一种形式的数字小数锁相环，区别于图12b中的锁相环，图12c中的这种适合于高频场合。即采用预分频器的高频数字小数锁相环。其他部分与图12b相同，在此不再赘述。
在射频应用中，数控振荡器C1输出频率比较高，而频率计数器E无法直接对数控振荡器C1的输出频率进行频率计数。这种情况下，需要在数控振荡器C1之后加入一个预分频H，将数控振荡器C1的输出频率降频到频率计数器E能够处理的范围。
另外，本发明还提供了数字整数锁相环，参见图12d。图12d与图12a的区别是省掉了Sigma-Delta调制器，因数是数字整数锁相环，因此不需要Sigma-Delta调制器。
本发明以上实施例提供的频率校正方法、设备和系统可以显著缩短校正时间，并且不影响校正精度的要求。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制。虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发 明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (11)

  1. 一种锁相环频率校正方法，其特征在于，应用于对多频带压控振荡器的子频带选择；包括：
    在计数时间TCNT[k]内，对压控振荡器在当前工作子频带下输出的所述频率信号进行频率计数，得到频率计数值FCNT[k]，其中，当前工作子频带对应二进制搜索树中的当前节点的二进制数值；
    计算所述FCNT[k]与目标频率计数值FCNTTARGET[k]的误差，并将所述误差的绝对值与预定值进行比较，根据比较结果，在TCNT[k]的取值范围内动态调整所述TCNT[k]，并结合二进制搜索算法，确定所述压控振荡器工作的目标子频带。
  2. 根据权利要求1所述的锁相环频率校正方法，其特征在于，所述根据比较结果，在TCNT[k]的取值范围内动态调整所述TCNT[k]，并结合二进制搜索算法，确定所述压控振荡器工作的目标子频带，具体为：
    如果判断所述误差为0，将当前子频带作为所述压控振荡器工作的目标子频带；
    如果判断所述误差大于0且小于预定值，则增大计数时间基准TCNT[k]继续读取压控振荡器在当前子频带输出的频率信号进行频率计数的频率计数值，计算新读取的所述频率计数值与所述FCNTTARGET[k]的误差，如果误差为0，则将当前子频带作为压控振荡器工作的目标子频带，如果误差不为0，继续进行所述误差与所述预定值的比较，一直增大TCNT[k]到TCNT[k]的取值范围内的最大值时，强制进入二进制搜索的下一个子频带；二进制搜索结束时，将所述误差最小值对应的子频带作为所述压控振荡器工作的目标子频带；
    如果判断所述误差大于或等于预定值，则停止对当前子频带对应的压控振荡器的输出频率的计数，进入二进制搜索的下一个子频带。
  3. 根据权利要求2所述的锁相环频率校正方法，其特征在于，所述进入二进制搜索的下一个子频带，具体为：
    当所述频率计数值大于所述目标频率计数值时，则在二进制搜索路径上选择节点的二进制数值比当前工作子频带小的子频带作为下一个子频带；
    当所述频率计数值小于所述目标频率计数值时，则在二进制搜索路径 上选择节点的二进制数值比当前工作子频带大的子频带作为下一个子频带。
  4. 根据权利要求1或2所述的锁相环频率校正方法，其特征在于，所述TCNT[k]＝TREF*R[k]；所述FCNTTARGET[k]＝R[k]×FCW；
    其中，TREF为输入锁相环的参考时钟信号的周期；R[k]为计数时间参数，是随当前时间k变化的正整数，k为正整数；所述FCW是锁相环的频率控制字信号，为已知量。
  5. 根据权利要求4所述的锁相环频率校正方法，其特征在于，所述R[k]＝2k-1；
    所述TCNT[k]＝TREF*R[k]＝TREF*2k-1；
    所述FCNTTARGET[k]＝2k-1×FCW；
    所述R[k]的最大取值为Rmax，当A＝fREF/fRES为2的整数次幂时，则Rmax＝A；当A不为2的整数次幂时，Rmax取大于A的2的整数次幂中的最小值；
    其中，fREF＝1/TREF；fRES为锁相环的目标精度，为已知量。
  6. 一种锁相环频率校正系统，其特征在于，包括：锁相环、频率计数器、控制器，所述锁相环包括多频带的压控振荡器；
    所述锁相环，用于根据输入的参考时钟信号，控制所述压控振荡器输出频率信号；
    所述频率计数器，用于在计数时间TCNT[k]内，对所述压控振荡器在当前工作子频带下输出的所述频率信号进行频率计数，得到频率计数值FCNT[k]，其中，当前工作子频带对应二进制搜索树中的当前节点的二进制数值；
    所述控制器，用于计算所述FCNT[k]与目标频率计数值FCNTTARGET[k]的误差，并将所述误差的绝对值与预定值进行比较，根据比较结果，在TCNT[k]的取值范围内动态调整所述TCNT[k]，并结合二进制搜索算法，确定所述压控振荡器工作的目标子频带。
  7. 根据权利要求6所述的锁相环频率校正系统，其特征在于，所述控制器根据比较结果，在TCNT[k]的取值范围内动态调整所述TCNT[k]，并结合二进制搜索算法，确定所述压控振荡器工作的目标子频带，具体为：
    如果判断所述误差为0，将当前子频带作为所述压控振荡器工作的目标 子频带；
    如果判断所述误差大于0且小于预定值，则增大计数时间基准TCNT[k]继续读取压控振荡器在当前子频带输出的频率信号进行频率计数的频率计数值，计算新读取的所述频率计数值与所述FCNTTARGET[k]的误差，如果误差为0，则将当前子频带作为压控振荡器工作的目标子频带，如果误差不为0，继续进行所述误差与所述预定值的比较，一直增大TCNT[k]到TCNT[k]的取值范围内的最大值时，强制进入二进制搜索的下一个子频带；二进制搜索结束时，将所述误差最小值对应的子频带作为所述压控振荡器工作的目标子频带；
    如果判断所述误差大于或等于预定值，则停止对当前子频带对应的压控振荡器的输出频率的计数，进入二进制搜索的下一个子频带。
  8. 根据权利要求7所述的锁相环频率校正系统，其特征在于，所述控制器用于进入二进制搜索的下一个子频带，具体为：
    当所述频率计数值大于所述目标频率计数值时，则在二进制搜索路径上选择节点的二进制数值比当前工作子频带小的子频带作为下一个子频带；
    当所述频率计数值小于所述目标频率计数值时，则在二进制搜索路径上选择节点的二进制数值比当前工作子频带大的子频带作为下一个子频带。
  9. 根据权利要求6-8任一项所述的锁相环频率校正系统，其特征在于，所述TCNT[k]＝TREF*R[k]；所述FCNTTARGET[k]＝R[k]×FCW；
    其中，TREF为输入锁相环的参考时钟信号的周期；R[k]为计数时间参数，是随当前时间k变化的正整数，k为正整数；所述FCW是锁相环的频率控制字信号，为已知量。
  10. 根据权利要求9所述的锁相环频率校正系统，其特征在于，所述R[k]＝2k-1；
    所述TCNT[k]＝TREF*R[k]＝TREF*2k-1；
    所述FCNTTARGET[k]＝2k-1×FCW；
    所述R[k]的最大取值为Rmax，当A＝fREF/fRES为2的整数次幂时，则Rmax＝A；当A不为2的整数次幂时，Rmax取大于A的2的整数次幂中的最小值；
    其中，fREF＝1/TREF；fRES为锁相环的目标精度，为已知量。
  11. 根据权利要求6所述的锁相环频率校正系统，其特征在于，所述锁相环包括：模拟整数锁相环、模拟小数锁相环、数字整数锁相环和数字小数锁相环。
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