WO2014061760A1

WO2014061760A1 - Method for forming pattern and method for producing device

Info

Publication number: WO2014061760A1
Application number: PCT/JP2013/078243
Authority: WO
Inventors: 陽司渡邉
Original assignee: 株式会社ニコン
Priority date: 2012-10-19
Filing date: 2013-10-17
Publication date: 2014-04-24
Also published as: KR20150070374A; JP6347329B2; KR20180039188A; US9946160B2; TW201826342A; TWI623019B; US10222700B2; US20150309416A1; US20180224745A1; JP2018137484A; KR101974796B1; TW201432784A; JPWO2014061760A1; TWI667690B

Abstract

This method for forming a pattern has: a step for forming, on a first mask layer on the first intermediate layer of a wafer, a third and fourth plurality of line patterns, which have differing etching characteristics and have a first direction as the lengthwise direction thereof, in a manner so that one edge section of the third and fourth plurality of line patterns are adjacent; a step for successively eliminating a portion of the third and fourth line patterns; a step for forming a mask pattern by filling a concavity of the first mask layer with a mask material and eliminating the line patterns; and a step for processing the first intermediate layer via the mask pattern. It is possible to form a pattern containing a detailed, non-cyclic section using an exposure device or a lithography step.

Description

Pattern forming method and device manufacturing method

The present invention relates to a pattern forming method for forming a pattern on a substrate and a device manufacturing method using the pattern forming method.

In an exposure apparatus that uses ultraviolet light from the far ultraviolet region to the vacuum ultraviolet region, for example, as exposure light used in a lithography process for manufacturing an electronic device (microdevice) such as a semiconductor element, in order to increase the resolution, For example, the exposure wavelength has been shortened, the illumination conditions have been optimized, and the immersion method has been applied to further increase the numerical aperture of the projection optical system. Recently, in order to form a periodic circuit pattern with a finer pitch than the resolution limit of the exposure tool, the pitch division method (Pitch-Splitting Process) and the spacer double patterning method (Spacer Double Patterning Process, Spacer transfer Process) Alternatively, Sidewall transfer Process) has been proposed (see Non-Patent Document 1, for example).

The former pitch division method is roughly classified into a double exposure method (Double Exposure Process) and a LELE (Litho-Etch-Litho-Etch) method or an LPLE (Litho-Process-Litho-Etch) method. In the double exposure method, the image of the first and second mask patterns having a pitch twice that of the finally formed device pattern is exposed to the nonlinear resist with the phases shifted from each other, and then etching or the like is performed. (For example, refer nonpatent literature 2). In the LELE method or the LPLE method, a process such as etching is performed between the exposure of the image of the first mask pattern and the exposure of the image of the second mask pattern.

In the latter spacer / double patterning method (spacer process method or sidewall method), for example, a plurality of line patterns whose line width is ¼ of the pitch by exposing and developing a mask pattern image having a pitch twice that of the device pattern. , And spacers are deposited in the space portions (side wall portions) on both sides of each line pattern, and then, for example, each line pattern is removed to obtain a pattern having a pitch of 1/2 (for example, Non-Patent Document 3). reference).

According to the conventional pattern formation method including the pitch division method or the spacer double patterning method, it is possible to form a periodic circuit pattern having a finer pitch than the resolution limit of the exposure apparatus. However, with the conventional pattern forming method, it has been difficult to form a circuit pattern including an aperiodic portion finer than the resolution limit of the exposure apparatus with high accuracy.
In view of such circumstances, the aspect of the present invention makes it possible to form, for example, a pattern including a fine non-periodic portion smaller than the resolution limit of an exposure apparatus using an exposure apparatus or a lithography process. For the purpose.

According to the first aspect, a pattern forming method is provided. The pattern forming method includes a plurality of first line patterns having a first direction as a longitudinal direction, and a plurality of second lines having the first direction as a longitudinal direction and different etching characteristics from the first line pattern. Forming a pattern such that at least one edge portion is adjacent; and removing at least a part of the plurality of first line patterns by etching.
In the pattern forming method according to the second aspect, a plurality of first line patterns whose longitudinal direction is the first direction are formed on the second layer on the first layer of the substrate, and the first direction is the longitudinal direction. In addition, a plurality of second line patterns having different etching characteristics from the first line pattern are formed so that at least one edge portion is adjacent, and a part of the plurality of first line patterns is etched. Removing a portion of the plurality of second line patterns by etching, and depositing a first mask material on a portion of the second layer where the first and second line patterns are missing, The first and second line patterns of the second layer are removed to form a first mask layer, and the first layer is processed through the first mask layer.

According to a third aspect of the present invention, there is provided a pattern forming method comprising: forming a first pattern having a first line pattern on a substrate; and extending in a direction intersecting the first line pattern on the first pattern. Forming a second pattern having a two-line pattern; forming a third pattern having a plurality of third line patterns having a longitudinal direction in a direction intersecting the second line pattern as an upper portion of the second pattern. Forming a fourth pattern having a first opening on top of the third pattern; removing a portion of the third line pattern through the first opening; Removing a part of the second pattern using an edge portion of the three-line pattern or a portion corresponding to the edge portion.
Moreover, according to the 4th aspect, the device manufacturing method including the process of forming a circuit pattern in the board | substrate using the pattern formation method of the 1st-3rd aspect is provided.

According to the first and second aspects, a plurality of first line patterns and second line patterns having finer line widths can be formed based on, for example, a line pattern formed using an exposure apparatus. A non-periodic portion can be formed by removing a part of the plurality of first line patterns using the difference in etching characteristics. Then, using the non-periodic portion, a pattern including a fine non-periodic portion, for example, smaller than the resolution limit of the exposure apparatus can be formed using the exposure apparatus or the lithography process.
According to the third aspect, a plurality of third line patterns are formed above the second line pattern, and the second line pattern is removed using the edge portion of the third line pattern. The boundary can be determined with high accuracy.

FIG. 2A is a block diagram showing a main part of a pattern forming system used in the embodiment, and FIG. 2B is a view showing a schematic configuration of an exposure apparatus 100 in FIG. (A) is an enlarged view showing a part of a circuit pattern of a device layer to be processed in an example of an embodiment, and (B) is a diagram showing an arrangement of a plurality of hole patterns in the circuit pattern of FIG. 2 (A). It is a flowchart which shows the pattern formation method of an example of embodiment. (A) is an enlarged plan view showing a part of the first L & S pattern formed first on the device layer of the wafer, and (B) is a side view of FIG. 4 (A) as viewed from the + Y direction. (A) is an enlarged plan view showing a part of the pattern of the first reticle, and (B), (C), (D), (E), and (F) are the second L & S on the second mask layer of the wafer. (G) is an enlarged plan view showing a second L & S pattern formed on the wafer in each step until the pattern is formed. (A) is an enlarged plan view showing a part of the pattern of the second reticle, (B) is an enlarged cross-sectional view showing a state where a hard mask layer to a photoresist layer are formed on the second mask layer of the wafer, (C) is an enlarged sectional view showing a state in which a pattern is formed on the hard mask layer, and (D) is an enlarged sectional view showing a state in which a spacer layer is formed on the uppermost layer of the wafer. (A) is an enlarged cross-sectional view showing a state in which a part (side wall portion) of the spacer layer is left, B) is an enlarged cross-sectional view showing a state in which the third L & S pattern of the wafer is formed, and (C) is the first view. 4 is an enlarged cross-sectional view showing a state in which an L & S pattern for 4 is formed, (D) is an enlarged cross-sectional view showing a wafer in which a photoresist layer is further formed from an organic film, and (E) is a third and fourth L & S pattern. FIG. (A) is an enlarged plan view showing a part of a wafer on which an image of the pattern of the third reticle is exposed, (B) is an enlarged plan view showing a state where a part of the organic film is peeled, and (C) is a first plan view. 3 is an enlarged cross-sectional view showing a state in which a part of the L & S pattern 3 is removed, and FIG. 4D is an enlarged plan view showing a state in which the remaining organic film is removed. (A) is an enlarged plan view showing a state where the image of the pattern of the fourth reticle is exposed on the wafer on which the photoresist layer is further formed from the organic film, and (B) is a state where a part of the organic film is peeled off. (C) is an enlarged sectional view showing a state in which a part of the fourth L & S pattern is removed, and (D) is an enlarged plan view showing a state in which the remaining organic film is removed. (A) is an enlarged plan view showing a state in which the material of the first mask layer is filled between the third and fourth L & S patterns of FIG. 9 (D), and (B) shows the third and third states from the state of FIG. It is an enlarged plan view which shows the state which removed the 4th L & S pattern. (A) is an enlarged plan view showing the pattern of the first mask layer, (B) is an enlarged plan view showing the pattern of the second mask layer, (C) is an enlarged plan view showing the composite mask pattern, and (D) is the wafer. FIG. 9E is an enlarged cross-sectional view showing a state where the first intermediate layer is etched, and FIG. 9E is an enlarged cross-sectional view showing a state where the device layer of the wafer is etched. It is a flowchart which shows an example of the manufacturing process of an electronic device.

An example of a preferred embodiment of the present invention will be described with reference to FIGS. First, an example of a pattern forming system used for forming a circuit pattern of an electronic device (microdevice) such as a semiconductor element in the present embodiment will be described.
FIG. 1A shows a main part of the pattern forming system of the present embodiment, and FIG. 1B shows a scanning exposure apparatus (projection exposure apparatus) comprising a scanning stepper (scanner) in FIG. ) 100 schematic configuration. 1A, a pattern forming system includes an exposure apparatus 100, a coater / developer 200 for applying and developing a photoresist (photosensitive material) on a wafer (substrate), a thin film forming apparatus 300, dry and wet etching on a wafer. An etching apparatus 400 for performing the above, a transfer system 500 for transferring a wafer between these apparatuses, a host computer (not shown), and the like.

In FIG. 1B, an exposure apparatus 100 includes an illumination system 10, a reticle stage RST that holds a reticle R (mask) that is illuminated by exposure illumination light (exposure light) IL from the illumination system 10, and a reticle R. A projection unit PU including a projection optical system PL that projects the emitted illumination light IL onto the surface of the wafer W (substrate), a wafer stage WST that holds the wafer W, and a computer that comprehensively controls the operation of the entire apparatus. A main control device (not shown) is provided. Hereinafter, in FIG. 1B, the Z axis is taken in parallel with the optical axis AX of the projection optical system PL, and along the direction in which the reticle R and the wafer W are relatively scanned in a plane (substantially a horizontal plane) perpendicular thereto. The Y axis is taken along the X axis along the direction perpendicular to the Z axis and the Y axis, and the rotation (tilt) directions around the X axis, the Y axis, and the Z axis are described as the θx, θy, and θz directions, respectively. I do.

The illumination system 10 includes a light source that generates illumination light IL and an illumination optical system that illuminates the reticle R with the illumination light IL, as disclosed in, for example, US Patent Application Publication No. 2003/025890. As the illumination light IL, for example, ArF excimer laser light (wavelength 193 nm) is used. As the illumination light IL, KrF excimer laser light (wavelength 248 nm), harmonics of a YAG laser or a solid-state laser (such as a semiconductor laser), or a bright line (such as i-line) of a mercury lamp can be used.

The illumination optical system includes a polarization control optical system, a light quantity distribution forming optical system (such as a diffractive optical element or a spatial light modulator), an optical integrator (such as a fly-eye lens or a rod integrator (an internal reflection type integrator)), etc. It has an optical system, a reticle blind (variable field stop), etc. (all not shown). The illumination system 10 includes a slit-like illumination area IAR elongated in the X direction on the pattern surface (lower surface) of the reticle R defined by the reticle blind, dipole illumination, quadrupole illumination, annular illumination, coherence factor (σ value). The illumination light IL with a predetermined polarization state is illuminated with a substantially uniform illuminance distribution under illumination conditions such as small illumination or normal illumination.

A reticle stage RST that holds the reticle R by vacuum suction or the like is movable on the upper surface of the reticle base (not shown) parallel to the XY plane at a constant speed in the Y direction, and in the X and Y positions. And the rotation angle in the θz direction can be adjusted. The position information of the reticle stage RST is obtained with a resolution of, for example, about 0.5 to 0.1 nm via the movable mirror 14 (or the mirror-finished side surface of the stage) by the reticle interferometer 18 including a multi-axis laser interferometer. Always detected. The position and speed of reticle stage RST are controlled by controlling a reticle stage drive system (not shown) including a linear motor and the like based on the measurement value of reticle interferometer 18.

The projection unit PU disposed below the reticle stage RST includes a lens barrel 24 and a projection optical system PL having a plurality of optical elements held in the lens barrel 24 in a predetermined positional relationship. The projection optical system PL is, for example, telecentric on both sides and has a predetermined projection magnification β (for example, a reduction magnification of 1/4 times, 1/5 times, etc.). Due to the illumination light IL that has passed through the reticle R, an image of the circuit pattern in the illumination area IAR of the reticle R passes through the projection optical system PL to form an exposure area IA (conjugation with the illumination area IAR) in one shot area of the wafer W. Region). A wafer W as a substrate of the present embodiment is used for pattern formation on the surface of a disk-shaped base material having a diameter of about 200 mm, 300 mm, or 450 mm made of, for example, silicon (or SOI (silicon on insulator) or the like). Including thin film (oxide film, metal film, polysilicon film, etc.) formed. Further, a photoresist (photosensitive material) is applied to the surface of the wafer W to be exposed with a predetermined thickness (for example, about several tens of nm to 200 nm).

Further, the exposure apparatus 100 performs exposure using a liquid immersion method, so that the lower end of the lens barrel 24 that holds the tip lens 26 that is the optical element on the most image plane side (wafer W side) constituting the projection optical system PL. A nozzle unit 32 that constitutes a part of the local liquid immersion device 30 for supplying the liquid Lq between the tip lens 26 and the wafer W is provided so as to surround the periphery of the part. The supply port for the liquid Lq of the nozzle unit 32 is connected to a liquid supply device (not shown) via a supply flow path and a supply pipe 34A. The liquid Lq recovery port of the nozzle unit 32 is connected to a liquid recovery device (not shown) via a recovery flow path and a recovery pipe 34B. The detailed configuration of the local immersion apparatus 30 is disclosed in, for example, US Patent Application Publication No. 2007/242247.

Wafer stage WST is mounted on upper surface 12a parallel to the XY plane of base board 12 so as to be movable in the X and Y directions. Wafer stage WST is provided in stage body 20, wafer table WTB mounted on the upper surface of stage body 20, and stage body 20, and the position (Z) of wafer table WTB (wafer W) with respect to stage body 20 (Z Position) and a Z-leveling mechanism that relatively drives the tilt angles in the θx direction and the θy direction. Wafer table WTB is provided with a wafer holder (not shown) that holds wafer W on a suction surface substantially parallel to the XY plane by vacuum suction or the like. Around the wafer holder (wafer W) on the upper surface of wafer table WTB, a flat plate (repellent repellent surface) that is substantially flush with the surface of wafer W (wafer surface) and that has been subjected to a liquid repellent treatment with respect to liquid Lq. (Liquid plate) 28 is provided.

Also, an oblique-incidence autofocus sensor (not shown) that measures the Z position of a plurality of measurement points on the wafer surface with the same configuration as disclosed in, for example, US Pat. No. 5,448,332. Is provided. During the exposure, the Z leveling mechanism of wafer stage WST is driven so that the wafer surface is focused on the image plane of projection optical system PL based on the measurement value of the autofocus sensor.

Further, a reflecting surface is formed on each of the end surfaces in the Y direction and the X direction of the wafer table WTB by mirror finishing. By projecting an interferometer beam from a plurality of laser interferometers constituting the wafer interferometer 16 onto its reflecting surface (which may be a moving mirror), the position information of the wafer stage WST (at least in the X and Y directions) And a rotation angle in the θz direction) are measured with a resolution of about 0.5 to 0.1 nm, for example. The position and speed of wafer stage WST are controlled by controlling a wafer stage drive system (not shown) including a linear motor and the like based on the measured values. Note that the position information of wafer stage WST may be measured by an encoder type detection apparatus having a diffraction grating scale and a detection head.

In addition, exposure apparatus 100 is incorporated in wafer stage WST in order to measure the position of a wafer alignment system AL that measures the position of a predetermined alignment mark on wafer W and the image position of projection optical system PL of the alignment mark on reticle R. An aerial image measurement system (not shown). Using these aerial image measurement systems (reticle alignment systems) and wafer alignment systems AL, alignment between the reticle R and each shot area of the wafer W is performed.

During exposure of the wafer W, the wafer stage WST is moved in the X and Y directions (step movement), so that the shot area to be exposed on the wafer W is moved in front of the exposure area IA. Further, the liquid Lq is supplied between the projection optical system PL and the wafer W from the local liquid immersion device 30. Then, while projecting an image of a part of the pattern of the reticle R by the projection optical system PL onto one shot area of the wafer W, the reticle R and the wafer W are synchronized in the Y direction via the reticle stage RST and the wafer stage WST. The pattern image of the reticle R is scanned and exposed to the shot area. By repeating the step movement and scanning exposure, the image of the pattern of the reticle R is exposed to each shot area of the wafer W by the step-and-scan method and the liquid immersion method.

Next, as an example, a circuit pattern to be manufactured in the present embodiment is a circuit pattern 70 for a gate cell of an SRAM (Static RAM) as a semiconductor element, as shown in the partial enlarged view of FIG. . Hereinafter, the line and space pattern is also referred to as an L & S pattern. The circuit pattern 70 is configured by arranging a line pattern 72 having a line width d / 2 and a space portion 73 having a width d / 2 on the surface of the substrate 36 of the wafer at a pitch (period) d in the X direction which is a periodic direction. In the first L & S pattern 71, a plurality of

rows

75A, 75B, 75C, and 75D are removed by removing portions of the width e from the plurality of line patterns 72 in the Y direction (longitudinal direction of the line pattern 72) orthogonal to the X direction.

Hole patterns

74, 74A, and 74C (non-periodic portions) are formed. FIG. 2B shows an arrangement of a plurality of

hole patterns

74, 74A, and 74C in FIG. As an example, the hole pattern 74 is a pattern having the smallest width in the X direction formed on one line pattern 72 and having the smallest width d, and the hole pattern 74A is a plurality of adjacent (in this case, two) line patterns 72. The X-direction width formed above is a 2d pattern, and the hole pattern 74C is a pattern elongated in the X-direction formed on five adjacent line patterns 72.

The period in the Y direction of two hole patterns 74 arranged along the same line pattern 72 is f (the interval is (fe)), and the two hole patterns 74 arranged in the X direction (or 74, 74A). Etc.) in the X direction is (m + 1) d (m = 0, 1, 2,...). Therefore, the arrangement of the plurality of

hole patterns

74, 74A, and 74C includes irregular portions in a staggered or checkered pattern. Further, as an example, the period f is about twice to several times the width e, and the minimum intervals in the X direction and Y direction of the two

adjacent hole patterns

74, 74A, 72C are d and (fe), respectively. is there. The shape and arrangement of the

hole patterns

74, 74A and 74C are arbitrary. The directions of the X axis and the Y axis in FIG. 2A are the same as those when the wafer W on which the circuit pattern 70 in FIG. 2A is formed is placed on the wafer stage WST of the exposure apparatus 100 in FIG. The exposure apparatus 100 is parallel to the X-axis and Y-axis directions.

In this embodiment, as an example, the width e of the hole pattern 74 is longer than the line width (d / 2) of the line pattern 72 in the X direction (the width e is, for example, about d / 2 to d). Specifically, for example, if the line width (d / 2) is about 10 to 13 nm, the width e is about 15 to 20 nm, for example. Further, it is assumed that the line width (d / 2) and the width e are finer than the resolution limit (half pitch in the case of a periodic pattern) of the immersion type exposure apparatus 100. Accordingly, the line width (d / 2) of the L & S pattern 71 is finer than the resolution limit of the exposure apparatus 100, and the circuit pattern 70 is aperiodic at intervals smaller than the resolution limit of the exposure apparatus 100. It is also a pattern including a plurality of

hole patterns

74, 74A, 74C (non-periodic portions) having a width e arranged (semi-periodically).

In this case, the position of the L & S pattern 71 (line pattern 72) in the X direction and the position of each hole pattern 74 in the Y direction are based on alignment marks (not shown) used when forming the L & S pattern 71, for example. Is set (measured). As an example, if the line width (d / 2) is approximately 1/4 of the resolution limit of the exposure apparatus 100, the resolution limit of the exposure apparatus 100 is approximately 2d. When the resolution limit of the exposure apparatus 100 is, for example, about 40 to 60 nm, the line width (d / 2) becomes about 10 to 15 nm accordingly.

Hereinafter, an example of a pattern forming method for forming the circuit pattern 70 using the pattern forming system of the present embodiment will be described with reference to the flowchart of FIG. In this embodiment, the solution of the exposure apparatus 100 is solved by using a quadruple pattern forming method (Quadruple® Patterning® Process) in which a spacer double patterning method (Spacer Double Patterning Process, Spacer transfer Process or Sidewall transfer Process) is substantially repeated twice. A pattern finer than the image limit is formed.

First, in step 102 of FIG. 3, as shown in FIG. 4B using the thin film forming apparatus 300, for example, hafnium dioxide (HfO ₂ ) and the like are formed on the flat surface of the substrate 36 made of silicon, for example. A device layer 38 made of a thin film of titanium nitride (TiN) is formed. Note that an oxide film, a nitride film, or the like may be formed on the bottom surface of the device layer 38 (the surface of the base material 36). In the next step 104, as shown in FIG. 4A, the device layer 38 is formed by using the above fourfold pattern forming method, as shown in FIG. A first L & S pattern 71 in which line patterns 38A are arranged at a pitch d in the X direction is formed. The line pattern 38A corresponds to the line pattern 72 of FIG. 2, but the hole pattern 74 is not formed at this stage. The 4-fold pattern forming method is a method of repeating a spacer double patterning method (hereinafter also referred to as a 2-fold pattern forming method) described later twice (details will be described later). Further, the L & S pattern 71 can be exposed to a large number of electron beams that can draw a minute dot pattern that can be turned on / off and can be deflected by a minute amount without using the exposure apparatus 100, for example. You may form using the electron beam exposure apparatus which can expose arbitrary fine circuit patterns on this substrate surface, moving. In this case, the line width (d / 2) of the line pattern 38A of the L & S pattern 71 can be made finer than 1/4 of the resolution limit (half pitch) of the exposure apparatus 100.

In the next step 106, a first intermediate layer 40 (protective film for the device layer 38) made of, for example, tetraethyl orthosilicate (TEOS) is formed so as to cover the device layer 38 (FIG. 4B). reference). Note that silicon oxide (SiO ₂ ) or the like can be used instead of the TEOS film. Further, as shown in FIG. 5B, a second mask layer 42 made of a material containing carbon (organic material), for example, is formed on the first intermediate layer 40. For example, ACL (Amorphous Carbon Layer) can be used as the organic material.

In the next step 108, the second mask layer 42 is stretched in the X direction with a line width (fe) in the Y direction as shown in the enlarged plan view of FIG. A second L & S pattern 43 formed by arranging a plurality of line patterns 42A in the Y direction at a pitch f is formed. As will be described later, the space portion 42B of the second L & S pattern 43 defines the edge portion (width e) in the ± Y direction of the hole pattern 74 and the like finally formed in FIG. The width in the Y direction of the portion 42B is e (the same as the width of the hole pattern 74 etc.). Further, the circuit pattern formed in each shot region of the wafer W is a pattern in which a portion having the same size as the pattern of FIG. 2A or 5G is periodically repeated in the X direction and the Y direction. . Further, enlarged cross-sectional views along the Y-axis in FIGS. 5B to 5F, which will be described later, correspond to the front view of the portion shown in FIG. 2A or FIG. The enlarged cross-sectional views along the X-axis such as (B) to (D) correspond to side views of the part shown in FIG. 2 (A) or FIG. 5 (G) viewed from the + Y direction.

The operation of step 108 (double pattern formation method) of this embodiment is divided into steps 130 to 146. That is, in step 130, as shown in FIG. 5B, the second intermediate layer 44A is formed on the surface of the second mask layer 42 of the wafer W using the thin film forming apparatus 300, and the coater / developer 200 For example, a positive photoresist layer 46A is applied to the surface of the intermediate layer 44A. As the second intermediate layer 44A, an antireflection film, BARC (Bottom Anti-Reflection Coating), may be used. In step 132, the wafer W is placed on the wafer stage WST of the immersion type exposure apparatus 100 shown in FIG. As shown in the enlarged view of FIG. 5A, the pattern of the reticle (reticle R1) of the exposure apparatus 100 is a line pattern R1a made of a light-shielding film having a line width of f / β (β is the projection magnification). It is an L & S pattern arranged at a pitch of 2f / β in the direction. Then, the exposure apparatus 100 exposes each shot area of the wafer W with a pattern image 47Y of the reticle R1 (an image having a pitch 2f in the Y direction). Since the line width (half pitch) of the image 47Y is f (approximately 1 to 2 times the resolution limit), the image 47Y can be projected with high accuracy by the exposure apparatus 100. At this time, the alignment of the image 47Y in the X direction and the Y direction is performed using an alignment mark (not shown) on the device layer 38 of the wafer W and an alignment mark (not shown) of the reticle R1.

In the next step 134, the photoresist layer 46A of the wafer W is developed by the coater / developer 200, and each resist pattern RP1 (see FIG. 5B) formed by the development is slimmed to obtain a line width of (f− The resist pattern RP2 of e) is formed. Instead of performing slimming, the width in the Y direction of the portion (unexposed portion) where the exposure amount is equal to or less than the photosensitive level in the image 47Y for one pitch is set to (fe) during exposure. You may set it. Thereafter, the second intermediate layer 44A and the second mask layer 42 of the wafer W are etched by the etching apparatus 400, and the resist pattern is removed, whereby the line pattern 42a of the second mask layer having the line width (fe) is formed. An L & S pattern arranged at a pitch 2f in the Y direction is formed (see FIG. 5C). A first spacer layer 48A is deposited on the L & S pattern (see FIG. 5D).

In the next step 136, the etching apparatus 400 performs anisotropic etching in the direction perpendicular to the surface of the spacer layer 48A of the wafer W, and then the line pattern 42a of the second mask layer is removed. As a result, as shown in FIG. 5E, an L & S pattern in which a plurality of spacer portions (sidewall portions) 48ASa having a line width e are arranged at a pitch f in the Y direction is formed on the surface of the first intermediate layer 40. . In this way, an L & S pattern with the initial pitch 2f halved is formed. The operations of steps 134 and 136 are also the pitch division method of the double pattern formation method. In the above step 104, a spacer layer is further deposited on FIG. 5E, and the double pattern formation method is repeatedly executed, so that the pitch is 1 of the pitch of the first pattern in the quadruple pattern formation method. A pattern of / 4 is formed.

Then, after depositing another second mask layer material so as to cover the L & S pattern of FIG. 5E in step 138, CMP (Chemical-Mechanical Polishing) is performed so that the spacer portion 48ASa appears. 48ASa is removed by etching. As a result, as shown in FIG. 5F, a line pattern 42A having a line width (fe) of the second mask layer is formed on the surface of the first intermediate layer 40 with a pitch f with a space portion 42B having a width e interposed therebetween. A second L & S pattern 43 arranged in the Y direction is formed. Thereafter, in step 146, the space portion 42B of the second L & S pattern 43 is filled with, for example, silicon (Si) or polysilicon (the same material as the hard mask layer 50). When step 104 is executed using exposure apparatus 100, the same operation as steps 130 to 136 is performed using a reticle in which an L & S pattern having a line width of 4d / β and a pitch of 8d / β is formed in the X direction. Is executed twice.

In step 110 following step 108, a hard mask layer 50 made of, for example, silicon (Si) or polysilicon is formed so as to cover the second L & S pattern 43 (second mask layer 42) formed in step 108 (FIG. 6 (B)). Thereafter, in step 112, an intermediate layer 51 made of an organic material, a third intermediate layer 44B (for example, BARC), and a photoresist layer 46B are formed on the hard mask layer 50. Then, wafer W is placed on wafer stage WST of exposure apparatus 100. The reticle stage RST of the exposure apparatus 100 is loaded with a second reticle R2 instead of the reticle R1. In the pattern of reticle R2, as shown in the enlarged view of FIG. 6A, line pattern R2a made of a light-shielding film having a line width of 2d / β (β is a projection magnification) is arranged at a pitch of 4d / β in the X direction. L & S pattern. Then, after aligning the reticle R2 using an alignment mark (not shown) of the reticle R2, the exposure apparatus 100 forms an image 47X of the pattern of the reticle R2 on each shot area of the wafer W (an image having a pitch 4d in the X direction). To expose. Since the line width (half pitch) of the image 47Y is almost the resolution limit, the image 47Y can be formed with high accuracy by the exposure apparatus 100. The exposed wafer W is developed.

In step 114, the third intermediate layer 44B and the intermediate layer 51 are etched using the resist pattern RP3 having a line width d obtained by slimming the resist pattern RP3 having a line width 4d of the wafer W as a mask. Instead of slimming, the line width of the resist pattern may be adjusted to d by controlling the exposure amount according to the photosensitive level of the resist. Further, by peeling off the resist pattern and the third intermediate layer 44B, an L & S pattern in which line patterns 51A having a line width d in the X direction of the intermediate layer 51 are arranged at a pitch 4d in the X direction is formed (FIG. 6C )reference). A third L & S pattern thin film 52 made of silicon nitride (SiN) is deposited thereon as a third spacer layer, and the thin film 52 is etched so that the remaining thin film 52 has the same thickness as the line pattern 51A. (See FIG. 7A). Then, by removing the line pattern 51A, an L & S pattern in which the line pattern 52A of the thin film 52 having a line width d in the X direction (here, the line pattern extending in the Y direction) is arranged at a pitch 2d in the X direction is formed. (See FIG. 7B).

In the next step 116, a thin film 54 as a spacer layer for the fourth L & S pattern made of silicon dioxide (SiO ₂ ) is deposited so as to cover the line pattern 52A, and the surface of the thin film 54 is flush with the surface of the line pattern 52A. CMP is performed so that As a result, as shown in FIG. 7C, the line pattern 54A of the thin film 54 is deposited and left so as to fill the space portion between the X directions of the line pattern 52A. Hereinafter, a pattern in which a plurality of line patterns 52A are arranged at a pitch 2d in the X direction is referred to as a third L & S pattern 53, and a pattern in which a plurality of line patterns 54A are arranged at a pitch 2d in the X direction is referred to as a fourth L & S pattern 55. (Refer to FIG. 7E). Thus, the third L & S pattern 53 is formed substantially by a double pattern formation method (double patterning method).

The positioning accuracy (alignment accuracy) δX in the X direction of the third L & S pattern 53 is substantially the positioning accuracy of the image of the second reticle R2 in FIG. 6A, and the positioning accuracy δX (FIG. 7 ( Positioning is easy because reference to (B) is about ± d / 4 or less with respect to the first L & S pattern 71 of FIG. Furthermore, in this embodiment, the line pattern 52A of the third L & S pattern 53 is silicon nitride, the line pattern 54A of the fourth L & S pattern 55 is silicon dioxide, and the

line patterns

52A and 54A have different etching characteristics. .

In the next step 118, as shown in FIG. 7D, a material containing carbon such as ACL (Amorphous Carbon Layer) is used so as to cover the third and fourth L &

S patterns

53, 55 of the wafer W. An organic film 58, a BARC (Bottom-Anti-Reflection-Coating) film 60A, and a positive photoresist layer 46C, for example, are formed. Further, the wafer W is transported to the exposure apparatus 100, and a third reticle pattern image R3P having the shaded portion in FIG. The image R3P only needs to have a shape that covers a portion of the third L & S pattern 53 (line pattern 52A) to be left. For this reason, the resolution of the image R3P only needs to be approximately 2d (half pitch) in the X direction and approximately 3e (half pitch) in the Y direction, and can be exposed with high accuracy by the exposure apparatus EX. Further, the alignment accuracy of the image R3P in the X direction and the Y direction may be ± d / 2 and ± e / 2 or less, respectively, and alignment during exposure is easy. Further, in FIGS. 7E and 8A to 8D, the positions of the

hole patterns

74, 74A, and 74C in FIG. 2B are indicated by dotted lines.

Thereafter, the exposed wafer W is developed by the coater / developer 200, the BARC film 60A is etched using the remaining resist pattern as a mask, the organic film 58 is further etched to remove the BARC film 60A, etc. As shown in FIG. 8B, a protective pattern 58A that is a pattern of the organic film 58 is left in a portion corresponding to the image R3P. At this time, the line pattern 52A of the third L & S pattern and the line pattern 54A of the fourth L & S pattern are exposed at portions other than the protective pattern 58A.

Further, only the third L & S pattern 53 (line pattern 52A made of SiN) is etched, and the fourth L & S pattern 55 (line pattern 54A made of SiO ₂ ), the organic film part 58 and the hard mask layer 50 are not etched. Using the plasma etching phase, only the third L & S pattern 53 (line pattern 52A) is etched using the protective pattern 58A as a mask. For example, when plasma etching is used, a gas obtained by diluting hexafluoride gas (CF ₆ ) with helium (He) gas can be used as an etching gas for etching only the line pattern 52A made of SiN. As a result, as shown in FIG. 8C, a part of the third L & S pattern 53 is removed, and the partial pattern 52A1 at the bottom of the protection pattern 58A is left out of the line pattern 52A. Thereafter, the protective pattern 58A is removed by etching, so that the partial pattern 52A1 is exposed as shown in FIG. 8D.

In the next step 120, as shown in FIG. 9A, an organic film 59 made of a material containing carbon such as ACL, a BARC film 60B, and the like, so as to cover the surface of the wafer W in FIG. Then, for example, a positive type photoresist layer 46D is formed. Further, the wafer W is transported to the exposure apparatus 100, and an image R4P of the pattern of the fourth reticle having the shaded portion in FIG. The image R4P may have a shape that covers a portion of the fourth L & S pattern 55 (line pattern 54A) to be left. Therefore, the resolution of the image R4P only needs to be approximately 2d (half pitch) in the X direction and approximately 3e (half pitch) in the Y direction, and can be exposed with high accuracy by the exposure apparatus EX. Furthermore, the alignment accuracy of the image R4P in the X direction and the Y direction may be ± d / 2 and ± e / 2 or less, respectively, and alignment during exposure is easy.

Thereafter, the exposed wafer W is developed by the coater / developer 200, the BARC film 60B is etched using the remaining resist pattern as a mask, the organic film 59 is further etched to remove the BARC film 60B, etc. As shown in FIG. 9B, a protective pattern 59A that is a pattern of the organic film 59 is left in a portion corresponding to the image R4P. At this time, the partial pattern 52A1 (a part of the line pattern 52A) and the line pattern 54A of the fourth L & S pattern are exposed at portions other than the protective pattern 59A.

Further, an etching solution (or plasma) that etches only the fourth L & S pattern 55 (line pattern 54A made of SiO ₂ ) without etching the organic film 59, the partial pattern 52A1 (line pattern 52A made of SiN), and the hard mask layer 50. Using the etching phase, only the fourth L & S pattern 55 (line pattern 54A) is etched using the protective pattern 59A as a mask. For example, when plasma etching is used, a CF gas (fluorine-based gas) such as trifluoromethane (CHF ₃ ) or carbon tetrafluoride (CF ₄ ) is used as an etching gas for etching only the line pattern 54A made of SiO _2. Gas) diluted with argon (Ar) gas can be used. Thereby, as shown in FIG. 9C, part of the line pattern 54A is removed. Thereafter, the protective pattern 59A is removed. At this time, as shown in FIG. 9D, only the partial pattern 54A1 on the bottom surface of the protective pattern 59A is left among the line patterns 54A. As can be seen from FIG. 9D, the remaining partial patterns 52A1 and 54A1 define the positions of the edge portions in the X direction of the hole pattern 74 and the like.

In the next step 122, as shown in FIG. 10A, the first mask layer made of the same organic material as the second mask layer 42 is interposed between the partial patterns 52A1 and 54A1 on the hard mask layer 50 of the wafer W. Fill material 56 and planarize its surface by CMP. In step 124, as shown in FIG. 10B, the partial pattern 52A1 (third L & S pattern 53), the partial pattern 54A1 (fourth L & S pattern 55), and the hard mask layer 50 (second L & S pattern 43) of the wafer W. The material of the line part 42B is included, and among these, the part located at the bottom of the partial patterns 52A1 and 54A1) is sequentially removed by etching. As a result, in the material 56 of the first mask layer, the portions where the partial patterns 52A1 and 54A1 exist are openings 56a that define the positions of the edge portions in the X direction, such as the hole patterns 74, respectively. As a result, the second L & S pattern 43 (second mask layer 42) and the material 56 (first mask layer) provided with the openings 56a are formed so as to be stacked above the device layer 38.

In this case, as shown in FIG. 11A, the material 56 provided with the openings 56a can be regarded as a first mask pattern MP1 that can be etched at a plurality of openings 56a. Further, as shown in FIG. 11B, the second L & S pattern 43 can be regarded as a second mask pattern MP2 that can be etched in the space part 42B (opening part) between the line patterns 42A. However, actually, the material of the hard mask layer 50 remains at the bottom of the portion of the space portion 42B of the mask pattern MP2 where the material 56 of the mask pattern MP1 remains. As a result, when the lower layer material is etched through the mask patterns MP1 and MP2, the mask patterns MP1 and MP2 are, as shown in FIG. 10C, the openings 56a of the mask pattern MP1 and the openings of the mask pattern MP2. The portion overlapping (space portion 42B) acts as a composite mask pattern MP3 having a plurality of openings MP3a, MP3b, MP3c having a width d in the X direction and a width e in the Y direction. The plurality of openings MP3a and the like of the composite mask pattern MP3 have the same arrangement as the plurality of hole patterns 74 and the like in the circuit pattern 70 of FIG.

Then, in step 126, as shown in FIG. 11D, the first intermediate layer 40 is etched through the synthetic mask pattern MP3 composed of the first mask layer and the second mask layer, so that the first intermediate layer 40 Openings 40a and the like are respectively formed at positions corresponding to the hole patterns 74 and the like. Further, in step 128, the line pattern 38A (72) of the device layer 38 is etched through the first intermediate layer 40, so that each line pattern 38A is non-periodically arranged as shown in FIG. Thus, a circuit pattern 70 in which the hole pattern 74 and the like are formed is formed.

As described above, according to the present embodiment, since the L & S patterns 71 and 43 (patterns of the second mask layer) are formed by using the quadruple pattern formation method or the double pattern formation method in

steps

104 and 108, exposure is performed. A periodic pattern finer than the resolution limit of the apparatus 100 can be formed on the wafer W with high accuracy using the exposure apparatus 100. In steps 112 to 116, the third L & S pattern 53 and the fourth L & S pattern 55 (the pattern of the first mask layer) are formed by substantially using the double pattern forming method. A pattern with a finer line width can be formed with high accuracy so that the edge portions are adjacent to each other. Further, in

steps

118 and 120, a part of the L &

S patterns

53 and 55 is selectively removed sequentially using the difference in etching characteristics between the third L & S pattern 53 and the fourth L & S pattern 55. Accordingly, a pattern (partial pattern 52A1, 54A1) for forming the opening 56a corresponding to the hole pattern 74 and the like irregularly arranged at intervals smaller than the resolution limit of the exposure apparatus 100 to be formed is exposed. It can be formed using the apparatus 100 (lithography process). Therefore, by etching the first intermediate layer 40 and the device layer 38 using the finally formed synthetic mask pattern MP3 (steps 126 and 128), the non-periodic pattern is finer than the resolution limit of the exposure apparatus 100. A circuit pattern 70 including a large portion (hole pattern 74) can be formed with high accuracy.

The effects and the like of this embodiment are as follows.
In the pattern forming method using the pattern forming system including the exposure apparatus 100 of the present embodiment, the first L & S pattern 71 having a plurality of first line patterns 38A (72) arranged in the X direction on the wafer W (substrate). (Step 104) for forming (first pattern), step 106 for forming first intermediate layer 40 (first layer) so as to cover first L & S pattern 71, and on first intermediate layer 40 (first layer) The first mask layer (second layer) includes a plurality of line patterns 52A having the Y direction (first direction) as the longitudinal direction, the Y direction being the longitudinal direction, and the line pattern 52A (first line pattern). Steps 112 to 116 for forming a plurality of line patterns 54A (second line patterns) having different etching characteristics so that at least one edge portion is adjacent to each other; Step 118 for removing a part of the line pattern 52A by etching, Step 120 for removing a part of the plurality of line patterns 54A by etching, and portions where the

line patterns

52A and 54A of the first mask layer are missing. Depositing a material 56 (material of the first mask layer) 122; removing a partial pattern 52A1, 54A1 in the material 56 (first mask layer) to form a first mask pattern MP1; And step 126 of processing the first intermediate layer 40 through one mask pattern MP1.

According to the present embodiment, a plurality of line patterns 52A having fine line widths can be formed based on a line pattern made of the resist pattern RP3 (or RP4) formed using the exposure apparatus 100, and the plurality of line patterns 52A. A plurality of line patterns 54A can be formed based on the above. Furthermore, a non-periodic portion (a portion corresponding to the opening 56a) can be formed by sequentially removing a part of the

line patterns

52A and 54A using the difference in etching characteristics of the

line patterns

52A and 54A. Then, by processing the first intermediate layer 40 through the first mask pattern MP1 having the non-periodic portion as an opening,

hole patterns

74, 74A, which are arranged aperiodically at fine intervals. 74C can be formed with high accuracy.

Therefore, the circuit pattern 70 including the non-periodic portions (

hole patterns

74, 74A, 74C) finer than the resolution limit of the exposure apparatus 100 is formed with high accuracy using a lithography process including exposure by the exposure apparatus 100. it can.
In

steps

102 and 108 and steps 112 to 116, a quadruple or double pattern formation method is used, so that a periodic pattern finer than the resolution limit of the exposure apparatus 100 can be obtained with high accuracy. Can be formed. If the size and interval of the

hole patterns

74, 74A, and 74C to be formed are larger than ½ or less of the resolution limit of the exposure apparatus 100, for example, steps 102 and 108 and steps 112 to 116 are performed. A double patterning method (for example, a spacer double patterning method) can be used substantially. Further, in place of the spacer double patterning method, a double patterning method using a double exposure process, a LELE (Litho-Etch-Litho-Etch) method, a LPLE (Litho-Process-Litho-Etch) method, or the like. (Pitch division method) can also be used.

In the above embodiment, in order to selectively dry-etch the SiN portion (line pattern 52A) with respect to the SiO ₂ portion (line pattern 54A), for example, as disclosed in JP-A-08-264510, Chemical dry etching using fluorine radicals and hydrogen radicals may be employed.
As a condition for selectively etching the SiN portion (line pattern 52A) and the SiO ₂ portion (line pattern 54A), as disclosed in, for example, Japanese Patent Laid-Open No. 05-160077, dry SiN (silicon nitride) is used. CHF ₃ , CF ₄ , Ar and oxygen (O ₂ ) may be used as etching gases during etching, and CHF ₃ , CF ₄ and Ar may be used as etching gases during dry etching of the SiO ₂ part (silicon dioxide).
Further, for example, the line pattern 52A is formed from a metal film such as aluminum, the line pattern 54A is formed from SiN, the etching of the line pattern 52A is performed using a chlorine-based gas, and the etching of the line pattern 54A is performed using the above-described fluorine-based gas. You may make it perform using.

In the above-described embodiment, for example, an L & S pattern having a pitch of ¼ is formed from an L & S pattern (reticle pattern image) based on a four-fold pattern formation method. However, an L & S pattern having a pitch of 1 / (2 ^k ) with respect to the pitch of the original pattern by repeating the spacer double patterning method k times (k is an integer of 3 or more) for the original pattern. (This becomes the first L & S pattern 71, the second L & S pattern 43, the third L & S pattern 53, 53A, and / or the fourth L & S pattern 55, 55A). Thereby, it is possible to form a circuit pattern having a periodic and aperiodic structure finer than 1/4 of the resolution limit of the exposure apparatus 100.

Further, in each of the above embodiments, a part of the periodic pattern (the first L & S pattern 71) is removed. A pattern forming method is applicable. Also, the above pattern forming method can be applied when an aperiodic pattern is added to a periodic pattern or an aperiodic pattern.
In each of the above-described embodiments, the first mask material 56 is filled in the first and second line patterns (the third L & S pattern 53 and the fourth L & S pattern 55). Although the mask layer is formed, a part of the lower layer may be etched using a portion where the first and second line patterns are left.

In each of the above embodiments, the first and second line patterns (third L & S pattern 53 and fourth L & S pattern 55) having different etching characteristics are used. However, these first and second lines are used. Only one of the patterns may be used.
Next, when manufacturing a semiconductor device (electronic device) such as an SRAM using the pattern forming method of each of the above embodiments, the semiconductor device performs a function / performance design of the semiconductor device as shown in FIG. 221; manufacturing a mask (reticle) based on this design step 222; manufacturing a semiconductor device substrate (or wafer substrate) 223; substrate processing step 224; device assembly step (dicing process, bonding process) , Including a processing process such as a packaging process) 225, an inspection step 226, and the like. Further, the substrate processing step 224 includes the pattern forming method of the above-described embodiment (steps 102 to 128 in FIG. 3). The pattern forming method is a step of exposing a reticle pattern to a substrate with an exposure apparatus, and exposing the substrate. It includes a step of developing the substrate and a step of heating (curing) and etching the developed substrate.

In other words, the device manufacturing method includes a substrate processing step 224. In the substrate processing step 224,

hole patterns

74, 74A, and 74C are formed on the substrate (wafer W) using the pattern forming method of the above embodiment. The process to do is included. As an example, the pattern formed on the substrate is a pattern obtained by removing a part of the periodic pattern (first L & S pattern 71).

According to this device manufacturing method, a semiconductor device including a circuit pattern including an aperiodic portion finer than the resolution limit of the exposure apparatus can be manufactured with high accuracy using the exposure apparatus.
The device to be manufactured in the above embodiment can be any semiconductor device such as DRAM, CPU, DSP other than SRAM. Furthermore, the pattern forming method of the above-described embodiment can also be applied when manufacturing an imaging device other than a semiconductor device, or an electronic device (microdevice) such as MEMS (Microelectromechanical Systems).

Further, in the above embodiment, as the exposure apparatus, a dry type exposure apparatus that is not an immersion type may be used. In addition to an exposure apparatus that uses ultraviolet light as exposure light, an EUV exposure apparatus that uses EUV light (Extreme Ultraviolet Light) having a wavelength of several nanometers to several tens of nanometers as exposure light, or an electron beam exposure that uses an electron beam as exposure light. An apparatus or the like may be used.
In addition, this invention is not limited to the above-mentioned embodiment, A various structure can be taken in the range which does not deviate from the summary of this invention.

R, R1, R2 ... reticle, W ... wafer (substrate), MP3 ... synthetic mask pattern, 36 ... substrate, 38 ... device layer, 38A ... line pattern, 42A ... line pattern, 43 ... second L & S pattern (line) (And space pattern), 50 ... hard mask layer, 52A ... line pattern, 53 ... third L & S pattern, 54A ... line pattern, 56 ... material of first mask layer, 56a ... opening, 70 ... circuit pattern, 71 ... First L & S pattern, 72 ... line pattern, 74, 74A, 74C ... hole pattern, 100 ... exposure apparatus

Claims

A pattern forming method comprising:
At least one of a plurality of first line patterns having a first direction as a longitudinal direction and a plurality of second line patterns having the first direction as a longitudinal direction and different etching characteristics from the first line pattern. Forming the edges of the two adjacent to each other;
Removing at least some of the plurality of first line patterns by etching;
A pattern forming method comprising:
2. The pattern forming method according to claim 1, further comprising: removing a part of the plurality of second line patterns by etching.
3. The pattern forming method according to claim 2, further comprising forming a first mask layer in a portion removed by the etching.
The plurality of first and second line patterns are formed on a first layer of a substrate,
The pattern forming method according to claim 3, further comprising processing the first layer through the first mask layer.
A pattern forming method comprising:
The second layer on the first layer of the substrate has a plurality of first line patterns having a first direction as a longitudinal direction, the first direction as a longitudinal direction, and the first line pattern and etching characteristics. A plurality of different second line patterns are formed so that at least one edge portion is adjacent,
Removing a part of the plurality of first line patterns by etching;
Removing a part of the plurality of second line patterns by etching;
Depositing a first mask material on the portion of the second layer where the first and second line patterns are missing;
Removing the first and second line patterns of the second layer to form a first mask layer;
A pattern forming method, wherein the first layer is processed through the first mask layer.
When removing a part of the plurality of first line patterns by etching, the second line pattern is not etched,
6. The pattern forming method according to claim 5, wherein when the part of the plurality of second line patterns is removed by etching, the first line pattern is not etched.
Etching of the first and second line patterns is performed by dry etching,
The pattern forming method according to claim 5, wherein the etching gas for the first line pattern and the etching gas for the second line pattern are different from each other.
8. The common range in the longitudinal direction of the plurality of first line patterns is removed when a part of the plurality of first line patterns is removed by etching. 9. The pattern formation method as described in any one of Claims.
When a part of the plurality of first line patterns is removed by etching, a portion inside the first rectangular region or outside the first rectangular region is removed from the plurality of first line patterns. The pattern formation method according to claim 1, wherein:
The common range in the longitudinal direction of the plurality of second line patterns is removed when part of the plurality of second line patterns is removed by etching. Or the pattern formation method of Claim 7.
When a part of the plurality of second line patterns is removed by etching, a portion inside the second rectangular region or outside the second rectangular region is removed from the plurality of second line patterns. The pattern forming method according to claim 2, claim 6, or claim 7.
When forming the plurality of first line patterns and the plurality of second line patterns in the second layer,
Exposing an image of a first line and space pattern having the first direction as a longitudinal direction on the substrate by an exposure device;
Forming a second line-and-space pattern having a period of ½ or less in a direction orthogonal to the first direction with respect to the image of the first line-and-space pattern; The pattern formation method according to any one of claims 5 to 7.
13. The pattern forming method according to claim 12, wherein the period of the second line and space pattern is 1/4 of the period of the first line and space pattern.
A plurality of third line patterns having a second direction perpendicular to the first direction as a longitudinal direction are formed on a third layer different from the second layer on the first layer of the substrate to form a second line Forming a mask layer,
The said 1st layer is processed through the said 1st mask layer and the said 2nd mask layer when processing the said 1st layer, The any one of Claims 5-7 characterized by the above-mentioned. The pattern forming method according to 1.
15. The pattern forming method according to claim 14, wherein the plurality of third line patterns have a width of a line portion and a width of a space portion substantially equal to each other.
The pattern forming method according to claim 14, wherein the plurality of third line patterns have a width of a line portion wider than a width of a space portion.
When forming the plurality of third line patterns in the third layer,
Exposing an image of a third line-and-space pattern having the second direction as a longitudinal direction on the substrate by an exposure apparatus;
Forming a fourth line and space pattern having a period of 1/2 or less in a direction orthogonal to the second direction with respect to an image of the third line and space pattern; The pattern formation method as described in any one of Claim 14 to 16.
18. The pattern forming method according to claim 17, wherein a period of the fourth line and space pattern is ¼ of a period of the third line and space pattern.
On the first layer of the substrate, a line and space pattern having the first direction as a longitudinal direction is formed,
6. The line pattern of the line and space pattern of the first layer is removed when the first layer is processed through the first mask layer. 6. Item 8. The pattern forming method according to any one of Items 7 to 8.
A pattern forming method comprising:
Forming a first pattern having a first line pattern on a substrate;
Forming a second pattern having a second line pattern extending in a direction intersecting the first line pattern on the first pattern;
Forming a third pattern having a plurality of third line patterns with a longitudinal direction in a direction intersecting the second line pattern formed on the second pattern;
Forming a fourth pattern having a first opening on top of the third pattern;
Removing a part of the third line pattern through the first opening;
Removing a portion of the second pattern using an edge portion of the third line pattern or a portion corresponding to the edge portion;
A pattern forming method including:
Forming a first mask layer on the removed portion of the third line pattern;
21. The pattern forming method according to claim 20, wherein the portion corresponding to the edge portion of the third line pattern is an edge portion of the first mask layer.
Forming a plurality of fourth line patterns having the longitudinal direction of the third line pattern as a longitudinal direction on the second pattern;
The pattern forming method according to claim 20 or 21, wherein edges of the third line pattern and the fourth line pattern are adjacent to each other.
The pattern forming method according to claim 22, wherein the third line pattern and the fourth line pattern have different edging characteristics.
24. The pattern forming method according to claim 20, further comprising removing a part of the first pattern through the second pattern from which a part has been removed.
A device manufacturing method including a step of forming a circuit pattern on the substrate using the pattern forming method according to any one of claims 1 to 24.
26. The device manufacturing method according to claim 25, wherein the circuit pattern formed on the substrate includes a plurality of aperiodic hole patterns.