JP2001203139A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the pattern accuracy transferred on a semiconductor wafer with a photomask. SOLUTION: ON a photomask, where plural line-like optical transmission patterns 3a are formed, exposure is conducted. A photomask, where plural line-like optical transmission patterns 3a which extend in a direction crossing the optical transmission patterns 3a and on which phase shifters 5 are arranged in one of adjacent patterns, is formed, and an exposure is conducted. Thus, the whole pattern is formed in a resist film on a shading area surrounded by both optical transmission patterns 3a and 3b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to an exposure technique for transferring a predetermined pattern onto a semiconductor substrate.

[0002]

2. Description of the Related Art The miniaturization of the pattern of a semiconductor device has been achieved by improving the performance of a reduction projection exposure apparatus mainly used in a lithography process in a semiconductor device manufacturing process. However, in order to further improve the fine workability, it is necessary to increase the numerical aperture NA of the reduction projection exposure apparatus, apply a super-resolution technique such as a phase shift mask technique, a modified illumination (or oblique incidence illumination) technique, or the like. OPC (Optical Pr
oximity effect correction) technology must be applied. In particular, in order to obtain high resolution in a fine hole pattern arranged at high density, it is necessary to shorten the wavelength of exposure light and to use a reduction projection exposure apparatus having a high NA projection lens. As investment is required and the level of fine processing of semiconductor devices is accelerating year by year, it is not realistic to make new capital investment without ending depreciation of semiconductor manufacturing devices.

Therefore, as a means for obtaining a high resolution by an existing semiconductor manufacturing apparatus, there is the above-mentioned super-resolution technique. Phase shift mask technology, which is one of the super-resolution technologies, is a technology for improving resolution and depth of focus by manipulating the phase of light transmitted through a photomask (including a reticle). There are a translucent phase shift mask technology used as a shifter, a Levenson type phase shift mask technology in which a phase shifter is arranged in one of transmission regions adjacent to each other, and the phases of light transmitted through both transmission regions are inverted with each other. In the modified illumination technique, which is one of the super-resolution techniques, in an exposure apparatus, a stop not provided on the optical axis of an optical system is inserted, an exposure light beam is obliquely incident on a photomask, and diffracted by the photomask. This is a technique for improving the resolution and the depth of focus by exposing only the 0th-order light and + 1st-order or -1st-order light. For example, a ring-shaped illumination light source having a ring shape or a quadrupole having only four light sources is provided. Illumination and the like are typical.

On the other hand, a pattern on a photomask (hereinafter, referred to as a pattern)
There is a method of applying OPC to improve the fidelity resolution performance of a mask pattern. This involves transferring a mask pattern onto a semiconductor wafer, extracting defective portions of the transferred pattern, and correcting the mask pattern or OP.
This is a method of applying feedback to a photomask so that a desired pattern is formed on a semiconductor wafer by a method of manually arranging a C pattern. Then, OPC placement rules are created by this method, and DA (DesignAutomati
on) There is also a method to automatically correct on (rule-based OP
C). Further, a method of directly optimizing an OPC pattern on DA by performing a detailed simulation of the light intensity distribution of the mask pattern (simulation base OP)
C) has also been proposed.

[0005]

However, the present inventor has found that there are the following problems in the super-resolution technology and the OPC technology.

That is, in the super-resolution technology, it is becoming difficult to secure a sufficient process margin and a faithful resolution of a mask pattern in response to the current demand for continuous miniaturization.

In the OPC technology, although the fidelity resolution of a mask pattern is improved by arranging OPC patterns, it still takes time to see the completion of a design environment centered on an OPC automatic arranging method and a verification tool. . For this reason, it is necessary to perform a trial and error between the transfer resist pattern verification and the DA verification, it takes time and effort to optimize the photomask, and there is a problem that the product development period is lengthened or fluctuated.

Further, based on the results of the present invention, the present inventors investigated known examples from the viewpoint of overlay exposure technology. As a result, for example, Japanese Patent Application Laid-Open No. HEI 1-107527 (first study technique) discloses that line and space patterns intersecting each other are overlapped and exposed, and a rectangular pattern is overlapped on both overlapping portions (AND portion). Are disclosed. However, this technique does not mention the use of the super-resolution technique, and cannot cope with fine processing at the deep submicron level. Also, Japanese Patent Application Laid-Open
Japanese Patent Application Laid-Open No. 51068 (second study technique) discloses that a phase shift mask and a normal photomask (binary mask) are used.
A technique of transferring a comb-shaped electrode pattern or the like using a single mask has been disclosed. However, in this technique, a pattern (OR portion) of a fine pattern and a rough pattern is formed by two exposures, and the resolution by the two exposures cannot be said to be sufficient. Also, Japanese Patent Application Laid-Open No. 9-32
Japanese Patent Publication No. 1245 (Third Examination Technology) discloses a technique of forming a wiring pattern without constriction at an OR portion of both patterns by performing exposure with two photomasks of a linear pattern and a dockbone pattern. This is the same technical idea as the above second study technology. Also, Japanese Patent Application Laid-Open
Japanese Patent Application Laid-Open No. 12543 (4th study technique) discloses a technique in which two linear grating phase shift masks are overlapped and exposed, and a fine hole pattern is transferred to an intersection (AND portion) of each phase shift mask. Have been. In this technique, it is essential to use a phase shift mask for both photomasks. Further, Japanese Unexamined Patent Application Publication No. 11-143085
Japanese Patent Application Laid-Open Publication No. H5 (5th study technique) discloses that a substrate having a multi-valued intensity distribution on a substrate to be exposed by performing superimposed exposure of normal exposure and two-beam interference exposure to provide a region having a binary light intensity. Is disclosed. The multi-level exposure amount distribution is defined as one-valued, two-valued, three-valued, including the case where the exposure amount is zero. In the multi-level exposure method, it is necessary to control the exposure so that an optical resolution contrast can be obtained at a binary exposure level or higher with respect to 0 value (zero exposure amount) and 1 value (exposure amount 1). In addition, there is a complicated process and a reduced process margin.

An object of the present invention is to provide a technique capable of improving the fidelity of a pattern transferred to a semiconductor wafer by a photomask.

Another object of the present invention is to provide a technique capable of improving the resolution of a pattern transferred to a semiconductor wafer by a photomask.

Another object of the present invention is to provide a technique capable of improving a process margin in exposure processing.

It is another object of the present invention to provide a technique capable of facilitating a photomask manufacturing process.

Another object of the present invention is to provide a technique capable of shortening the manufacturing time of a photomask.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the present invention provides a first mask in which a plurality of first patterns extending in a first direction are arranged at a first distance and a second pattern extending in a second direction intersecting the first direction. A plurality of the second patterns are arranged at a second distance smaller than the first distance and are superposed and exposed on a second mask provided with a phase shifter on one of the second patterns adjacent to each other. Forming a resist pattern in which a resist portion corresponding to the first pattern and the second pattern is left and a resist portion corresponding to a region surrounded by the first pattern and the second pattern is removed; Things.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the present invention in detail,
The meaning of the terms in the present application is as follows. 1. The semiconductor wafer (semiconductor substrate) refers to a silicon single crystal substrate (generally a substantially circular shape), a sapphire substrate, a glass substrate, other insulating, anti-insulating or semiconductor substrates, and a composite substrate thereof used for manufacturing a semiconductor device. . 2. When referring to the “light-shielding region”, “light-shielding film”, and “light-shielding pattern”, 40% of the exposure light applied to the region
It has an optical property of transmitting less than. Generally, those having a percentage of less than 30% are used. On the other hand, the terms “transparent” and “transparent film” indicate that the film has an optical property of transmitting 60% or more of the exposure light applied to the region. Generally, 90% or more is used. 3. In the field of semiconductors, ultraviolet light is classified as follows.
The wavelength is less than about 400 nm, about 50 nm or more ultraviolet rays, 300 nm or more near ultraviolet rays, less than 300 nm, 20
0 nm or more is far ultraviolet light, and less than 200 nm is vacuum ultraviolet light.
Further, it is similarly possible that the principle of the present invention can be applied to a short wavelength end region of ultraviolet light of less than 100 nm and 50 nm or more. 4. When referring to the "metal film" with respect to the mask light shielding material,
Refers to similar compounds of chromium, chromium oxide, and other metals, and broadly includes simple substances, compounds, composites, and the like containing a metal element that have a light-blocking effect. 5. A photomask or a mask is a mask structure in which a pattern image is formed on a mask substrate. A pattern that is 1 to 10 times the size of the actual pattern is formed, and a “reticle” used for projection exposure by a stepper or photo repeater is also included in the photomask. It also includes a phase shift mask. 6. Phase shift mask (or phase shift reticle)
Refers to a photomask (or reticle) in which contrast is improved when a pattern is transferred by selectively shifting the phase of light using a phase shifter on a substrate on which a pattern is formed. There are Levenson type, halftone type and edge enhancement type. 7. The phase shifter refers to a substance or means that generates a phase difference by modulating the wavelength of light in a phase shift mask. Further, the phase difference refers to a phase difference caused by a speed difference of light when the light passes through two substances having different refractive indexes. In the case of a phase shift mask using a transparent film, the phase difference φ from air can be expressed by φ = 2π (n−1) d / λ.
Here, λ is the wavelength of light, n is the refractive index of the phase shifter, and d is the film thickness. 8. The “halftone phase shift mask” is a type of phase shift mask, and the transmittance of a halftone film serving as a phase shifter and a light-shielding film is 1% or more and less than 40%, and is compared with a portion without the transmittance. In this case, the phase shift amount at this time has a halftone shifter that inverts the phase of light. 9. A “Levenson-type phase shift mask (abbreviated as Levenson mask)” is a type of phase shift mask that inverts the phases of adjacent openings separated by a light-shielding region to obtain a clear image by the interference. It is. 10. Normal illumination is non-deformed illumination, and refers to illumination having a relatively uniform light intensity distribution. 11. Deformation illumination is illumination in which the illuminance at the central part is lowered, and is a super-resolution technique using multipole illumination such as oblique illumination, annular illumination, quadrupole illumination, or quadrupole illumination, or a pupil filter equivalent thereto. including.

In the following embodiments, where necessary for the sake of convenience, the description will be made by dividing into a plurality of sections or embodiments, but unless otherwise specified, they are not irrelevant to each other. One has a relationship of some or all of the other modifications, details, supplementary explanations, and the like.

In the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), the number is particularly limited to a specific number and is clearly limited to a specific number in principle. Except in some cases, the number is not limited to the specific number, and may be more than or less than the specific number.

Furthermore, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified, and when it is deemed essential in principle. Needless to say, there is nothing.

Similarly, in the following embodiments, when referring to the shapes, positional relationships, and the like of the components and the like, unless otherwise specified, and in principle, it is considered that it is clearly not the case, etc. And those similar or similar to the shape or the like. This is the same for the above numerical values and ranges.

Further, in the present application, the term “semiconductor device” means not only a device formed on a semiconductor such as a silicon wafer or a sapphire substrate or an insulator substrate, but also a TFT (Tin-type) unless otherwise specified. Film-Trans
This includes those made on other insulating substrates such as glass such as istor) and STN (Super-Twisted-Nematic) liquid crystal.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) First, before describing an embodiment of the present invention, a technique studied by the inventor and a problem thereof will be described.

FIG. 1 shows a photomask studied by the present inventors. 1A is a plan view of a main part of the photomask, FIG. 1B is a cross-sectional view taken along line AA of FIG. 1A, and FIG. 1C is a cross-sectional view taken along line BB of FIG. ing. On the main surface of the transparent mask substrate 50 constituting the photomask,
Light transmission pattern 51 in the form of a plane lattice forming light transmission region
And a plurality of planar rectangular light-shielding patterns 52 that are surrounded by the lattice-shaped light-transmitting patterns 51 to form a light-shielding region. The light transmission pattern 51 is formed by overlapping a plurality of band-shaped patterns extending in the vertical direction in FIG. It is formed by removing the metal film forming the light-shielding region on the main surface of the substrate 50. The light-shielding pattern 52 is, for example, as shown in FIG.
(A) is formed so that the horizontal dimension is longer than the vertical dimension, and is formed by leaving the metal film forming the light-shielding region. In FIG. 1A, the shading pattern 52 is hatched to make the drawing easier to see.

FIG. 2A shows an exposure area 53a of the resist film 53 when such a photomask pattern is transferred to the resist film 53 by using a reduction projection exposure apparatus. For the resist film 53, for example, a negative resist is used. Exposure area 53a irradiated with exposure light
Are shown in white, and the unexposed area 53b which is not irradiated with the exposure light is shaded. Exposure area 53a
Is a region irradiated with light transmitted through the light transmission pattern 51 of the photomask, and is formed in the same planar lattice shape as the light transmission pattern 51. The unexposed region 53b is a region where light irradiation is blocked by the pattern 52 of the photomask, and is formed in a rectangular shape like the light blocking pattern 52.

FIG. 2B shows the resist film 5 after the development process.
3 shows a partial plan view. FIG. 2C is a cross-sectional view taken along line AA in FIG. Resist film 5
The hatched area 3 is indicated by hatching, and the removed area is indicated by white. Since the resist film 53 is a negative type, the resist film 53 in the exposed area 53a is left, and the unexposed area 53b is left.
Of the resist film 53 is removed. As a result, in the resist film 53, a plurality of openings 54 are regularly formed at predetermined intervals so as to correspond to the unexposed regions 53b. However, the planar shape of the opening 54 is the same as that of the unexposed area 53.
Unlike the planar shape of b, the corners are large and the amount of shrinkage of the entire pattern is large. This problem,
This is particularly apparent when the focus of the exposure apparatus shifts.
In FIG. 2B, reference numeral 55 indicates a semiconductor substrate, and reference numeral 56 indicates an insulating film. FIG. 2C shows a case where a hole pattern 57 is formed in the insulating film 56 by performing an etching process on the insulating film 56 using the remaining resist film 53 as an etching mask. A hole pattern 57 having the same planar shape as the opening 54 is formed in the insulating film 56.

Therefore, in the present invention, one pattern is transferred to a negative resist film by overlapping two photomasks each having a simple pattern formed thereon.

First, a first specific example is shown in FIGS. FIGS. 3 and 4 show examples of the structure of the two photomasks 1A and 1B when a substantially rectangular pattern having an aspect ratio of 1: 3 or more is transferred to a negative resist film. FIGS. 3A and 4A show the photomask 1A,
1B is a plan view of an essential part, and FIGS. 3 and 4B are cross-sectional views taken along line AA in FIG.
In FIGS. 3 and 4A, the light-shielding area and the phase shifter are hatched for easy understanding of the drawings.

A photomask (first mask) 1 shown in FIG.
A is a binary mask having, for example, a duty ratio of 1: 3 or more. The mask substrate 2a constituting the photomask 1A is made of, for example, transparent synthetic quartz, and has a plurality of planar band-shaped light transmission patterns 3a on its main surface.
The light-shielding pattern 4a is interposed between the adjacent parts. The light transmission pattern 3a is a pattern formed by removing a metal film that forms the light-shielding pattern 4a on the main surface of the mask substrate 2a. FIG. 3 ( a) is formed to extend along the vertical direction.

On the other hand, in the photomask (second mask) 1B, the line size and the space size are, for example, 1/2 of the minimum processing pitch of the semiconductor device (device) with a line and space of 1: 1. Since a high resolution is required, the Levenson type phase shift mask method is applied. The mask substrate 2b constituting the photomask 1B is made of the same material as that of the mask substrate 2a, and has a plurality of planar band-shaped light transmission patterns 3b (see FIG. 4) on the main surface of the mask substrate 2b as shown in FIG. Are arranged so as to sandwich the light-shielding pattern 4b (corresponding to the space) between adjacent lines. The light transmission pattern 3b is formed by removing the metal film for forming the light shielding pattern 4b on the main surface of the mask substrate 2b, and the light transmission pattern 3b is formed such that adjacent ones are parallel to each other as shown in FIG. ) In the horizontal direction (the direction orthogonal to the direction in which the light transmission pattern 3a extends). In the photomask 1B, the phase shifter 5 is arranged on one of the light transmission patterns 3b adjacent to each other. The phase shifter 5 has a function of inverting the phase of light transmitted through the photomask 1B. That is, the phase of the light transmitted through the pattern 3b on which the phase shifter 5 is disposed is shifted 180 degrees from the phase of the light transmitted through the pattern 3b on which the phase shifter 5 is not disposed. ing. The phase shifter 5 is formed, for example, by a groove dug in the thickness direction of the mask substrate 2b. However, the phase shifter 5 is not limited to this, and can be variously changed. For example, the phase shifter 5 may be formed of a transparent film or a translucent film.

Light-shielding pattern 4 of photomasks 1A and 1B
Reference numerals a and 4b denote light-shielding regions that block exposure light, and are formed by leaving a metal film for forming the light-shielding regions. The light-shielding patterns 4a and 4b are made of a material that blocks light transmission, such as a single film of chromium or a laminated film of chromium and chromium oxide. The width of the light-shielding pattern 4a (the horizontal dimension in FIG. 3A) is formed wider than the width of the light-shielding pattern 4b (the vertical dimension in FIG. 4A).

In the exposure process, after the exposure process using the photomask 1A, the exposure process using the photomask 1B is continuously performed. For example, after transferring the pattern of the photomask 1A to the resist film, the photomask 1B is set in the exposing device instead of the photomask 1A, and the pattern of the photomask 1B is transferred to the same resist film. FIG. 5 schematically shows an overlapping state of the patterns of the two photomasks 1A and 1B. The patterns of the photomasks 1A and 1B are exposed individually as described above. Here, the patterns are formed so that the two-dimensional positional relationship between the two photomasks 1A and 1B can be understood. Are superimposed. As shown in FIG. 5, at the time of exposure, both photomasks 1A and 1B are arranged in a state where their light transmission patterns 3a and 3b are aligned (intersecting) with each other.

FIGS. 6 (a) to 6 (c) express the exposure state on the resist film side in each of FIGS. 3 to 5 in a multi-valued manner.

FIG. 6A shows the exposure level of the surface to be exposed in a multi-valued manner when only the photomask 1A shown in FIG. 3 is used. A region P1 (a band-like region extending in the vertical direction in FIG. 6A with hatching) is a region corresponding to the light transmission pattern 3a of the photomask 1A, and the exposure level of "1" is displayed. Have been. The region N1 (a band-shaped region sandwiched between the regions P1 and extending in the vertical direction in FIG. 6A) is a light-shielding pattern 4a of the photomask 1A.
And the exposure level of “0” value is displayed since it is an unexposed area.

FIG. 6B expresses the exposure level of the surface to be exposed in a multi-valued manner when only the photomask 1B of FIG. 4 is used. A region P2 (a band-like region extending in the horizontal direction in FIG. 6B with hatching) is a region corresponding to the light transmission pattern 3b of the photomask 1B, and the exposure level of “1” is displayed. Have been. The region N2 (a band-like region sandwiched between the regions P2 and extending in the horizontal direction in FIG. 6B) is a light-shielding pattern 4b of the photomask 1B.
And the exposure level of “0” value is displayed since it is an unexposed area.

FIG. 6C shows two photomasks 1A,
The exposure level of the surface to be exposed in the case of FIG. Since the overlapping area P3 of the areas P1 and P2 receives the exposure of the “1” value twice, the effective exposure level becomes the “2” value. In addition, the area N
The overlapping region N3 (AND region, rectangular region in which the horizontal dimension in FIG. 6C is longer than the vertical dimension in FIG. 6C) of 1 and N2 is exposed regardless of which of the photomasks 1A and 1B is used. Therefore, the exposure level becomes the “0” value. Therefore, when a negative resist film is used, the exposure level (line portion) of “1” value and “2”
Obtaining an optical resolution contrast between the exposure level of the value (line overlapping portion) and the exposure level of the “0” value (the unexposed portion) provides a substantially rectangular area N3 in the negative resist film. A pattern (opening) can be formed.

FIG. 7 shows the two photomasks 1A and 1A.
B, a resist film 6 applied on a semiconductor wafer
(Exposed area 6P is hatched for easy viewing of the drawing). As the resist film 6, for example, a chemically amplified negative resist film is used. The exposure area 6P is an exposure area 6P1 extending in a strip shape in the vertical direction in FIG. 7 (corresponding to the above-described area P1).
7, an exposure region 6P2 (corresponding to the above-described region P2) extending in the lateral direction in a strip shape in FIG. It has a lattice shape. The unexposed area 6N
This is a region corresponding to the region N3, and has a planar rectangular shape whose horizontal dimension in FIG. 7 is longer than its vertical dimension.

FIG. 8A shows a case where such a resist film 6 has been subjected to a developing process. FIG. 8B is a cross-sectional view taken along the line AA of FIG. Shaded hatching is shown in the region where the resist film 6 is left, and the removed region is shown in white. Here, since the resist film 6 is a negative type, the resist film 6 in the exposed region 6P in FIG. 7 is left, and the resist film 6 in the unexposed region 6N is removed. As a result, in the resist film 6, a plurality of openings 7 are regularly formed at predetermined intervals so as to correspond to the unexposed areas 6N. Also in this case, the planar shape of the opening 7 is different from the planar shape of the unexposed region 6N, and is a rectangular pattern with rounded corners. The amount of shrinkage is small, and can be close to the planar shape of the unexposed area 6N, that is, the designed planar shape.

The semiconductor substrate 8 shown in FIG. 8B is a semiconductor thin plate called a semiconductor wafer made of, for example, single crystal silicon and having a substantially circular shape in a plane. The insulating film 9 on the semiconductor substrate 8 is, for example, a silicon oxide film, a silicon nitride film, an SOG (Spin On Glass) film, or a PSG (Phospho Silo).
icate Glass film, BPSG (Boro Phospho SilicateGl)
(ass) A single film of the film or a laminated film obtained by stacking two or more of these films. FIG. 8 (c)
Uses the remaining resist film 6 as an etching mask,
By performing the etching process on the insulating film 9,
A case where a hole pattern 10 is formed in the insulating film 9 is shown. A hole pattern 10 having the same planar shape as the opening 7 is formed in the insulating film 9.

FIG. 9 schematically explains the reason why the planar shape of the opening 7 is not completely rectangular but rounded at its corners. Areas with relatively thin hatching are areas where the cross-linking reaction of the resist film due to acid diffusion has progressed despite being originally light-shielding areas, and areas with relatively dark hatching The shaded area indicates an area where the crosslinking reaction has not progressed (unexposed area N). Arrows indicate the direction of progress of the crosslinking reaction.

That is, in the overlapping area of the light transmitting patterns 3a and 3b, both transmitted lights overlap, and the effective exposure level is "2" (see FIG. 6C). 3b and in the vicinity thereof,
In the area shown by the circle in FIG. 9, the crosslinking reaction of the resist film due to the acid diffusion proceeds in the direction shown by the arrow, and the resist film is in the same state as when the resist film is exposed in spite of being a light shielding area. . Therefore, an opening 7 (see FIG. 8), which is smaller than the original and has rounded corners, is formed in the resist film after development. In the case of the first embodiment, the reason why the roundness is small is that the light transmissive patterns 3a and 3b are separately exposed, so that the range of the cross-linking reaction of the resist film due to acid diffusion can be reduced.

Next, a second example (modification) of the technical concept of the present invention will be described. 10 and 11 show specific examples. FIGS. 10 and 11A are plan views of essential parts of the photomasks 1C and 1D, and FIGS. 10B and 11B are cross-sectional views taken along line AA of FIGS. ing. FIG. 12 shows the two photomasks 1.
The overlapping state of the C and 1D patterns is schematically shown. The patterns to be transferred to the resist film in the photomasks 1C and 1D of FIGS. 10 and 11 are the same as those of the photomasks shown in FIGS. Also,
In FIGS. 10 (a), 11 (a) and 12,
Shaded hatching is applied to the light-shielding region and the phase shifter for easy understanding of the drawing.

In the photomask 1C shown in FIG. 10, for example, the duty ratio in the horizontal direction in FIG. 10 is 1: 3 or more, and the duty ratio in the vertical direction in FIG.
y) The plurality of light transmission patterns 3c so that the ratio becomes 1: 1.
Are arranged regularly. Light transmission pattern 3c
Has a square shape. Here, FIG.
In the illustrated example, the Levenson-type phase shift mask method is applied to the photomask 1C in order to obtain the vertical optical resolution contrast. That is, the phase shifter 5 is attached to one of the light transmission patterns 3c adjacent to each other.
Is arranged. Therefore, the phase of the light transmitted through the light transmission pattern 3c in which the phase shifter is not disposed is zero.
On the other hand, the phase of the light transmitted through the light transmission pattern 3c in which the phase shifter 5 is disposed is 180 degrees inverted.

On the other hand, the photomask 1D is the same as the photomask 1B. The light transmission pattern 3d and the light shielding pattern 4d of the photomask 1D correspond to the light transmission pattern 3b and the light shielding pattern 4b of the photomask 1B, respectively. Here, the photomasks 1C, 1
When D is overlapped, as shown in FIG.
The light transmission pattern 3d of the photomask 1D is arranged between the light transmission patterns 3c of C in the vertical direction in FIG. That is, the light transmission patterns 3c in the dot arrangement of the photomask 1C are arranged so as to separate the horizontally adjacent light shielding patterns 4d in FIG. At the time of the overlapping, a part of the light transmission pattern 3c of the photomask 1C (a part in the vertical direction in FIG. 12) may overlap a part of the light transmission pattern 3d of the photomask 1D. By designing in this manner, it is possible to facilitate the planar alignment of the photomasks 1C and 1D. The mask substrates 2c and 2d of the photomasks 1C and 1D are made of the same material as the mask substrates 2a and 2b of the photomasks 1A and 1B. The light-shielding patterns 4c and 4d of the photomasks 1C and 1D are made of the same material as the light-shielding patterns 4a and 4b of the photomasks 1A and 1B. The phase shifters 5 of the photomasks 1C and 1D are the same as the phase shifters 5 of the photomask 1B. Also,
The exposure process in this case is the same as the case where the photomasks 1A and 1B are used, and thus the description is omitted.

FIGS. 13A to 13C correspond to FIGS.
Are multivalued representations of the exposure state on the resist film side in each of the above.

FIG. 13A shows the photomask 1 of FIG.
The exposure level of the surface to be exposed when only C is used is expressed in a multi-valued manner. An area P4 (area shaded by hatching) is an area corresponding to the light transmission pattern 3c of the photomask 1C, and displays an exposure level of “1”. Area N4 (area other than area P4)
Is an area corresponding to the light-shielding pattern 4c of the photomask 1C, and since it is an unexposed area, an exposure level of “0” value is displayed.

FIG. 13B shows the photomask 1 of FIG.
The exposure level of the surface to be exposed when only D is used is expressed in multiple values. An area P5 (area shaded with hatching) is an area corresponding to the light transmission pattern 3d of the photomask 1D, and displays an exposure level of "1". Area N5 (area other than area P5)
Is an area corresponding to the light-shielding pattern 4d of the photomask 1D, and is an unexposed area, so that an exposure level of "0" is displayed.

FIG. 13C shows two photomasks 1.
The exposure level of the surface to be exposed in the case of FIG. The area P6 is
This is a region exposed in one of the regions P4 and P5, and the exposure level is “1”. Since the area P7 is originally exposed by the area P5, the exposure level should be "1". However, since the leaked light of the diffracted light from the area P4 reaches the area P7, the area P7 is subjected to the overlapping exposure by the leaked light. Therefore, the exposure level of the area P7 is “1.5”. Also,
An overlapping area (AND area) N6 of the areas N4 and N5 (FIG. 1)
The rectangular area 3c whose horizontal dimension is longer than the vertical dimension) is not exposed when any of the photomasks 1C and 1D is used.
The value is “0”. Therefore, when a negative resist film is used, the exposure level of “1” value (line portion and dot portion) and the exposure level of “1.5” value (leakage overlap portion of diffracted light) Forming a substantially rectangular pattern (opening) in the region N6 of the negative resist film by obtaining an optical resolution contrast between the exposure level (unexposed portion) and the "0" value. Can be.

The distribution of exposed areas and unexposed areas when the two photomasks 1C and 1D of FIGS. 10 and 11 are used is the same as that of FIG. The state in which the resist film has been subjected to the development processing is the same as in FIGS. 8A and 8B. However, when the photomasks 1C and 1D are used, the roundness of the corners of the opening 7 can be further reduced than when the photomasks 1A and 1B are used.
The transfer shape and accuracy of the pattern can be improved. Further, it becomes possible to easily control the shape of the pattern to be transferred. This is Photomask 1
When C and 1D are used, as shown in FIG. 13C, the exposure level of the area P7 can be set to a value of "1.5", which is smaller than the exposure level of the area P3 of FIG. This is because, since the amount can be reduced, the range in which the cross-linking reaction of the resist film due to acid diffusion proceeds on the corner side of the pattern to be transferred can be small. Also in this case, the cross-sectional view of the hole pattern formed in the insulating film using the resist film left after the developing process as an etching mask is the same as FIG. 8C.

Next, with respect to various pairs of photomasks, when the plane aspect ratio of the pattern to be transferred (opening 7) was changed variously, an experiment of the pattern formed on the resist film and the light intensity distribution was carried out. The results will be described.

First, before describing the experimental results, the structure of the photomask in the case where the two masks used in the experiment are binary masks and in the case where the two masks are both Levenson masks will be described.

FIG. 14 and FIG. 15 show the case where both of them are binary masks. (A) of FIG. 14 and FIG.
FIG. 14 is a plan view of a main part of the photomasks 1E and 1F, and FIG.
And (b) of FIG. 15 are AA of each figure (a).
FIG. 4 shows a sectional view of the line. In FIGS. 14 and 15A, the shaded area is hatched for easy understanding of the drawings.

The photomask 1E shown in FIG. 14 is the same as the photomask 1A. The light transmitting pattern 3e and the light shielding pattern 4e of the photomask 1E are the light transmitting pattern 3a and the light shielding pattern 4 of the photomask 1A, respectively.
a. On the other hand, the photomask 1 shown in FIG.
F is almost the same as the photomask 1B, except that the phase shifter 5 (see FIG. 3B) of the photomask 1B is not formed. The light transmission pattern 3f and the light shielding pattern 4f of the photomask 1F correspond to the light transmission pattern 3b and the light shielding pattern 4b of the photomask 1B, respectively. FIG. 16 schematically shows a pattern in which the patterns of the photomasks 1E and 1F are overlapped.

FIGS. 17 and 18 show the case where both the Levenson masks are used. FIGS. 17A and 18A are plan views of main parts of the photomasks 1G and 1H.
(B) of FIG. 17 and FIG. 18 are cross-sectional views taken along line AA of (a) of each figure. In FIGS. 17 and 18A, the light-shielding region and the phase shifter are hatched for easy understanding of the drawings.

The photomask 1G shown in FIG. 17 is almost the same as the photomask 1A, except that the phase shifter 5 is arranged on one of the light transmission patterns 3g adjacent to each other. The light transmission pattern 3g and the light shielding pattern 4g of the photomask 1G correspond to the light transmission pattern 3a and the light shielding pattern 4a of the photomask 1A, respectively. The operation of the transmitted light by the phase shifter 5 is the same as that of the photomask 1B, and thus the description is omitted. On the other hand, FIG.
Is the same as the photomask 1B. The light transmission pattern 3h and the light shielding pattern 4h of the photomask 1H correspond to the light transmission pattern 3b and the light shielding pattern 4b of the photomask 1B, respectively.
FIG. 19 schematically shows a pattern in which the patterns of the photomasks 1G and 1H are overlapped.

Next, the experimental results when the photomasks 1A to 1H are used will be described with reference to FIGS. Here, the first photomasks 1A, 1C,
By changing the pattern pitch of 1E and 1G, the aspect ratio of the pattern to be transferred was changed from 1: 1 to 1: 4.

FIGS. 20 to 23 show the case where a binary mask is used for each of the two sheets, and the aspect ratio of the pattern to be transferred corresponds to 1: 1 to 1: 4. 20 to 23, (a) is a plan view of a main part of a first photomask 1E, (b) is a plan view of a main part of a second photomask 1F, and (c) is a stack of the photomasks 1E and 1F. The exposure surfaces of the resist film in the case where the resist film is exposed to light are shown. 24 to 27 show simulations of the light intensity distribution corresponding to FIGS. 20 to 23,
In each figure, (a) shows two photomasks 1E and 1F.
, A planar light intensity distribution diagram obtained by overlapping exposure, (b)
Is a cross-sectional light intensity distribution diagram in the lateral direction (X direction) of FIG.
(C) shows a sectional light intensity distribution diagram in the vertical direction (Y direction) of (a). It can be seen that in such a superposition exposure of two binary masks, sufficient resolution performance cannot be obtained in both the X and Y directions at any aspect ratio.

FIGS. 28 to 31 show the case where the Levenson mask is used for both sheets, and the aspect ratio of the pattern to be transferred corresponds to 1: 1 to 1: 4. 28A to 31, (a) is a plan view of a main part of a first photomask 1G, (b) is a plan view of a main part of a second photomask 1H, and (c) is a stack of the photomasks 1G and 1H. The exposed surfaces of the resist film in the case of exposing the resist film are shown. FIGS. 32 to 35 show simulations of light intensity distributions corresponding to FIGS. 28 to 31,
In each figure, (a) shows two photomasks 1G and 1H.
, A planar light intensity distribution diagram obtained by overlapping exposure, (b)
Is a cross-sectional light intensity distribution diagram in the lateral direction (X direction) of FIG.
(C) shows a sectional light intensity distribution diagram in the vertical direction (Y direction) of (a). In such overlapping exposure of two binary masks, when the pattern to be transferred has an aspect ratio of 1: 1, a sufficient optical contrast is obtained in the X and Y directions. However, when the aspect ratio is 1: 3 or more, it has been found from the experimental results of the present inventors that the optical contrast in the X direction decreases and the separation and resolution performance by the phase shifter cannot be obtained.

FIGS. 36 to 39 show the case where the photomasks 1A and 1B of the technical idea of the present invention are used.
The aspect ratio of the pattern to be transferred is 1: 1 to 1:
4 respectively. 36A to 39, (a) is a plan view of a main part of the first photomask 1A,
(B) is a plan view of a main part of the second photomask 1B, (c).
Indicates the exposed surface of the resist film when the photomasks 1A and 1B are overlaid and exposed. Also, FIG.
FIG. 43 shows a simulation of the light intensity distribution corresponding to FIG. 36 to FIG.
A planar light intensity distribution diagram obtained by superposing and exposing the photomasks 1A and 1B, (b) is a cross-sectional light intensity distribution diagram in the lateral direction (X direction) of (a), and (c) is FIG. 3A shows a cross-sectional light intensity distribution diagram in the vertical direction (Y direction). In such overlapping exposure of two photomasks, when the aspect ratio of the pattern to be transferred is 1: 3 or more, the same level of optical contrast as in the case of using the two Levenson masks is obtained. ing. Therefore, when transferring an approximately rectangular fine pattern having an aspect ratio of 1: 3 or more, it is not always necessary to use two Levenson masks, and it is necessary to perform exposure by overlapping a Levenson mask and a binary mask. It has been found from the experimental results of the present inventors that sufficient resolution is possible.
In this case, there is no need to consider the phase of the transmitted light and it is not necessary to form a phase shifter, so that the design and manufacture of the photomask 1A are easy.

FIGS. 44 to 47 show the case where the photomasks 1C and 1D according to the technical idea of the present invention are used.
The aspect ratio of the pattern to be transferred is 1: 1 to 1:
4 respectively. 44A to 47B, (a) is a plan view of a main part of the first photomask 1C,
(B) is a plan view of a main part of the second photomask 1D, (c).
Indicates exposure surfaces of the resist film when the photomasks 1C and 1D are overlapped and exposed. In addition, FIG.
FIG. 51 shows a simulation of the light intensity distribution corresponding to FIG. 44 to FIG.
A planar light intensity distribution diagram obtained by superposing and exposing two photomasks 1C and 1D, (b) is a cross-sectional light intensity distribution diagram in the horizontal direction (X direction) of (a), and (c) is FIG. 3A shows a cross-sectional light intensity distribution diagram in the vertical direction (Y direction). In such a superposition exposure of two photomasks, X and X are independent of the difference in aspect ratio of the pattern to be transferred.
High optical resolution contrast is obtained in the Y direction.
In this case, as described above, the photomask 1A,
The roundness of the corner of the opening 7 can be further reduced as compared with the case where 1B is used, and the transfer shape and accuracy of the pattern can be improved. Further, it becomes possible to easily control the shape of the pattern to be transferred.

Next, the exposure process of the first embodiment will be described with reference to FIG. FIG. 52 is a process flow chart of the exposure process.

First, two photomasks 1A and 1B (or 1C and 1D) are loaded in a reduction projection exposure apparatus. Further, a semiconductor wafer as a substrate to be exposed is loaded into the reduction projection exposure apparatus. The resist film 6 (see FIG. 8B) is already applied on the main surface of the semiconductor wafer (Step 101). Subsequently, the first photomask 1A (or 1C) is removed from the mask stocker of the reduction projection exposure apparatus.
The wafer is loaded on the mask stage of the reduction projection exposure apparatus (Step 102). Then, on the mask stage, the first
The first photomask 1A (or 1C) and the mask stage are aligned in a planar manner.
The alignment accuracy between A (or 1C) and the mask stage is improved (step 103). Thereafter, when the semiconductor wafer is loaded on the wafer stage, planar alignment between the photomask 1A (or 1C) and the semiconductor wafer is performed. Thereby, the photomask 1A (or 1)
Improve the planar alignment accuracy between C) and the semiconductor wafer (step 104). After going through such a process,
An exposure process is performed using the photomask 1A (or 1C) (Step 105).

Next, instead of the first photomask 1A (or 1C), a second photomask 1B (or 1C) is used.
D) is loaded on the mask stage of the reduction projection exposure apparatus (step 106). Subsequently, the second photomask 1
Also for B (or 1D), steps 107 and 1 similar to the first photomask planar alignment step 103 and the semiconductor wafer planar alignment step 104 are performed.
08. However, at this stage (first exposure processing step 1)
Since the semiconductor wafer is not attached to or detached from the wafer stage after (after step 05), the step 108 of aligning the semiconductor wafer in a planar manner can be omitted. That is, here, the positioning information obtained in step 104 is used as it is. As a result, the error in the above step 104 is added to the value in step 10
The potential of adding a new error re-measured at 8 can be avoided. After such a process, the photomask 1B (or 1D) is continuously formed following the first exposure process.
Is performed (step 109). Then, after passing through such steps 101 to 109, the semiconductor wafer is moved to the developing unit (step 110), and the developing processing is performed.

Next, an example of a reduction projection exposure apparatus used in the first embodiment is shown in FIG. This reduction projection exposure apparatus 1
1 is, for example, a reduction ratio of 1/4, the exposure light is a KrF excimer laser (wavelength λ = 0.248 μm), the coherency σ is 0.3 or less, preferably 0.1 or less, and the aperture characteristic NA of the projection optical lens is 0. 68 is an exposure apparatus. Although not particularly limited, the reduction projection exposure apparatus 11 includes a mask stocker that can store two or more types of different photomasks. However, the present invention is not limited to the exposure apparatus under the above conditions, and can be variously applied. For example, a KrF excimer stepper (reduction ratio of 1/5), NA: 0.6 to 0.
68, σ: 0.3 to 0.8 or annular illumination is applicable.

The exposure light emitted from the exposure light source 11a of the reduction projection exposure apparatus 11 is applied to the photomask 1A (or 1B, 1C, 1D) via the fly-eye lens 11b, the condenser lenses 11c, 11d, and the mirror 11e. You. Photomask 1A (or 1B, 1C, 1D)
Is transferred to a resist film (the above-described chemically amplified negative resist film) applied on the main surface of the semiconductor substrate (semiconductor wafer) 8 on the sample stage 11g via the projection lens 11f. Photomask 1A (or 1B, 1
C, 1D) are mounted on the mask stage 11h in a state where the relative plane position between the center of the plane and the optical axis of the projection lens 11f is accurately aligned. The mask stage 11h includes a photomask 1A (or 1B, 1C, 1P).
It is installed on the main surface of D) so as to be movable in the horizontal and vertical directions. The movement of the mask stage 11h is controlled by the mask position control means 11i. The sample stage 11g is mounted on a Z stage 11j. The Z stage 11j is mounted on the XY stage 11k so as to be movable in the optical axis direction of the projection lens 11f (vertical direction in FIG. 53). The XY stage 11k is installed so as to be movable in a direction horizontal to the main surface of the semiconductor substrate 8 and in X and Y directions crossing each other.
Such a Z stage 11j and an XY stage 11k
Are driven by respective driving units 11p and 11q in response to a control command from the main control system 11m. Therefore, it is possible to move the semiconductor substrate 8 to a desired exposure position. The plane position is the Z stage 11
The position of the mirror 11r fixed to j is accurately monitored by the laser length measuring device 11s.

Next, the technical idea of the present invention is described, for example, by DRA.
A case where the invention is applied to M will be described. FIG. 54 is an overall plan view of a semiconductor chip 8C on which the DRAM of the present embodiment is formed. As shown in the figure, for example, a large number of memory arrays MARY are arranged along the X direction (long side direction of the semiconductor chip 8C) and the Y direction (long side direction of the semiconductor chip 8C) on the main surface of the planar rectangular semiconductor chip 8C. Are arranged in a matrix. A sense amplifier SA is arranged between memory arrays MARY adjacent to each other along the X direction. In the center of the main surface of the semiconductor chip 8C, control circuits such as a word driver WD and a data line selection circuit,
Input / output circuits, bonding pads, and the like are arranged.

FIGS. 55 and 56 are enlarged plan views of main parts of a memory cell array MARY of a DRAM, and FIGS.
FIG. 3 is a sectional view taken along line AA of FIG. FIG. 55 is a plan view showing a state where a contact hole for electrically connecting the bit line and the source / drain semiconductor region of the memory cell selection MISFET is formed. FIG. FIG. 3 shows a plan view of a stage where a lower electrode of a capacitive element for use C is formed.

The memory cell of the DRAM is formed in a p-type well 12 formed on the main surface of a semiconductor substrate 8 made of p-type single crystal silicon. The p-type well 12 in the region (memory array) in which the memory cell is formed
In order to prevent noise from entering from an input / output circuit or the like formed in another region, the semiconductor substrate 8 is electrically separated by an n-type semiconductor region 13 formed thereunder.

The memory cell is a memory cell selecting MISF.
It has a stacked structure in which an information storage capacitor C is arranged above ETQs. MIS for memory cell selection
The FET Qs is composed of an n-channel type MISFET,
It is formed in the active region L of the mold well 12. The active region L is formed of an elongated island-shaped pattern extending straight along the X direction in FIGS. 55 and 56. Each active region L has one of a source and a drain (n-type semiconductor region). ) For memory cell selection sharing each other
Two FETs Qs are formed adjacent to each other in the X direction.

An element isolation region surrounding the active region L is formed by a trench-type element isolation portion (trench isolation) 14 formed by embedding an insulating film made of a silicon oxide film or the like in a shallow groove formed in a p-type well 12. It is configured. The insulating film buried in the groove-shaped element isolation portion 14 is flattened so that its surface is substantially the same height as the surface of the active region L. Since the element isolation region formed by such a groove-type element isolation portion 14 cannot have a bird's beak at the end of the active region L, the LOCOS
The effective area of the active region L is larger than that of an element isolation region (field oxide film) of the same size formed by the (Local Oxidization of Silicon: selective oxidation) method. Also,
Excellent flatness.

The memory cell selecting MISFET Qs mainly includes a gate insulating film 15, a gate electrode 16, and a pair of n-type semiconductor regions 17, 1 constituting a source and a drain.
7. The gate electrode 16 is formed integrally with the word line WL, and extends linearly in the Y direction with the same width and the same space. The gate electrode 16 (word line WL) is made of, for example, a low-resistance polycrystalline silicon film doped with an n-type impurity such as P (phosphorus), and a barrier metal such as a WN (tungsten nitride) film formed thereon. It has a polymetal structure composed of a layer and a refractory metal film such as a W (tungsten) film formed thereon. Since the gate electrode 16 (word line WL) having a polymetal structure has lower electric resistance than a gate electrode formed of a polycrystalline silicon film or a polycide film, the signal delay of the word line WL can be reduced. However, the gate electrode 16 may be composed of a single film of a polycrystalline silicon film, or may have the above-mentioned polycide structure in which a silicide film such as tungsten silicide is stacked on the polycrystalline silicon film.

On the gate electrode 16 (word line WL) of the memory cell selecting MISFET Qs, a cap insulating film 18 made of a silicon nitride film or the like is formed.
On the side wall of (word line WL), an insulating film 19 made of, for example, a silicon nitride film is formed. As described later, the cap insulating film 18 and the insulating film 19 of the memory array
It is used as an etching stopper when a contact hole is formed in a self-aligned (self-aligned) manner above the source and drain (n-type semiconductor regions 17, 17) of the memory cell selection MISFET Qs. MI for memory cell selection
SFET Qs, n-channel MISFETs Qn and p
On the channel type MISFET Qp, SOG (Spin On
Glass) film 20a is formed. Also, the SOG film 2
0a, two insulating films 20b and 20c made of silicon oxide or the like are formed on the upper insulating film 20a.
c is flattened so that its surface is substantially the same height over the entire area of the semiconductor substrate 8.

A pair of n-type semiconductor regions 17, 1 constituting the source and drain of the memory cell selecting MISFET Qs
7, the insulating films 20b and 20c and the SOG film 2
Contact holes 21a and 21b penetrating through Oa are formed. These contact holes 21a, 21b
Inside the plug 22 formed of a low-resistance polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)).
Is embedded.

The diameter of the bottom of the contact holes 21a and 21b in the X direction depends on the space between the insulating film 19 on one side wall of the two opposing gate electrodes 16 (word lines WL) and the insulating film 19 on the other side wall. Stipulated. That is, the contact holes 21a and 21b are
6 (word line WL) in a self-aligned manner.

As shown in FIG. 56, one of the pair of contact holes 21a and 21b has one contact hole 2a.
The diameter of 1b in the Y direction is substantially the same as the dimension of the active region L in the Y direction. On the other hand, the diameter in the Y direction of the other contact hole 21a (the contact hole on the n-type semiconductor region 17 shared by the two memory cell selecting MISFETs Qs) is larger than the dimension of the active region L in the Y direction. Is also big. That is, the contact hole 21a is formed of a substantially rectangular planar pattern whose diameter in the Y direction is larger than the diameter in the X direction, and a part of the contact hole 21a extends from the active region L onto the groove-shaped element isolation portion 14. Are there. By configuring the contact hole 21a with such a pattern, the bit lines BL and n can be connected via the contact hole 21a.
When electrically connecting the pattern semiconductor region 17, the width of the bit line BL is partially increased to extend over the active region L, or a portion of the active region L is extended in the bit line BL direction. Since they do not need to be present, the memory cell size can be reduced.

The insulating film 20d is formed on the insulating film 20c. A through hole 23a is formed in the insulating film 20d on the contact hole 21a, and a Ti (titanium) film and a TiN (titanium nitride) are sequentially formed therein from the bottom.
A plug made of a conductive film in which a film and a W film are stacked is embedded. The through hole 23a is arranged above the groove-shaped element isolation portion 14 deviating from the active region L. The bit line BL is formed on the insulating film 21d. The bit line BL is arranged above the groove-shaped element isolation portion 13, and extends linearly in the X direction with the same width and the same space. The bit line BL is made of, for example, a tungsten film, and has a through hole 23a formed in the insulating film 20d and insulating films 20b to 20d thereunder.
MIS for memory cell selection through contact hole 21a formed in SOG film 20a and gate insulating film 15
It is electrically connected to one of the source and the drain of the FET Qs (the n-type semiconductor region 17 shared by the two memory cell selecting MISFETs Qs). Bit line BL
Is made of metal (tungsten), the sheet resistance can be reduced, so that information can be read and written at high speed. Further, since the bit line BL and the wiring of the peripheral circuit can be formed simultaneously in the same process, the manufacturing process of the DRAM can be simplified. Further, by configuring the bit line BL with a metal (tungsten) having high heat resistance and electromigration resistance, disconnection can be reliably prevented even when the width of the bit line BL is reduced.

On the bit line BL, insulating films 20e and 20f made of, for example, silicon oxide are formed. The upper insulating film 20f is flattened so that the surface is substantially the same height over the entire area of the semiconductor substrate 8. An insulating film 20g made of silicon nitride or the like is formed on the insulating film 20f of the memory cell array, and an information storage capacitor C is formed on the insulating film 20g. The information storage capacitive element C is a capacitive insulating film (dielectric film) made of a lower electrode (storage electrode) 24a, an upper electrode (plate electrode) 24b, and Ta ₂ O ₅ (tantalum oxide) provided therebetween. 24c. Lower electrode 2
4a is made of, for example, a low-resistance polycrystalline silicon film doped with P (phosphorus).
Consists of a membrane.

The lower electrode 24a of the information storage capacitor C
Are formed in an elongated, substantially rectangular pattern extending straight along the X direction in FIG. A capacitor hole (opening) described later for forming the lower electrode 24a
The above-mentioned technical idea of the present invention was applied when forming the. The lower electrode 24a is electrically connected to the plug 22 in the contact hole 21b through a plug 25 embedded in a through hole 23b penetrating the insulating film 21g and the insulating films 20d to 20f below the insulating film 21g.
2 and is electrically connected to the other of the source and the drain (the n-type semiconductor region 17) of the memory cell selection MISFET Qs. Lower electrode 24a and contact hole 2
A plug 25 made of, for example, a low-resistance polycrystalline silicon film doped with P (phosphorus) is buried in the through hole 23b formed between the plug 25 and the through hole 23b.

A two-layer insulating film 20h made of silicon oxide or the like is formed above the information storage capacitive element C, and a second-layer wiring 26a is formed thereon.
The second-layer wiring 26a is made of a conductive film mainly composed of an Al (aluminum) alloy. Second layer wiring 2
An insulating film 20 made of two layers of silicon oxide or the like is formed on 6a.
i, 20j are formed. Among them, the lower insulating film 20i is formed by a high density plasma (High Density Plasma) CVD method excellent in gap fill property of the wiring 26a. The insulating film 20 on this insulating film 20i
j is flattened so that its surface is substantially the same height over the entire area of the semiconductor substrate 8. A third-layer wiring 26b is formed on the insulating film 20j. The third-layer wiring 26b is made of a conductive film mainly composed of an Al alloy, like the second-layer wiring 26a.

Next, an example in which the technical idea of the present invention is applied to the above-described DRAM manufacturing method will be described with reference to FIGS. FIG. 58 shows the process up to the step of depositing the insulating film 20g made of, for example, a silicon nitride film. At this stage, the upper surface of the plug 25 is covered with the insulating film 20g. Subsequently, as shown in FIG. 59, after an insulating film 27 made of, for example, a silicon oxide film or the like is formed on the insulating film 20g, a capacitor for forming a lower electrode of the information storage capacitor is formed on the insulating film 27. The holes 7a (corresponding to the openings 7) are formed in the photomasks 1A, 1B (or 1C, 1C).
It is formed by a photolithography technique using D) and a dry etching technique. The upper surface of the plug 25 is exposed from the bottom surface of the capacitor hole 7a. The planar shape of capacitor hole 7a is equal to the planar shape of lower electrode 24a in FIG. In the first embodiment, by applying the technical concept of the present invention to the method of forming the capacitor hole 7a of the DRAM, the planar shape of the capacitor hole 7a can be made closer to the designed planar shape. That is, the roundness of the planar shape of the capacitor hole 7a can be reduced.
Therefore, the surface area of the lower electrode 24a formed by the capacitor hole 7a can be increased, so that the capacitance of the information storage capacitor C can be increased. Therefore, the operation reliability of the DRAM can be improved. Further, the refresh characteristics of the DRAM can be improved. Thereafter, as shown in FIG. 60, a conductor film 24 for forming a lower electrode is deposited in the capacitor hole 7a and on the upper surface of the insulating film 27 by a CVD method or a sputtering method, and then in the capacitor hole 7a and in the peripheral circuit region. A resist film 28a is formed. afterwards,
By using the resist film 28a as a mask to remove the conductive film 24 on the insulating film 27 by etching, the lower electrode 24a shown in FIG. 57 is formed. Then, the insulating film 20g
Is used as an etching mask, the insulating film 27 is removed, and then the capacitor insulating film 24c and the upper electrode 24b are formed. Subsequent steps may be performed by applying a normal DRAM manufacturing method, and a description thereof will be omitted.

According to the first embodiment, the following effects can be obtained. (1) By superposing and exposing two photomasks each having a simple pattern formed thereon, it becomes possible to easily resolve each pattern. (2) By superposing and exposing a normal photomask and a photomask having a phase shifter, it is possible to improve the resolution of a high-density and fine desired pattern. (3). According to the above (1) and (2), the fidelity of the pattern in the exposure processing can be improved. (4) According to the above (1) and (2), the process margin in the exposure processing can be improved. (5) According to the above (1), (2), (3), and (4), the resolution of a high-density and minute desired pattern can be
Since the fidelity and the process margin can be improved, a highly integrated and high performance semiconductor device can be provided at low cost.

(Embodiment 2) FIGS. 61 and 62A are plan views of main parts of photomasks 1I and 1J used in a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention. 61 and 62 (b) and (c) are cross-sectional views taken along line AA and line BB of FIG. FIG. 63 schematically shows an overlapping state of the patterns of the two photomasks 1I and 1J. The patterns to be transferred to the resist film in the photomasks 1I and 1J are the same as those in the photomask shown in FIGS. 3 and 4 used in the first embodiment. Also, FIGS. 61 (a), 62 (a) and 6
In FIG. 3, shaded hatching is applied to the light-shielding region for easy understanding of the drawing.

The arrangement of the light transmitting pattern 3i and the light shielding pattern 4i of the photomask (first mask) 1I is the same as the arrangement of the light transmitting pattern 3a and the light shielding pattern 4a of the photomask 1A. In addition, a photomask (second
The arrangement of the light transmitting pattern 3j and the light shielding pattern 4j of the (mask) 1J is the same as the arrangement of the light transmitting pattern 3b and the light shielding pattern 4b of the photomask 1B. The difference is that the light transmission patterns 3 of the photomasks 1I and 1J are different.
i, 3j, both photomasks 1I, 1
When J is overlapped, the width of the region where both light transmission patterns 3i and 3j intersect is smaller than the width of the region where they do not intersect. That is, in the intersecting region, a part of the light shielding patterns 4i, 4j protrudes from both long sides of the light transmitting patterns 3i, 3j toward the center. In the second embodiment as described above, as shown in FIG. When 1J is superimposed, the light-shielding patterns 4i1 and 4j, which are part of the light-shielding patterns 4i and 4j, are located in the intersection area of the light-transmitting patterns 3i and 3j.
1 will be arranged. This light-shielding pattern 4i1,
4j1 are arranged at the four corners of the light shielding patterns 4i and 4j for forming the pattern to be transferred to the resist film. As a result, as shown in FIG. 64, the progress of the crosslinking reaction of the resist film due to the acid diffusion from the intersection region of the light transmission patterns 3i and 3j to the light-shielding region can be suppressed, and the progress range can be reduced. As a result, the roundness of the corners of the opening 7 (see FIG. 8) formed in the developed resist film can be further reduced. Therefore, it is possible to improve the shape and dimensional accuracy of the transfer pattern as compared with the case where the photomasks 1A and 1B of the first embodiment are used (shown by broken lines). In FIG. 64, a region with relatively dark hatching indicates a region where the crosslinking reaction has not progressed. The relatively thin hatched hatching corresponds to the light-shielding pattern, and the white area corresponds to the light-transmitting pattern. Arrows indicate the direction of progress of the crosslinking reaction. The mask substrates 2i and 2j of the photomasks 1I and 1J are made of the same material as the mask substrates 2a and 2b of the photomasks 1A and 1B. The light-shielding patterns 4i and 4j of the photomasks 1I and 1J are made of the same material as the light-shielding patterns 4a and 4b of the photomasks 1A and 1B. Further, the exposure processing in this case is the same as that in the first embodiment, and the description is omitted. When the pattern size transferred onto the semiconductor wafer is on the order of submicrons, the light transmission pattern 3j of the photomask 1J also has
As in the case of the photomask 1B, it is necessary to dispose a phase shifter. However, when the pattern size to be transferred onto the semiconductor wafer is large, the phase shifter need not be provided.

(Embodiment 3) FIGS. 65 and 66 are plan views of main parts of photomasks 1K and 1M used in a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention. (B) of FIG. 66 is a cross-sectional view taken along line AA of (a) of each drawing. FIG. 65
66A and FIG. 66A, shaded hatching is applied to the light-shielding region for easy understanding of the drawing.

The photomask 1K shown in FIG. 65 is almost the same as the photomask 1A. The light transmission pattern 3k and the light shielding pattern 4k of the photomask 1K correspond to the light transmission pattern 3a and the light shielding pattern 4a of the photomask 1A, respectively. What is different is the light transmission pattern 3
k is the light transmission pattern 3a of the photomask 1A.
The width of the light transmitting pattern 3k and the light shielding pattern 4k is 1: 1. On the other hand, FIG.
Is substantially the same as the photomask 1F. Also in this case, the width dimension of the light transmitting pattern 3m and the light shielding pattern 4m is 1: 1. Light transmitting pattern 3m and light shielding pattern 4m of photomask 1M
Respectively correspond to the light transmission pattern 3f and the light shielding pattern 4f of the photomask 1F. FIG. 67 schematically shows a pattern in which the patterns of the photomasks 1K and 1M are overlapped. Here, the aspect ratio of the light shielding patterns 4k, 4m surrounded by the light transmitting patterns 3k, 3m is 1: 1.

The exposure processing is performed in the same manner as in the first embodiment.
After the exposure process using the photomask 1K, the photomask 1
An exposure process using M is performed. However, in the third embodiment, an overdose is performed during the exposure processing.
FIG. 68 is a diagram schematically showing such a case. As in the first embodiment, the cross-linking reaction of the resist film by the acid diffusion from the intersection area of the light transmission patterns 3k and 3m to the light shielding patterns 4k and 4m side. As a result, a flat circular light-shielding region can be formed. Therefore, by using a negative resist film as a resist film,
As shown in (a) and (b), fine openings 7 having a flat circular shape can be formed in the resist film 6. That is, in the third embodiment, the opening 7 having a plane dimension smaller than the transfer limit dimension of the pattern by the photolithography technique can be formed by actively utilizing the crosslinking reaction of the resist film due to the acid diffusion. it can. In FIG. 68, the regions with relatively dark hatching indicate regions where the crosslinking reaction has not progressed. The relatively thin hatched hatching corresponds to the light-shielding pattern, and the white area corresponds to the light-transmitting pattern. Arrows indicate the direction of progress of the crosslinking reaction. FIG. 69B is a cross-sectional view taken along line AA of FIG. FIG.
9 (c) shows a case where a hole pattern 10 is formed in the insulating film 9 using the remaining resist film 6 as an etching mask.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

For example, in the above-described embodiment, the case where the present invention is applied to the transfer of the capacitor hole for forming the lower electrode of the DRAM has been described.

The case where KrF is used as the exposure light source during the exposure processing has been described. However, the present invention is not limited to this.
nm) may be used. Further, modified illumination may be used.

In the above description, the invention made mainly by the present inventor is described in the DRA which is the application field in which the invention is based.
M has been described, but the present invention is not limited to this. For example, SRAM (Static Random Acce
ss Memory) or flash memory (EEPROM; E)
Semiconductor device having a memory circuit such as an electric erasable programmable read only memory (RAM), a semiconductor device having a logic circuit such as a microprocessor, or a hybrid semiconductor device in which the memory circuit and the logic circuit are provided on the same semiconductor substrate. Applicable to devices.

[0092]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows. (1) According to the present invention, it is possible to separate a desired pattern into simple patterns and transfer each simple pattern by exposure, thereby facilitating the resolution of each pattern. . (2) According to the present invention, it is possible to improve the resolution of a desired high-density and fine pattern by superposing and exposing a normal first mask and a second mask having a phase shifter. (3). According to the above (1) and (2), the fidelity of the pattern in the exposure processing can be improved. (4) According to the above (1) and (2), the process margin in the exposure processing can be improved. (5) According to the above (1), (2), (3), and (4), the resolution of a high-density and minute desired pattern can be
Since the fidelity and the process margin can be improved, a highly integrated and high performance semiconductor device can be provided at low cost.

[Brief description of the drawings]

FIG. 1A is a plan view of a main part of a photomask studied by the present inventors, FIG. 1B is a cross-sectional view taken along line AA of FIG.
FIG. 3 is a sectional view taken along line BB of FIG.

FIG. 2A is an explanatory view of an exposure region of a resist film when an exposure process is performed using the photomask of FIG. 1;
1 is a plan view of a pattern transferred to a resist film by an exposure process using the photomask of FIG. 1, (c) is a cross-sectional view taken along the line AA of (b), and (d) is a resist remaining after the development process. FIG. 4 is a cross-sectional view of a pattern formed by performing an etching process on a semiconductor substrate using a film as an etching mask.

3A is a plan view of a main part of a photomask used in a method of manufacturing a semiconductor device according to the present invention, and FIG.
It is sectional drawing of a line.

4A is a plan view of a main part of a photomask used in the method of manufacturing a semiconductor device according to the present invention, and FIG.
It is sectional drawing of a line.

FIG. 5 is an explanatory view schematically showing an overlapping state of light transmission patterns in both photomasks when overlay exposure is performed using the photomasks of FIGS. 3 and 4;

FIGS. 6A to 6C are explanatory diagrams in which the exposure state on the resist film side in each of FIGS.

FIG. 7 is an explanatory diagram of an exposure region of a resist film when an exposure process is performed using the photomasks of FIGS. 3 and 4;

8A is a plan view of a pattern transferred to a resist film by an exposure process using the photomask of FIGS. 3 and 4, FIG. 8B is a cross-sectional view taken along line AA of FIG. 3C is a cross-sectional view of a pattern formed by performing an etching process on the semiconductor substrate using the resist film left after the development process as an etching mask.

FIG. 9 is an explanatory view schematically showing the reason why the planar shape of the opening formed in the resist film is not completely rectangular but rounded at the corner.

10A is a plan view of a main part of another photomask used in the method for manufacturing a semiconductor device of the present invention, and FIG. 10B is a cross-sectional view taken along line AA of FIG.

11A is a plan view of a main part of another photomask used in the method for manufacturing a semiconductor device of the present invention, and FIG. 11B is a cross-sectional view taken along line AA of FIG.

FIG. 12 is an explanatory diagram schematically showing an overlapping state of light transmission patterns in both photomasks when overlay exposure is performed using the photomasks of FIGS. 10 and 11;

FIGS. 13A to 13C are explanatory diagrams in which the exposure state on the resist film side in each of FIGS.

14A is a plan view of a main part of a photomask studied by the present inventors, and FIG. 14B is a cross-sectional view taken along line AA of FIG.

15A is a plan view of a main part of a photomask studied by the present inventors, and FIG. 15B is a cross-sectional view taken along line AA of FIG.

FIG. 16 is an explanatory diagram schematically showing an overlapping state of light transmission patterns in both photomasks when overlay exposure is performed using the photomasks of FIGS. 14 and 15;

FIG. 17A is a plan view of a main part of another photomask studied by the present inventors, and FIG. 17B is a cross-sectional view taken along line AA of FIG.

18A is a plan view of a main part of another photomask studied by the present inventors, and FIG. 18B is a cross-sectional view taken along line AA of FIG.

FIG. 19 is an explanatory diagram schematically showing an overlapping state of light transmission patterns in both photomasks when overlay exposure is performed using the photomasks of FIGS. 17 and 18.

FIG. 20 (a) shows a case where two photomasks used for overlay exposure are binary masks and the aspect ratio of a pattern to be transferred using the two masks is 1: 1; Plan view of one main part of the mask,
(B) is a plan view of the other main part of the two photomasks,
(C) is an explanatory view of an exposure region of a resist film when an exposure process is performed using the photomasks of (a) and (b).

FIG. 21A is a diagram illustrating two binary photomasks used for the overlay exposure, in which the pattern to be transferred using the binary photomask has an aspect ratio of 1: 2; Plan view of one main part of the mask,
(B) is a plan view of the other main part of the two photomasks,
(C) is an explanatory view of an exposure region of a resist film when an exposure process is performed using the photomasks of (a) and (b).

FIG. 22A is a diagram showing two binary photomasks used for the overlay exposure in which the pattern to be transferred using the binary photomask has an aspect ratio of 1: 3. Plan view of one main part of the mask,
(B) is a plan view of the other main part of the two photomasks,
(C) is an explanatory view of an exposure region of a resist film when an exposure process is performed using the photomasks of (a) and (b).

FIG. 23 (a) is a diagram illustrating two binary photomasks used for superposition exposure when the aspect ratio of the pattern to be transferred using the binary photomask is 1: 4; Plan view of one main part of the mask,
(B) is a plan view of the other main part of the two photomasks,
(C) is an explanatory view of an exposure region of a resist film when an exposure process is performed using the photomasks of (a) and (b).

24A is an explanatory diagram of a planar light intensity distribution on an exposed surface of a resist film in a case where overlay exposure is performed using the photomasks of FIGS. 20A and 20B; FIG. FIG. 7A is an explanatory diagram of a light intensity distribution in a horizontal cross section, and FIG.

25 (a) is an explanatory view of a planar light intensity distribution on an exposed surface of a resist film when superposed and exposed using the photomasks of FIGS. 21 (a) and 21 (b), and FIG. FIG. 7A is an explanatory diagram of a light intensity distribution in a horizontal cross section, and FIG. 7C is an explanatory diagram of a light intensity distribution in a vertical cross section of FIG.

26A is an explanatory diagram of a planar light intensity distribution on an exposed surface of a resist film in a case where overlay exposure is performed using the photomasks of FIGS. 22A and 22B; FIG. FIG. 7A is an explanatory diagram of a light intensity distribution in a horizontal cross section, and FIG. 7C is an explanatory diagram of a light intensity distribution in a vertical cross section of FIG.

FIG. 27A is an explanatory view of a planar light intensity distribution on an exposed surface of a resist film when superposed exposure is performed using the photomasks of FIGS. 23A and 23B; FIG. 7A is an explanatory diagram of a light intensity distribution in a horizontal cross section, and FIG. 7C is an explanatory diagram of a light intensity distribution in a vertical cross section of FIG.

FIG. 28A shows a case where two photomasks used for overlay exposure are Levenson-type phase shift masks and the pattern to be transferred using the same has an aspect ratio of 1: 1. (B) is a plan view of the other main part of the two photomasks, and (c) is an exposure process using the photomasks (a) and (b). FIG. 4 is an explanatory diagram of an exposure region of a resist film when performing the operation.

FIG. 29 (a) shows a case where two photomasks used for the overlay exposure are Levenson-type phase shift masks and the pattern to be transferred using the photomasks has an aspect ratio of 1: 2; (B) is a plan view of the other main part of the two photomasks, and (c) is an exposure process using the photomasks (a) and (b). FIG. 4 is an explanatory diagram of an exposure region of a resist film when the process is performed.

FIG. 30A shows a case where two photomasks used for the overlay exposure are Levenson-type phase shift masks and the pattern to be transferred using the photomasks has an aspect ratio of 1: 3; (B) is a plan view of the other main part of the two photomasks, and (c) is an exposure process using the photomasks (a) and (b). FIG. 4 is an explanatory diagram of an exposure region of a resist film when the process is performed.

FIG. 31A shows a case where two photomasks used for the overlay exposure are Levenson-type phase shift masks and the pattern to be transferred using the photomask has an aspect ratio of 1: 4; (B) is a plan view of the other main part of the two photomasks, and (c) is an exposure process using the photomasks (a) and (b). FIG. 4 is an explanatory diagram of an exposure region of a resist film when the process is performed.

FIG. 32 (a) is an explanatory view of a planar light intensity distribution on an exposed surface of a resist film in a case where overlay exposure is performed using the photomasks of FIGS. 28 (a) and 28 (b); FIG. 7A is an explanatory diagram of a light intensity distribution in a horizontal cross section, and FIG. 7C is an explanatory diagram of a light intensity distribution in a vertical cross section of FIG.

FIG. 33 (a) is an explanatory view of a planar light intensity distribution on an exposed surface of a resist film in a case where overlapping exposure is performed using the photomasks of FIGS. 29 (a) and 29 (b); FIG. 7A is an explanatory diagram of a light intensity distribution in a horizontal cross section, and FIG. 7C is an explanatory diagram of a light intensity distribution in a vertical cross section of FIG.

34 (a) is an explanatory view of a planar light intensity distribution on an exposed surface of a resist film when superposed and exposed using the photomasks of FIGS. 30 (a) and 30 (b), and FIG. FIG. 7A is an explanatory diagram of a light intensity distribution in a horizontal cross section, and FIG. 7C is an explanatory diagram of a light intensity distribution in a vertical cross section of FIG.

FIG. 35 (a) is an explanatory view of a planar light intensity distribution on an exposed surface of a resist film in a case where overlay exposure is performed using the photomasks of FIGS. 31 (a) and 31 (b); FIG. 7A is an explanatory diagram of a light intensity distribution in a horizontal cross section, and FIG. 7C is an explanatory diagram of a light intensity distribution in a vertical cross section of FIG.

FIG. 36 (a) shows a case where two photomasks used for the overlay exposure are a binary mask and a Levenson-type phase shift mask, and the pattern to be transferred using the same has an aspect ratio of 1: 1. , A plan view of one main part of the two photomasks, (b) is a plan view of the other main part where the phase shifters of the two photomasks are arranged, and (c) is (a) and (b) FIG. 4 is an explanatory diagram of an exposure region of a resist film when an exposure process is performed using the photomask of FIG.

FIG. 37 (a) shows a case where two photomasks used for overlay exposure are a binary mask and a Levenson-type phase shift mask, and the pattern to be transferred using the same has an aspect ratio of 1: 2. , A plan view of one main part of the two photomasks, (b) is a plan view of the other main part where the phase shifters of the two photomasks are arranged, and (c) is (a) and (b) FIG. 4 is an explanatory diagram of an exposure region of a resist film when an exposure process is performed using the photomask of FIG.

FIG. 38 (a) shows a case where two photomasks used for superposition exposure are a binary mask and a Levenson type phase shift mask, and the pattern to be transferred using the photomask has an aspect ratio of 1: 3. , A plan view of one main part of the two photomasks, (b) is a plan view of the other main part where the phase shifters of the two photomasks are arranged, and (c) is (a) and (b) FIG. 4 is an explanatory diagram of an exposure region of a resist film when an exposure process is performed using the photomask of FIG.

FIG. 39 (a) shows a case where the two photomasks used for the overlay exposure are a binary mask and a Levenson-type phase shift mask, and the pattern to be transferred using the same has an aspect ratio of 1: 4. , A plan view of one main part of the two photomasks, (b) is a plan view of the other main part where the phase shifters of the two photomasks are arranged, and (c) is (a) and (b) FIG. 4 is an explanatory diagram of an exposure region of a resist film when an exposure process is performed using the photomask of FIG.

40 (a) is an explanatory view of a planar light intensity distribution on an exposed surface of a resist film in a case where overlay exposure is performed using the photomasks of FIGS. 36 (a) and 36 (b), and FIG. FIG. 7A is an explanatory diagram of a light intensity distribution in a horizontal cross section, and FIG. 7C is an explanatory diagram of a light intensity distribution in a vertical cross section of FIG.

FIG. 41 (a) is an explanatory view of a planar light intensity distribution on an exposed surface of a resist film in a case where overlay exposure is performed using the photomasks of FIGS. 37 (a) and 37 (b); FIG. 7A is an explanatory diagram of a light intensity distribution in a horizontal cross section, and FIG. 7C is an explanatory diagram of a light intensity distribution in a vertical cross section of FIG.

FIG. 42 (a) is an explanatory view of a planar light intensity distribution on an exposed surface of a resist film in a case where overlay exposure is performed using the photomasks of FIGS. 38 (a) and 38 (b); FIG. 7A is an explanatory diagram of a light intensity distribution in a horizontal cross section, and FIG. 7C is an explanatory diagram of a light intensity distribution in a vertical cross section of FIG.

FIG. 43 (a) is an explanatory diagram of a planar light intensity distribution on an exposed surface of a resist film when superposed exposure is performed using the photomasks of FIGS. 39 (a) and 39 (b); FIG. 7A is an explanatory diagram of a light intensity distribution in a horizontal cross section, and FIG. 7C is an explanatory diagram of a light intensity distribution in a vertical cross section of FIG.

FIG. 44A shows a case where two photomasks used for overlay exposure are Levenson-type phase shift masks and the pattern to be transferred using the photomask has an aspect ratio of 1: 1; FIG. 2B is a plan view of one main part of one photomask, FIG. 2B is a plan view of the other main part where the phase shifters of the two photomasks are arranged, and FIG.
FIG. 4 is an explanatory diagram of an exposure region of a resist film when an exposure process is performed using the photomasks of FIGS.

FIG. 45 (a) shows a case where two photomasks used for superposition exposure are Levenson-type phase shift masks and the pattern to be transferred using the photomasks has an aspect ratio of 1: 2; FIG. 2B is a plan view of one main part of one photomask, FIG. 2B is a plan view of the other main part where the phase shifters of the two photomasks are arranged, and FIG.
FIG. 4 is an explanatory diagram of an exposure region of a resist film when an exposure process is performed using the photomasks of FIGS.

FIG. 46 (a) shows a case where two photomasks used for the overlay exposure are Levenson-type phase shift masks, and the pattern to be transferred using the photomasks has an aspect ratio of 1: 3; FIG. 2B is a plan view of one main part of one photomask, FIG. 2B is a plan view of the other main part where the phase shifters of the two photomasks are arranged, and FIG.
FIG. 4 is an explanatory diagram of an exposure region of a resist film when an exposure process is performed using the photomasks of FIGS.

FIG. 47A shows a case where two photomasks used for the overlay exposure are Levenson-type phase shift masks and the pattern to be transferred using the photomask has an aspect ratio of 1: 4, and FIG. FIG. 2B is a plan view of one main part of one photomask, FIG. 2B is a plan view of the other main part where the phase shifters of the two photomasks are arranged, and FIG.
FIG. 4 is an explanatory diagram of an exposure region of a resist film when an exposure process is performed using the photomasks of FIGS.

FIG. 48 (a) is an explanatory diagram of a planar light intensity distribution on an exposed surface of a resist film in the case where overlay exposure is performed using the photomasks of FIGS. 44 (a) and 44 (b); FIG. 7A is an explanatory diagram of a light intensity distribution in a horizontal cross section, and FIG. 7C is an explanatory diagram of a light intensity distribution in a vertical cross section of FIG.

FIG. 49 (a) is an explanatory diagram of a planar light intensity distribution on an exposed surface of a resist film in a case where overlay exposure is performed using the photomasks of FIGS. 45 (a) and 45 (b); FIG. 7A is an explanatory diagram of a light intensity distribution in a horizontal cross section, and FIG. 7C is an explanatory diagram of a light intensity distribution in a vertical cross section of FIG.

FIG. 50 (a) is an explanatory view of a planar light intensity distribution on an exposed surface of a resist film in a case where overlay exposure is performed using the photomasks of FIGS. 46 (a) and 46 (b); FIG. 7A is an explanatory diagram of a light intensity distribution in a horizontal cross section, and FIG. 7C is an explanatory diagram of a light intensity distribution in a vertical cross section of FIG.

FIG. 51 (a) is an explanatory diagram of a planar light intensity distribution on an exposed surface of a resist film in a case where overlay exposure is performed using the photomasks of FIGS. 47 (a) and 47 (b); FIG. 7A is an explanatory diagram of a light intensity distribution in a horizontal cross section, and FIG. 7C is an explanatory diagram of a light intensity distribution in a vertical cross section of FIG.

FIG. 52 is a flowchart of an overlay exposure step in the method for manufacturing a semiconductor device according to one embodiment of the present invention;

FIG. 53 is an explanatory diagram of a reduction projection exposure apparatus used in the method for manufacturing a semiconductor device according to one embodiment of the present invention;

FIG. 54 is an overall plan view of a semiconductor chip included in a semiconductor device manufactured by a semiconductor device manufacturing method according to an embodiment of the present invention;

FIG. 55 is an enlarged plan view of a main part of a memory cell array of the semiconductor device of FIG. 54;

FIG. 56 is an enlarged plan view of a principal part of the memory cell array of the semiconductor device of FIG. 54;

FIG. 57 is a sectional view taken along line AA of FIG. 56.

FIG. 58 is an essential part cross sectional view of the semiconductor device of FIGS. 54-56 during a manufacturing step;

59 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 58;

60 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 59;

FIG. 61A is a plan view of a main part of a photomask used in a method for manufacturing a semiconductor device according to another embodiment of the present invention;
(B) is a sectional view taken along the line AA in (a), and (c) is a sectional view taken along the line BB in (a).

FIG. 62A is a plan view of a main part of a photomask used in a method for manufacturing a semiconductor device according to another embodiment of the present invention;
(B) is a sectional view taken along the line AA in (a), and (c) is a sectional view taken along the line BB in (a).

63 is an explanatory diagram schematically showing an overlapping state of light transmission patterns in both photomasks when overlay exposure is performed using the photomasks of FIGS. 61 and 62. FIG.

FIG. 64 is an explanatory view schematically showing the reason why the roundness of the planar shape of the opening formed in the resist film is reduced.

FIG. 65A is a plan view of a main part of a photomask used in a method for manufacturing a semiconductor device according to another embodiment of the present invention;
(B) is sectional drawing of the AA line of (a).

FIG. 66A is a plan view of a main part of a photomask used in a method for manufacturing a semiconductor device according to another embodiment of the present invention;
(B) is sectional drawing of the AA line of (a).

FIG. 67 is an explanatory diagram schematically showing an overlapping state of light transmission patterns in both photomasks when overlay exposure is performed using the photomasks of FIGS. 65 and 66.

FIG. 68 is an explanatory view schematically showing a planar shape of a fine opening formed in the resist film by the exposure processing shown in FIGS. 66 and 67;

69 (a) is a plan view of a pattern transferred to a resist film by an exposure process using the photomask of FIGS. 66 and 67, (b) is a cross-sectional view taken along line AA of (a),
(C) is a cross-sectional view of a pattern formed by performing an etching process on a semiconductor substrate using a resist film left after the development process as an etching mask.

[Explanation of symbols]

 1A, 1C, 1I Photomask (first mask) 1B, 1D, 1J Photomask (second mask) 1E-1H Photomask 1K Photomask 1M Photomask 2a-2k, 2m Mask substrate 3a-3k, 3m Light transmission pattern 4a-4k, 4m Light-shielding pattern 4i1, 4j1 Light-shielding pattern 5 Phase shifter 6 Resist film 6P Exposure area 6P1-6P3 Exposure area 6N Unexposed area 7 Opening 7a Capacitor hole 8 Semiconductor substrate (semiconductor wafer) 8C Semiconductor chip 9 Insulation film 10 Hole pattern 11 Reduction projection exposure apparatus 11a Exposure light source 11b Fly eye lens 11c, 11d Condenser lens 11e Mirror 11f Projection lens 11g Sample stage 11h Mask stage 11i Mask position control means 11j Z stage 11k XY stage 11m Control system 11p, 11q Driving means 11r Mirror 11s Laser length measuring device 12 p-type well 13 n-type semiconductor region 14 element isolation part 15 gate insulating film 16 gate electrode 17 n-type semiconductor region 18 cap insulating film 19 insulating film 20a SOG film 20b 20j Insulating film 21a, 21b Contact hole 22 Plug 23a, 23b Through hole 24a Lower electrode 24 Conductive film 24b Upper electrode 24c Capacitive insulating film 25 Plug 26a Wiring 26b Wiring 27 Insulating film 28a Resist film P1, P2, P4, P5, P6 , P7 area N1 to N6 area MARY memory array SA sense amplifier WD word driver C information storage capacitor element Qs memory cell selection MISFET L active area WL word line BL bit line 50 mask substrate 51 light transmission pattern 2 light shielding pattern 53 resist film 53a exposed region 53b unexposed region 54 opening 55 a semiconductor substrate 56 insulation films 57 hole pattern

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuyuki Sumukai 6-chome, Shinmachi, Ome-shi, Tokyo 3 Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Jun Nanjo 5-chome, Josuihoncho, Kodaira-shi, Tokyo 22-1, Hitachi Ltd. Hitachi Systems Ltd. Systems (72) Inventor Nobuo Hasegawa 6-16 Shinmachi, Ome-shi, Tokyo 3 Device Development Center, Hitachi, Ltd. (72) Inventor Hiroyuki Uchiyama 5-2-1, Kamizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Group 5F046 AA13 AA20 AA25 BA04 BA08 5F083 AD24 AD48 AD49 BS00 ER22 JA06 JA36 JA39 JA40 JA53 KA20 LA29 MA03 MA06 MA17 MA20 PR01 PR23 PR29

Claims (5)

[Claims] 1. An exposure step of: (a) depositing a resist film on a semiconductor wafer; (b) an exposure step of superposing and exposing two masks on the resist film; and (c) after the exposure step, By performing development processing on the resist film,
A developing step of transferring a desired resist pattern to the resist film, wherein the exposing step comprises: (b1) disposing a plurality of first patterns extending in a first direction at a first distance from the resist film. Performing a first exposure process using the first mask thus formed; and (b2) forming a second pattern extending in a second direction intersecting the first direction on the resist film with a distance greater than the first distance. Performing a second exposure process using a second mask provided with a plurality of phase shifters on one of the second patterns adjacent to each other and spaced apart by a narrow second distance, and The pattern is a second resist portion corresponding to a region surrounded by the first pattern and the second pattern, wherein a first resist portion corresponding to the first pattern and the second pattern is left in the resist film. But A method for manufacturing a semiconductor device, wherein the pattern is a pattern obtained by removing. 2. A step of: (a) depositing a resist film on a semiconductor wafer; (b) an exposing step of superposing and exposing two masks on the resist film; and (c) after the exposing step, By performing development processing on the resist film,
A developing step of transferring a desired resist pattern to the resist film, wherein the exposing step comprises: (b1) disposing a plurality of first patterns extending in a first direction at a first distance from the resist film. Performing a first exposure process using the first mask thus formed; and (b2) forming a second pattern extending in a second direction intersecting the first direction on the resist film with a distance greater than the first distance. Performing a second exposure process using a second mask provided with a plurality of phase shifters on one of the second patterns adjacent to each other and spaced apart by a narrow second distance, and The pattern is a second resist portion corresponding to a region surrounded by the first pattern and the second pattern, wherein a first resist portion corresponding to the first pattern and the second pattern is left in the resist film. But A semiconductor which is a pattern obtained by removing, wherein in each of the first pattern of the first mask and the second pattern of the second mask, the width of an overlapping region is smaller than that of a non-overlapping region. Device manufacturing method. (A) depositing a resist film on a semiconductor wafer; (b) exposing two masks on the resist film; and (c) exposing the resist film after the exposing step. By performing development processing on the resist film,
A developing step of transferring a desired resist pattern to the resist film, wherein the exposing step comprises:
A plurality of third patterns arranged at predetermined intervals along a direction and a second direction intersecting the direction, and
Performing a first exposure process using a first mask provided with a phase shifter on one of the third patterns adjacent to each other;
(B2) a plurality of second patterns extending in the second direction are arranged on the resist film so as to be arranged between adjacent third patterns adjacent in the first direction; and
Performing a second exposure process using a second mask provided with a phase shifter on one of the second patterns adjacent to each other, wherein the desired resist pattern is the second pattern in the resist film. And a first resist portion corresponding to the third pattern is left, and a second resist portion corresponding to a region surrounded by the second pattern and the third pattern is removed. A method for manufacturing a semiconductor device. 4. An exposure step of: (a) depositing a resist film on a semiconductor wafer; (b) an exposure step of superposing and exposing two masks on the resist film; and (c) after the exposure step, By performing development processing on the resist film,
A developing step of transferring a desired resist pattern to the resist film; and (d) a step of forming a hole pattern in the semiconductor wafer using the desired resist pattern as an etching mask. ) The first resist film is
Performing a first exposure process using a first mask in which a plurality of first patterns extending in a direction are arranged at a first distance apart from each other;
(B2) performing a second exposure process on the resist film using a second mask in which a plurality of second patterns extending in a second direction intersecting the first direction are arranged at a second distance. And the desired resist pattern corresponds to the first pattern and the second pattern in the resist film, and
A resist portion exposed by the overexposure from the intersection of the first pattern and the second pattern is left, and a resist corresponding to a region other than the resist portion and surrounded by the first pattern and the second pattern is left. A method of manufacturing a semiconductor device, comprising: a pattern having a portion removed. 5. An exposure step of: (a) depositing a resist film on a semiconductor wafer; (b) an exposure step of superposing and exposing two masks on the resist film; and (c) after the exposure step, By performing development processing on the resist film,
A developing step of transferring a desired resist pattern to the resist film, wherein the exposing step comprises: (b1) disposing a plurality of first patterns extending in a first direction at a first distance from the resist film. Performing a first exposure process using the first mask thus formed; and (b2) forming a second pattern extending in a second direction intersecting the first direction on the resist film with a distance greater than the first distance. Performing a second exposure process using a second mask provided with a plurality of phase shifters on one of the second patterns adjacent to each other, the plurality of being disposed at a narrow second distance, and The pattern is a second resist portion corresponding to a region surrounded by the first pattern and the second pattern, wherein a first resist portion corresponding to the first pattern and the second pattern is left in the resist film. A method of forming a hole pattern in the semiconductor wafer by performing an etching process on the semiconductor wafer using the resist pattern as an etching mask. Method.