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WO2013127337A1 - 氧化物半导体薄膜晶体管及其制造方法与显示装置 - Google Patents

氧化物半导体薄膜晶体管及其制造方法与显示装置 Download PDF

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Publication number
WO2013127337A1
WO2013127337A1 PCT/CN2013/071939 CN2013071939W WO2013127337A1 WO 2013127337 A1 WO2013127337 A1 WO 2013127337A1 CN 2013071939 W CN2013071939 W CN 2013071939W WO 2013127337 A1 WO2013127337 A1 WO 2013127337A1
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Prior art keywords
layer
oxide semiconductor
transition
oxygen content
transition layer
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PCT/CN2013/071939
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English (en)
French (fr)
Inventor
谢振宇
徐少颖
阎长江
李田生
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北京京东方光电科技有限公司
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Priority to US13/983,868 priority Critical patent/US8987074B2/en
Publication of WO2013127337A1 publication Critical patent/WO2013127337A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Oxide semiconductor thin film transistor method of manufacturing the same, and display device
  • the present invention relates to the field of semiconductor technology, and in particular to an oxide semiconductor thin film transistor and a method of fabricating the same, and a display device using the oxide semiconductor thin film transistor. Background technique
  • TFT thin film transistor
  • a typical transparent metal oxide material for forming an oxide semiconductor layer is indium gallium oxide (IGZO). Since such a thin film transistor manufactured by IGZO (hereinafter referred to as IGZO thin film transistor) has good bending properties and electrical properties, and has a low process temperature at the time of fabrication, it is suitable for use in fabricating a flexible substrate.
  • IGZO thin film transistor since such a thin film transistor manufactured by IGZO (hereinafter referred to as IGZO thin film transistor) has good bending properties and electrical properties, and has a low process temperature at the time of fabrication, it is suitable for use in fabricating a flexible substrate.
  • TFT substrates prepared by IGZO are less stable in air and more sensitive to oxygen and water vapor. The main reason is that oxygen and water vapor can pass through the protective layer on the IGZO, which deteriorates the performance of the amorphous indium gallium oxide IGZO. Therefore, it is necessary to prepare a high-quality protective film on IGZO
  • the conventional IGZO thin film transistor substrate has an etch barrier structure, that is, an etch barrier layer made of SiNx or SiOx is formed on the IGZO layer, thereby protecting the IGZO layer from being damaged during the preparation of the source and drain electrodes, thereby improving the TFT.
  • the stability of the substrate is not limited to, but not limited
  • the IGZO thin film transistor includes: a gate metal layer 11 formed on a substrate, a gate insulating layer 12 formed on the gate metal layer 11, and an oxide semiconductor layer 13 formed on the gate insulating layer 12 formed on the IGZO semiconductor layer 13. a barrier layer 14 (made of, for example, SiOx); a source/drain metal layer 15 formed on the barrier layer 14, the IGZO semiconductor layer 13, and the gate insulating layer 12; formed on the source/drain metal layer 15, the gate insulating layer 12 And a passivation layer 16 on the portion of the barrier layer 14, and a pixel electrode layer 17 formed on the passivation layer 16.
  • the pixel electrode 17 is required to be fabricated only when a display device such as an array substrate is fabricated, and does not itself belong to a part of the IGZO thin film transistor.
  • embodiments of the present invention provide an oxidation which can improve the stability of an oxide semiconductor thin film transistor device and improve the interface characteristics between the oxide semiconductor layer and the gate insulating layer and the barrier layer.
  • an oxide semiconductor thin film transistor including a gate insulating layer, an oxide semiconductor layer, and a barrier layer, wherein the gate insulating layer and the oxide semiconductor layer are provided A first transition layer is formed therebetween, and the oxygen content of the first transition layer is higher than the oxygen content of the oxide semiconductor layer.
  • a method of fabricating an oxide semiconductor thin film transistor including:
  • a passivation layer is formed on the source/drain metal layer, the gate insulating layer, and a portion of the barrier layer. According to still another aspect of the present invention, a display device including the above-described oxide semiconductor thin film transistor is provided.
  • 1 is a schematic view showing the structure of an oxide semiconductor thin film transistor in the prior art
  • 2 is a cross-sectional view showing the structure of an oxide semiconductor thin film transistor according to a first embodiment of the present invention
  • Figure 3 is a cross-sectional view showing the structure of an oxide semiconductor thin film transistor according to a second embodiment of the present invention.
  • Fig. 4 is a cross-sectional view showing the structure of an oxide semiconductor thin film transistor according to a third embodiment of the present invention. detailed description
  • oxygen content refers to the percentage of the number of oxygen atoms in the metal oxide layer to the total number of atoms
  • amount of oxygen refers to the preparation (for example, by sputtering) of a metal oxide layer.
  • the mass of oxygen introduced at the time, "% by mass of oxygen as a total gas” refers to the mass of oxygen as a percentage of the mass of the total sputtering gas when the metal oxide layer is deposited.
  • Embodiments of the present invention provide a method for improving the stability of an IGZO thin film transistor device and improving the interface characteristics of the oxide semiconductor layer and SiOx, thereby obtaining a better lattice matching oxygen.
  • the bottom gate type thin film transistor will be described below as an example, but it is understood that the present invention is equally applicable to a top gate type thin film transistor.
  • Fig. 2 shows a cross-sectional structure of an oxide semiconductor thin film transistor according to a first embodiment of the present invention.
  • the thin film transistor includes: a gate metal layer 21 formed on a substrate; a gate insulating layer 22 formed on the gate metal layer 21; a transition layer 23 formed on the gate insulating layer 22; an oxide semiconductor formed on the transition layer 23.
  • the pixel electrode layer 28 formed on the passivation layer 27 is required to be formed only when a display device such as an array substrate is fabricated, and does not itself belong to a part of the IGZO thin film transistor.
  • the transition layer 23 is disposed between the gate insulating layer 22 and the oxide semiconductor layer 24, and the oxygen content of the transition layer 23 is higher than that of the oxide semiconductor layer 24.
  • the transition layer 23 and the oxide semiconductor layer 24 are made of the same metal oxide (e.g., a metal oxide containing indium, gallium, and rhodium), but the oxygen content of the two is different.
  • IGZO indium gallium oxide
  • the metal oxide is not limited to IGZO.
  • the characteristics of IGZO are susceptible to the film preparation process, especially in relation to the amount of oxygen in the atmosphere at the time of preparation.
  • the amount of oxygen in the preparation is relatively low, the oxygen content of the formed IGZO film is relatively low, and the IGZO film exhibits electrical conductivity; when the amount of oxygen in the preparation is relatively high, the oxygen content of the formed IGZO film is relatively high, The IGZO film exhibits insulating properties. Therefore, when the transition layer 23 having a relatively high oxygen content is disposed between the IGZO semiconductor layer 24 and the SiOx gate insulating layer 22, since the transition layer 23 is insulated, the IGZO semiconductor layer 24 and the SiOx gate insulating layer 22 are enhanced. The interface characteristics improve stability and make the lattice match better.
  • the oxide semiconductor layer 24 and the transition layer 23 can be deposited by, for example, RF magnetron sputtering, and the sputtering gas during deposition contains oxygen (0 2 ) and a shielding gas (for example, nitrogen, argon). Wait) .
  • the control of the oxygen content in the deposited metal oxide can be achieved by adjusting the proportion of oxygen in the sputtering gas during deposition.
  • the concentration of 0 2 i.e., the oxygen percentage of the total gas
  • the concentration of 0 2 may be in the range of 30% to 100%.
  • an oxide semiconductor layer is deposited on the transition layer 23 24, to adjust the concentration of the sputter gas 02, so that this time the concentration of 02 is less than the concentration of the transition layer 23 is deposited, e.g., in the range of 10% to 30%.
  • the oxygen content of the first transition layer is 35% to 40%, and the oxygen content of the oxide semiconductor layer is 25 to 35%.
  • the above structural design of the present invention improves the interface characteristics of the oxide semiconductor layer IGZO and the gate insulating layer SiOx because of defects and a certain proportion of H ions in the gate insulating film, and H ions and oxygen in the metal oxide
  • the combination affects the distribution and content of oxygen in the metal oxide semiconductor and ultimately affects the stability of the oxide semiconductor.
  • the role of the transition layer is to avoid the combination of H ions and oxygen, thereby maintaining the oxygen content in the metal oxide at a certain level, which not only maintains the stability of the metal oxide characteristics, but also makes the lattice matching better. .
  • Fig. 3 shows a cross-sectional structure of an oxide semiconductor thin film transistor according to a second embodiment of the present invention.
  • the thin film transistor includes: a gate metal layer 21 formed on a substrate; a gate insulating layer 22 formed on the gate metal layer 21; a transition layer 23 formed on the gate insulating layer 22; and a transition layer 31 formed on the transition layer 23.
  • the oxygen amount is lower than the oxygen content of the transition layer 23; and the barrier layer 25 formed on the oxide semiconductor layer 24; the source/drain metal layer 26 formed on the barrier layer 25, the oxide semiconductor layer 24, and the gate insulating layer 22.
  • the thin film transistor may further include a pixel electrode layer 28 formed on the passivation layer 27.
  • the transition layer 31 is further included in the embodiment, and the material of the transition layer 31 is the same as that of the transition layer 23 and the oxide semiconductor layer 24 in the first embodiment, but the oxygen content thereof is The oxygen content higher than that of the oxide semiconductor layer 24 is lower than the oxygen content of the transition layer 23, thereby further improving the interface characteristics of the oxide semiconductor layer IGZO and the gate insulating layer SiOx, improving the stability and matching the lattice. It is better and makes the electrical properties of the TFT significantly improved.
  • Fig. 4 shows a cross-sectional structure of an oxide semiconductor thin film transistor according to a third embodiment of the present invention.
  • the oxide semiconductor thin film transistor of the present embodiment further includes: a transition layer 41 and a transition layer 42 formed between the barrier layer 25 and the oxide semiconductor layer 24, wherein the transition layer 41 The oxygen content is higher than the oxygen content of the oxide semiconductor layer 24; the oxygen content of the transition layer 42 is higher than the oxygen content of the oxide semiconductor layer 24 and lower than the oxygen content of the transition layer 41.
  • the oxide semiconductor layer 24, the transition layer 23, the transition layer 31, the transition layer 41, and the transition layer 42 are each made of a metal oxide containing indium, gallium, or the like, such as IGZO.
  • Gate insulating layer 22 and barrier layer 25 are all made of SiOx.
  • the oxygen content of the transition layer 41 and the transition layer 42 may preferably be the same as the oxygen content of the transition layer 23 and the transition layer 31, respectively, to reduce the number of times of preparation conditions.
  • the oxygen content of these four layers may also differ from each other.
  • the length of the transition layer 41 and the transition layer 42 in the channel direction is smaller than the length of the oxide semiconductor layer 24 (X direction in FIG. 4), so that the source/drain electrodes and the oxide semiconductor layer 24 of the thin film transistor can be made. Achieve better electrical contact.
  • the transition layer 41 and the transition layer 42 can also be deposited by, for example, radio frequency magnetron sputtering, and the sputtering gas during deposition contains 02 and a shielding gas (e.g., nitrogen, argon, etc.).
  • the concentration of 0 2 may be in the range of 10% to 30%; when the transition layer 41 is deposited, the concentration of 0 2 in the sputtering gas is adjusted, so that The concentration is higher than the concentration when the oxide semiconductor layer 24 is deposited, for example, in the range of 30% to 100%; and when the transition layer 42 is deposited, the concentration of 02 in the sputtering gas is further adjusted to make the concentration of the transition layer 42.
  • the above-mentioned structural design of the present invention is improved not only by improving the interface characteristics between the oxide semiconductor layer IGZO and the gate insulating layer SiOx but also improving the interface characteristics between the oxide semiconductor layer IGZO and the barrier layer SiOx. , thereby improving the stability of the thin film transistor. It can be understood that the above object can also be achieved in the case where the above thin film transistor does not include the transition layer 42.
  • a method of fabricating the oxide semiconductor thin film transistor of the first embodiment described above comprising:
  • An oxide semiconductor layer 24 is formed on the transition layer 23, and the oxygen content of the transition layer 23 is higher than that of the oxide semiconductor layer 24;
  • a source/drain metal layer 26 is formed on the barrier layer 25, the oxide semiconductor layer 24, and the gate insulating layer 22;
  • a passivation layer 27 is formed on the source/drain metal layer 26, the gate insulating layer 22, and the partial barrier layer 25.
  • the oxygen content of the transition layer 23 can be adjusted by adjusting the oxygen that is introduced during deposition to the total gas.
  • the percentage of mass is controlled. That is, the amount of oxygen which controls the transition layer 23 at the time of deposition is larger than the amount of oxygen of the oxide semiconductor layer 24 at the time of deposition.
  • the mass percentage of oxygen to the total gas may be in the range of 30% to 100%.
  • the oxide semiconductor layer 24 is deposited on the transition layer 23, it may be, for example, in the range of 10% to 30%, and lower than the mass percentage of oxygen of the total sputtering gas when the transition layer 23 is formed.
  • the method may further include forming a transition layer 31 between the transition layer 23 and the oxide semiconductor layer 24, the oxygen content of the transition layer 31 being higher than that of the oxide semiconductor layer 24 and lower than that of the transition layer 23 Oxygen content.
  • the oxygen percentage of the total gas is greater than the mass percentage of the oxide semiconductor layer 24 when deposited and less than the mass percentage of the transition layer 23 at the time of deposition.
  • the method may further include forming a transition layer 41 between the barrier layer 25 and the oxide semiconductor layer 24, the transition layer 41 having an oxygen content higher than that of the oxide semiconductor layer 24.
  • the method may further include a transition layer 42 formed between the transition layer 41 and the oxide semiconductor layer 24, the transition layer 42 having a higher oxygen content than the oxide semiconductor layer 24 and lower than the transition layer 41. Oxygen content.
  • a display device comprising the oxide semiconductor thin film transistor of any of the above embodiments.
  • An example of the display device is a liquid crystal display device in which an array substrate and a counter substrate are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, a color film substrate.
  • the pixel electrode of each pixel unit of the array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display device further includes a backlight that provides backlighting for the array substrate.
  • OLED organic electroluminescence display device
  • an organic light emitting material stack is formed on the array substrate, and a pixel electrode of each pixel unit is used as an anode or a cathode for driving the organic light emitting material to emit light. Perform the display operation.
  • Still another example of the display device is an electronic paper display device in which an electronic ink layer is formed on an array substrate, and a pixel electrode of each pixel unit serves as a voltage for applying a charged microparticle moving in the driving electronic ink to perform a display operation .
  • the interface characteristics between the two are improved, and the oxide semiconductor layer is More than one transition layer is disposed between the barrier layers, which improves the interface characteristics of the barrier layer SiOx and the oxide semiconductor IGZO thin film layer, so that the lattice matching is better, thereby improving the electrical characteristics and stability of the TFT. Since the electrical characteristics of the TFT directly affect the quality of the display screen, the quality of the display screen is also improved.
  • the oxide semiconductor thin film transistor is used for a display device such as an array substrate, the screen frequency of the display device is improved, and the quality of the image is not affected.
  • the thin film transistor of the present invention can also be used in other fields than the display field, such as in the field of integrated circuit manufacturing.

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Abstract

一种氧化物半导体薄膜晶体管及其制备方法与显示装置。氧化物半导体薄膜晶体管包括栅绝缘层（22）、氧化物半导体层（24）和阻挡层（25），其中在所述栅绝缘层（22）和所述氧化物半导体层（24）之间形成有第一过渡层（23），所述第一过渡层（23）的含氧量高于所述氧化物半导体层（24）的含氧量。上述氧化物半导体薄膜晶体管提高了氧化物半导体层（24）和阻挡层（25）之间的晶格匹配及界面特性，使得薄膜晶体管具有较好的稳定性。

Description

氧化物半导体薄膜晶体管及其制造方法与显示装置 技术领域
本发明涉及半导体技术领域， 尤其涉及一种氧化物半导体薄膜晶体管及 其制造方法， 和釆用该氧化物半导体薄膜晶体管的显示装置。 背景技术
作为薄膜晶体管 （TFT ) 的代表， 氧化物半导体薄膜晶体管被视为新一 代显示器用薄膜晶体管 （TFT ) 。
在 TFT驱动基板中，用于制作氧化物半导体层的典型的透明金属氧化物 材料为铟镓辞氧化物（IGZO )。 由于这种由 IGZO制造的薄膜晶体管（下文 简称为 IGZO薄膜晶体管）具有较好的弯曲性能和电学性能， 并且在制作时 工艺温度低， 因此适于用来制作柔性基板。 但是， IGZO制备的 TFT基板在 空气中稳定性较差， 对氧气和水蒸气比较敏感。 主要是因为氧气和水蒸气可 以透过 IGZO上面的保护层， 使非晶的铟镓辞氧化物 IGZO性能恶化。 因此， 需要在 IGZO上制备高质量的保护膜， 以提高 TFT基板的稳定性。
传统 IGZO薄膜晶体管基板具有刻蚀阻挡型结构， 即在 IGZO层上制作 一层由 SiNx或者 SiOx构成的刻蚀阻挡层， 由此可以在制备源漏电极时保护 IGZO层不被破坏， 从而提高 TFT基板的稳定性。
例如，如图 1所示，示出了现有技术的 IGZO薄膜晶体管的结构。该 IGZO 薄膜晶体管包括： 形成在基板上的栅金属层 11 , 在栅金属层 11上形成的栅 绝缘层 12; 形成在栅绝缘层 12上的氧化物半导体层 13 , 形成在 IGZO半导 体层 13上的阻挡层 14(该阻挡层例如由 SiOx制成）；形成在阻挡层 14、IGZO 半导体层 13、 栅绝缘层 12上的源漏金属层 15; 形成在源漏金属层 15、 栅绝 缘层 12及部分阻挡层 14上的钝化层 16, 以及形成在钝化层 16上的像素电 极层 17。 这里， 像素电极 17只有在制作阵列基板等显示器件时才需要制作， 本身并不属于 IGZO薄膜晶体管的一部分。
上述 IGZO薄膜晶体管所存在的问题是， IGZO半导体层与栅绝缘层以 及阻挡层之间的界面特性和晶格匹配较差， 因此 IGZO薄膜晶体管的稳定性 仍比较差。 发明内容
针对上述现有技术存在的问题， 本发明的实施例提供了一种可以提高氧 化物半导体薄膜晶体管器件的稳定性， 并且改善氧化物半导体层与栅绝缘层 以及阻挡层之间的界面特性的氧化物半导体薄膜晶体管及其制造方法和显示 装置。
根据本发明的一个方面， 提供一种氧化物半导体薄膜晶体管， 该氧化物 半导体薄膜晶体管包括栅绝缘层、 氧化物半导体层和阻挡层， 其中在所述栅 绝缘层和所述氧化物半导体层之间形成有第一过渡层， 所述第一过渡层的含 氧量高于所述氧化物半导体层的含氧量。
根据本发明的另一方面，提供一种氧化物半导体薄膜晶体管的制造方法， 包括：
在基板上形成栅金属层；
在所述栅金属层上形成栅绝缘层；
在所述栅绝缘层上形成第一过渡层；
在所述第一过渡层上形成氧化物半导体层， 所述第一过渡层的含氧量高 于所述氧化物半导体层的含氧量；
在所述氧化物半导体层上形成阻挡层；
在所述阻挡层、所述氧化物半导体层、所述栅绝缘层上形成源漏金属层； 以及
在所述源漏金属层、 所述栅绝缘层及部分所述阻挡层上形成钝化层。 根据本发明的又一方面， 提供一种显示装置， 包括上述的氧化物半导体 薄膜晶体管。
附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。 其中：
图 1为示出现有技术中氧化物半导体薄膜晶体管的结构的示意图； 图 2为示出根据本发明第一实施例的氧化物半导体薄膜晶体管的结构的 剖面图；
图 3为示出根据本发明第二实施例的氧化物半导体薄膜晶体管的结构的 剖面图；
图 4为示出根据本发明第三实施例的氧化物半导体薄膜晶体管的结构的 剖面图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性，而只是用来区分不同的组成部分。同样， "一个 "或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包 含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵 盖出现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排 除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语并非限定于物理 的或者机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被描述对 象的绝对位置改变后， 则该相对位置关系也可能相应地改变。
在本发明中， 术语 "含氧量" 指的是金属氧化物层中氧原子数量占总原 子数量的百分比， "氧气量" 指的是在制备（例如通过溅射法沉积）金属氧 化物层时所通入的氧气的质量， "氧气占总气体的质量百分比" 指的是在沉 积金属氧化物层时， 氧气的质量占总溅射气体的质量的百分比。
本发明的实施例提供了一种可以提高 IGZO薄膜晶体管器件的稳定性， 并且改善氧化物半导体层与 SiOx的界面特性， 从而得到晶格匹配更好的氧 化物半导体薄膜晶体管及其制造方法与显示装置。 以下以底栅型薄膜晶体管 为例进行描述， 但可以理解， 本发明同样适用于顶栅型薄膜晶体管。
图 2示出了根据本发明第一实施例的氧化物半导体薄膜晶体管的剖面结 构。 该薄膜晶体管包括： 形成于基板上的栅金属层 21; 形成在栅金属层 21 上的栅绝缘层 22;形成在栅绝缘层 22上的过渡层 23; 形成在过渡层 23上的 氧化物半导体层 24,其中过渡层 23的含氧量高于氧化物半导体层 24的含氧 量； 以及形成在氧化物半导体层 24上的阻挡层 25; 形成在阻挡层 25、 氧化 物半导体层 24、 栅绝缘层 22上的源漏金属层 26; 形成在源漏金属层 26、 栅 绝缘层 22及部分阻挡层 25上的钝化层 27。 形成在钝化层 27上的像素电极 层 28只有在制作阵列基板等显示器件时才需要制作，本身并不属于 IGZO薄 膜晶体管的一部分。
在该第一实施例中，过渡层 23设置于栅绝缘层 22与氧化物半导体层 24 之间， 且过渡层 23的含氧量高于氧化物半导体层 24的含氧量。 在一个示例 中， 过渡层 23与氧化物半导体层 24由相同的金属氧化物（例如含有铟、 镓 以及辞的金属氧化物）制成， 但是二者的含氧量不同。 下面以铟镓辞氧化物 (IGZO)为例进行描述， 但可以理解的是， 金属氧化物并不限于 IGZO。
作为一种氧化物半导体材料， IGZO 的特性容易受到薄膜制备工艺的影 响， 尤其是与制备时气氛中的氧气量相关。 当制备时氧气量比较低时， 所形 成的 IGZO薄膜的含氧量比较低， 则 IGZO薄膜呈现导电特性； 当制备时氧 气量比较高时， 所形成的 IGZO薄膜的含氧量比较高， 则 IGZO薄膜呈现绝 缘特性。 因此， 当在 IGZO半导体层 24与 SiOx栅绝缘层 22之间设置含氧量 较高的过渡层 23时， 由于过渡层 23为绝缘的， 增强了 IGZO半导体层 24 与 SiOx栅绝缘层 22之间的界面特性， 提高了稳定性以及使得晶格的匹配性 更好。
更具体地， 本实施例中， 氧化物半导体层 24和过渡层 23可通过例如射 频磁控溅射法沉积， 沉积时的溅射气体包含氧气（02 )及保护气体（例如氮 气、 氩气等） 。 通过调节沉积时氧气在溅射气体中的比例， 能实现对沉积后 的金属氧化物中的含氧量的控制。 例如， 在制备薄膜晶体管的过程中， 当在 栅绝缘层 22上沉积过渡层 23时， 02的浓度（即氧气占总气体的质量百分比） 可以在 30%~100%的范围内。 接下来， 在过渡层 23上沉积氧化物半导体层 24时， 调节溅射气体中 02的浓度， 使此时 02的浓度低于沉积过渡层 23时 的浓度， 例如， 在 10%~30%的范围内。 最终测得第一过渡层的含氧量为 35%~40%, 氧化物半导体层的含氧量为 25~35%。
釆用本发明的上述结构设计， 改善了氧化物半导体层 IGZO与栅绝缘层 SiOx 的界面特性， 因为栅绝缘层薄膜中存在缺陷和一定比例的 H 离子， H 离子会与金属氧化物中的氧结合， 由此影响金属氧化物半导体中的氧的分布 和含量， 并最终影响到氧化物半导体的稳定性。 而过渡层的作用是避免 H离 子与氧的结合， 从而将金属氧化物中的氧含量维持在一定的水平， 这样不仅 能保持金属氧化物特性的稳定性， 也使得晶格的匹配性更好。
图 3示出了根据本发明第二实施例的氧化物半导体薄膜晶体管的剖面结 构。 该薄膜晶体管包括： 形成于基板上的栅金属层 21 ; 形成在栅金属层 21 上的栅绝缘层 22;形成在栅绝缘层 22上的过渡层 23; 形成在过渡层 23上的 过渡层 31 ;形成在过渡层 31上的氧化物半导体层 24,其中过渡层 23的含氧 量高于氧化物半导体层 24的含氧量， 过渡层 31的含氧量高于氧化物半导体 层 24的含氧量并低于过渡层 23 的含氧量； 以及形成在氧化物半导体层 24 上的阻挡层 25; 形成在阻挡层 25、 氧化物半导体层 24、 栅绝缘层 22上的源 漏金属层 26; 形成在源漏金属层 26、栅绝缘层 22及部分阻挡层 25上的钝化 层 27。可选地，该薄膜晶体管还可包括形成在钝化层 27上的像素电极层 28。
与第一实施例相比，在本实施例中进一步包括了过渡层 31 ,该过渡层 31 的材料与第一实施例中过渡层 23、 氧化物半导体层 24的材料相同， 但其含 氧量高于氧化物半导体层 24的含氧量并低于过渡层 23的含氧量， 从而进一 步改善了氧化物半导体层 IGZO与栅绝缘层 SiOx的界面特性，提高了稳定性 以及使得晶格的匹配性更好， 并使 TFT的电学特性有显著的提高。
图 4示出了根据本发明第三实施例的氧化物半导体薄膜晶体管的剖面结 构。 与第二实施例的薄膜晶体管相比， 本实施例的氧化物半导体薄膜晶体管 还包括： 形成在阻挡层 25与氧化物半导体层 24之间的过渡层 41和过渡层 42, 其中过渡层 41 的含氧量高于氧化物半导体层 24的含氧量； 过渡层 42 的含氧量高于氧化物半导体层 24的含氧量并低于过渡层 41的含氧量。 本实 施例中， 氧化物半导体层 24、 过渡层 23、 过渡层 31、 过渡层 41和过渡层 42 均由包含铟、 镓、 辞的金属氧化物制成， 例如 IGZO。 栅绝缘层 22和阻挡层 25均由 SiOx制成。
在本实施例中， 过渡层 41和过渡层 42的含氧量优选地可分别与过渡层 23和过渡层 31的含氧量相同， 以减少对制备条件的设定次数。 然而， 这四 层的含氧量也可彼此不同。
优选地， 过渡层 41和过渡层 42在沿沟道方向的长度均小于氧化物半导 体层 24的长度（图 4中的 X方向）， 这样可以使薄膜晶体管的源漏电极与氧 化物半导体层 24实现更好的电接触。
过渡层 41和过渡层 42可同样通过例如射频磁控溅射法沉积， 沉积时的 溅射气体含有 02及保护气体（例如氮气、 氩气等）。 在制备薄膜晶体管的过 程中， 当沉积氧化物半导体层 24时， 02的浓度可以在 10%~30%的范围内； 当沉积过渡层 41时， 调节溅射气体中 02的浓度， 使其浓度高于沉积氧化物 半导体层 24时的浓度，例如在 30%~100%的范围内；且当沉积过渡层 42时， 进一步调节溅射气体中 02的浓度， 使过渡层 42的浓度高于沉积氧化物半导 釆用本发明的上述结构设计， 不仅改善了氧化物半导体层 IGZO与栅绝 缘层 SiOx间的界面特性， 还改善了氧化物半导体层 IGZO与阻挡层 SiOx间 的界面特性， 从而提高了薄膜晶体管的稳定性。 可以理解， 在上述薄膜晶体 管不包含过渡层 42的情况下， 同样可以实现上述目的。
根据本发明的第四实施例， 还提供一种制造上述第一实施例的氧化物半 导体薄膜晶体管的方法， 该方法包括：
在基板上形成栅金属层 21 ;
在栅金属层 21上形成栅绝缘层 22;
在栅绝缘层 22上形成过渡层 23;
在过渡层 23上形成氧化物半导体层 24,过渡层 23的含氧量高于氧化物 半导体层 24的含氧量；
在氧化物半导体层 24上形成阻挡层 25;
在阻挡层 25、 氧化物半导体层 24、 栅绝缘层 22上形成源漏金属层 26; 和
在源漏金属层 26、 栅绝缘层 22及部分阻挡层 25上形成钝化层 27。 如前所述，过渡层 23的含氧量可以通过调节沉积时通入的氧气占总气体 的质量百分比来控制。也就是，控制过渡层 23在沉积时的氧气量大于氧化物 半导体层 24在沉积时的氧气量。 在一个示例中， 当在栅绝缘层 22上沉积过 渡层 23时，氧气占总气体的质量百分比可在 30%~100%的范围内。在过渡层 23上沉积氧化物半导体层 24时， 可以例如在 10%~30%的范围内， 且低于形 成过渡层 23时的氧气占总溅射气体的质量百分比。
进一步地， 该方法还可包括在过渡层 23与氧化物半导体层 24之间形成 过渡层 31 ,过渡层 31的含氧量高于氧化物半导体层 24的含氧量并低于过渡 层 23的含氧量。 在一个示例中， 在沉积过渡层 31时， 氧气占总气体的质量 百分比大于氧化物半导体层 24沉积时的质量百分比且小于过渡层 23在沉积 时的质量百分比。
在另一个实施例中， 该方法还可包括在阻挡层 25与氧化物半导体层 24 之间形成过渡层 41 ,该过渡层 41的含氧量高于氧化物半导体层 24的含氧量。
进一步地， 该方法还可包括在过渡层 41与氧化物半导体层 24之间形成 的过渡层 42,过渡层 42含氧量高于氧化物半导体层 24的含氧量并低于过渡 层 41的含氧量。
根据本发明的第五实施例， 还提供一种显示装置， 包括上述任一实施例 的氧化物半导体薄膜晶体管。
该显示装置的一个示例为液晶显示装置， 其中， 阵列基板与对置基板彼 此对置以形成液晶盒， 在液晶盒中填充有液晶材料。 该对置基板例如为彩膜 基板。 阵列基板的每个像素单元的像素电极用于施加电场对液晶材料的旋转 的程度进行控制从而进行显示操作。 在一些示例中， 该液晶显示装置还包括 为阵列基板提供背光的背光源。
该显示装置的另一个示例为有机电致发光显示装置 （OLED ) , 其中， 阵列基板上形成有有机发光材料叠层， 每个像素单元的像素电极作为阳极或 阴极用于驱动有机发光材料发光以进行显示操作。
该显示装置的再一个示例为电子纸显示装置， 其中， 阵列基板上形成有 电子墨水层， 每个像素单元的像素电极作为用于施加驱动电子墨水中的带电 微颗粒移动以进行显示操作的电压。
综上所述， 在本发明中， 通过在氧化物半导体层与栅绝缘层之间设置一 层以上的过渡层， 改善了二者间的界面特性， 以及通过在氧化物半导体层与 阻挡层之间设置一层以上的过渡层， 改善了阻挡层 SiOx 与氧化物半导体 IGZO薄膜层的界面特性， 使得晶格的匹配性更好， 从而提高了 TFT的电学 特性和稳定性。 由于 TFT的电学特性直接影响了显示画面的品质， 因此也就 提高了显示画面的品质。 另外， 当将上述氧化物半导体薄膜晶体管用于制作 阵列基板等显示器件时， 提高了显示器件的刷屏频率， 并且保证了图像的质 量不受影响。 当然， 本发明的薄膜晶体管， 还可用于除显示领域之外的其他 领域， 如应用于集成电路制造领域等。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种氧化物半导体薄膜晶体管， 包括栅绝缘层、 氧化物半导体层和阻 挡层， 其中在所述栅绝缘层和所述氧化物半导体层之间形成有第一过渡层， 所述第一过渡层的含氧量高于所述氧化物半导体层的含氧量。
2、 如权利要求 1所述的氧化物半导体薄膜晶体管， 还包括：
形成于基板上的栅金属层， 所述栅绝缘层、 第一过渡层、 氧化物半导体 层和阻挡层依次形成在该栅金属层上；
形成在所述阻挡层、 所述氧化物半导体层、 所述栅绝缘层上的源漏金属 层； 和
形成在所述源漏金属层、 所述栅绝缘层及部分所述阻挡层上的钝化层。
3、如权利要求 1所述的氧化物半导体薄膜晶体管，还包括： 形成在所述 阻挡层与所述氧化物半导体层之间的第二过渡层， 所述第二过渡层的含氧量 高于所述氧化物半导体层的含氧量。
4、如权利要求 1所述的氧化物半导体薄膜晶体管，还包括： 形成在所述 第一过渡层与所述氧化物半导体层之间的第三过渡层， 所述第三过渡层的含 氧量高于所述氧化物半导体层的含氧量并低于所述第一过渡层的含氧量。
5、如权利要求 3所述的氧化物半导体薄膜晶体管，还包括： 形成在所述 第二过渡层与所述氧化物半导体层之间的第四过渡层， 所述第四过渡层含氧 量高于所述氧化物半导体层的含氧量并低于所述第二过渡层的含氧量。
6、 如权利要求 4 所述的氧化物半导体薄膜晶体管， 其中所述氧化物半 导体层、 所述第一过渡层和所述第三过渡层由相同的金属氧化物材料制成， 而各层的含氧量不同。
7、 如权利要求 5 所述的氧化物半导体薄膜晶体管， 其中所述氧化物半 导体层、所述第二过渡层和所述第四过渡层均由相同的金属氧化物材料制成， 而各层的含氧量不同。
8、 如权利要求 1 所述的氧化物半导体薄膜晶体管， 其中所述氧化物半 导体层由包含铟、 镓、 辞的金属氧化物制成。
9、 如权利要求 1 所述的氧化物半导体薄膜晶体管， 其中所述第一过渡 层的含氧量为 35%~40%, 氧化物半导体层的含氧量为 25%~35%。
10、 如权利要求 5所述的氧化物半导体薄膜晶体管， 其中所述第二过渡 层和所述第四过渡层的沿沟道方向的长度均小于所述氧化物半导体层的长 度。
11、 一种用于制造氧化物半导体薄膜晶体管的方法， 包括：
在基板上形成栅金属层；
在所述栅金属层上形成栅绝缘层；
在所述栅绝缘层上形成第一过渡层；
在所述第一过渡层上形成氧化物半导体层， 所述第一过渡层的含氧量高 于所述氧化物半导体层的含氧量；
在所述氧化物半导体层上形成阻挡层；
在所述阻挡层、所述氧化物半导体层、所述栅绝缘层上形成源漏金属层； 以及
在所述源漏金属层、 所述栅绝缘层及部分所述阻挡层上形成钝化层。
12、如权利要求 11所述的方法，还包括： 在所述阻挡层与所述氧化物半 导体层之间形成第二过渡层， 所述第二过渡层的含氧量高于所述氧化物半导 体层的含氧量。
13、如权利要求 11所述的方法，还包括： 在所述第一过渡层与所述氧化 物半导体层之间形成第三过渡层， 所述第三过渡层的含氧量高于所述氧化物 半导体层的含氧量并低于所述第一过渡层的含氧量。
14、如权利要求 12所述的方法，还包括： 在所述第二过渡层与所述氧化 物半导体层之间形成的第四过渡层， 所述第四过渡层含氧量高于所述氧化物 半导体层的含氧量并低于所述第二过渡层的含氧量。
15、如权利要求 13所述的方法， 其中所述氧化物半导体层、所述第一过 渡层和所述第三过渡层均由相同的金属氧化物材料制成， 而各层的含氧量不 同。
16、如权利要求 14所述的方法， 其中所述氧化物半导体层、所述第二过 渡层和所述第四过渡层均由相同的金属氧化物材料制成， 而各层的含氧量不 同。
17、如权利要求 11方法，其中在通过溅射法形成所述氧化物半导体层时， 氧气占总溅射气体的质量百分比为 10%~30%。
18、如权利要求 17方法， 其中在通过溅射法形成所述第一过渡层时， 氧 气占总气体的质量百分比为 30%~100%, 且高于形成氧化物半导体时的氧气 占总溅射气体的质量百分比。
19、如权利要求 18所述的氧化物半导体薄膜晶体管，其中在通过溅射法 形成所述第三过渡层时， 氧气占总气体的质量百分比大于所述氧化物半导体 层沉积时的质量百分比且小于第一过渡层在沉积时的质量百分比。
20、 一种显示装置， 包括权利要求 1所述的氧化物半导体薄膜晶体管。
PCT/CN2013/071939 2012-02-28 2013-02-27 氧化物半导体薄膜晶体管及其制造方法与显示装置 WO2013127337A1 (zh)

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