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WO2018040608A1 - 氧化物薄膜晶体管及其制备方法、阵列基板、显示装置 - Google Patents

氧化物薄膜晶体管及其制备方法、阵列基板、显示装置 Download PDF

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Publication number
WO2018040608A1
WO2018040608A1 PCT/CN2017/083197 CN2017083197W WO2018040608A1 WO 2018040608 A1 WO2018040608 A1 WO 2018040608A1 CN 2017083197 W CN2017083197 W CN 2017083197W WO 2018040608 A1 WO2018040608 A1 WO 2018040608A1
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layer
film transistor
thin film
active layer
oxide thin
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PCT/CN2017/083197
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English (en)
French (fr)
Inventor
刘威
方金钢
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京东方科技集团股份有限公司
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Priority to US15/571,553 priority Critical patent/US10192991B2/en
Publication of WO2018040608A1 publication Critical patent/WO2018040608A1/zh

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
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    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/38—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions
    • H01L21/383—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions using diffusion into or out of a solid from or into a gaseous phase
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
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    • G02F1/167—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect by electrophoresis
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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • Embodiments of the present invention relate to an oxide thin film transistor, a method of fabricating the same, an array substrate, and a display device.
  • Oxide thin film transistor has the advantages of high mobility, good stability, simple fabrication process, etc.
  • the oxide semiconductor material represented by indium gallium zinc oxide (IGZO) is in thin film transistor liquid crystal display (TFT-LCD), active matrix organic Applications in the fields of light-emitting diode panels (AMOLED), electronic paper display panels, and integrated circuits are very widespread.
  • Top-gate oxide thin film transistors play a vital role in the application of large-sized display panels, which can greatly improve the electrical performance of thin film transistors, for example, improve the stability and uniformity of thin film transistors.
  • At least one embodiment of the present invention provides a method of fabricating an oxide thin film transistor, the method comprising: providing a substrate; depositing an active layer film, a gate insulating film, and a gate metal layer sequentially on the substrate a thin film, and patterning the active layer film, the gate insulating layer film, and the gate metal layer film to form an active layer, a gate insulating layer, and a gate metal layer, respectively; depositing an insulating layer at a first temperature The layer film is patterned and formed to form an insulating layer; wherein a portion of the active layer not overlapping the gate metal layer is electrically formed to form a conductor during deposition of the insulating layer film.
  • the preparation method provided by at least one embodiment of the present invention further includes depositing a source/drain electrode layer film on the insulating layer and patterning it to form a source/drain electrode layer.
  • the preparation method provided by at least one embodiment of the present invention further includes: forming a via hole on the insulating layer, and the conductive portion of the active layer and the source/drain electrode layer pass through the via hole connection.
  • the preparation method provided by at least one embodiment of the present invention further includes: A buffer layer is formed between the board and the active layer.
  • the material of the active layer includes indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), gallium zinc oxide (GZO). .
  • IGZO indium gallium zinc oxide
  • IZO indium zinc oxide
  • ZnO zinc oxide
  • GZO gallium zinc oxide
  • the first temperature is 290 ° C and above.
  • the first temperature is 290 ° C to 400 ° C.
  • the preparation method provided by at least one embodiment of the present invention further includes performing plasma treatment on a portion of the active layer that is not overlapped with the gate metal layer.
  • At least one embodiment of the present invention also provides an oxide thin film transistor including: a substrate; an active layer, a gate insulating layer, a gate metal layer, and an insulating layer sequentially disposed on the substrate a layer and a source/drain electrode layer, wherein a surface of a portion of the active layer not overlapping the gate metal layer is provided with a conductor in a direction perpendicular to the base substrate, the conductor being The insulating layer is formed when deposited at a first temperature, and the conductor is electrically connected to the source/drain electrode layer.
  • the first temperature is 290 ° C or higher.
  • the first temperature is 290 ° C to 400 ° C.
  • the conductor is formed by plasma processing.
  • the gas forming the plasma includes nitrogen gas, argon gas, and helium gas.
  • the material of the active layer includes indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), gallium zinc oxide ( GZO).
  • IGZO indium gallium zinc oxide
  • IZO indium zinc oxide
  • ZnO zinc oxide
  • GZO gallium zinc oxide
  • the oxide thin film transistor according to at least one embodiment of the present invention further includes a buffer layer disposed between the base substrate and the active layer.
  • the material of the buffer layer includes an oxide of silicon or a nitride of silicon.
  • At least one embodiment of the present invention also provides an array substrate comprising any of the above oxide films Transistor.
  • At least one embodiment of the present invention also provides a display device including any of the above array substrates.
  • FIG. 1 is a schematic structural view of a top gate type oxide thin film transistor
  • FIG. 2 is a schematic structural diagram of a top gate type oxide thin film transistor according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a flow chart of a method for fabricating a top gate type oxide thin film transistor according to an embodiment of the present invention
  • FIGS. 5a-5h are process diagrams of a method of fabricating a top-gate oxide thin film transistor according to an embodiment of the present invention.
  • the oxide active layer of the source region and the drain region can be subjected to conductor treatment, so that the thin film transistor has better switching characteristics.
  • a commonly used method of conducting a conductor is to bombard the surface of the active layer with a plasma to make the active layer surface.
  • the structure of the layer changes to enhance its electrical conductivity.
  • a silicon oxide film or a silicon nitride film is usually prepared at a relatively low temperature, and the film quality of the obtained silicon oxide film or silicon nitride film is not good due to low temperature, and the temperature is low.
  • the structure of the active layer surface be further changed, such as the loss of oxygen and the enhancement of its electrical properties, thus causing the final thin film transistor switching characteristics to be unsatisfactory.
  • FIG. 1 is a schematic structural view of a current top gate type oxide thin film transistor including a base substrate 1 and a buffer layer 2 sequentially disposed on the base substrate 1.
  • the exposed active layer 3 is subjected to plasma treatment, and the portion of the active layer 3 not overlapping the gate metal layer 5 and the gate insulating layer 4 is performed.
  • the insulating layer film is deposited by a conventional low-temperature silicon oxide process (for example, a chemical vapor deposition process), but the film quality of the insulating layer prepared by using the low-temperature deposition insulating film is not good, and At a lower temperature (below 250 ° C), the surface of the portion of the active layer 3 that does not overlap with the gate metal layer 5 and the gate insulating layer 4 is not effectively promoted to further lose oxygen, so that this portion cannot be further conductorized.
  • a conventional low-temperature silicon oxide process for example, a chemical vapor deposition process
  • Table 1 is data of an on-state current (Ion) and an off-state current (Ioff) which were tested by applying different voltages to the source 8 and the drain 7 of one example of the top gate type oxide thin film transistor shown in FIG. As can be seen from Table 1, when different voltages are applied to the source 8 and the drain 7, the current when the top gate type oxide thin film transistor shown in Fig. 1 is in an on state is small.
  • Embodiments of the present invention provide a top gate type oxide thin film transistor including: a base substrate; an active layer, a gate insulating layer, and a gate sequentially disposed on the base substrate a metal layer, an insulating layer, and a source/drain electrode layer. a surface of a portion of the active layer not overlapping the gate metal layer is disposed in a direction perpendicular to the substrate, and the conductor is formed when the insulating layer is deposited at a first temperature, the conductor and the source leak The pole layer is electrically connected.
  • depositing an insulating layer film at a high temperature may enable the active layer
  • the structure is further changed to enhance its electrical properties, thereby improving the electrical performance of the thin film transistor.
  • FIG. 2 is a schematic structural view of a top gate type oxide thin film transistor according to an embodiment of the present invention.
  • the top gate type oxide thin film transistor includes: a base substrate 1; an active layer 3, a gate insulating layer 4, a gate metal layer 5, and an insulating layer 6 which are sequentially disposed on the base substrate. And source and drain electrode layers (including drain 7, source 8).
  • a surface of a portion of the active layer 3 not overlapping the gate metal layer 5 is provided with a conductor 9 which is formed when the insulating layer 6 is deposited at a first temperature,
  • the conductor 9 is electrically connected to the source/drain electrode layer (including the drain 7 and the source 8).
  • the insulating layer is deposited at a first temperature (not shown) such that a portion of the active layer 3 not overlapping the gate metal layer 5 is conductorized.
  • the active layer 3 is made of an oxide semiconductor material, and portions of the active layer 3 that are not overlapped with the gate metal layer 5 (source region and drain region) may be conductorized by, for example, a plasma treatment process to increase Conductivity reduces the ohmic contact resistance caused when it comes into contact with, for example, a metal conductive film.
  • a method of depositing an insulating thin film at a high temperature is employed, and the top gate type oxide thin film transistor is in a vacuum high temperature state, and the active layer 3 is not overlapped with the gate metal layer 5 (ie, The portion of the source layer that is conductorized) further deoxidizes, so that the conductivity of the portion of the active layer that is electrically conductive is further enhanced, thereby improving the electrical characteristics of the thin film transistor, even when the insulating film is deposited above 350 ° C.
  • the conductor treatment effect can be achieved without a separate plasma treatment, for example, the on-state current is increased and the off-state current is lowered.
  • Table 2 shows the data of the on-state current (Ion) and the off-state current (Ioff) obtained by applying different voltages to the source 8 and the drain 7 of one example of the top gate type oxide thin film transistor shown in FIG. .
  • the top gate type oxide thin film shown in FIG. 2 Compared with the data obtained by testing the top gate type oxide thin film transistor shown in FIG. 1, under the same conditions (except for the preparation conditions of the insulating layer), the top gate type oxide thin film shown in FIG.
  • the on-state current of the membrane transistor becomes large, and its off-state current becomes small.
  • the top-gate oxide thin film transistor shown in FIG. 1 has an on-state current of 5.6E-8 and an off-state current of 4.0E-15; the top gate type oxide shown in FIG.
  • the thin film transistor has an on-state current of 2.8E-5 and an off-state current of 4.0E-16. From the above data, it can be concluded that the on-state current of the thin film transistor shown in FIG. 2 is 500 times that of the thin film transistor shown in FIG.
  • the off-state current of the thin film transistor shown in 1 is 1/10.
  • the on-state current of the top gate type oxide thin film transistor in the embodiment of the present invention is remarkably improved, and the off-state current is remarkably lowered.
  • the first temperature of depositing the insulating layer film is 290 ° C and above, for example, the first temperature is 290 ° C - 400 ° C, such as 290 ° C, 300 ° C, 350 ° C, 400 ° C .
  • the first temperature range is higher than the temperature at which the insulating layer film is deposited in the preparation process of the thin film transistor shown in FIG. 1, and is a high temperature process.
  • an insulating layer film for example, a silicon oxide film or a silicon nitride film
  • a portion of the active layer 3 that does not overlap with the gate metal layer 5 is further deoxidized, and the active layer
  • the conductorized portion is further conductorized to form a thin film transistor whose electrical characteristics satisfy the requirements.
  • the active layer 3 is processed by plasma to form the conductor 9.
  • the surface of the oxide active layer 3 is bombarded with plasma so as not to overlap with the gate metal layer 5.
  • the conductivity of the portion is enhanced to form the conductor 9 (the portion where the active layer is conductorized).
  • the top gate type oxide thin film transistor is in a vacuum high temperature state, and the conductor 9 is further deoxidized, exhibiting stronger and more stable conductivity, thereby improving the electrical characteristics of the thin film transistor.
  • a plasma can be generated using a radio frequency tube having a power of 10 W to 5000 W, and the duration of the plasma treatment is 30. Seconds to 30 minutes.
  • the gas forming the plasma includes a protective atmosphere or a reactive atmosphere
  • the protective atmosphere may be one of nitrogen gas, argon gas, helium gas, neon gas, or a mixed gas.
  • the reactive atmosphere may be one of air, oxygen, hydrogen, ammonia, carbon dioxide or a mixed gas.
  • the material of the active layer 3 is a metal oxide such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), or gallium zinc oxide (GZO).
  • the active layer 3 may be deposited by magnetron sputtering and then formed by a patterning process, and may have a thickness of 30-50 nm, for example, It can be 30 nm, 40 nm, and 50 nm.
  • the material of the gate metal layer 5 may be a copper-based metal, for example, copper (Cu), copper-molybdenum alloy (Cu/Mo), copper-titanium alloy (Cu/Ti), copper-molybdenum-titanium alloy (Cu/Mo/ Ti), copper-molybdenum-tungsten alloy (Cu/Mo/W), copper-molybdenum-niobium alloy (Cu/Mo/Nb), etc.; the material of the gate metal layer may also be a chromium-based metal, for example, a chromium-molybdenum alloy (Cr/Mo) ), chrome-titanium alloy (Cr/Ti), chromium-molybdenum-titanium alloy (Cr/Mo/Ti), and the like.
  • a chromium-based metal for example, a chromium-molybdenum alloy (Cr/Mo) ), chrome-titanium alloy (Cr/Ti
  • materials used as the gate insulating film include silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), or other suitable materials.
  • the top gate type oxide thin film transistor may further include a buffer layer 2 disposed between the base substrate 1 and the active layer 3, and the buffer layer 2 acts as a transition film between the active layer 3 and the base substrate 1.
  • the layer makes the bonding between the active layer 3 and the base substrate 1 more stable, and can prevent harmful impurities, ions, and the like in the base substrate 1 from diffusing to the active layer 3.
  • the material of the buffer layer 2 includes an oxide of silicon (SiOx) or a nitride of silicon (SiNx), silicon oxide.
  • the buffer layer 2 may be a single layer structure composed of silicon nitride or silicon oxide, or a two-layer structure composed of silicon nitride and silicon oxide.
  • FIG. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • the array substrate includes the top gate type oxide thin film transistor of the first embodiment.
  • the array substrate further includes a pixel electrode 12, a second insulating layer 13, and a passivation layer. 14.
  • the pixel electrode 12 is electrically connected to a drain hole 7 of the thin film transistor through a via hole formed in the second insulating layer 13 and the passivation layer 14, for example.
  • the source electrode 8 of the thin film transistor is electrically connected or integrally formed with a data line (not shown), and the gate metal layer 5 of the thin film transistor is electrically connected or integrally formed with a gate line (not shown).
  • the data lines and the gate lines cross each other to define sub-pixels on the array substrate, and the thin film transistor serves as a switching element of the sub-pixel.
  • the pixel electrode 12 is formed of a transparent conductive material or a metal material.
  • the material forming the pixel electrode 12 includes indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide ( GZO) zinc oxide (ZnO), indium oxide (In 2 O 3 ), aluminum zinc oxide (AZO), carbon nanotubes, and the like.
  • the material of the passivation layer 14 may be silicon nitride (SiNx), silicon oxide (SiOx), acrylic resin, or the like.
  • the material of the second insulating layer 13 may be an organic insulating material or an inorganic insulating material. Or a laminated structure formed of an organic insulating material and an inorganic insulating material.
  • the material forming the insulating layer is silicon nitride (SiNx), silicon oxide (SiOx), an acrylic resin or the like.
  • the array substrate can be applied to, for example, a liquid crystal display panel, an organic light emitting diode display panel, an electronic paper display panel, or the like.
  • Embodiments of the present disclosure also provide a display device including any of the above array substrates.
  • an example of the display device is a liquid crystal display device in which an array substrate and a counter substrate are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, a color filter substrate.
  • the pixel electrode of each sub-pixel of the array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display device further includes a backlight that provides backlighting for the array substrate.
  • OLED organic light emitting diode display device
  • OLED organic light emitting diode display device
  • an organic light emitting material stack is formed on the array substrate, and a pixel electrode of each pixel unit is used as an anode or a cathode for driving the organic light emitting material to emit light. Display operation.
  • Still another example of the display device is an electronic paper display device in which an electronic ink layer is formed on an array substrate, and a pixel electrode of each pixel unit serves as a voltage for applying a charged microparticle moving in the driving electronic ink to perform a display operation .
  • FIG. 4 is a flow chart of a method for fabricating a top gate type oxide thin film transistor according to an embodiment of the present invention.
  • the process of preparing a top gate type oxide thin film transistor includes: providing a substrate; sequentially depositing an active layer film, a gate insulating film, and a gate metal film on the substrate, and bonding the active layer film and the gate The insulating layer film and the gate metal layer film are patterned to form an active layer, a gate insulating layer and a gate metal layer, respectively; the insulating layer film is deposited at a first temperature and patterned to form an insulating layer, wherein A portion of the active layer that does not overlap the gate metal layer is deposited in the process of depositing the insulating layer film to form a conductor.
  • the process of preparing the top gate type oxide thin film transistor it is further included to perform plasma processing on a portion of the active layer that is not overlapped with the gate metal layer.
  • the method further comprises: depositing a source/drain electrode layer film on the insulating layer film, and patterning the same to form a source/drain electrode layer.
  • the method further includes forming a via hole on the insulating layer, and the conductorized portion of the active layer is electrically connected to the source/drain electrode layer through the via hole.
  • a buffer layer is formed between the base substrate and the active layer.
  • 5a-5h are process diagrams of the preparation of a top gate type oxide thin film transistor in an embodiment of the present invention.
  • an example of a process of preparing a top gate type oxide thin film transistor provided by an embodiment of the present invention includes the steps described below.
  • a base substrate 1 is provided and a buffer layer 2 is formed on the base substrate.
  • the base substrate 1 may be a glass substrate.
  • the material of the buffer layer 2 includes silicon oxide (SiOx) or silicon nitride (SiNx), silicon oxynitride (SiOxNy).
  • the buffer layer 2 may be a single layer structure composed of silicon nitride or silicon oxide, or a two-layer structure composed of silicon nitride and silicon oxide.
  • an active layer film is deposited on the buffer layer 2 and the active layer film is patterned to form the active layer 3.
  • the material of the active layer 3 is a metal oxide such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), or gallium zinc oxide (GZO).
  • the active layer 3 may be deposited by magnetron sputtering and then formed by a patterning process, and may have a thickness of 30 to 50 nm, for example, 30 nm, 40 nm or 50 nm.
  • the patterning process is, for example, a photolithography patterning process, which includes, for example, coating a photoresist layer on a structure layer to be patterned, and exposing the photoresist layer using a mask to expose The photoresist layer is developed to obtain a photoresist pattern, the structural layer is etched using a photoresist pattern, and then the photoresist pattern is optionally removed.
  • the patterning process may also be a screen printing, an inkjet printing method, or the like, as needed.
  • a gate insulating film is deposited on the active layer 3, and the gate insulating film is patterned to form the gate insulating layer 4.
  • materials used as the gate insulating film include silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), or other suitable materials.
  • the material of the gate metal layer 5 may be a copper-based metal, for example, copper (Cu), copper-molybdenum alloy (Cu/Mo), copper-titanium alloy (Cu/Ti), copper-molybdenum-titanium alloy (Cu/Mo/ Ti), copper-molybdenum-tungsten alloy (Cu/Mo/W), copper-molybdenum-niobium alloy (Cu/Mo/Nb), etc.; the material of the gate metal layer may also be a chromium-based metal, for example, a chromium-molybdenum alloy (Cr/Mo) ), chrome-titanium alloy (Cr/Ti), chromium-molybdenum-titanium alloy (C
  • the gas forming the plasma includes a protective atmosphere or a reactive atmosphere, and for example, the protective atmosphere may be one of nitrogen gas, argon gas, helium gas, neon gas, or a mixed gas.
  • the reactive atmosphere may be one of air, oxygen, hydrogen, ammonia, carbon dioxide or a mixed gas.
  • an insulating layer film is deposited on the buffer layer 2 by using a first temperature, and the gate metal of the active layer 3 is not deposited during the deposition of the insulating layer film (for example, a silicon oxide film or a silicon nitride film).
  • the insulating layer film for example, a silicon oxide film or a silicon nitride film.
  • the portion where the layer 5 overlaps is further deoxidized, that is, the portion 9 of which the active layer is conductorized is further conductorized to form a thin film transistor whose electrical characteristics satisfy the demand.
  • the first temperature used to deposit the insulating layer is 290 ° C and above.
  • the first temperature used in depositing the insulating layer is 290 ° C - 400 ° C, for example, 290 ° C, 300 ° C, 350 ° C or 400 ° C.
  • the material of the insulating layer is silicon nitride (SiNx) or silicon oxide (SiOx).
  • a via hole 10 is formed on the insulating layer.
  • the via 10 is connected to the conductor 9, i.e., the conductor 9 is exposed.
  • a source/drain electrode layer film is deposited on the insulating layer 6, and patterned by a patterning process to form a source/drain electrode layer (including the drain electrode 7 and the source electrode 8).
  • the source-drain electrode layer is electrically connected to the conductor 9 through the via 10 (see FIG. 5g).
  • the steps of forming the gate insulating layer 4 and the gate metal layer 5 shown in FIGS. 5c and 5d are combined, that is, the gate insulating film and the gate metal film are successively deposited, and then The gate insulating layer 4 and the gate metal layer 5 are obtained by the same patterning process.
  • Embodiments of the present invention provide an oxide thin film transistor, a method of fabricating the same, an array substrate, and a display device, and have at least one of the following beneficial effects:

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Abstract

一种氧化物薄膜晶体管及其制备方法、阵列基板、显示装置。该氧化物薄膜晶体管的制备方法，包括：提供衬底基板；在所述衬底基板上依次沉积有源层薄膜、栅绝缘层薄膜和栅极金属层薄膜，并对所述有源层薄膜、所述栅绝缘层薄膜和所述栅极金属层薄膜进行构图工艺分别形成有源层、栅绝缘层和栅极金属层；在第一温度下沉积绝缘层薄膜并对其进行构图工艺以形成绝缘层；其中，在沉积所述绝缘层薄膜的过程中所述有源层未与所述栅极金属层重叠的部分被导体化以形成导体。在第一温度下沉积绝缘层薄膜的过程可使有源层进一步失氧，从而使其导电性能增强，进而可提高薄膜晶体管的电学性能。

Description

氧化物薄膜晶体管及其制备方法、阵列基板、显示装置 技术领域
本发明的实施例涉及一种氧化物薄膜晶体管及其制备方法、阵列基板、显示装置。
背景技术
氧化物薄膜晶体管具有高迁移率、稳定性好、制作工艺简单等优点，以铟镓锌氧化物(IGZO)为代表的氧化物半导体材料在薄膜晶体管液晶显示器(TFT-LCD)、有源矩阵有机发光二极体面板(AMOLED)、电子纸显示面板以及集成电路等领域的应用非常广泛。
氧化物薄膜晶体管中栅极和源极之间产生的电容较小，使得显示面板可以具有高分辨率、低功耗等优点。顶栅型氧化物薄膜晶体管在大尺寸显示面板的应用中起着至关重要的作用，能够很大程度地提高薄膜晶体管的电学性能，例如，提高薄膜晶体管的稳定性和均匀性。
发明内容
本发明至少一实施例提供一种氧化物薄膜晶体管的制备方法，该制备方法包括：提供衬底基板；在所述衬底基板上依次沉积有源层薄膜、栅绝缘层薄膜和栅极金属层薄膜，并对所述有源层薄膜、所述栅绝缘层薄膜和所述栅极金属层薄膜进行构图工艺分别形成有源层、栅绝缘层和栅极金属层；在第一温度下沉积绝缘层薄膜并对其进行构图工艺以形成绝缘层；其中，在沉积所述绝缘层薄膜的过程中所述有源层的未与所述栅极金属层重叠的部分被导体化以形成导体。
例如，本发明至少一实施例提供的制备方法，还包括：在所述绝缘层上沉积源漏电极层薄膜，并对其进行图案化处理形成源漏电极层。
例如，本发明至少一实施例提供的制备方法，还包括：在所述绝缘层上形成过孔，所述有源层的被导体化的部分与所述源漏电极层通过所述过孔电连接。
例如，本发明至少一实施例提供的制备方法，还包括：在所述衬底基 板和所述有源层之间形成缓冲层。
例如，在本发明至少一实施例提供的制备方法中，所述有源层的材料包括氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化镓锌(GZO)。
例如，在本发明至少一实施例提供的制备方法中，所述第一温度为290℃及以上。
例如，在本发明至少一实施例提供的制备方法中，所述第一温度为290℃-400℃。
例如，本发明至少一实施例提供的制备方法，还包括对所述有源层未与所述栅极金属层重叠的部分进行等离子体处理。
本发明至少一实施例还提供一种氧化物薄膜晶体管，该氧化物薄膜晶体管包括：衬底基板；依次设置在所述衬底基板上的有源层、栅绝缘层、栅极金属层、绝缘层和源漏电极层，其中，在垂直于所述衬底基板的方向上，所述有源层未与所述栅极金属层重叠的部分的表面设置有导体，所述导体是在所述绝缘层在第一温度下沉积时所形成的，所述导体与所述源漏电极层电连接。
例如，在本发明至少一实施例提供的氧化物薄膜晶体管中，所述第一温度为290℃及以上。
例如，在本发明至少一实施例提供的氧化物薄膜晶体管中，所述第一温度为290℃-400℃。
例如，在本发明至少一实施例提供的氧化物薄膜晶体管中，通过等离子体处理方式形成所述导体。
例如，在本发明至少一实施例提供的氧化物薄膜晶体管中，形成所述等离子体的气体包括氮气、氩气、氦气。
例如，在本发明至少一实施例提供的氧化物薄膜晶体管中，所述有源层的材料包括氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化镓锌(GZO)。
例如，本发明至少一实施例提供的氧化物薄膜晶体管，还包括设置于所述衬底基板和所述有源层之间的缓冲层。
例如，在本发明至少一实施例提供的氧化物薄膜晶体管中，所述缓冲层的材料包括硅的氧化物或硅的氮化物。
本发明至少一实施例还提供一种阵列基板，包括上述任一氧化物薄膜 晶体管。
本发明至少一实施例还提供一种显示装置，包括上述任一阵列基板。
附图说明
图1为一种顶栅型氧化物薄膜晶体管的结构示意图；
图2为本发明一实施例提供的一种顶栅型氧化物薄膜晶体管的结构示意图；
图3为本发明一实施例提供的一种阵列基板的结构示意图；
图4为本发明一实施例提供的一种顶栅型氧化物薄膜晶体管的制备方法的流程图；以及
图5a-5h为本发明一实施例提供的一种顶栅型氧化物薄膜晶体管的制备方法的过程图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在顶栅型氧化物薄膜晶体管的制备过程中，可以将源极区域和漏极区域的氧化物有源层进行导体化处理，使薄膜晶体管具有较好的开关特性。常用的导体化处理的方法是利用等离子体轰击有源层的表面，使有源层表 层的结构发生变化，从而增强其导电性能。但是在后续的绝缘层沉积时，通常采用在较低温度下制备氧化硅薄膜或者氮化硅薄膜，由于温度低，所得到的氧化硅薄膜或氮化硅薄膜的膜质不好，且温度低也不能使得有源层表层的结构进一步发生变化，例如失去氧元素而使其电学特性增强，因此导致最后的薄膜晶体管开关特性不尽如人意。
例如，图1为当前的一种顶栅型氧化物薄膜晶体管的结构示意图，该顶栅型氧化物薄膜晶体管包括衬底基板1以及依次设置在所述衬底基板1上的缓冲层2、有源层3、栅绝缘层4、栅极金属层5、绝缘层6和源漏电极层(包括漏极7和源极8)。在栅极金属层5与栅绝缘层4刻蚀完成后，对暴露出的有源层3进行等离子体处理，将有源层3未与栅极金属层5和栅绝缘层4重叠的部分进行导体化；在形成绝缘层6的过程中，采用常规的低温氧化硅工艺(例如化学气相沉积工艺)沉积绝缘层薄膜，但是，采用低温沉积绝缘层薄膜制备的绝缘层的膜质不好，并且在较低的温度(250℃以下)下也不能有效促进有源层3未与栅极金属层5和栅绝缘层4重叠的部分表面进一步失去氧元素，从而不能使此部分进一步被导体化。
表一为对图1所示的顶栅型氧化物薄膜晶体管的一个示例的源极8和漏极7施加不同电压进行测试得到的开态电流(Ion)和关态电流(Ioff)的数据。从表一中可以看出，对源极8和漏极7施加不同电压时，当图1所示的顶栅型氧化物薄膜晶体管处于开启状态时的电流较小。
表一
Vds Ion Ioff Ion/Ioff
0.1 1.1E-9 9.0E-15 1.2E+5
5.1 5.6E-8 4.0E-15 1.4E+7
10.1 1.1E-7 5.0E-15 2.3E+7
15.1 1.8E-7 1.0E-15 1.8E+8
20.1 2.7E-7 2.0E-15 1.4E+8
本发明的实施例提供了一种顶栅型氧化物薄膜晶体管，该顶栅型氧化物薄膜晶体管，包括：衬底基板；依次设置在衬底基板上的有源层、栅绝缘层、栅极金属层、绝缘层和源漏电极层。在垂直于衬底基板的方向上，有源层未与栅极金属层重叠的部分的表面设置有导体，该导体是在绝缘层在第一温度下沉积时所形成的，该导体与源漏电极层电连接。在该顶栅型氧化物薄膜晶体管的制备过程中，在高温下沉积绝缘层薄膜可使有源层的 结构进一步发生变化，使其电学特性增强，从而可以提高薄膜晶体管的电学性能。
本发明的实施例提供一种顶栅型氧化物薄膜晶体管，图2为本发明一实施例提供的一种顶栅型氧化物薄膜晶体管的结构示意图。例如，如图2所示，该顶栅型氧化物薄膜晶体管包括：衬底基板1；依次设置在衬底基板上的有源层3、栅绝缘层4、栅极金属层5、绝缘层6和源漏电极层(包括漏极7、源极8)。在垂直于衬底基板1的方向上，有源层3未与栅极金属层5重叠的部分的表面设置有导体9，该导体是在绝缘层6在第一温度下沉积时所形成的，导体9与源漏电极层(包括漏极7、源极8)电连接。例如，该绝缘层在第一温度下沉积(未示出)以使有源层3未与栅极金属层5重叠的部分被导体化。
有源层3采用氧化物半导体材料制备，并且有源层3的未与栅极金属层5重叠的部分(源极区域和漏极区域)可以通过例如等离子体处理工艺而导体化，以增加其导电性，降低其与例如金属导电薄膜接触时导致的欧姆接触电阻。在绝缘层6的形成过程中，采用高温沉积绝缘层薄膜的方式，且该顶栅型氧化物薄膜晶体管处于真空高温状态中，有源层3未与栅极金属层5重叠的部分(即有源层被导体化的部分)会进一步失氧，使得有源层被导体化的部分的导电性进一步增强，从而使该薄膜晶体管的电学特性提高，甚至在350℃以上沉积的这层绝缘薄膜时，并不需要单独的等离子体处理即可达到导体化处理效果，例如，使得其开态电流提高，关态电流降低。
表二为对图2所示的顶栅型氧化物薄膜晶体管的一个示例的源极8和漏极7施加不同的电压进行测试得到的开态电流(Ion)和关态电流(Ioff)的数据。
表二
Vds Ion Ioff Ion/Ioff
0.1 5.9E-7 4.0E-16 1.5E+09
5.1 2.8E-5 4.0E-16 7.1E+10
10.1 5.4E-5 1.2E-15 4.5E+10
15.1 8.0E-5 4.0E-16 2.0E+11
与对图1所示的顶栅型氧化物薄膜晶体管测试得到的数据相比，在同样的条件(除了绝缘层的制备条件以外)下，图2所示的顶栅型氧化物薄 膜晶体管的开态电流变大，并且其关态电流变小。例如，当电压为5.1V时，图1所示的顶栅型氧化物薄膜晶体管的开态电流为5.6E-8，关态电流为4.0E-15；图2所示的顶栅型氧化物薄膜晶体管的开态电流为2.8E-5，关态电流为4.0E-16。从上述数据可以得出：图2中所示的薄膜晶体管的开态电流为图1中所示的薄膜晶体管的开态电流的500倍，图2中所示的薄膜晶体管的关态电流为图1中所示的薄膜晶体管的关态电流的1/10。与图1中的顶栅型氧化物薄膜晶体管相比，本发明的实施例中的顶栅型氧化物薄膜晶体管的开态电流显著提高，关态电流明显降低。
例如，在形成绝缘层6的过程中，沉积绝缘层薄膜的第一温度为290℃及以上，例如，该第一温度为290℃-400℃，例如290℃、300℃、350℃、400℃。该第一温度范围比图1所示的薄膜晶体管的制备过程沉积绝缘层薄膜的温度要更高，属于高温工艺。在该第一温度下，在沉积绝缘层薄膜(例如氧化硅薄膜、氮化硅薄膜)的过程中，有源层3的未与栅极金属层5重叠的部分会进一步失氧，有源层被导体化的部分会被进一步导体化，以形成电学特性满足需求的薄膜晶体管。
例如，有源层3通过等离子体进行处理以形成导体9。
例如，在衬底基板1上依次设置有源层3、栅绝缘层4、栅极金属层5之后，用等离子体轰击氧化物有源层3的表面使其未与栅极金属层5重叠的部分的表层结构发生变化，使该部分的导电性增强，形成导体9(有源层被导体化的部分)。在高温沉积绝缘层薄膜的过程中，顶栅型氧化物薄膜晶体管处于真空高温状态，导体9会进一步失氧，表现出更强更稳定的导电性，从而提高薄膜晶体管的电学特性。
用等离子体对有源层3的未与栅极金属层5重叠的部分进行处理的过程中，例如，可以采用功率为10W～5000W的射频管产生等离子体，且等离子体处理的持续时间为30秒至30分钟。
例如，形成等离子体的气体包括保护性气氛或者反应性气氛，例如，保护性气氛可以为氮气、氩气、氦气、氖气中的一种或者混合气体。反应性气氛可以为空气、氧气、氢气、氨气、二氧化碳中的一种或者混合气体。
例如，有源层3的材料为氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化镓锌(GZO)等金属氧化物。该有源层3可以利用磁控溅射的方式沉积，然后通过构图工艺形成，其厚度可以为30-50nm，例如， 可以为30nm、40nm以及50nm。
例如，该栅极金属层5的材料可以为铜基金属，例如，铜(Cu)、铜钼合金(Cu/Mo)、铜钛合金(Cu/Ti)、铜钼钛合金(Cu/Mo/Ti)、铜钼钨合金(Cu/Mo/W)、铜钼铌合金(Cu/Mo/Nb)等；该栅金属层的材料也可以为铬基金属，例如，铬钼合金(Cr/Mo)、铬钛合金(Cr/Ti)、铬钼钛合金(Cr/Mo/Ti)等。
例如，被用作栅绝缘层薄膜的材料包括氮化硅(SiNx)、氧化硅(SiOx)、氧化铝(Al2O3)、氮化铝(AlN)或其他适合的材料。
例如，该顶栅型氧化物薄膜晶体管还可以包括设置于衬底基板1和有源层3之间的缓冲层2，缓冲层2在有源层3与衬底基板1之间充当一个过渡膜层，使有源层3与衬底基板1之间结合得更稳固，且可以防止衬底基板1中的有害杂质、离子等扩散到有源层3。
例如，缓冲层2的材料包括硅的氧化物(SiOx)或硅的氮化物(SiNx)、氧化硅。例如，该缓冲层2可以为由氮化硅或者氧化硅构成的单层结构，或者由氮化硅和氧化硅构成的双层结构。
本发明的实施例还提供一种阵列基板，图3为本发明一实施例提供的一种阵列基板的结构示意图。例如，如图3所示，该阵列基板包括实施例一中的顶栅型氧化物薄膜晶体管，例如，如图3所示该阵列基板还包括像素电极12、第二绝缘层13和钝化层14。
例如，像素电极12通过形成在第二绝缘层13和钝化层14中的过孔例如与薄膜晶体管的漏极7电连接。薄膜晶体管的源极8与数据线(未示出)电连接或一体形成，薄膜晶体管的栅极金属层5与栅线(未示出)电连接或一体形成。通常，数据线和栅线彼此交叉界定了阵列基板上的子像素，而该薄膜晶体管作为该子像素的开关元件。
例如，像素电极12采用透明导电材料形成或金属材料形成，例如，形成该像素电极12的材料包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)氧化锌(ZnO)、氧化铟(In2O3)、氧化铝锌(AZO)和碳纳米管等。
例如，该钝化层14的材料可以为氮化硅(SiNx)、氧化硅(SiOx)、丙烯酸类树脂等。
例如，第二绝缘层13的材料可以为有机绝缘材料或者无机绝缘材料 或者有机绝缘材料和无机绝缘材料形成的叠层结构。例如，形成该绝缘层的材料为氮化硅(SiNx)、氧化硅(SiOx)、丙烯酸类树脂等。
例如，该阵列基板可应用于例如液晶显示面板、有机发光二极管显示面板、电子纸显示面板等。
本公开的实施例还提供了一种显示装置，其包括上述任一阵列基板。
例如，该显示装置的一个示例为液晶显示装置，其中，阵列基板与对置基板彼此对置以形成液晶盒，在液晶盒中填充有液晶材料。该对置基板例如为彩膜基板。阵列基板的每个子像素的像素电极用于施加电场对液晶材料的旋转的程度进行控制从而进行显示操作。在一些示例中，该液晶显示装置还包括为阵列基板提供背光的背光源。
该显示装置的另一个示例为有机发光二极管显示装置(OLED)，其中，阵列基板上形成有有机发光材料叠层，每个像素单元的像素电极作为阳极或阴极用于驱动有机发光材料发光以进行显示操作。
该显示装置的再一个示例为电子纸显示装置，其中，阵列基板上形成有电子墨水层，每个像素单元的像素电极作为用于施加驱动电子墨水中的带电微颗粒移动以进行显示操作的电压。
本发明的实施例还提供一种顶栅型氧化物薄膜晶体管的制备方法，例如，图4为本发明一实施例提供的一种顶栅型氧化物薄膜晶体管的制备方法的流程图。例如，制备顶栅型氧化物薄膜晶体管的过程包括：提供衬底基板；在衬底基板上依次沉积有源层薄膜、栅绝缘层薄膜和栅极金属层薄膜，并对有源层薄膜、栅绝缘层薄膜和栅极金属层薄膜进行构图工艺分别形成有源层、栅绝缘层和栅极金属层；在第一温度下沉积绝缘层薄膜并对其进行构图工艺以形成绝缘层，其中，在沉积绝缘层薄膜的过程中有源层的未与栅极金属层重叠的部分被导体化以形成导体。
例如，在制备该顶栅型氧化物薄膜晶体管的过程中，还包括对有源层的未与栅极金属层重叠的部分进行等离子体处理。
例如，在制备该顶栅型氧化物薄膜晶体管的过程中，还包括：在绝缘层薄膜上沉积源漏电极层薄膜，并对其进行图案化处理形成源漏电极层。
例如，在制备该顶栅型氧化物薄膜晶体管的过程中，还包括：在所述绝缘层上形成过孔，有源层的被导体化的部分与源漏电极层通过过孔电连接。
例如，在制备该顶栅型氧化物薄膜晶体管的过程中，还包括在衬底基板和有源层之间形成缓冲层。
图5a-5h为本发明的实施例中的顶栅型氧化物薄膜晶体管制备的过程图。参照图5a-5h，本发明的实施例提供的顶栅型氧化物薄膜晶体管的制备过程的一个示例包括如下所述的步骤。
如图5a所示，提供一衬底基板1并在该衬底基板上形成缓冲层2。例如，该衬底基板1可以为玻璃基板。例如，缓冲层2的材料包括硅氧化物(SiOx)或硅氮化物(SiNx)、硅氮氧化物(SiOxNy)。例如，该缓冲层2可以为由氮化硅或者氧化硅构成的单层结构，或者由氮化硅和氧化硅构成的双层结构。
如图5b所示，在缓冲层2上沉积一层有源层薄膜并对该有源层薄膜进行构图工艺以形成有源层3。例如，该有源层3的材料为氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化镓锌(GZO)等金属氧化物。该有源层3可以利用磁控溅射的方式沉积，然后通过构图工艺形成，其厚度可以为30-50nm，例如，可以为30nm、40nm或50nm。
在本发明的实施例中，构图工艺例如为光刻构图工艺，其例如包括：在需要被构图的结构层上涂覆光刻胶层，使用掩膜板对光刻胶层进行曝光，对曝光的光刻胶层进行显影以得到光刻胶图案，使用光刻胶图案对结构层进行蚀刻，然后可选地去除光刻胶图案。根据需要，构图工艺还可以是丝网印刷、喷墨打印方法等。
如图5c所示，在有源层3上沉积一层栅绝缘层薄膜，并对该栅绝缘层薄膜进行构图工艺以形成栅绝缘层4。例如，被用作栅绝缘层薄膜的材料包括氮化硅(SiNx)、氧化硅(SiOx)、氧化铝(Al2O3)、氮化铝(AlN)或其他适合的材料。
如图5d所示，在栅绝缘层4上沉积一层栅极金属层薄膜，并对该栅极金属层薄膜进行构图工艺以形成栅极金属层5。例如，栅极金属层5与栅绝缘层4重叠。例如，该栅极金属层5的材料可以为铜基金属，例如，铜(Cu)、铜钼合金(Cu/Mo)、铜钛合金(Cu/Ti)、铜钼钛合金(Cu/Mo/Ti)、铜钼钨合金(Cu/Mo/W)、铜钼铌合金(Cu/Mo/Nb)等；该栅金属层的材料也可以为铬基金属，例如，铬钼合金(Cr/Mo)、铬钛合金(Cr/Ti)、铬钼钛合金(Cr/Mo/Ti)等。
如图5e所示，对有源层3未与栅极金属层5重叠的部分进行等离子体处理，用等离子体轰击氧化物有源层3的同时其表面未与栅极金属层5重叠的部分的表层结构发生变化，使该部分的导电性增强，即形成有源层被导体化的部分9。例如，形成等离子体的气体包括保护性气氛或者反应性气氛，例如，保护性气氛可以为氮气、氩气、氦气、氖气中的一种或者混合气体。反应性气氛可以为空气、氧气、氢气、氨气、二氧化碳中的一种或者混合气体。
如图5f所示，采用第一温度在缓冲层2上沉积绝缘层薄膜，在沉积绝缘层薄膜(例如氧化硅薄膜、氮化硅薄膜)的过程中，有源层3的未与栅极金属层5重叠的部分会进一步失氧，即有源层被导体化的部分9会被进一步导体化，以形成电学特性满足需求的薄膜晶体管。例如，沉积绝缘层时采用的第一温度为290℃及以上。进一步地，沉积绝缘层时采用的第一温度为290℃-400℃，例如，290℃、300℃、350℃或400℃。例如，该绝缘层的材料为氮化硅(SiNx)或者氧化硅(SiOx)。
如图5g所示，在绝缘层上形成过孔10。例如，该过孔10与导体9连接，即暴露出导体9。
如图5h所示，在绝缘层6上沉积源漏电极层薄膜，并通过构图工艺对其进行图案化处理形成源漏电极层(包括漏极7和源极8)。
例如，源漏电极层与导体9通过过孔10(参见图5g)电连接。
在本发明的另一个示例中，例如，图5c和5d所示的形成栅绝缘层4和栅极金属层5的步骤合并，也即，连续沉积栅绝缘层薄膜和栅极金属层薄膜，然后通过同一构图工艺得到栅绝缘层4和栅极金属层5。
本发明的实施例提供一种氧化物薄膜晶体管及其制备方法、阵列基板、显示装置，并且具有以下至少一项有益效果：
(1)在沉积绝缘层薄膜的过程中采用高温(即第一温度)沉积，形成的绝缘层的膜质好；
(2)在有源层上形成导体，从而显著提高薄膜晶体管的电学特性。
对于本公开，还有以下几点需要说明：
(1)本发明实施例附图只涉及到与本发明实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本发明的实施例的附图中，层或区 域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本发明的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，本发明的保护范围应以所述权利要求的保护范围为准。
本申请要求于2016年8月31日递交的中国专利申请第201610798600.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (18)

  1. 一种氧化物薄膜晶体管的制备方法，包括：
    提供衬底基板；
    在所述衬底基板上依次沉积有源层薄膜、栅绝缘层薄膜和栅极金属层薄膜，并对所述有源层薄膜、所述栅绝缘层薄膜和所述栅极金属层薄膜进行构图工艺分别形成有源层、栅绝缘层和栅极金属层；
    在第一温度下沉积绝缘层薄膜并对其进行构图工艺以形成绝缘层；
    其中，在沉积所述绝缘层薄膜的过程中所述有源层未与所述栅极金属层重叠的部分被导体化以形成导体。
  2. 根据权利要求1所述的制备方法，还包括：在所述绝缘层上沉积源漏电极层薄膜，并对其进行图案化处理形成源漏电极层。
  3. 根据权利要求2所述的制备方法，还包括：在所述绝缘层上形成过孔，所述有源层的被导体化的部分与所述源漏电极层通过所述过孔电连接。
  4. 根据权利要求1-3中任一项所述的制备方法，还包括：在所述衬底基板和所述有源层之间形成缓冲层。
  5. 根据权利要求1-4中任一项所述的制备方法，其中，所述有源层的材料包括氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化镓锌(GZO)。
  6. 根据权利要求5所述的制备方法，其中，所述第一温度为290℃及以上。
  7. 根据权利要求6所述的制备方法，其中，所述第一温度为290℃-400℃。
  8. 根据权利要求1-7中任一项所述的制备方法，还包括：对所述有源层未与所述栅极金属层重叠的部分进行等离子体处理。
  9. 一种氧化物薄膜晶体管，包括：
    衬底基板；
    依次设置在所述衬底基板上的有源层、栅绝缘层、栅极金属层、绝缘层和源漏电极层；其中，
    在垂直于所述衬底基板的方向上，所述有源层未与所述栅极金属层重 叠的部分的表面设置有导体，所述导体是在所述绝缘层在第一温度下沉积时所形成的，所述导体与所述源漏电极层电连接。
  10. 根据权利要求9所述的氧化物薄膜晶体管，其中，所述第一温度为290℃及以上。
  11. 根据权利要求10所述的氧化物薄膜晶体管，其中，所述第一温度为290℃-400℃。
  12. 根据权利要求9-11中任一项所述的氧化物薄膜晶体管，其中，通过等离子体处理方式形成所述导体。
  13. 根据权利要求12所述的氧化物薄膜晶体管，其中，形成所述等离子体的气体包括氮气、氩气、氦气。
  14. 根据权利要求9-13中任一项所述的氧化物薄膜晶体管，其中，所述有源层的材料包括氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化镓锌(GZO)。
  15. 根据权利要求14所述的氧化物薄膜晶体管，还包括设置于所述衬底基板和所述有源层之间的缓冲层。
  16. 根据权利要求15所述的氧化物薄膜晶体管，其中，所述缓冲层的材料包括硅的氧化物或硅的氮化物。
  17. 一种阵列基板，包括权利要求9-16中任一项所述的氧化物薄膜晶体管。
  18. 一种显示装置，包括如权利要求17所述的阵列基板。
PCT/CN2017/083197 2016-08-31 2017-05-05 氧化物薄膜晶体管及其制备方法、阵列基板、显示装置 WO2018040608A1 (zh)

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