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WO2013157080A1 - Dispositif à semi-conducteurs et son procédé de fabrication - Google Patents

Dispositif à semi-conducteurs et son procédé de fabrication Download PDF

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Publication number
WO2013157080A1
WO2013157080A1 PCT/JP2012/060347 JP2012060347W WO2013157080A1 WO 2013157080 A1 WO2013157080 A1 WO 2013157080A1 JP 2012060347 W JP2012060347 W JP 2012060347W WO 2013157080 A1 WO2013157080 A1 WO 2013157080A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
region
manufacturing
insulating material
layer
Prior art date
Application number
PCT/JP2012/060347
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English (en)
Japanese (ja)
Inventor
関根弘一
目黒弘一
Original Assignee
株式会社ディスコ
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Publication date
Application filed by 株式会社ディスコ filed Critical 株式会社ディスコ
Priority to PCT/JP2012/060347 priority Critical patent/WO2013157080A1/fr
Publication of WO2013157080A1 publication Critical patent/WO2013157080A1/fr

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Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a structure of an external terminal of the semiconductor device and a method of forming the external terminal.
  • CSP chip size package
  • a semiconductor chip is mounted on a lead frame or an interposer, and an electrical connection is made by a bonding wire or a flip chip.
  • External terminals such as grid array (LGA) or land grid array (LGA) are connected.
  • WLP wafer level package
  • a first manufacturing form of WLP is a wiring (rewiring and rewiring) that electrically couples an assembly of semiconductor chips on which a passivation film is formed to a chip pad (chip take-out electrode) corresponding to the opening of the passivation film.
  • external terminals soldder balls, bonding wires, etc.
  • the wafer is diced to obtain individual semiconductor devices to obtain individual CSPs.
  • an assembly of semiconductor chips on which a passivation film is formed is diced to obtain a plurality of independent chips, and each of the plurality of semiconductor chips is sealed with an insulating resin, respectively.
  • a wiring (sometimes referred to as rewiring), an external terminal, and the like that are electrically coupled to the chip pad corresponding to the opening of the corresponding passivation film are formed.
  • the semiconductor chip includes at least a semiconductor substrate (substrate), an electronic circuit (circuit element) such as a transistor, internal wiring for supplying power and signals to the electrical circuit, a plurality of electrical nodes and a plurality of internal wirings included in the electronic circuit. Insulation material that ensures independence, and passivation material.
  • the transistor is included in a semiconductor substrate or stacked as a three-dimensional structure on the semiconductor substrate.
  • the plurality of internal wirings are mainly formed as a multilayer wiring layer on a semiconductor substrate.
  • the passivation material is an insulating layer that protects the semiconductor chip on the uppermost layer of the multilayer wiring layer. The passivation function increases the reliability of the device by protecting the semiconductor chip from contamination such as moisture and mobile ions.
  • Patent Document 4 Cutting (Patent Document 4), grinding (Patent Document 5), and polishing (Patent Document 6) are disclosed as flattening techniques.
  • Patent Document 4 will be described later as a comparative example in the embodiment for carrying out the invention.
  • the gray tone mask creates a slit portion having a resolution lower than the limit resolution of the exposure machine, and the slit portion blocks a part of light to realize intermediate exposure.
  • the halftone mask performs intermediate exposure using a semi-transmissive film as an example. In any case, three exposure levels of an exposed portion, an intermediate exposed portion, and an unexposed portion can be expressed by one exposure, and two types of resist films can be formed after development.
  • Patent Documents 1 to 8 are incorporated in the present invention, and the contents disclosed by each of Patent Documents 1 to 8 are disclosed in the present specification. Part.
  • the present invention discloses a semiconductor device and a manufacturing method thereof with further reduced manufacturing costs, and discloses a wafer level package as a semiconductor device and a manufacturing method thereof as one embodiment.
  • a semiconductor device includes, for example, a substrate including a circuit element, a first metal wiring electrically coupled to the circuit element, and a first metal layer formed on the surface of the substrate; A passivation layer formed of a first insulating material covering the first metal layer; a first insulating layer formed of a second insulating material covering the passivation layer and including a first opening; A second metal layer including a second metal wiring formed in the first opening and electrically coupled to the first metal wiring; and electrically coupled to the second metal wiring; An external terminal formed on a surface of the second metal wiring, wherein the first opening has a first region having a first depth, and the first region is shallower than the first depth. A second region having a second depth that is a depth at which the insulating layer of the second layer remains. Wherein the second metal wiring is formed on the first and second regions.
  • a first metal layer including a first metal wiring electrically coupled to the circuit element is formed on the surface of the substrate on which the circuit element is formed.
  • An external terminal for coupling to the surface of the second metal wiring, and forming the first opening includes a first region having a first depth, A depth at which the first insulating layer remains to be shallower than a depth.
  • a second region having a depth, and simultaneously forming the second metal wiring is formed in the first and second regions.
  • FIGS. 2A to 2F are cross-sectional views taken along the line XX of FIG. 1 for explaining the steps of the WLP according to the first embodiment of the present invention.
  • FIGS. 3G to 3K are cross-sectional views taken along the line XX of FIG. 1 for explaining the steps of the WLP according to the first embodiment of the present invention.
  • 4A to 4F are diagrams for explaining other steps of the WLP according to the first embodiment of the present invention.
  • FIGS. 5A to 5D are cross-sectional views illustrating a process of WLP according to the second embodiment of the present invention.
  • 6E to 6G are cross-sectional views illustrating a process of WLP according to the second embodiment of the present invention.
  • FIG. 5 is a flowchart comparing the WLP process according to the first and second embodiments of the present invention and the conventional WLP process.
  • FIG. 8A is a schematic plan view of a fan-in type CSP
  • FIGS. 8B and 8C are diagrams showing a process of a fan-in type WLP according to the first or second embodiment of the present invention. It is the top view to explain and its sectional drawing.
  • FIGS. 9A to 9D are a plan view and a cross-sectional view for explaining a process of a fan-in type WLP according to the first or second embodiment of the present invention.
  • FIGS. 9A to 9D are a plan view and a cross-sectional view for explaining a process of a fan-in type WLP according to the first or second embodiment of the present invention.
  • FIGS. 10A to 10D are a plan view and a cross-sectional view illustrating a process of fan-in type WLP according to the first or second embodiment of the present invention.
  • FIGS. 11A and 11B are a plan view and a cross-sectional view illustrating a process of fan-in type WLP according to the first or second embodiment of the present invention.
  • 12A to 12E are cross-sectional views illustrating an example of manufacturing a fan-out type WLP substrate according to the first or second embodiment of the present invention.
  • FIG. 13 (A) is a schematic plan view of a fan-out type CSP
  • FIGS. 13 (B) and (C) show the steps of the fan-out type WLP according to the first or second embodiment of the present invention.
  • FIGS. 14A to 14D are a plan view and a cross-sectional view illustrating a process of fan-out type WLP according to the first or second embodiment of the present invention.
  • FIGS. 15A to 15D are a plan view and a cross-sectional view for explaining a process of a fan-out type WLP according to the first or second embodiment of the present invention.
  • FIGS. 16A to 16F are cross-sectional views for explaining a process of WLP according to the third embodiment of the present invention.
  • 17A to 17F are cross-sectional views illustrating other steps of WLP according to the third embodiment of the present invention. It is a figure which shows the example of the other layout pattern by a grating mask.
  • FIGS. 19A and 19B are cross-sectional views illustrating the process of WLP according to the fourth embodiment of the present invention.
  • 20A and 20B are cross-sectional views for explaining a process of WLP according to the fifth embodiment of the present invention.
  • 21A to 21E are cross-sectional views for explaining a process of WLP according to the sixth embodiment of the present invention.
  • 22A to 22D are cross-sectional views for explaining a process of WLP according to the seventh embodiment of the present invention.
  • FIGS. 23E to 23H are cross-sectional views for explaining a process of WLP according to the seventh embodiment of the present invention.
  • FIG. 3 is a first example of a cross-sectional view taken along line YY of FIG. 1 for explaining a process of WLP according to the first embodiment of the present invention.
  • FIG. 5 is a second example of the YY sectional view of FIG. 1 for explaining the process of WLP according to the first embodiment of the present invention.
  • It is a table
  • 3 is a schematic view showing an example of craze generated in the insulating photosensitive polyimide film 30.
  • FIG. 28 (a) and 28 (b) are graphs showing stress-strain curves of various resins.
  • FIGS. 29A and 29B are schematic views of the cutting at the height h1 in FIG.
  • an example of a semiconductor device and a manufacturing method thereof according to the present invention is applied to a WLP related to at least a part of a plurality of manufacturing steps included in the first or second manufacturing mode described above.
  • An example of the semiconductor device according to the present invention is a product obtained from such WLP.
  • the present invention is not necessarily limited to the semiconductor device related to WLP and the manufacturing method thereof, and may be an individual semiconductor device other than WLP and a method of manufacturing the same. That is, the present invention is widely applied to semiconductor devices and manufacturing methods thereof. It should be noted that the scale of the drawing and the ratio of each element are emphasized for easy understanding of the features of the invention, and are not necessarily the same as the actual device scale and the ratio.
  • FIG. 1 is a schematic plan view of a semiconductor chip related to a semiconductor device configured by using the manufacturing method according to the first embodiment of the present invention (plan view seen from an external terminal of the semiconductor device).
  • 1 illustrates one semiconductor chip on a semiconductor wafer.
  • a semiconductor wafer (not shown) includes a plurality of semiconductor chips.
  • One semiconductor chip 10 (semiconductor device 10) on the wafer is represented by a rectangular outer shape 10A.
  • the semiconductor chip 10 includes a silicon substrate 12, and a plurality of circuit elements 14 are formed on one main surface 12 ⁇ / b> A of the silicon substrate 12.
  • the silicon substrate 12 is not limited to a silicon material and may be other materials.
  • the circuit element 14 is an electronic circuit such as a transistor as an example.
  • FIG. 1 illustrates two circuit elements 14.
  • a single-layer or multi-layer wiring 16 is formed on the main surface 12A of the silicon substrate 12, and the wiring 16 constitutes an electrical path between the circuit element 14 and the chip extraction electrode 18.
  • the chip extraction electrode 18 is a so-called chip pad.
  • the chip extraction electrode 18 may be formed by exposing a partial region of the uppermost wiring 16 with a passivation layer, or a metal layer may be separately formed on the wiring 16.
  • a large number of such semiconductor chips 10 are formed on a wafer, and the silicon substrate 12 and the wiring 16 are protected by a passivation layer (passivation material).
  • the structure so far is manufactured in a so-called semiconductor pre-process. Thereafter, the metal pattern 52 and the external terminal 70 are formed on the main surface 12A of these semiconductor chips by a WLP process as will be described later.
  • the external terminals 70 are solder balls, bonding wires, etc., and their shapes and materials are not limited. That is, in the WLP process, the chip extraction electrode 18 (chip pad) manufactured in the previous process is electrically connected to the external terminal 70 as the semiconductor device by the metal pattern 52 as the rewiring.
  • the silicon substrate 12 includes a silicon material 12-1 and a multilayer wiring part 12-2.
  • the silicon material 12-1 includes the circuit element 14.
  • the multilayer wiring portion 12-2 includes a plurality of internal wirings (a plurality of internal wiring layers) that are stacked to electrically connect the circuit elements 14 and the wirings 16, and an insulating material that electrically insulates the plurality of internal wirings ( Insulating layer).
  • a well-known damascene technique may be used.
  • the chip extraction electrode 18 and the wiring 16 are included in the same wiring layer (first metal layer).
  • the same wiring layer is positioned as the uppermost wiring layer in the plurality of internal wiring layers.
  • the plurality of internal wiring layers are included in the multilayer wiring portion 12-2.
  • the same wiring layer (chip take-out electrode 18 and wiring 16) which is one of a plurality of elements constituting the features of the invention, is represented on the main surface 12A of the silicon substrate 12. Yes. That is, in order to make it easy to understand the structure of the embodiment for realizing the invention, it is simplified and described.
  • the chip extraction electrode 18 and the wiring 16 are formed on the main surface 12A of the silicon substrate 12.
  • the chip extraction electrode 18 is made of a conductive metal material such as Al, Au, or Cu, for example.
  • a passivation layer 20 made of silicon nitride (Si 3 N 4 ) or the like is formed on the entire surface of the substrate with a predetermined film thickness.
  • the passivation layer 20 has a convex-concave shape, but may be a planarized passivation layer 20.
  • an opening 20A for exposing the chip extraction electrode 16 is formed by using a known photolithography process.
  • an insulating photosensitive polyimide film 30 (second insulating material, which is a first insulating layer, is formed on the entire surface of the substrate so as to cover the passivation layer 20 by spin coating or the like. ) Is applied.
  • the photosensitive polyimide film 30 may be either a positive type or a negative type, but the example shown in the figure shows a positive type.
  • the film 30 is not limited to a polyimide material, and may be a material mainly composed of a phenol resin, an unsaturated polyester resin, a melamine resin, or a urea resin, for example. This will be described in detail with reference to FIG.
  • the photosensitive polyimide film 30 is exposed using a grating mask (halftone mask) 40 capable of changing the amount of transmitted light.
  • a grating mask halftone mask
  • Hitachi Kasei HD-8910 can be used as the grating mask 40, and the photosensitive polyimide film 30 can be subjected to grayscale (stepwise) exposure by varying the amount of transmitted light.
  • grayscale stepwise exposure by varying the amount of transmitted light.
  • the developed photosensitive polyimide film 30 a film thickness corresponding to the exposure amount remains. That is, the remaining film thickness is small in the region where the exposure amount is larger, and the remaining film thickness is thick in the region where the exposure amount is small.
  • the grating mask 40 includes a region that transmits the light amount L1, a region that transmits a light amount L2 that is smaller than the light amount L1, and a light shielding region 40A.
  • the light amount L1 is the opening 20A of the passivation layer 20. Expose areas that are aligned with.
  • the light quantity L2 is an area that continues laterally from the opening 20A, and exposes an area in which a metal layer will be formed later.
  • the light amount L1 is a value sufficient to completely remove the polyimide film 30 when developed, and the light amount L2 is a value that leaves a predetermined film thickness on the polyimide film 30.
  • the photosensitive polyimide film 30 is developed. As shown in FIG. 2 (F), the photosensitive polyimide film 30 is formed with an opening 32 having a step according to the amount of light.
  • the opening 32 has a first region 32A having a depth reaching the opening 20A at a position aligned with the opening 20A of the passivation layer 20, and a depth smaller than the first region 32A and laterally from the first region 32A. And a second region 32B extending at a certain depth.
  • the size of the first region 32 ⁇ / b> A is approximately the same as the opening 20 ⁇ / b> A of the passivation layer 20.
  • a metal layer 50 (second metal layer) made of a conductive metal material is formed over the entire surface of the substrate.
  • the metal layer 50 is not necessarily a single layer and may be a multilayer.
  • a seed metal such as Ti or Cu is formed as a first example, and then Cu is formed by electroplating.
  • a barrier metal such as Ti or Cu may be formed by physical vapor deposition such as sputtering or ion plating, and then Cu may be formed.
  • the metal layer 50 has a thickness sufficient to fill the opening 20 ⁇ / b> A of the passivation layer 20 and the opening of the first region 32 ⁇ / b> A of the photosensitive polyimide film 30.
  • a planarization process is performed, and the metal layer 50 is patterned at the same time.
  • the metal layer 50 reflects the unevenness of the base, and a step is formed on the surface thereof.
  • at least one of grinding, polishing, and cutting is used to remove the metal layer 50 and a part of the underlying polyimide film 30.
  • Grinding is “shaving the substance” with a grindstone.
  • Polishing is “polishing material” with abrasive grains.
  • Cutting is “cutting out the substance” with a sharp blade or the like.
  • CMP Chemical Mechanical Polishing
  • CMP Chemical Mechanical Polishing
  • the cutting is performed by using the side surfaces of the polyimide film 30 and the metal layer 50 as viewpoints (for example, from left to right).
  • a cutting blade (bit (beitel)) that scans the main surface of the substrate 12 in the horizontal direction. or a cutting tool).
  • bit Gibtel
  • the cutting blade is positioned on the surface K1, and the polyimide film 30 and the metal layer 50 above it are removed. Therefore, the height of the cutting blade is kept constant throughout the cutting process.
  • the cutting blade is positioned on the surface K1, and the polyimide film 30 and the metal layer 50 above it are cut.
  • the reference point of the height h1 is not limited to the main surface of the substrate 12, but may be an underline (back surface) of the silicon substrate.
  • “grinding” and “polishing” are performed, for example, by rotating a grindstone in which abrasive grains are hardened with a binder to “shave” or “shave” the workpiece. Accordingly, the height of the grindstone varies over the grinding process.
  • the metal layer 50 and the polyimide film 30 are polished from the main surface of the substrate 12 to the surface K1 reaching a certain height h1. In this way, even if a similar workpiece is finally completed, the principles of movement and cutting of the cutting blade and the grindstone, which are jigs, and the wear principle of the jigs are completely different.
  • the film 30 (second insulating material, first insulating layer) is not limited to the polyimide material, and for example, phenol resin, unsaturated polyester resin, melamine resin, or urea.
  • a material mainly composed of a resin is preferable.
  • the cause of wear of the cutting blade is firstly the hardness of the material to be cut, and secondly, the stickiness of the material (that is, the magnitude of elastic elongation).
  • the cutting blade cuts a sticky material (workpiece)
  • the cutting blade drags an uncut material.
  • a material to be cut (workpiece) mainly composed of unsaturated polyester resin, melamine resin or urea resin in addition to phenol resin is useful.
  • Cutting with a cutting blade does not cause plastic deformation due to local heat generation during cutting, and in order to improve the sharpness of the cutting blade, the film 30 has an appropriate elastic modulus, a small distortion with respect to a limit stress, and a strength comparison. This is because a low resin is considered good.
  • FIG. 24 and FIG. 25 show the YY line cross section of FIG. 1 as an example of each preferred embodiment for cutting.
  • the phenolic resin 460 is exposed using a grating mask (halftone mask) 40. Thereafter, a groove 462 (which corresponds to the opening 32) corresponding to the phenol resin 460 is formed in the development process.
  • the cross section of the first resin 460 (phenol resin 460) adjacent to the groove 462 is a rectangle substantially perpendicular to the surface of the substrate 450.
  • the metal layer 50 (second metal layer) is formed as a multi-layered two-layer metal layer (the first metal 470 having relatively high hardness and the relative hardness. Second metal 480) having a low thickness was deposited by physical vapor deposition. As a result, the film formation state shown in FIG. 24 is obtained.
  • the first metal 470 may be Ti, Cr, Ta, or Pd, and the second metal 480 may be Cu or Al. As can be seen from these materials, there is a difference in hardness between the first metal 470 used as a barrier metal and the second metal 480 used as a wiring metal.
  • the byte 480 in FIG. 24 is installed in the same manner as in FIG.
  • the first metal 470 formed on the side surface (side wall of the first resin 460) of the groove 462 in FIG. 24 is not formed, that is, the height corresponds to a place where the thickness is zero.
  • the cutting blade 490 is installed at the height H0 to cut the first resin 460 and the second metal 480. As a result, the intermediate shown in FIG. 3 (H) is obtained.
  • a first metal 470 having a relatively high hardness is formed from the upper surface of the first resin 460 to the upper part of the side surface of the groove 462.
  • the thickness of the first metal 470 formed on the side surface of the first resin 460 gradually decreases and eventually becomes zero.
  • a second metal 480 is formed on the first metal 470 formed on the bottom of the groove 462, the upper surface of the first resin 460, and the upper part of the side surface of the groove 462.
  • the second metal 480 may be formed to fill the groove 462 like the metal layer 50 in FIG. Note that the thickness of the first metal 470 formed on the upper surface of the first resin 460 and the thickness of the first metal 470 formed on the bottom of the groove 462 are substantially the same.
  • the cutting feature is that a cutting blade 490 is installed along a cutting line having a height H0 corresponding to a place where the thickness of the first metal 470 is not formed and the thickness is zero.
  • the cutting is performed by scanning the cutting blade 490 along the line. Therefore, the cutting blade 490 cuts only the two types of the first resin 460 that is the softest and the second metal 480 that is relatively harder than the first metal 470.
  • the thickness of the second metal 480 is arbitrary and is not directly related to the installation height H of the cutting blade 490.
  • the cutting blade 490 may cut only the first resin 460 on the cutting line having the height H0.
  • the cutting line having the height H1 may be the surface of the second metal 480 formed in the groove 462.
  • softest means the softest material among a plurality of materials to be cut.
  • the first metal 470 having a relatively high hardness is also formed on the side surface of the groove 462. Therefore, three types of materials including the first metal 470 are cut. Compared with such a case, in the present embodiment, the degree of wear of the cutting blade 490 is the smallest, and the life of the cutting blade 490 can be maximized.
  • the cutting may be performed aiming at the height.
  • the film thickness T1 of the first metal 470 is the same as that of the same first metal 470 formed on the upper surface of the first resin 460. It is thinner than the thickness T2 (see the enlarged view of region B in FIG. 19). You may cut with this cutting line of height H1.
  • the cutting blade 490 cuts three types of the first metal 470, the second metal 480, and the first resin 460, but the film thickness T1 of the first metal 470 is It is small enough to satisfy the above conditions. Compared with the case of cutting at a position higher than the height H1, the degree of wear of the cutting blade 490 is small, and the life of the cutting blade 490 can be extended.
  • Patent Document 4 is compared with one embodiment of the present invention as a comparative example.
  • the technique of Patent Document 4 discloses that the cutting blade is brought into contact with an arbitrary position on the side wall of the groove and is cut in the X direction, there is no disclosure about the hardness of the metal and the deterioration (wear) of the cutting blade.
  • the height of the cutting blade from the viewpoint of suppressing the deterioration of the cutting blade has not been studied, and there is no disclosure or suggestion.
  • the present invention it is possible to suppress the wear of the cutting blade and to improve the cutting performance by strictly defining the relationship between the set height of the cutting blade and the first metal 470. Has an effect. Furthermore, according to the present invention, by precisely defining the relationship between the material of the first resin 460 as electrical insulation described later and the cutting blade, it is possible to suppress cutting blade wear and improve cutting performance. Has a noticeable effect.
  • the present invention is to cut the first metal 470 as much as possible by cutting the first metal 470 so that the thickness of the first metal 470 becomes thinner or zero. This is one feature of each of the embodiments.
  • the physical constant and the wear of the cutting blade 490 will be considered.
  • FIG. 26 is a table showing physical properties of various resins and metals preferable for one embodiment of the present invention using a cutting blade.
  • FIG. 26 includes a phenol resin as a representative material that can be used as the first resin 460. Further, Ti is included as a representative metal that can be used as the first metal 470, and Cu or Al is included as a representative metal that can be used as the second metal 480.
  • Polyimide resin is a comparative example of phenol resin.
  • the material to be cut When cutting with the cutting blade 490, the material to be cut receives resistance to the cutting blade 490, and the cause of the wear of the cutting blade 490 is firstly the hardness of the material to be cut, and secondly, the material There is stickiness (that is, the size of elastic elongation). This is because when the cutting blade 490 cuts a sticky material, the cutting blade 490 drags an uncut material. Ti is a material that wears the cutting blade 490 in particular because of its high hardness and stickiness.
  • a height corresponding to a place where the first metal 470 having a high hardness represented by Ti is not formed or where the thickness is thin is cut. To do. Thereby, the cutting amount of the first metal 470 was suppressed. Therefore, the wear of the cutting blade 490 can be suppressed, and its life can be greatly extended.
  • phenolic resins generally have many network-forming groups such as functional alkyl groups and hydroxyl groups necessary for polymer construction, and have a dense three-dimensional structure compared to network-forming groups such as polyimide imide groups. Therefore, the elastic modulus is relatively high, the hardness is high, and the plastic deformation (craze deformation) range is small.
  • the phenolic resin is mainly composed of an annular structure, so that it is easy to perform cutting work without causing problems such as a cutting object adhering to the cutting blade and deterioration in processing performance. Thus, the problem in processing is eliminated by reducing the difference in characteristics from the metal on cutting.
  • the first resin 460 may contain an unsaturated polyester resin, melamine resin, or urea resin as a main component in addition to the phenol resin. This is because cutting with a cutting blade is preferably a thermosetting resin that does not cause plastic deformation due to local heat generation during cutting. Moreover, in order to improve the sharpness of the cutting blade, the first resin 460 is considered to be a resin having an appropriate elastic modulus, a small distortion with respect to a limit stress, and a relatively low strength. It is preferable that at least the range of plastic deformation leading to fracture of the first resin is smaller than the range of plastic deformation of polyimide.
  • the tensile strength of the first resin is preferably smaller than that of polyimide. As a specific numerical value, it is preferable that the first resin has less than 10% of strain to reach rupture with respect to stress. In addition, the tensile strength of the first resin (tensile strength) is preferably 80 MPa or less.
  • FIG. 27 is a schematic diagram showing an example of craze generated in a resin (polyimide resin or the like) that is not suitable as the first resin 460 in FIG. 24 (one embodiment of the present invention using a cutting blade).
  • Craze means a state in which two-dimensional chains of two-dimensional entangled atomic chains are aligned and difficult to break. As shown in FIG. 27, when a force F is applied when trying to open a plastic bag, the organic bulk part 492 and the part that expands and becomes cloudy separates into a craze 494, which is a phenomenon of extremely strong resistance. Craze 494 that appears cloudy includes fibrils 496 that are microfibers and voids 498 that are voids.
  • FIG. 28 is a graph showing stress-strain curves of various resins.
  • the first resin 460 a resin having a strain with respect to stress of several percent or less is preferable, and the resin is a material that hardly causes craze and has little entanglement with the cutting blade.
  • the above-mentioned phenol resin, unsaturated polyester resin, melamine resin, or urea resin all satisfy such conditions. This is because it contains a ⁇ -type cyclic group that is hard and has little elongation.
  • the polyimide resin is a resin having a high strength in which the strain with respect to the stress reaches several tens of percent, and the crazing shown in FIG. 27 is likely to occur. Accordingly, as the material of the first resin 460, polyimide resin is inappropriate because there is a possibility that the cutting performance by the cutting blade 490 may be deteriorated.
  • the photosensitive polyimide film 30 is suitable as an insulating material in the first embodiment of the present invention using techniques of “grinding” and “polishing” other than cutting.
  • phenolic resins There are two types of phenolic resins: phenolic and formaldehyde mixed, polymerized by acid catalyst, polymerized novolak type, and resin called resol type, polymerized by alkali catalyst.
  • the former is thermoplastic as it is, and is liquid in the low molecular state.
  • hexamethylenetetramine or the like is mixed with this as 1 to 20% by weight of a curing agent, it undergoes condensation polymerization and becomes a thermosetting resin. Since the latter itself has a self-reactive active group, it is cured by heating.
  • the novolak type that allows easy control of the thermosetting polymerization reaction is mainly used.
  • What is referred to as a permanent resist in the present application is a novolak type, and when processed as a photoresist, 100% of the novolak type phenol resin is occupied by this component.
  • macromonomers having various strengths such as fillers such as cellulose, pigments (particularly black pigments), fillers (silica glass fine particles), etc., are used as the total amount of additives. About 0.1 to 50% by weight may be mixed.
  • the phenolic resin is fragile as an electronic material because it has little elongation and high strength, as can be seen from the stress-strain curve in FIG.
  • an epoxy-modified phenolic resin modified part, that is, the epoxy properties become stronger depending on the mixing percentage
  • a polyvinyl acetal-modified phenolic resin due to poor heat resistance can do.
  • Modifications have been made to improve various properties, such as using a nitrile rubber-modified phenol resin to improve thermal cycle reliability, or using a rosin-modified phenol resin to improve printability.
  • the mixing ratio of the modified resin is 1% to 50% by weight. Therefore, in the present text, “having a phenol resin as a main component” is defined as 50% by weight or more of a phenol resin.
  • Melamine resin is synthesized by polymerization condensation reaction of methylolmelamine obtained by condensation reaction of melamine and formaldehyde, but has a higher impact strength than urea resin because it forms a nitrogen cyclic group.
  • reinforced plastics are made by impregnating methylol melamine into fibers and the like, but as an electronic component, 5 to 40% by weight of a cellulose additive is added. Of course, it can withstand use as 100% resin. Modification with epoxy or urea resin can be done freely by adding appropriate amounts of epoxy monomer and urea during synthesis. Further, by mixing, a resin having intermediate properties can be obtained.
  • “having melamine resin as a main component” is defined herein to be 50% by weight or more.
  • Unsaturated polyester resin is a thermosetting resin made by condensation polymerization of unsaturated polyesters such as maleic anhydride and isophthalic acid and polyhydric alcohols such as ethylene glycol, both maleic anhydride and styrene are cyclic groups, It is characterized by high mechanical strength. Therefore, 100% resin can also be used. In particular, it is excellent for use as a reinforced plastic impregnated into fibers.
  • a myriad of different types of ester compounds can be made, but in order to maintain the smoothness of the surface as a modified resin with different types of resins, modification by mixing pentadiene during synthesis, mixing with compatible acrylic urethane, and yellowing due to light Modifications to prevent alteration are considered.
  • “based on unsaturated polyester resin” means 50% by weight or more. Define.
  • Urea resin (urea resin) is synthesized by condensation reaction of urea and formaldehyde, and because it is a linear network without cyclic compounds, fracture toughness decreases. Therefore, it is rare to use 100% resin, and in order to increase fracture toughness, it is considered that 0.5 to 30% by weight of a glycine compound having a bisphenol A skeleton, which is a cyclic compound, is added and modified during synthesis. . Cellulose is often used as a filler, and the mechanical properties can be adjusted by adding 5 to 40% by weight. Good consistency with melamine resin and phenol resin, and by adding melamine and phenol during the reaction, intermediate properties between each other are born. In the present text, “based on urea resin” is defined as 50% by weight or more.
  • FIG. 29 is a schematic view of the resin and metal after cutting at the height H0 in FIG. 24 as seen from the cross section.
  • FIG. 29A shows a case where the material of FIG. 24 is used as it is, and the first resin 460 (phenol resin or the like) and the second metal 480 (Cu or Al) are alternately cut.
  • FIG. 29B shows a case where the first resin 460 of FIG. 19 is temporarily changed to a polyimide resin 461.
  • cutting is performed without any problem as shown in FIG. Since the first resin 460 is hard and has a low elongation property, when the first resin 460 is cut, a gap is not easily generated between the adjacent second metals 480 that are cut together. Further, the first resin 460 is hardly peeled from the substrate 450. Therefore, there is a remarkable effect that the metal wiring pattern forming the wiring is prevented from being distorted.
  • the wiring / resin pattern may be distorted.
  • metal dropout, resin dropout, internal voids, and the like are likely to occur, and there is a possibility that wiring breaks and wiring shorts may occur.
  • the adhesion area between the resin and the metal, the metal and the substrate, and the resin and the substrate is originally small. Peeling 467, 469) is likely to occur. Therefore, it is important to use the first resin 460 that is easy to cut as shown in FIG.
  • the substrate 450 has a passivation film 444 on at least a part of its surface, and the passivation film 444 is in contact with the first resin 460.
  • the passivation film 444 and the first resin 460 are in contact with each other, the adhesion (adhesive force) of the first resin 460 is improved, and the cutting performance is further improved.
  • the passivation film 444 of this embodiment is mainly composed of polyimide resin.
  • Any of a phenol resin, an unsaturated polyester resin, a melamine resin, and a urea resin used as the first resin 460 in contact with the passivation film 444 is a photosensitive resin that adheres to a polyimide resin, and has a strong adhesive force and is easy to cut. Has performance. This is because the material of the first resin 460 has a relatively large number of carboxyl groups, hydroxyl groups, and imide groups that are reactive with the carboxyl groups and imide groups, which are reactive groups of the polyimide resin that is the material of the passivation film 444. This is because it is included in the main chain and sub-chain.
  • the description returns to the description of FIGS. 2 and 3 (the manufacturing process of the WLP according to the first embodiment).
  • the resin 30 and the metal layer 50 are ground or polished from the upper surface to the surface K1 reaching the height h1.
  • the resin 30 and the metal layer 50 are cut from the side surface along the surface K1 by the cutting blade installed at the height h1.
  • FIG. 3 (H) shows a state after flattening.
  • the surface 32 of the polyimide film 30 and the surface of the metal layer 50 have substantially the same height, and a metal pattern (metal wiring) 52 is formed in the opening 32 of the polyimide film 30.
  • the metal pattern 52 is a second metal layer.
  • the metal pattern 52 has a shape corresponding to the opening 32 (FIG. 2F) of the polyimide film 30, and therefore the metal pattern 52 is chipped through the opening 20A of the passivation 20 (FIG. 2C).
  • a solder resist 60 is applied to the entire surface of the substrate, and exposure and development are performed by, for example, a known photolithography process. As shown in FIG. An opening 60A of the solder resist 60 is formed so as to expose the second region 52B having a flat surface. Note that the solder resist may form the opening 60A by a laser manufacturing method instead of the photolithography manufacturing method. Next, as shown in FIG. 3K, solder balls 70 (external terminals 70) are formed through the openings 60A. Thus, the WLP process is performed, and thereafter, the substrate is diced to obtain individual CSP semiconductor chips.
  • Solder resist materials include, for example, novolak type cyanate resins, bisphenol A type cyanate resins, bisphenol E type cyanate resins, cyanate resins such as bisphenol type cyanate resins such as tetramethylbisphenol F type cyanate resin; phenol novolac resins, cresol novolac resins, Phenolic resins such as bisphenol A novolac resins, novolac type phenolic resins, unmodified resole phenolic resins, oil-modified resol phenolic resins modified with tung oil, linseed oil, walnut oil, etc .; bisphenol A type epoxy resins Bisphenol F type epoxy resin, bisphenol S type epoxy resin, bisphenol E type epoxy resin, bisphenol M type epoxy resin, bisphenol P type epoxy resin Bisphenol type epoxy resins such as xyphenol resin and bisphenol Z type epoxy resin; Novolak type epoxy resins such as phenol novolac type epoxy resin and cresol novolak type epoxy resin; Biphenyl type epoxy resin,
  • Resin having a triazine ring unsaturated polyester resin, bismaleimide resin, polyurethane resin, diallyl phthalate resin, silicone resin, benzoxazine Resins having, polyimide resin, polyamideimide resin, benzocyclobutene resin, and the like. In the present invention, one of these may be used alone, or two or more may be used in combination. Moreover, you may use together what has different weight average molecular weights of the same kind of resin. Furthermore, you may use together the said 1 type, or 2 or more types, and those prepolymers.
  • the content of the thermosetting resin is not particularly limited, but is preferably 50 to 100% by weight based on the entire resin composition.
  • the opening 32 leading to the opening 20A is formed in the upper photosensitive polyimide film 30 of the passivation layer 20, but the opening 20A and the opening 32 are continuously formed. You may make it form in.
  • the process is shown in FIG.
  • chip takeout electrodes 18 and wirings 16 are formed on the main surface 12A of the substrate 12, and then a passivation layer 20 is formed on the entire surface of the substrate as shown in FIG. 4B.
  • a photosensitive polyimide film 30 is applied to the entire surface of the substrate so as to cover the passivation layer 20, and then a grating mask 40 is used as shown in FIG. 4D.
  • the grating mask 40 includes a region that transmits the light amount L1, a region that transmits a light amount L2 smaller than the light amount L1, and a light shielding region 40A.
  • openings 32 having shapes corresponding to the light amounts L1 and L2 are formed in the photosensitive polyimide film 30, and the openings
  • the part 32 includes a first region 32A having a depth reaching the passivation layer 20, and a second region having a depth shallower than the first region 32A and extending laterally at a constant depth. And a region 32B.
  • the photosensitive polyimide film 30 is used, and the passivation layer 20 exposed by the first region 32A is removed by etching, whereby the opening 20A of the chip extraction electrode 18 is formed.
  • the WLP process of the second embodiment of the present invention will be described.
  • the solder ball 70 is formed by single-layer wiring
  • the solder ball 70 is formed by two-layer wiring
  • the single-layer wiring includes, for example, two metal layers that do not sandwich an insulating layer.
  • the barrier metal layer and the copper layer disclosed in the first embodiment are two metal layers sandwiching an insulating layer.
  • Differences from the first embodiment will be mainly described, and the first embodiment will be applied mutatis mutandis.
  • the planarized metal pattern 52 and the polyimide film 30 are then formed as shown in FIG.
  • a photosensitive polyimide film 80 is applied to the entire surface of the substrate so as to cover it. Both the polyimide film 30 and the polyimide film 80 are insulating layers.
  • the photosensitive polyimide film 80 is exposed using the grating mask 42.
  • the grating mask 42 includes a region that transmits the light amount L1, a region that transmits a light amount L2 less than the light amount L1, and a light shielding region 42A.
  • the light amount L1 is a value sufficient to remove all of the photosensitive polyimide film 80.
  • the light quantity L2 is a value that leaves a predetermined film thickness on the photosensitive polyimide 80.
  • the opening 82 includes a first region 82A having a depth reaching the underlying metal pattern 52, and a second region having a depth shallower than that of the first region 82A and extending laterally at a certain depth. 82B.
  • a metal layer 90 is formed on the front surface of the substrate so as to cover the polyimide film 80.
  • the metal layer 90 may be either a single layer or a multilayer as in the first embodiment.
  • a planarization process is performed. The flattening process is performed using at least one of grinding, polishing, and cutting, as in the first embodiment.
  • a part of the metal layer 90 and the polyimide film 80 is removed by performing a planarization process on a surface K2 having a height h2 from the main surface of the substrate 12.
  • the film 80 is not limited to the polyimide material as in the first embodiment, and for example, a material mainly composed of a phenol resin, an unsaturated polyester resin, a melamine resin, or a urea resin is preferable. .
  • a metal pattern 92 having a surface substantially the same as the surface of the polyimide film 80 is formed.
  • the metal pattern 92 has first and second regions 92A and 92B corresponding to the first and second regions 82A and 82B of the opening 82, respectively.
  • solder resist 62 is applied, and an opening is formed so as to expose the second region 92B of the metal pattern 92 by a photolithography process, as shown in FIG. 6G.
  • a solder ball 70 electrically connected to the metal pattern 92 is formed.
  • FIG. 7 compares the manufacturing method according to this embodiment related to the formation of the WLP wiring and the conventional manufacturing method.
  • the method for forming the external terminals is omitted.
  • a photosensitive resin is applied (S1), exposed using a predetermined mask pattern (S2), and the photosensitive resin is developed (S3).
  • a seed metal such as Ti is formed by sputtering (S4), and then a photolithographic process is again performed by applying a photosensitive resist (S5), exposure (S6), and development (S7), and by electroplating, Cu or the like It includes steps of forming metal wiring (S8), stripping the resist (S9), and etching the seed metal (S10).
  • the photosensitive polyimide resin is applied from the state shown in FIG. 2C (S101: FIG. 2D), and the grating mask is applied. Exposure is performed (S102: FIG. 2E), development is performed (S103: FIG. 2F), and metal wiring is formed by physical vapor deposition or electrolytic plating (S104: FIG. 3G).
  • the method includes surface grinding (S105: FIG. 3H), and the number of steps can be significantly reduced as compared with the conventional manufacturing method.
  • the surface grinding (S105) may be surface cutting.
  • the process of removing the photosensitive polyimide resin is unnecessary, and this also contributes to the reduction of the number of processes.
  • the CSP obtained by the manufacturing method of the above embodiment is a BGA in which solder balls are formed as external terminals.
  • the external terminals may be LGA having a planar shape.
  • the external terminal may be a bonding wire 71 using a bonder as shown in FIG.
  • the photosensitive resin exposed by the grating mask may be either a positive type or a negative type, and the material is not limited to the polyimide type.
  • the grating mask is not limited in its form as long as the amount of light transmission can be adjusted, and may be a halftone mask, for example.
  • FIG. 8A shows a schematic plan view of a fan-in type CSP in which external terminals 110A to 110D are formed on the surface of the CSP by WLP.
  • the fan-in type CSP 100 has a plurality of external terminals 110 (110A to 110D) formed on the surface inside the outer shape 100A of the semiconductor chip.
  • the external terminal 110A is connected to a chip pad (chip take-out electrode) 130A formed on the main surface of the substrate via a first layer wiring 120A above the passivation layer, and the external terminal 110C is connected to the first layer wiring 120C. It is connected to a chip pad (chip take-out electrode) 130C formed on the main surface of the substrate.
  • the external terminal 110B is connected to a chip pad (chip take-out electrode) 130B on the main surface of the substrate via a second layer wiring 120B above the passivation layer and above the first layer, and the external terminal 110D has two layers.
  • the wiring 120D is connected to a chip pad (chip extraction electrode) 130D. Since the wirings 120A and 120C and the wirings 120B and 120D intersect, the wiring layer above the passivation layer needs to have at least a two-layer structure.
  • FIG. 8B is a plan view when the wirings 120A and 120C in the first layer are finished, and FIG. 8C shows a cross section taken along line XX.
  • Chip pads 130A to 130D are formed on the main surface of the substrate 140, and regions other than the chip pads 130A to 130D are covered with a passivation layer 150.
  • the wiring 120A of the first layer is patterned so that one end thereof is connected to the chip pad 130A and the other end extends in a diagonal direction, and the wiring 120C has one end connected to the chip. It is connected to the pad 130C and patterned so that the other end extends in a diagonal direction.
  • the first contact pads 122B and 122D are simultaneously formed on the chip pads 130B and 130D.
  • the first-layer wirings 120A, 120C, 122B, and 122D may be formed using the steps up to the first embodiment (FIGS. 2A to 3H), or Alternatively, it may be formed by using the conventional method shown in FIG.
  • the first-layer wiring is an example constituted by a stack of a seed metal and a metal electroplated thereon. In other words, the manufacturing method of this embodiment is used for forming at least the second-layer wiring.
  • the second layer wiring is formed.
  • the second embodiment described above (FIGS. 5 to 6) is cited.
  • a photosensitive insulating resin 160 is applied to the entire surface of the substrate.
  • exposure is performed using a grating mask.
  • the conductive insulating resin 160 is exposed.
  • the exposed areas 160A and 160B are indicated by solid lines.
  • the region of the photosensitive insulating resin 160 aligned with the first contact pads 122B and 122D is exposed with a relatively large amount of light so as to form openings to the contact pads 122B and 122D, and the second layer wiring 120B ( 8A) and 120D (FIG.
  • the two regions 160B aligned with the respective ends of the first-layer wirings 120A and 120C are also exposed with a relatively large amount of light so as to form openings to the first-layer wirings 120A and 120C.
  • the openings 162 and 164 having a film thickness corresponding to the light amount are formed.
  • the opening 162 includes a first region 162A having a depth reaching the contact pads 122B and 122D, and a second region having a depth shallower than that of the first region 162A and extending diagonally at a constant depth. 162B.
  • the opening 164 has substantially the same depth as the depth of the first region 162A reaching the first-layer wirings 120A and 120C.
  • a second metal layer 170 is formed on the entire surface of the substrate including the opening 162.
  • the metal layer 170 includes a seed metal such as Ti or Cu and a Cu metal electrolytically plated thereon.
  • the surface is flattened.
  • the flattening process is performed using at least one of grinding, polishing, and cutting as in the first and second embodiments.
  • the metal layer 170 and the photosensitive insulating resin 160 existing at a certain height or more from the main surface of the substrate are removed.
  • patterned second layer wirings 120 ⁇ / b> B and 120 ⁇ / b> D are formed in the opening 162 of the photosensitive insulating resin 160.
  • the wirings 120B and 120D include a shape obtained by transferring the shape of the opening 162, and are connected to the contact pads 122B and 122D in a region corresponding to the first region 162A ((FIG.
  • the wirings 120B and 120D extend with a substantially constant film thickness in a region corresponding to the second region 162B.
  • the opening 164 FIG. 10A
  • the external terminals 110A110C are electrically connected to the first wirings 120A and 120C and the chip pads 130A and 130C through the second metal layer 170 of the corresponding opening 164.
  • the external terminals 110B and 110D are electrically connected to the corresponding second-layer wirings 120B and 120D and chip pads 130B and 130D, respectively.
  • the fan-out type CSP has a semiconductor chip and an insulating resin that has a larger outer shape than the semiconductor chip and supports the semiconductor chip, and the external terminals are formed on the insulating resin beyond the outer shape of the semiconductor chip. Is. This type can form a larger number of external terminals than the fan-in type.
  • FIG. 12 shows an example of manufacturing a fan-out type WLP substrate.
  • the semiconductor wafer W on which the passivation layer 244 is formed is diced using a grindstone S or a laser, separated into individual semiconductor chips, and then as shown in FIG. 12B.
  • the semiconductor chips 200 are aligned on the chip fixing tape 210.
  • An adhesive layer 210A is formed on the surface of the chip fixing tape 210, and the main surface of the semiconductor chip 200 is fixed by the adhesive layer 210A.
  • the main surface of the semiconductor chip 200 is a surface on which the circuit element 14, the chip extraction electrode 18, and the wiring 16 (FIG. 2) are formed.
  • FIG. 2 shows an example of manufacturing a fan-out type WLP substrate.
  • each semiconductor chip 200 on the chip fixing tape 210 is sealed with an insulating resin 220, as shown in FIG. Then, the chip fixing tape 210 is peeled off together with the adhesive layer 210A, whereby the fan-out WLP substrate 230 is completed.
  • FIG. 12E is an enlarged cross-sectional view of one semiconductor chip 200 included in the fan-out WLP substrate 230.
  • the top and bottom are shown opposite to the drawing of FIG.
  • the side surface and the back surface of the substrate 240 indicated by the semiconductor chip 200 are sealed with the insulating resin 220, and the main surface is exposed from the insulating resin 220.
  • a chip pad (chip extraction electrode) 242 is formed on the main surface of the substrate 240, and a region excluding the chip pad is protected by the passivation layer 244.
  • the process when the fan-out WLP substrate is used in the manufacturing method according to the present embodiment is performed by using the fan-in WLP substrate shown in FIGS. 8 to 11 except that the external terminals are formed on the insulating resin 220. This is substantially the same as the process used. Therefore, the same reference numerals as those in FIGS. 8 to 11 are used for explanation.
  • FIG. 13A shows a schematic plan view of a fan-out type CSP in which external terminals 110A to 110D are formed on the surface of the CSP.
  • the external terminals 110A to 110D are formed in a region of the insulating resin 220 existing outside the outer shape 100A of the semiconductor chip.
  • the external terminals 110A and 110C are respectively connected to chip pads (chip take-out electrodes) 130A and 130B formed on the main surface of the substrate via wirings 120A and 120C in the first layer above the passivation layer.
  • 110D is connected to chip pads 130B and 130D formed on the main surface of the substrate via wirings 120B and 120D in the second layer above the passivation layer and above the first layer, respectively.
  • FIGS. 13B and 13C illustrate a case where the first wirings 120A and 120C and the contact pads 122B and 122D are formed on the main surface of the substrate 140 (240 in FIG. 12E) and the insulating resin 220.
  • the state where the photosensitive insulating resin 160 is applied is shown.
  • FIG. 13C shows a cross section taken along line XX shown in FIG.
  • the photosensitive insulating resin 160 is exposed using a grating mask.
  • the exposure region is a range indicated by a solid line of a region 160A straddling the outer shape 100A of the semiconductor chip and a region 160B that is the outer periphery of the outer shape 100A of the semiconductor chip.
  • FIGS. 13B illustrate a case where the first wirings 120A and 120C and the contact pads 122B and 122D are formed on the main surface of the substrate 140 (240 in FIG. 12E) and the insulating resin 220.
  • FIG. 13C shows a cross section taken along line XX shown
  • the photosensitive insulating resin 160 is developed to form openings 162 and 164 corresponding to the regions 160A and 160B.
  • the opening 162 has a first region 162A having a depth reaching the contact pads 122B and 122D and a depth shallower than that of the first region 162A, and a predetermined thickness of the photosensitive insulating resin 160 remains. 2 regions 162B.
  • the opening 164 has a depth substantially the same as the depth of the first region 162A that reaches the ends of the first-layer wirings 120A and 120C.
  • a second metal layer 170 by seed metal and electrolytic plating is formed on the entire surface of the substrate, and then FIGS.
  • the metal layer and the photosensitive insulating resin 160 are planarized, and the second-layer wirings 120B and 120D are patterned.
  • the metal layer 170 physical vapor deposition may be used as in the first and second embodiments.
  • the flattening process is performed using at least one of grinding, polishing, and cutting as in the first and second embodiments.
  • the external terminals 110A to 110D are formed on the main surface of the insulating resin 220.
  • FIG. 16 is a diagram for explaining a manufacturing method according to the third embodiment of the present invention.
  • a photosensitive insulating resin 310 is applied on a base layer 300 such as a substrate or a wiring layer used for WLP or the like.
  • the base layer 300 includes the silicon substrate 12 illustrated in FIG. 2C, the wiring layer (the chip extraction electrode 18 and the wiring 16), and the passivation layer 20.
  • the photosensitive insulating resin 310 is exposed using a grating mask 320.
  • the grating mask 320 includes a plurality of transmission regions having different light transmittances.
  • a plurality of regions having respective light transmittances of (0), (0.3), (0.5), (0.7), and (1) are formed on the grating mask 320.
  • the light transmittance of (0) means that the photosensitive insulating resin 310 is not substantially exposed to light.
  • FIG. 16C a plurality of openings 312 having different thicknesses of the insulating resin are formed in the photosensitive insulating resin 310 in accordance with the respective exposure amounts. .
  • FIG. 16C a plurality of openings 312 having different thicknesses of the insulating resin are formed in the photosensitive insulating resin 310 in accordance with the respective exposure amounts. .
  • a metal layer 330 is formed so as to cover the photosensitive insulating resin 320, and thereafter, a planarization process is performed on a surface K1 having a height h1 from the main surface of the base layer 300.
  • a plurality of metal wirings 332 having different film thicknesses as shown in FIG.
  • the wiring resistance value of each of the plurality of metal wirings 332 can be adjusted. This is because the wiring resistance value depends on the cross-sectional area if the line width is the same.
  • the film thickness of the metal wiring 332 is appropriately selected according to the environment to be used (electric characteristic specifications and reliability specifications for which each of the plurality of metal wirings 332 is required).
  • the grating mask 320 can be replaced with a halftone mask.
  • the formation of the metal layer 330 is performed using physical vapor deposition or electrolytic plating as in the first and second embodiments.
  • the flattening process is performed using at least one of grinding, polishing, and cutting.
  • As the material of the insulating resin 310 all materials disclosed in the first and second embodiments can be applied.
  • FIG. 17 is a diagram for explaining a modification of the third embodiment of the present invention.
  • a photosensitive insulating resin 310A is applied on a base layer 300 such as a substrate or a wiring layer used for WLP or the like.
  • the photosensitive insulating resin 310A is exposed using the mask 320A.
  • the grating mask 320A is continuously formed with transmissive regions having different light transmittances.
  • the light transmittance is (1), (0.7), (0.5), (0.3) in the right direction from the viewpoint of the region where the photosensitive insulating resin 310 is substantially exposed. Are arranged in such a manner that the light transmittance is increased (or decreased) in one direction.
  • the photosensitive insulating resin 310A is developed, as shown in FIG. 17C, the photosensitive insulating resin 310A is formed with an opening 314 whose film thickness changes stepwise.
  • a metal layer 330 is formed as shown in FIG. 17D, and planarization is performed on the surface K1 having a height h1 from the main surface of the base layer 300, as shown in FIG.
  • Metal wirings 332A having different film thicknesses can be formed in the openings 314.
  • the metal layer 332A For the formation of the metal layer 332A, physical vapor deposition may be used as in the first and second embodiments.
  • the flattening process is performed using at least one of grinding, polishing, and cutting as in the first and second embodiments.
  • a solder resist is formed, and then, for example, it is formed in the vicinity of reference numeral 332A described in FIG. 17E so that the external terminal is connected to the metal layer 332A.
  • the light transmittance of the grating mask 320A changes linearly (analog value; analog method)
  • the remaining film thickness of the opening 314 is linear (slope) as shown in FIG.
  • the film thickness of the corresponding metal wiring 332A can be changed more linearly.
  • the formation height of the metal layer 332A is controlled to be lower than the height h1, the thickness of the metal wiring 332A can be made constant while being linear.
  • FIG. 18A corresponds to FIG. 17F, and shows a three-dimensional view of the metal wiring 332B obtained when the photosensitive insulating resin 310A is exposed using the grating mask 320A as in the third embodiment. It is represented by a perspective view.
  • the opening 352 formed in the photosensitive insulating resin 350 is connected to the contact hole 352A reaching the conductive region 342 formed in the main surface of the base layer 340 and the contact hole 352A. If the groove 352B has a uniform depth when the groove 352B for forming the wiring is provided, a substantially perpendicular step is formed at the boundary with the contact hole 353A. In this case, as shown in FIG.
  • the metal wiring 360 is formed with a film thickness that follows the step at a right angle at a substantially right step corner portion.
  • the photosensitive insulating resin 350 such as polyimide shrinks its volume by baking, a stress P obtained by combining the stress Px in the X direction and the stress Py in the Y direction is generated in the corner portion 362 of the metal wiring 360. Therefore, from the viewpoint of reliability, “disconnection of the metal wiring 360 or destruction of the insulating resin 350 or deterioration of the adhesion between the metal wiring 360 and the insulating resin 350” related to the resultant force P must be examined.
  • the inclination of the corner portion is made gentle by providing an inclination to at least a part of the side surface (cross section) of the opening of the photosensitive insulating resin 310A as in this embodiment.
  • the stress P generated in the corner portion can be reduced.
  • the stress P can be reduced.
  • the step shape of FIG. 17 (E) and the slope shape of FIG. 17 (F), FIG. 18 (A) and FIG. 18 (D) are from the viewpoint of moisture resistance. Also improve the reliability.
  • an external terminal (not shown) is formed at the place where the reference numeral 332B in FIG. 17F is described, similarly to the external terminal 70 shown in FIG.
  • a solder resist is formed on the entire surface of the substrate other than the external terminals.
  • moisture enters from the boundary between the external terminal or the external terminal and the solder resist, and the chip take-out electrode (not shown; To the chip take-out electrode 18 shown in FIG. Finally, the chip takeout electrode is corroded.
  • the semiconductor device of the present application is generally connected with its external terminals facing the mother board on the ground side.
  • the external terminal 70 shown in FIG. 3K is in a state where the drawing is rotated 180 degrees. Therefore, the moisture must move in the direction opposite to the direction of gravity through the slope shape (FIG. 17F). In other words, the slope shape suppresses the movement of moisture to the chip extraction electrode.
  • the respective volumes of the metal wiring (metal layer 330) in the slope shape (FIG. 17F) and the metal wiring (metal layer 330) in the step shape (FIG. 17E) are the same as the metal in FIG.
  • the volume of the wiring 360 is larger. Therefore, disconnection of the metal wiring due to corrosion can be suppressed.
  • a fourth embodiment of the present invention will be described. Differences from the third embodiment will be mainly described, and the third embodiment will be applied mutatis mutandis to the substantially overlapping portions.
  • a plurality of conductive regions for example, the wiring 404 and the chip extraction electrode 402 included in the wiring layer are formed on the main surface of the base layer 400, and are photosensitive so as to cover them.
  • An insulating resin 410 is formed.
  • An opening 412 is formed in the photosensitive insulating resin 410 by adjusting the light transmittance of the grating mask.
  • the opening 412 has a first region 412A having a depth reaching the chip extraction electrode 402, a second region 412B having a depth smaller than the depth of the first region 412A, and a depth smaller than the second region 412B. And a third region 412C.
  • the third region 412C is formed at a position overlapping with the wiring 404. Then, as shown in FIG. 19B, when the metal wiring 420 is formed, the metal wiring 420 is electrically connected to the chip extraction electrode 402 and is relatively thick between the wiring 404. The film thickness of the insulating resin 410 remains. Therefore, the parasitic capacitance Cp between the metal wiring 420 and the wiring 404 can be reduced.
  • a fifth embodiment of the present invention will be described. Differences from the third and fourth embodiments will be mainly described, and the third embodiment will be applied mutatis mutandis to the overlapping portions.
  • a conductive region 502 (wiring 502) is formed on the main surface of the base layer 500, and a photosensitive insulating resin 510 is formed so as to cover it.
  • tapers having various shapes are formed on the side surface 512A of the opening 512 of the photosensitive insulating resin 510. be able to.
  • a positive taper is formed on the side surface 512A.
  • a metal layer is formed on the entire surface, and the surface is flattened to form a metal wiring 520 having a reverse taper (inverted triangle) corresponding to the normal taper of the insulating resin 510 as shown in FIG. Is done.
  • the capacitive coupling area facing the conductive region 502 is reduced, and the parasitic capacitance Cp is reduced.
  • the width of the metal wiring 520 is increased upward along the taper, the current density of the metal wiring 520 can be improved and the resistance of the wiring 502 can be reduced.
  • the taper can be applied in various shapes such as a triangle, a trapezoid, a semicircle, and a semi-elliptical shape. Further, by controlling the light transmittance of the grating mask in, for example, a matrix shape or an array shape so as to realize a checker pattern, the taper line segment is further uneven, that is, the surface of the insulating resin 510 is uneven (patternedpatternindented). Surface) is also useful.
  • the surface of the metal wiring 520 that is in surface contact with the insulating resin 510 has an uneven shape corresponding to the uneven shape of the insulating resin 510. Thereby, both adhesiveness improves and the path
  • the surface treatment of the insulating resin 510 can be formed into a concavo-convex shape by chemical treatment such as dry etching.
  • the transmissive region may be formed while repeating a slight increase and decrease in an analog or digital manner in the light transmittance direction from (1) to (0.3). . Further, a minute increase / decrease is developed in the transmissive region in the X and Y directions, respectively, thereby realizing a minute layout pattern having a height difference as shown in FIG. 17A, for example.
  • FIG. 17A shows a checker pattern 310B (protruding positive dod array pattern 310B) in slope-shaped insulating resin 310A.
  • the corresponding metal wiring 332A in the slope shape also has a lattice shape (not shown) corresponding to the checker pattern 310B.
  • the uneven shape of the tapered line segment can also be applied to the step-shaped line segment shown in FIG.
  • the light transmittance is changed from (1) to (0.3) in steps (every (1), every (0.7), (0.5). ), And every (0.3)), the transmission region may be formed while repeating a minute increase / decrease in an analog or digital manner. Further, in the transmission region for each step, a minute increase / decrease is developed in the X and Y directions, thereby realizing a layout pattern similar to FIG. 17A for each step.
  • the positive dod array pattern 310B on the surface of the insulating resin may be a negative dod array pattern.
  • the uneven shape may be a geometric pattern, that is, not limited to a checker pattern, and may be a stripe pattern, for example.
  • FIG. 21A is a diagram corresponding to FIG. 4C described in the first embodiment. Differences from the first to fifth embodiments will be mainly described, and the first to fifth embodiments will be applied mutatis mutandis to the substantially overlapping portions.
  • selected chip take-out electrodes on the main surface on the substrate 12 are commonly connected by a metal layer.
  • FIG. 21B a relatively large amount of light L1 is applied to the regions that are respectively aligned with the two chip extraction electrodes that are to be commonly wired, and a relatively small amount of light L2 is applied to the region where other metal wirings are patterned.
  • the grating mask 40 is configured to irradiate. In the example shown in the figure, the light quantity L1 is applied to the regions that are respectively aligned with the chip extraction electrodes on both sides.
  • the photosensitive polyimide film 30 is developed to form openings 32 corresponding to the light amounts L1 and L2.
  • the opening 32 has a first region 32A that exposes the passivation layer 20 at a position corresponding to each of the chip extraction electrodes on both sides, and a second region that has a depth smaller than the first region 32A and has a predetermined film thickness. And a region 32B. In this state, both ends of the second region 32B are sandwiched between the first regions 32A.
  • the passivation layer 20 is etched using the photosensitive polyimide film 30 as an etching mask. Therefore, a contact hole for exposing the chip take-out electrode is formed at each position matching the plurality of first regions 32A of the passivation layer 20.
  • the subsequent steps are the same as those in the first embodiment.
  • the metal layer 40 is formed on the entire surface of the substrate, and then the surface having a height h1 from the main surface of the substrate 12 is formed. A flattening process is performed at K1.
  • a patterned metal wiring 42A is formed in the opening of the photosensitive polyimide film 30 as shown in FIG. Therefore, the metal wiring 42A electrically connects the chip extraction electrodes on both sides.
  • a semiconductor chip may be provided with a plurality of ground terminals or power supply terminals. In such a case, the two first regions 32A can be interconnected together by the metal wiring 42A.
  • the external terminals are formed without using the “formation of the opening 60A by the patterning of the solder resist” shown in FIG. FIG. 22A corresponds to FIG. 2D of the first embodiment.
  • the grating mask 40 includes a light transmission region where the light transmission amount is L1> L2> L3. However, these light transmission regions are formed continuously.
  • an opening 36 as shown in FIG. 22C is formed.
  • the opening 36 includes a first region 36A having a depth reaching the chip extraction electrode, a second region 36B having a depth smaller than the first region 36A and having a predetermined film thickness, and a second region 36B. And a third region 36C having a predetermined film thickness that is shallower than the region 36B.
  • a solder resist 60 is applied so as to cover the metal layer 50.
  • a planarization process is performed on a surface K1 having a height h1 from the main surface of the substrate 12.
  • the height h1 is a height at which a part of the metal layer 50 on the third region 36C remains and is exposed.
  • solder balls 70 as external terminals are formed on the metal wiring 52.
  • a bonding wire 71 using a bonder may be used instead of the solder ball 70.
  • the exposed region of the metal wiring 52 is substantially equal to the connection area between the solder ball 70 or the bonding wire 71 and the metal wiring 52.
  • the mold resin 73 is further applied so as to seal the bonding wire 71.
  • the mold resin 73 also covers the solder resist 62 and the polyimide film 30 (first insulating layer).
  • Reference numeral 72 denotes a metal material, and a part thereof is exposed to the outside of the semiconductor device 600.
  • the metal material 72 is electrically connected to the bonding wire 71 and thus is electrically connected to the chip extraction electrode 18.
  • the seventh embodiment since it is not necessary to pattern the solder resist by a photolithography process, the number of processes by WLP can be further reduced, and the manufacturing cost can be reduced.
  • the number of processes can be reduced, and reliability can be improved with respect to the insulating layer and the metal wiring layer applied to the upper layer of the passivation layer, which is a severe external environmental condition.
  • the volume amount (cross-sectional area amount) of the metal wiring can be arbitrarily set in consideration of electrical characteristics or reliability.
  • the shape of the opening of the insulating layer in which the metal layer is embedded can be arbitrarily set.
  • the present invention has been described in detail above, but the present invention is not limited to the specific embodiment, and various modifications can be made within the scope of the present invention described in the claims.
  • Deformation / change is possible.
  • the step structure for example, FIG. 17 (E)
  • the slope structure for example, FIG. 17 (F), FIG. 18 (D)
  • the parasitic capacitance Cp disclosed in the fourth embodiment are used.
  • the structure to be reduced for example, FIG. 19B
  • the structure to reduce the parasitic capacitance Cp disclosed in the fifth embodiment for example, FIG. 20B
  • the sixth embodiment for example, FIG. 21.
  • Each of (E)) can be applied to at least one of the structure of the first layer and the structure of the second layer in the structure of the two-layer wiring disclosed in the second embodiment (for example, FIG. 6E).
  • the structure disclosed in the seventh embodiment can be applied to the structure of the second layer in the structure of the two-layer wiring disclosed in the second embodiment (for example, FIG. 6E).
  • Each of the structures disclosed in the third to seventh embodiments includes a fan-in type CSP semiconductor device (for example, FIG. 11) and a fan-out type CSP semiconductor device (for example, FIG. 15D). Applicable to each.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteurs qui comprend, par exemple : un substrat (12) qui comprend un élément de circuit ; une électrode (18) sortant d'une puce, qui est électriquement connectée à l'élément de circuit, et qui est formée sur la surface du substrat ; une couche de passivation (20) qui recouvre l'électrode sortant de la puce ; une résine isolante (30), qui recouvre la couche de passivation (20), et qui a une première ouverture formée dans celle-ci ; un câblage métallique (52), qui est formé dans la première ouverture, et qui est électriquement connecté à l'électrode sortant de la puce ; et une borne externe (70), qui est formée sur la surface du câblage métallique (52). La première ouverture comprend une première région (52A) ayant une première profondeur, et une seconde région (52B) ayant une seconde profondeur, qui est inférieure à la première profondeur, et au niveau de laquelle la résine isolante photosensible (30) est laissée, et le câblage métallique (52) est formé dans les première et seconde régions.
PCT/JP2012/060347 2012-04-17 2012-04-17 Dispositif à semi-conducteurs et son procédé de fabrication WO2013157080A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021501459A (ja) * 2017-10-05 2021-01-14 日本テキサス・インスツルメンツ合同会社 半導体パッケージングのための構造及び方法
CN113169166A (zh) * 2018-11-20 2021-07-23 凸版印刷株式会社 半导体封装基板及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004349610A (ja) * 2003-05-26 2004-12-09 Casio Comput Co Ltd 半導体装置およびその製造方法
JP2006287095A (ja) * 2005-04-04 2006-10-19 Seiko Epson Corp 半導体装置及びその製造方法
JP2008233844A (ja) * 2007-03-22 2008-10-02 Samsung Sdi Co Ltd 半導体装置およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004349610A (ja) * 2003-05-26 2004-12-09 Casio Comput Co Ltd 半導体装置およびその製造方法
JP2006287095A (ja) * 2005-04-04 2006-10-19 Seiko Epson Corp 半導体装置及びその製造方法
JP2008233844A (ja) * 2007-03-22 2008-10-02 Samsung Sdi Co Ltd 半導体装置およびその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021501459A (ja) * 2017-10-05 2021-01-14 日本テキサス・インスツルメンツ合同会社 半導体パッケージングのための構造及び方法
CN113169166A (zh) * 2018-11-20 2021-07-23 凸版印刷株式会社 半导体封装基板及其制造方法

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