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WO2013157080A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2013157080A1
WO2013157080A1 PCT/JP2012/060347 JP2012060347W WO2013157080A1 WO 2013157080 A1 WO2013157080 A1 WO 2013157080A1 JP 2012060347 W JP2012060347 W JP 2012060347W WO 2013157080 A1 WO2013157080 A1 WO 2013157080A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
region
manufacturing
insulating material
layer
Prior art date
Application number
PCT/JP2012/060347
Other languages
French (fr)
Japanese (ja)
Inventor
関根弘一
目黒弘一
Original Assignee
株式会社ディスコ
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Filing date
Publication date
Application filed by 株式会社ディスコ filed Critical 株式会社ディスコ
Priority to PCT/JP2012/060347 priority Critical patent/WO2013157080A1/en
Publication of WO2013157080A1 publication Critical patent/WO2013157080A1/en

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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a structure of an external terminal of the semiconductor device and a method of forming the external terminal.
  • CSP chip size package
  • a semiconductor chip is mounted on a lead frame or an interposer, and an electrical connection is made by a bonding wire or a flip chip.
  • External terminals such as grid array (LGA) or land grid array (LGA) are connected.
  • WLP wafer level package
  • a first manufacturing form of WLP is a wiring (rewiring and rewiring) that electrically couples an assembly of semiconductor chips on which a passivation film is formed to a chip pad (chip take-out electrode) corresponding to the opening of the passivation film.
  • external terminals soldder balls, bonding wires, etc.
  • the wafer is diced to obtain individual semiconductor devices to obtain individual CSPs.
  • an assembly of semiconductor chips on which a passivation film is formed is diced to obtain a plurality of independent chips, and each of the plurality of semiconductor chips is sealed with an insulating resin, respectively.
  • a wiring (sometimes referred to as rewiring), an external terminal, and the like that are electrically coupled to the chip pad corresponding to the opening of the corresponding passivation film are formed.
  • the semiconductor chip includes at least a semiconductor substrate (substrate), an electronic circuit (circuit element) such as a transistor, internal wiring for supplying power and signals to the electrical circuit, a plurality of electrical nodes and a plurality of internal wirings included in the electronic circuit. Insulation material that ensures independence, and passivation material.
  • the transistor is included in a semiconductor substrate or stacked as a three-dimensional structure on the semiconductor substrate.
  • the plurality of internal wirings are mainly formed as a multilayer wiring layer on a semiconductor substrate.
  • the passivation material is an insulating layer that protects the semiconductor chip on the uppermost layer of the multilayer wiring layer. The passivation function increases the reliability of the device by protecting the semiconductor chip from contamination such as moisture and mobile ions.
  • Patent Document 4 Cutting (Patent Document 4), grinding (Patent Document 5), and polishing (Patent Document 6) are disclosed as flattening techniques.
  • Patent Document 4 will be described later as a comparative example in the embodiment for carrying out the invention.
  • the gray tone mask creates a slit portion having a resolution lower than the limit resolution of the exposure machine, and the slit portion blocks a part of light to realize intermediate exposure.
  • the halftone mask performs intermediate exposure using a semi-transmissive film as an example. In any case, three exposure levels of an exposed portion, an intermediate exposed portion, and an unexposed portion can be expressed by one exposure, and two types of resist films can be formed after development.
  • Patent Documents 1 to 8 are incorporated in the present invention, and the contents disclosed by each of Patent Documents 1 to 8 are disclosed in the present specification. Part.
  • the present invention discloses a semiconductor device and a manufacturing method thereof with further reduced manufacturing costs, and discloses a wafer level package as a semiconductor device and a manufacturing method thereof as one embodiment.
  • a semiconductor device includes, for example, a substrate including a circuit element, a first metal wiring electrically coupled to the circuit element, and a first metal layer formed on the surface of the substrate; A passivation layer formed of a first insulating material covering the first metal layer; a first insulating layer formed of a second insulating material covering the passivation layer and including a first opening; A second metal layer including a second metal wiring formed in the first opening and electrically coupled to the first metal wiring; and electrically coupled to the second metal wiring; An external terminal formed on a surface of the second metal wiring, wherein the first opening has a first region having a first depth, and the first region is shallower than the first depth. A second region having a second depth that is a depth at which the insulating layer of the second layer remains. Wherein the second metal wiring is formed on the first and second regions.
  • a first metal layer including a first metal wiring electrically coupled to the circuit element is formed on the surface of the substrate on which the circuit element is formed.
  • An external terminal for coupling to the surface of the second metal wiring, and forming the first opening includes a first region having a first depth, A depth at which the first insulating layer remains to be shallower than a depth.
  • a second region having a depth, and simultaneously forming the second metal wiring is formed in the first and second regions.
  • FIGS. 2A to 2F are cross-sectional views taken along the line XX of FIG. 1 for explaining the steps of the WLP according to the first embodiment of the present invention.
  • FIGS. 3G to 3K are cross-sectional views taken along the line XX of FIG. 1 for explaining the steps of the WLP according to the first embodiment of the present invention.
  • 4A to 4F are diagrams for explaining other steps of the WLP according to the first embodiment of the present invention.
  • FIGS. 5A to 5D are cross-sectional views illustrating a process of WLP according to the second embodiment of the present invention.
  • 6E to 6G are cross-sectional views illustrating a process of WLP according to the second embodiment of the present invention.
  • FIG. 5 is a flowchart comparing the WLP process according to the first and second embodiments of the present invention and the conventional WLP process.
  • FIG. 8A is a schematic plan view of a fan-in type CSP
  • FIGS. 8B and 8C are diagrams showing a process of a fan-in type WLP according to the first or second embodiment of the present invention. It is the top view to explain and its sectional drawing.
  • FIGS. 9A to 9D are a plan view and a cross-sectional view for explaining a process of a fan-in type WLP according to the first or second embodiment of the present invention.
  • FIGS. 9A to 9D are a plan view and a cross-sectional view for explaining a process of a fan-in type WLP according to the first or second embodiment of the present invention.
  • FIGS. 10A to 10D are a plan view and a cross-sectional view illustrating a process of fan-in type WLP according to the first or second embodiment of the present invention.
  • FIGS. 11A and 11B are a plan view and a cross-sectional view illustrating a process of fan-in type WLP according to the first or second embodiment of the present invention.
  • 12A to 12E are cross-sectional views illustrating an example of manufacturing a fan-out type WLP substrate according to the first or second embodiment of the present invention.
  • FIG. 13 (A) is a schematic plan view of a fan-out type CSP
  • FIGS. 13 (B) and (C) show the steps of the fan-out type WLP according to the first or second embodiment of the present invention.
  • FIGS. 14A to 14D are a plan view and a cross-sectional view illustrating a process of fan-out type WLP according to the first or second embodiment of the present invention.
  • FIGS. 15A to 15D are a plan view and a cross-sectional view for explaining a process of a fan-out type WLP according to the first or second embodiment of the present invention.
  • FIGS. 16A to 16F are cross-sectional views for explaining a process of WLP according to the third embodiment of the present invention.
  • 17A to 17F are cross-sectional views illustrating other steps of WLP according to the third embodiment of the present invention. It is a figure which shows the example of the other layout pattern by a grating mask.
  • FIGS. 19A and 19B are cross-sectional views illustrating the process of WLP according to the fourth embodiment of the present invention.
  • 20A and 20B are cross-sectional views for explaining a process of WLP according to the fifth embodiment of the present invention.
  • 21A to 21E are cross-sectional views for explaining a process of WLP according to the sixth embodiment of the present invention.
  • 22A to 22D are cross-sectional views for explaining a process of WLP according to the seventh embodiment of the present invention.
  • FIGS. 23E to 23H are cross-sectional views for explaining a process of WLP according to the seventh embodiment of the present invention.
  • FIG. 3 is a first example of a cross-sectional view taken along line YY of FIG. 1 for explaining a process of WLP according to the first embodiment of the present invention.
  • FIG. 5 is a second example of the YY sectional view of FIG. 1 for explaining the process of WLP according to the first embodiment of the present invention.
  • It is a table
  • 3 is a schematic view showing an example of craze generated in the insulating photosensitive polyimide film 30.
  • FIG. 28 (a) and 28 (b) are graphs showing stress-strain curves of various resins.
  • FIGS. 29A and 29B are schematic views of the cutting at the height h1 in FIG.
  • an example of a semiconductor device and a manufacturing method thereof according to the present invention is applied to a WLP related to at least a part of a plurality of manufacturing steps included in the first or second manufacturing mode described above.
  • An example of the semiconductor device according to the present invention is a product obtained from such WLP.
  • the present invention is not necessarily limited to the semiconductor device related to WLP and the manufacturing method thereof, and may be an individual semiconductor device other than WLP and a method of manufacturing the same. That is, the present invention is widely applied to semiconductor devices and manufacturing methods thereof. It should be noted that the scale of the drawing and the ratio of each element are emphasized for easy understanding of the features of the invention, and are not necessarily the same as the actual device scale and the ratio.
  • FIG. 1 is a schematic plan view of a semiconductor chip related to a semiconductor device configured by using the manufacturing method according to the first embodiment of the present invention (plan view seen from an external terminal of the semiconductor device).
  • 1 illustrates one semiconductor chip on a semiconductor wafer.
  • a semiconductor wafer (not shown) includes a plurality of semiconductor chips.
  • One semiconductor chip 10 (semiconductor device 10) on the wafer is represented by a rectangular outer shape 10A.
  • the semiconductor chip 10 includes a silicon substrate 12, and a plurality of circuit elements 14 are formed on one main surface 12 ⁇ / b> A of the silicon substrate 12.
  • the silicon substrate 12 is not limited to a silicon material and may be other materials.
  • the circuit element 14 is an electronic circuit such as a transistor as an example.
  • FIG. 1 illustrates two circuit elements 14.
  • a single-layer or multi-layer wiring 16 is formed on the main surface 12A of the silicon substrate 12, and the wiring 16 constitutes an electrical path between the circuit element 14 and the chip extraction electrode 18.
  • the chip extraction electrode 18 is a so-called chip pad.
  • the chip extraction electrode 18 may be formed by exposing a partial region of the uppermost wiring 16 with a passivation layer, or a metal layer may be separately formed on the wiring 16.
  • a large number of such semiconductor chips 10 are formed on a wafer, and the silicon substrate 12 and the wiring 16 are protected by a passivation layer (passivation material).
  • the structure so far is manufactured in a so-called semiconductor pre-process. Thereafter, the metal pattern 52 and the external terminal 70 are formed on the main surface 12A of these semiconductor chips by a WLP process as will be described later.
  • the external terminals 70 are solder balls, bonding wires, etc., and their shapes and materials are not limited. That is, in the WLP process, the chip extraction electrode 18 (chip pad) manufactured in the previous process is electrically connected to the external terminal 70 as the semiconductor device by the metal pattern 52 as the rewiring.
  • the silicon substrate 12 includes a silicon material 12-1 and a multilayer wiring part 12-2.
  • the silicon material 12-1 includes the circuit element 14.
  • the multilayer wiring portion 12-2 includes a plurality of internal wirings (a plurality of internal wiring layers) that are stacked to electrically connect the circuit elements 14 and the wirings 16, and an insulating material that electrically insulates the plurality of internal wirings ( Insulating layer).
  • a well-known damascene technique may be used.
  • the chip extraction electrode 18 and the wiring 16 are included in the same wiring layer (first metal layer).
  • the same wiring layer is positioned as the uppermost wiring layer in the plurality of internal wiring layers.
  • the plurality of internal wiring layers are included in the multilayer wiring portion 12-2.
  • the same wiring layer (chip take-out electrode 18 and wiring 16) which is one of a plurality of elements constituting the features of the invention, is represented on the main surface 12A of the silicon substrate 12. Yes. That is, in order to make it easy to understand the structure of the embodiment for realizing the invention, it is simplified and described.
  • the chip extraction electrode 18 and the wiring 16 are formed on the main surface 12A of the silicon substrate 12.
  • the chip extraction electrode 18 is made of a conductive metal material such as Al, Au, or Cu, for example.
  • a passivation layer 20 made of silicon nitride (Si 3 N 4 ) or the like is formed on the entire surface of the substrate with a predetermined film thickness.
  • the passivation layer 20 has a convex-concave shape, but may be a planarized passivation layer 20.
  • an opening 20A for exposing the chip extraction electrode 16 is formed by using a known photolithography process.
  • an insulating photosensitive polyimide film 30 (second insulating material, which is a first insulating layer, is formed on the entire surface of the substrate so as to cover the passivation layer 20 by spin coating or the like. ) Is applied.
  • the photosensitive polyimide film 30 may be either a positive type or a negative type, but the example shown in the figure shows a positive type.
  • the film 30 is not limited to a polyimide material, and may be a material mainly composed of a phenol resin, an unsaturated polyester resin, a melamine resin, or a urea resin, for example. This will be described in detail with reference to FIG.
  • the photosensitive polyimide film 30 is exposed using a grating mask (halftone mask) 40 capable of changing the amount of transmitted light.
  • a grating mask halftone mask
  • Hitachi Kasei HD-8910 can be used as the grating mask 40, and the photosensitive polyimide film 30 can be subjected to grayscale (stepwise) exposure by varying the amount of transmitted light.
  • grayscale stepwise exposure by varying the amount of transmitted light.
  • the developed photosensitive polyimide film 30 a film thickness corresponding to the exposure amount remains. That is, the remaining film thickness is small in the region where the exposure amount is larger, and the remaining film thickness is thick in the region where the exposure amount is small.
  • the grating mask 40 includes a region that transmits the light amount L1, a region that transmits a light amount L2 that is smaller than the light amount L1, and a light shielding region 40A.
  • the light amount L1 is the opening 20A of the passivation layer 20. Expose areas that are aligned with.
  • the light quantity L2 is an area that continues laterally from the opening 20A, and exposes an area in which a metal layer will be formed later.
  • the light amount L1 is a value sufficient to completely remove the polyimide film 30 when developed, and the light amount L2 is a value that leaves a predetermined film thickness on the polyimide film 30.
  • the photosensitive polyimide film 30 is developed. As shown in FIG. 2 (F), the photosensitive polyimide film 30 is formed with an opening 32 having a step according to the amount of light.
  • the opening 32 has a first region 32A having a depth reaching the opening 20A at a position aligned with the opening 20A of the passivation layer 20, and a depth smaller than the first region 32A and laterally from the first region 32A. And a second region 32B extending at a certain depth.
  • the size of the first region 32 ⁇ / b> A is approximately the same as the opening 20 ⁇ / b> A of the passivation layer 20.
  • a metal layer 50 (second metal layer) made of a conductive metal material is formed over the entire surface of the substrate.
  • the metal layer 50 is not necessarily a single layer and may be a multilayer.
  • a seed metal such as Ti or Cu is formed as a first example, and then Cu is formed by electroplating.
  • a barrier metal such as Ti or Cu may be formed by physical vapor deposition such as sputtering or ion plating, and then Cu may be formed.
  • the metal layer 50 has a thickness sufficient to fill the opening 20 ⁇ / b> A of the passivation layer 20 and the opening of the first region 32 ⁇ / b> A of the photosensitive polyimide film 30.
  • a planarization process is performed, and the metal layer 50 is patterned at the same time.
  • the metal layer 50 reflects the unevenness of the base, and a step is formed on the surface thereof.
  • at least one of grinding, polishing, and cutting is used to remove the metal layer 50 and a part of the underlying polyimide film 30.
  • Grinding is “shaving the substance” with a grindstone.
  • Polishing is “polishing material” with abrasive grains.
  • Cutting is “cutting out the substance” with a sharp blade or the like.
  • CMP Chemical Mechanical Polishing
  • CMP Chemical Mechanical Polishing
  • the cutting is performed by using the side surfaces of the polyimide film 30 and the metal layer 50 as viewpoints (for example, from left to right).
  • a cutting blade (bit (beitel)) that scans the main surface of the substrate 12 in the horizontal direction. or a cutting tool).
  • bit Gibtel
  • the cutting blade is positioned on the surface K1, and the polyimide film 30 and the metal layer 50 above it are removed. Therefore, the height of the cutting blade is kept constant throughout the cutting process.
  • the cutting blade is positioned on the surface K1, and the polyimide film 30 and the metal layer 50 above it are cut.
  • the reference point of the height h1 is not limited to the main surface of the substrate 12, but may be an underline (back surface) of the silicon substrate.
  • “grinding” and “polishing” are performed, for example, by rotating a grindstone in which abrasive grains are hardened with a binder to “shave” or “shave” the workpiece. Accordingly, the height of the grindstone varies over the grinding process.
  • the metal layer 50 and the polyimide film 30 are polished from the main surface of the substrate 12 to the surface K1 reaching a certain height h1. In this way, even if a similar workpiece is finally completed, the principles of movement and cutting of the cutting blade and the grindstone, which are jigs, and the wear principle of the jigs are completely different.
  • the film 30 (second insulating material, first insulating layer) is not limited to the polyimide material, and for example, phenol resin, unsaturated polyester resin, melamine resin, or urea.
  • a material mainly composed of a resin is preferable.
  • the cause of wear of the cutting blade is firstly the hardness of the material to be cut, and secondly, the stickiness of the material (that is, the magnitude of elastic elongation).
  • the cutting blade cuts a sticky material (workpiece)
  • the cutting blade drags an uncut material.
  • a material to be cut (workpiece) mainly composed of unsaturated polyester resin, melamine resin or urea resin in addition to phenol resin is useful.
  • Cutting with a cutting blade does not cause plastic deformation due to local heat generation during cutting, and in order to improve the sharpness of the cutting blade, the film 30 has an appropriate elastic modulus, a small distortion with respect to a limit stress, and a strength comparison. This is because a low resin is considered good.
  • FIG. 24 and FIG. 25 show the YY line cross section of FIG. 1 as an example of each preferred embodiment for cutting.
  • the phenolic resin 460 is exposed using a grating mask (halftone mask) 40. Thereafter, a groove 462 (which corresponds to the opening 32) corresponding to the phenol resin 460 is formed in the development process.
  • the cross section of the first resin 460 (phenol resin 460) adjacent to the groove 462 is a rectangle substantially perpendicular to the surface of the substrate 450.
  • the metal layer 50 (second metal layer) is formed as a multi-layered two-layer metal layer (the first metal 470 having relatively high hardness and the relative hardness. Second metal 480) having a low thickness was deposited by physical vapor deposition. As a result, the film formation state shown in FIG. 24 is obtained.
  • the first metal 470 may be Ti, Cr, Ta, or Pd, and the second metal 480 may be Cu or Al. As can be seen from these materials, there is a difference in hardness between the first metal 470 used as a barrier metal and the second metal 480 used as a wiring metal.
  • the byte 480 in FIG. 24 is installed in the same manner as in FIG.
  • the first metal 470 formed on the side surface (side wall of the first resin 460) of the groove 462 in FIG. 24 is not formed, that is, the height corresponds to a place where the thickness is zero.
  • the cutting blade 490 is installed at the height H0 to cut the first resin 460 and the second metal 480. As a result, the intermediate shown in FIG. 3 (H) is obtained.
  • a first metal 470 having a relatively high hardness is formed from the upper surface of the first resin 460 to the upper part of the side surface of the groove 462.
  • the thickness of the first metal 470 formed on the side surface of the first resin 460 gradually decreases and eventually becomes zero.
  • a second metal 480 is formed on the first metal 470 formed on the bottom of the groove 462, the upper surface of the first resin 460, and the upper part of the side surface of the groove 462.
  • the second metal 480 may be formed to fill the groove 462 like the metal layer 50 in FIG. Note that the thickness of the first metal 470 formed on the upper surface of the first resin 460 and the thickness of the first metal 470 formed on the bottom of the groove 462 are substantially the same.
  • the cutting feature is that a cutting blade 490 is installed along a cutting line having a height H0 corresponding to a place where the thickness of the first metal 470 is not formed and the thickness is zero.
  • the cutting is performed by scanning the cutting blade 490 along the line. Therefore, the cutting blade 490 cuts only the two types of the first resin 460 that is the softest and the second metal 480 that is relatively harder than the first metal 470.
  • the thickness of the second metal 480 is arbitrary and is not directly related to the installation height H of the cutting blade 490.
  • the cutting blade 490 may cut only the first resin 460 on the cutting line having the height H0.
  • the cutting line having the height H1 may be the surface of the second metal 480 formed in the groove 462.
  • softest means the softest material among a plurality of materials to be cut.
  • the first metal 470 having a relatively high hardness is also formed on the side surface of the groove 462. Therefore, three types of materials including the first metal 470 are cut. Compared with such a case, in the present embodiment, the degree of wear of the cutting blade 490 is the smallest, and the life of the cutting blade 490 can be maximized.
  • the cutting may be performed aiming at the height.
  • the film thickness T1 of the first metal 470 is the same as that of the same first metal 470 formed on the upper surface of the first resin 460. It is thinner than the thickness T2 (see the enlarged view of region B in FIG. 19). You may cut with this cutting line of height H1.
  • the cutting blade 490 cuts three types of the first metal 470, the second metal 480, and the first resin 460, but the film thickness T1 of the first metal 470 is It is small enough to satisfy the above conditions. Compared with the case of cutting at a position higher than the height H1, the degree of wear of the cutting blade 490 is small, and the life of the cutting blade 490 can be extended.
  • Patent Document 4 is compared with one embodiment of the present invention as a comparative example.
  • the technique of Patent Document 4 discloses that the cutting blade is brought into contact with an arbitrary position on the side wall of the groove and is cut in the X direction, there is no disclosure about the hardness of the metal and the deterioration (wear) of the cutting blade.
  • the height of the cutting blade from the viewpoint of suppressing the deterioration of the cutting blade has not been studied, and there is no disclosure or suggestion.
  • the present invention it is possible to suppress the wear of the cutting blade and to improve the cutting performance by strictly defining the relationship between the set height of the cutting blade and the first metal 470. Has an effect. Furthermore, according to the present invention, by precisely defining the relationship between the material of the first resin 460 as electrical insulation described later and the cutting blade, it is possible to suppress cutting blade wear and improve cutting performance. Has a noticeable effect.
  • the present invention is to cut the first metal 470 as much as possible by cutting the first metal 470 so that the thickness of the first metal 470 becomes thinner or zero. This is one feature of each of the embodiments.
  • the physical constant and the wear of the cutting blade 490 will be considered.
  • FIG. 26 is a table showing physical properties of various resins and metals preferable for one embodiment of the present invention using a cutting blade.
  • FIG. 26 includes a phenol resin as a representative material that can be used as the first resin 460. Further, Ti is included as a representative metal that can be used as the first metal 470, and Cu or Al is included as a representative metal that can be used as the second metal 480.
  • Polyimide resin is a comparative example of phenol resin.
  • the material to be cut When cutting with the cutting blade 490, the material to be cut receives resistance to the cutting blade 490, and the cause of the wear of the cutting blade 490 is firstly the hardness of the material to be cut, and secondly, the material There is stickiness (that is, the size of elastic elongation). This is because when the cutting blade 490 cuts a sticky material, the cutting blade 490 drags an uncut material. Ti is a material that wears the cutting blade 490 in particular because of its high hardness and stickiness.
  • a height corresponding to a place where the first metal 470 having a high hardness represented by Ti is not formed or where the thickness is thin is cut. To do. Thereby, the cutting amount of the first metal 470 was suppressed. Therefore, the wear of the cutting blade 490 can be suppressed, and its life can be greatly extended.
  • phenolic resins generally have many network-forming groups such as functional alkyl groups and hydroxyl groups necessary for polymer construction, and have a dense three-dimensional structure compared to network-forming groups such as polyimide imide groups. Therefore, the elastic modulus is relatively high, the hardness is high, and the plastic deformation (craze deformation) range is small.
  • the phenolic resin is mainly composed of an annular structure, so that it is easy to perform cutting work without causing problems such as a cutting object adhering to the cutting blade and deterioration in processing performance. Thus, the problem in processing is eliminated by reducing the difference in characteristics from the metal on cutting.
  • the first resin 460 may contain an unsaturated polyester resin, melamine resin, or urea resin as a main component in addition to the phenol resin. This is because cutting with a cutting blade is preferably a thermosetting resin that does not cause plastic deformation due to local heat generation during cutting. Moreover, in order to improve the sharpness of the cutting blade, the first resin 460 is considered to be a resin having an appropriate elastic modulus, a small distortion with respect to a limit stress, and a relatively low strength. It is preferable that at least the range of plastic deformation leading to fracture of the first resin is smaller than the range of plastic deformation of polyimide.
  • the tensile strength of the first resin is preferably smaller than that of polyimide. As a specific numerical value, it is preferable that the first resin has less than 10% of strain to reach rupture with respect to stress. In addition, the tensile strength of the first resin (tensile strength) is preferably 80 MPa or less.
  • FIG. 27 is a schematic diagram showing an example of craze generated in a resin (polyimide resin or the like) that is not suitable as the first resin 460 in FIG. 24 (one embodiment of the present invention using a cutting blade).
  • Craze means a state in which two-dimensional chains of two-dimensional entangled atomic chains are aligned and difficult to break. As shown in FIG. 27, when a force F is applied when trying to open a plastic bag, the organic bulk part 492 and the part that expands and becomes cloudy separates into a craze 494, which is a phenomenon of extremely strong resistance. Craze 494 that appears cloudy includes fibrils 496 that are microfibers and voids 498 that are voids.
  • FIG. 28 is a graph showing stress-strain curves of various resins.
  • the first resin 460 a resin having a strain with respect to stress of several percent or less is preferable, and the resin is a material that hardly causes craze and has little entanglement with the cutting blade.
  • the above-mentioned phenol resin, unsaturated polyester resin, melamine resin, or urea resin all satisfy such conditions. This is because it contains a ⁇ -type cyclic group that is hard and has little elongation.
  • the polyimide resin is a resin having a high strength in which the strain with respect to the stress reaches several tens of percent, and the crazing shown in FIG. 27 is likely to occur. Accordingly, as the material of the first resin 460, polyimide resin is inappropriate because there is a possibility that the cutting performance by the cutting blade 490 may be deteriorated.
  • the photosensitive polyimide film 30 is suitable as an insulating material in the first embodiment of the present invention using techniques of “grinding” and “polishing” other than cutting.
  • phenolic resins There are two types of phenolic resins: phenolic and formaldehyde mixed, polymerized by acid catalyst, polymerized novolak type, and resin called resol type, polymerized by alkali catalyst.
  • the former is thermoplastic as it is, and is liquid in the low molecular state.
  • hexamethylenetetramine or the like is mixed with this as 1 to 20% by weight of a curing agent, it undergoes condensation polymerization and becomes a thermosetting resin. Since the latter itself has a self-reactive active group, it is cured by heating.
  • the novolak type that allows easy control of the thermosetting polymerization reaction is mainly used.
  • What is referred to as a permanent resist in the present application is a novolak type, and when processed as a photoresist, 100% of the novolak type phenol resin is occupied by this component.
  • macromonomers having various strengths such as fillers such as cellulose, pigments (particularly black pigments), fillers (silica glass fine particles), etc., are used as the total amount of additives. About 0.1 to 50% by weight may be mixed.
  • the phenolic resin is fragile as an electronic material because it has little elongation and high strength, as can be seen from the stress-strain curve in FIG.
  • an epoxy-modified phenolic resin modified part, that is, the epoxy properties become stronger depending on the mixing percentage
  • a polyvinyl acetal-modified phenolic resin due to poor heat resistance can do.
  • Modifications have been made to improve various properties, such as using a nitrile rubber-modified phenol resin to improve thermal cycle reliability, or using a rosin-modified phenol resin to improve printability.
  • the mixing ratio of the modified resin is 1% to 50% by weight. Therefore, in the present text, “having a phenol resin as a main component” is defined as 50% by weight or more of a phenol resin.
  • Melamine resin is synthesized by polymerization condensation reaction of methylolmelamine obtained by condensation reaction of melamine and formaldehyde, but has a higher impact strength than urea resin because it forms a nitrogen cyclic group.
  • reinforced plastics are made by impregnating methylol melamine into fibers and the like, but as an electronic component, 5 to 40% by weight of a cellulose additive is added. Of course, it can withstand use as 100% resin. Modification with epoxy or urea resin can be done freely by adding appropriate amounts of epoxy monomer and urea during synthesis. Further, by mixing, a resin having intermediate properties can be obtained.
  • “having melamine resin as a main component” is defined herein to be 50% by weight or more.
  • Unsaturated polyester resin is a thermosetting resin made by condensation polymerization of unsaturated polyesters such as maleic anhydride and isophthalic acid and polyhydric alcohols such as ethylene glycol, both maleic anhydride and styrene are cyclic groups, It is characterized by high mechanical strength. Therefore, 100% resin can also be used. In particular, it is excellent for use as a reinforced plastic impregnated into fibers.
  • a myriad of different types of ester compounds can be made, but in order to maintain the smoothness of the surface as a modified resin with different types of resins, modification by mixing pentadiene during synthesis, mixing with compatible acrylic urethane, and yellowing due to light Modifications to prevent alteration are considered.
  • “based on unsaturated polyester resin” means 50% by weight or more. Define.
  • Urea resin (urea resin) is synthesized by condensation reaction of urea and formaldehyde, and because it is a linear network without cyclic compounds, fracture toughness decreases. Therefore, it is rare to use 100% resin, and in order to increase fracture toughness, it is considered that 0.5 to 30% by weight of a glycine compound having a bisphenol A skeleton, which is a cyclic compound, is added and modified during synthesis. . Cellulose is often used as a filler, and the mechanical properties can be adjusted by adding 5 to 40% by weight. Good consistency with melamine resin and phenol resin, and by adding melamine and phenol during the reaction, intermediate properties between each other are born. In the present text, “based on urea resin” is defined as 50% by weight or more.
  • FIG. 29 is a schematic view of the resin and metal after cutting at the height H0 in FIG. 24 as seen from the cross section.
  • FIG. 29A shows a case where the material of FIG. 24 is used as it is, and the first resin 460 (phenol resin or the like) and the second metal 480 (Cu or Al) are alternately cut.
  • FIG. 29B shows a case where the first resin 460 of FIG. 19 is temporarily changed to a polyimide resin 461.
  • cutting is performed without any problem as shown in FIG. Since the first resin 460 is hard and has a low elongation property, when the first resin 460 is cut, a gap is not easily generated between the adjacent second metals 480 that are cut together. Further, the first resin 460 is hardly peeled from the substrate 450. Therefore, there is a remarkable effect that the metal wiring pattern forming the wiring is prevented from being distorted.
  • the wiring / resin pattern may be distorted.
  • metal dropout, resin dropout, internal voids, and the like are likely to occur, and there is a possibility that wiring breaks and wiring shorts may occur.
  • the adhesion area between the resin and the metal, the metal and the substrate, and the resin and the substrate is originally small. Peeling 467, 469) is likely to occur. Therefore, it is important to use the first resin 460 that is easy to cut as shown in FIG.
  • the substrate 450 has a passivation film 444 on at least a part of its surface, and the passivation film 444 is in contact with the first resin 460.
  • the passivation film 444 and the first resin 460 are in contact with each other, the adhesion (adhesive force) of the first resin 460 is improved, and the cutting performance is further improved.
  • the passivation film 444 of this embodiment is mainly composed of polyimide resin.
  • Any of a phenol resin, an unsaturated polyester resin, a melamine resin, and a urea resin used as the first resin 460 in contact with the passivation film 444 is a photosensitive resin that adheres to a polyimide resin, and has a strong adhesive force and is easy to cut. Has performance. This is because the material of the first resin 460 has a relatively large number of carboxyl groups, hydroxyl groups, and imide groups that are reactive with the carboxyl groups and imide groups, which are reactive groups of the polyimide resin that is the material of the passivation film 444. This is because it is included in the main chain and sub-chain.
  • the description returns to the description of FIGS. 2 and 3 (the manufacturing process of the WLP according to the first embodiment).
  • the resin 30 and the metal layer 50 are ground or polished from the upper surface to the surface K1 reaching the height h1.
  • the resin 30 and the metal layer 50 are cut from the side surface along the surface K1 by the cutting blade installed at the height h1.
  • FIG. 3 (H) shows a state after flattening.
  • the surface 32 of the polyimide film 30 and the surface of the metal layer 50 have substantially the same height, and a metal pattern (metal wiring) 52 is formed in the opening 32 of the polyimide film 30.
  • the metal pattern 52 is a second metal layer.
  • the metal pattern 52 has a shape corresponding to the opening 32 (FIG. 2F) of the polyimide film 30, and therefore the metal pattern 52 is chipped through the opening 20A of the passivation 20 (FIG. 2C).
  • a solder resist 60 is applied to the entire surface of the substrate, and exposure and development are performed by, for example, a known photolithography process. As shown in FIG. An opening 60A of the solder resist 60 is formed so as to expose the second region 52B having a flat surface. Note that the solder resist may form the opening 60A by a laser manufacturing method instead of the photolithography manufacturing method. Next, as shown in FIG. 3K, solder balls 70 (external terminals 70) are formed through the openings 60A. Thus, the WLP process is performed, and thereafter, the substrate is diced to obtain individual CSP semiconductor chips.
  • Solder resist materials include, for example, novolak type cyanate resins, bisphenol A type cyanate resins, bisphenol E type cyanate resins, cyanate resins such as bisphenol type cyanate resins such as tetramethylbisphenol F type cyanate resin; phenol novolac resins, cresol novolac resins, Phenolic resins such as bisphenol A novolac resins, novolac type phenolic resins, unmodified resole phenolic resins, oil-modified resol phenolic resins modified with tung oil, linseed oil, walnut oil, etc .; bisphenol A type epoxy resins Bisphenol F type epoxy resin, bisphenol S type epoxy resin, bisphenol E type epoxy resin, bisphenol M type epoxy resin, bisphenol P type epoxy resin Bisphenol type epoxy resins such as xyphenol resin and bisphenol Z type epoxy resin; Novolak type epoxy resins such as phenol novolac type epoxy resin and cresol novolak type epoxy resin; Biphenyl type epoxy resin,
  • Resin having a triazine ring unsaturated polyester resin, bismaleimide resin, polyurethane resin, diallyl phthalate resin, silicone resin, benzoxazine Resins having, polyimide resin, polyamideimide resin, benzocyclobutene resin, and the like. In the present invention, one of these may be used alone, or two or more may be used in combination. Moreover, you may use together what has different weight average molecular weights of the same kind of resin. Furthermore, you may use together the said 1 type, or 2 or more types, and those prepolymers.
  • the content of the thermosetting resin is not particularly limited, but is preferably 50 to 100% by weight based on the entire resin composition.
  • the opening 32 leading to the opening 20A is formed in the upper photosensitive polyimide film 30 of the passivation layer 20, but the opening 20A and the opening 32 are continuously formed. You may make it form in.
  • the process is shown in FIG.
  • chip takeout electrodes 18 and wirings 16 are formed on the main surface 12A of the substrate 12, and then a passivation layer 20 is formed on the entire surface of the substrate as shown in FIG. 4B.
  • a photosensitive polyimide film 30 is applied to the entire surface of the substrate so as to cover the passivation layer 20, and then a grating mask 40 is used as shown in FIG. 4D.
  • the grating mask 40 includes a region that transmits the light amount L1, a region that transmits a light amount L2 smaller than the light amount L1, and a light shielding region 40A.
  • openings 32 having shapes corresponding to the light amounts L1 and L2 are formed in the photosensitive polyimide film 30, and the openings
  • the part 32 includes a first region 32A having a depth reaching the passivation layer 20, and a second region having a depth shallower than the first region 32A and extending laterally at a constant depth. And a region 32B.
  • the photosensitive polyimide film 30 is used, and the passivation layer 20 exposed by the first region 32A is removed by etching, whereby the opening 20A of the chip extraction electrode 18 is formed.
  • the WLP process of the second embodiment of the present invention will be described.
  • the solder ball 70 is formed by single-layer wiring
  • the solder ball 70 is formed by two-layer wiring
  • the single-layer wiring includes, for example, two metal layers that do not sandwich an insulating layer.
  • the barrier metal layer and the copper layer disclosed in the first embodiment are two metal layers sandwiching an insulating layer.
  • Differences from the first embodiment will be mainly described, and the first embodiment will be applied mutatis mutandis.
  • the planarized metal pattern 52 and the polyimide film 30 are then formed as shown in FIG.
  • a photosensitive polyimide film 80 is applied to the entire surface of the substrate so as to cover it. Both the polyimide film 30 and the polyimide film 80 are insulating layers.
  • the photosensitive polyimide film 80 is exposed using the grating mask 42.
  • the grating mask 42 includes a region that transmits the light amount L1, a region that transmits a light amount L2 less than the light amount L1, and a light shielding region 42A.
  • the light amount L1 is a value sufficient to remove all of the photosensitive polyimide film 80.
  • the light quantity L2 is a value that leaves a predetermined film thickness on the photosensitive polyimide 80.
  • the opening 82 includes a first region 82A having a depth reaching the underlying metal pattern 52, and a second region having a depth shallower than that of the first region 82A and extending laterally at a certain depth. 82B.
  • a metal layer 90 is formed on the front surface of the substrate so as to cover the polyimide film 80.
  • the metal layer 90 may be either a single layer or a multilayer as in the first embodiment.
  • a planarization process is performed. The flattening process is performed using at least one of grinding, polishing, and cutting, as in the first embodiment.
  • a part of the metal layer 90 and the polyimide film 80 is removed by performing a planarization process on a surface K2 having a height h2 from the main surface of the substrate 12.
  • the film 80 is not limited to the polyimide material as in the first embodiment, and for example, a material mainly composed of a phenol resin, an unsaturated polyester resin, a melamine resin, or a urea resin is preferable. .
  • a metal pattern 92 having a surface substantially the same as the surface of the polyimide film 80 is formed.
  • the metal pattern 92 has first and second regions 92A and 92B corresponding to the first and second regions 82A and 82B of the opening 82, respectively.
  • solder resist 62 is applied, and an opening is formed so as to expose the second region 92B of the metal pattern 92 by a photolithography process, as shown in FIG. 6G.
  • a solder ball 70 electrically connected to the metal pattern 92 is formed.
  • FIG. 7 compares the manufacturing method according to this embodiment related to the formation of the WLP wiring and the conventional manufacturing method.
  • the method for forming the external terminals is omitted.
  • a photosensitive resin is applied (S1), exposed using a predetermined mask pattern (S2), and the photosensitive resin is developed (S3).
  • a seed metal such as Ti is formed by sputtering (S4), and then a photolithographic process is again performed by applying a photosensitive resist (S5), exposure (S6), and development (S7), and by electroplating, Cu or the like It includes steps of forming metal wiring (S8), stripping the resist (S9), and etching the seed metal (S10).
  • the photosensitive polyimide resin is applied from the state shown in FIG. 2C (S101: FIG. 2D), and the grating mask is applied. Exposure is performed (S102: FIG. 2E), development is performed (S103: FIG. 2F), and metal wiring is formed by physical vapor deposition or electrolytic plating (S104: FIG. 3G).
  • the method includes surface grinding (S105: FIG. 3H), and the number of steps can be significantly reduced as compared with the conventional manufacturing method.
  • the surface grinding (S105) may be surface cutting.
  • the process of removing the photosensitive polyimide resin is unnecessary, and this also contributes to the reduction of the number of processes.
  • the CSP obtained by the manufacturing method of the above embodiment is a BGA in which solder balls are formed as external terminals.
  • the external terminals may be LGA having a planar shape.
  • the external terminal may be a bonding wire 71 using a bonder as shown in FIG.
  • the photosensitive resin exposed by the grating mask may be either a positive type or a negative type, and the material is not limited to the polyimide type.
  • the grating mask is not limited in its form as long as the amount of light transmission can be adjusted, and may be a halftone mask, for example.
  • FIG. 8A shows a schematic plan view of a fan-in type CSP in which external terminals 110A to 110D are formed on the surface of the CSP by WLP.
  • the fan-in type CSP 100 has a plurality of external terminals 110 (110A to 110D) formed on the surface inside the outer shape 100A of the semiconductor chip.
  • the external terminal 110A is connected to a chip pad (chip take-out electrode) 130A formed on the main surface of the substrate via a first layer wiring 120A above the passivation layer, and the external terminal 110C is connected to the first layer wiring 120C. It is connected to a chip pad (chip take-out electrode) 130C formed on the main surface of the substrate.
  • the external terminal 110B is connected to a chip pad (chip take-out electrode) 130B on the main surface of the substrate via a second layer wiring 120B above the passivation layer and above the first layer, and the external terminal 110D has two layers.
  • the wiring 120D is connected to a chip pad (chip extraction electrode) 130D. Since the wirings 120A and 120C and the wirings 120B and 120D intersect, the wiring layer above the passivation layer needs to have at least a two-layer structure.
  • FIG. 8B is a plan view when the wirings 120A and 120C in the first layer are finished, and FIG. 8C shows a cross section taken along line XX.
  • Chip pads 130A to 130D are formed on the main surface of the substrate 140, and regions other than the chip pads 130A to 130D are covered with a passivation layer 150.
  • the wiring 120A of the first layer is patterned so that one end thereof is connected to the chip pad 130A and the other end extends in a diagonal direction, and the wiring 120C has one end connected to the chip. It is connected to the pad 130C and patterned so that the other end extends in a diagonal direction.
  • the first contact pads 122B and 122D are simultaneously formed on the chip pads 130B and 130D.
  • the first-layer wirings 120A, 120C, 122B, and 122D may be formed using the steps up to the first embodiment (FIGS. 2A to 3H), or Alternatively, it may be formed by using the conventional method shown in FIG.
  • the first-layer wiring is an example constituted by a stack of a seed metal and a metal electroplated thereon. In other words, the manufacturing method of this embodiment is used for forming at least the second-layer wiring.
  • the second layer wiring is formed.
  • the second embodiment described above (FIGS. 5 to 6) is cited.
  • a photosensitive insulating resin 160 is applied to the entire surface of the substrate.
  • exposure is performed using a grating mask.
  • the conductive insulating resin 160 is exposed.
  • the exposed areas 160A and 160B are indicated by solid lines.
  • the region of the photosensitive insulating resin 160 aligned with the first contact pads 122B and 122D is exposed with a relatively large amount of light so as to form openings to the contact pads 122B and 122D, and the second layer wiring 120B ( 8A) and 120D (FIG.
  • the two regions 160B aligned with the respective ends of the first-layer wirings 120A and 120C are also exposed with a relatively large amount of light so as to form openings to the first-layer wirings 120A and 120C.
  • the openings 162 and 164 having a film thickness corresponding to the light amount are formed.
  • the opening 162 includes a first region 162A having a depth reaching the contact pads 122B and 122D, and a second region having a depth shallower than that of the first region 162A and extending diagonally at a constant depth. 162B.
  • the opening 164 has substantially the same depth as the depth of the first region 162A reaching the first-layer wirings 120A and 120C.
  • a second metal layer 170 is formed on the entire surface of the substrate including the opening 162.
  • the metal layer 170 includes a seed metal such as Ti or Cu and a Cu metal electrolytically plated thereon.
  • the surface is flattened.
  • the flattening process is performed using at least one of grinding, polishing, and cutting as in the first and second embodiments.
  • the metal layer 170 and the photosensitive insulating resin 160 existing at a certain height or more from the main surface of the substrate are removed.
  • patterned second layer wirings 120 ⁇ / b> B and 120 ⁇ / b> D are formed in the opening 162 of the photosensitive insulating resin 160.
  • the wirings 120B and 120D include a shape obtained by transferring the shape of the opening 162, and are connected to the contact pads 122B and 122D in a region corresponding to the first region 162A ((FIG.
  • the wirings 120B and 120D extend with a substantially constant film thickness in a region corresponding to the second region 162B.
  • the opening 164 FIG. 10A
  • the external terminals 110A110C are electrically connected to the first wirings 120A and 120C and the chip pads 130A and 130C through the second metal layer 170 of the corresponding opening 164.
  • the external terminals 110B and 110D are electrically connected to the corresponding second-layer wirings 120B and 120D and chip pads 130B and 130D, respectively.
  • the fan-out type CSP has a semiconductor chip and an insulating resin that has a larger outer shape than the semiconductor chip and supports the semiconductor chip, and the external terminals are formed on the insulating resin beyond the outer shape of the semiconductor chip. Is. This type can form a larger number of external terminals than the fan-in type.
  • FIG. 12 shows an example of manufacturing a fan-out type WLP substrate.
  • the semiconductor wafer W on which the passivation layer 244 is formed is diced using a grindstone S or a laser, separated into individual semiconductor chips, and then as shown in FIG. 12B.
  • the semiconductor chips 200 are aligned on the chip fixing tape 210.
  • An adhesive layer 210A is formed on the surface of the chip fixing tape 210, and the main surface of the semiconductor chip 200 is fixed by the adhesive layer 210A.
  • the main surface of the semiconductor chip 200 is a surface on which the circuit element 14, the chip extraction electrode 18, and the wiring 16 (FIG. 2) are formed.
  • FIG. 2 shows an example of manufacturing a fan-out type WLP substrate.
  • each semiconductor chip 200 on the chip fixing tape 210 is sealed with an insulating resin 220, as shown in FIG. Then, the chip fixing tape 210 is peeled off together with the adhesive layer 210A, whereby the fan-out WLP substrate 230 is completed.
  • FIG. 12E is an enlarged cross-sectional view of one semiconductor chip 200 included in the fan-out WLP substrate 230.
  • the top and bottom are shown opposite to the drawing of FIG.
  • the side surface and the back surface of the substrate 240 indicated by the semiconductor chip 200 are sealed with the insulating resin 220, and the main surface is exposed from the insulating resin 220.
  • a chip pad (chip extraction electrode) 242 is formed on the main surface of the substrate 240, and a region excluding the chip pad is protected by the passivation layer 244.
  • the process when the fan-out WLP substrate is used in the manufacturing method according to the present embodiment is performed by using the fan-in WLP substrate shown in FIGS. 8 to 11 except that the external terminals are formed on the insulating resin 220. This is substantially the same as the process used. Therefore, the same reference numerals as those in FIGS. 8 to 11 are used for explanation.
  • FIG. 13A shows a schematic plan view of a fan-out type CSP in which external terminals 110A to 110D are formed on the surface of the CSP.
  • the external terminals 110A to 110D are formed in a region of the insulating resin 220 existing outside the outer shape 100A of the semiconductor chip.
  • the external terminals 110A and 110C are respectively connected to chip pads (chip take-out electrodes) 130A and 130B formed on the main surface of the substrate via wirings 120A and 120C in the first layer above the passivation layer.
  • 110D is connected to chip pads 130B and 130D formed on the main surface of the substrate via wirings 120B and 120D in the second layer above the passivation layer and above the first layer, respectively.
  • FIGS. 13B and 13C illustrate a case where the first wirings 120A and 120C and the contact pads 122B and 122D are formed on the main surface of the substrate 140 (240 in FIG. 12E) and the insulating resin 220.
  • the state where the photosensitive insulating resin 160 is applied is shown.
  • FIG. 13C shows a cross section taken along line XX shown in FIG.
  • the photosensitive insulating resin 160 is exposed using a grating mask.
  • the exposure region is a range indicated by a solid line of a region 160A straddling the outer shape 100A of the semiconductor chip and a region 160B that is the outer periphery of the outer shape 100A of the semiconductor chip.
  • FIGS. 13B illustrate a case where the first wirings 120A and 120C and the contact pads 122B and 122D are formed on the main surface of the substrate 140 (240 in FIG. 12E) and the insulating resin 220.
  • FIG. 13C shows a cross section taken along line XX shown
  • the photosensitive insulating resin 160 is developed to form openings 162 and 164 corresponding to the regions 160A and 160B.
  • the opening 162 has a first region 162A having a depth reaching the contact pads 122B and 122D and a depth shallower than that of the first region 162A, and a predetermined thickness of the photosensitive insulating resin 160 remains. 2 regions 162B.
  • the opening 164 has a depth substantially the same as the depth of the first region 162A that reaches the ends of the first-layer wirings 120A and 120C.
  • a second metal layer 170 by seed metal and electrolytic plating is formed on the entire surface of the substrate, and then FIGS.
  • the metal layer and the photosensitive insulating resin 160 are planarized, and the second-layer wirings 120B and 120D are patterned.
  • the metal layer 170 physical vapor deposition may be used as in the first and second embodiments.
  • the flattening process is performed using at least one of grinding, polishing, and cutting as in the first and second embodiments.
  • the external terminals 110A to 110D are formed on the main surface of the insulating resin 220.
  • FIG. 16 is a diagram for explaining a manufacturing method according to the third embodiment of the present invention.
  • a photosensitive insulating resin 310 is applied on a base layer 300 such as a substrate or a wiring layer used for WLP or the like.
  • the base layer 300 includes the silicon substrate 12 illustrated in FIG. 2C, the wiring layer (the chip extraction electrode 18 and the wiring 16), and the passivation layer 20.
  • the photosensitive insulating resin 310 is exposed using a grating mask 320.
  • the grating mask 320 includes a plurality of transmission regions having different light transmittances.
  • a plurality of regions having respective light transmittances of (0), (0.3), (0.5), (0.7), and (1) are formed on the grating mask 320.
  • the light transmittance of (0) means that the photosensitive insulating resin 310 is not substantially exposed to light.
  • FIG. 16C a plurality of openings 312 having different thicknesses of the insulating resin are formed in the photosensitive insulating resin 310 in accordance with the respective exposure amounts. .
  • FIG. 16C a plurality of openings 312 having different thicknesses of the insulating resin are formed in the photosensitive insulating resin 310 in accordance with the respective exposure amounts. .
  • a metal layer 330 is formed so as to cover the photosensitive insulating resin 320, and thereafter, a planarization process is performed on a surface K1 having a height h1 from the main surface of the base layer 300.
  • a plurality of metal wirings 332 having different film thicknesses as shown in FIG.
  • the wiring resistance value of each of the plurality of metal wirings 332 can be adjusted. This is because the wiring resistance value depends on the cross-sectional area if the line width is the same.
  • the film thickness of the metal wiring 332 is appropriately selected according to the environment to be used (electric characteristic specifications and reliability specifications for which each of the plurality of metal wirings 332 is required).
  • the grating mask 320 can be replaced with a halftone mask.
  • the formation of the metal layer 330 is performed using physical vapor deposition or electrolytic plating as in the first and second embodiments.
  • the flattening process is performed using at least one of grinding, polishing, and cutting.
  • As the material of the insulating resin 310 all materials disclosed in the first and second embodiments can be applied.
  • FIG. 17 is a diagram for explaining a modification of the third embodiment of the present invention.
  • a photosensitive insulating resin 310A is applied on a base layer 300 such as a substrate or a wiring layer used for WLP or the like.
  • the photosensitive insulating resin 310A is exposed using the mask 320A.
  • the grating mask 320A is continuously formed with transmissive regions having different light transmittances.
  • the light transmittance is (1), (0.7), (0.5), (0.3) in the right direction from the viewpoint of the region where the photosensitive insulating resin 310 is substantially exposed. Are arranged in such a manner that the light transmittance is increased (or decreased) in one direction.
  • the photosensitive insulating resin 310A is developed, as shown in FIG. 17C, the photosensitive insulating resin 310A is formed with an opening 314 whose film thickness changes stepwise.
  • a metal layer 330 is formed as shown in FIG. 17D, and planarization is performed on the surface K1 having a height h1 from the main surface of the base layer 300, as shown in FIG.
  • Metal wirings 332A having different film thicknesses can be formed in the openings 314.
  • the metal layer 332A For the formation of the metal layer 332A, physical vapor deposition may be used as in the first and second embodiments.
  • the flattening process is performed using at least one of grinding, polishing, and cutting as in the first and second embodiments.
  • a solder resist is formed, and then, for example, it is formed in the vicinity of reference numeral 332A described in FIG. 17E so that the external terminal is connected to the metal layer 332A.
  • the light transmittance of the grating mask 320A changes linearly (analog value; analog method)
  • the remaining film thickness of the opening 314 is linear (slope) as shown in FIG.
  • the film thickness of the corresponding metal wiring 332A can be changed more linearly.
  • the formation height of the metal layer 332A is controlled to be lower than the height h1, the thickness of the metal wiring 332A can be made constant while being linear.
  • FIG. 18A corresponds to FIG. 17F, and shows a three-dimensional view of the metal wiring 332B obtained when the photosensitive insulating resin 310A is exposed using the grating mask 320A as in the third embodiment. It is represented by a perspective view.
  • the opening 352 formed in the photosensitive insulating resin 350 is connected to the contact hole 352A reaching the conductive region 342 formed in the main surface of the base layer 340 and the contact hole 352A. If the groove 352B has a uniform depth when the groove 352B for forming the wiring is provided, a substantially perpendicular step is formed at the boundary with the contact hole 353A. In this case, as shown in FIG.
  • the metal wiring 360 is formed with a film thickness that follows the step at a right angle at a substantially right step corner portion.
  • the photosensitive insulating resin 350 such as polyimide shrinks its volume by baking, a stress P obtained by combining the stress Px in the X direction and the stress Py in the Y direction is generated in the corner portion 362 of the metal wiring 360. Therefore, from the viewpoint of reliability, “disconnection of the metal wiring 360 or destruction of the insulating resin 350 or deterioration of the adhesion between the metal wiring 360 and the insulating resin 350” related to the resultant force P must be examined.
  • the inclination of the corner portion is made gentle by providing an inclination to at least a part of the side surface (cross section) of the opening of the photosensitive insulating resin 310A as in this embodiment.
  • the stress P generated in the corner portion can be reduced.
  • the stress P can be reduced.
  • the step shape of FIG. 17 (E) and the slope shape of FIG. 17 (F), FIG. 18 (A) and FIG. 18 (D) are from the viewpoint of moisture resistance. Also improve the reliability.
  • an external terminal (not shown) is formed at the place where the reference numeral 332B in FIG. 17F is described, similarly to the external terminal 70 shown in FIG.
  • a solder resist is formed on the entire surface of the substrate other than the external terminals.
  • moisture enters from the boundary between the external terminal or the external terminal and the solder resist, and the chip take-out electrode (not shown; To the chip take-out electrode 18 shown in FIG. Finally, the chip takeout electrode is corroded.
  • the semiconductor device of the present application is generally connected with its external terminals facing the mother board on the ground side.
  • the external terminal 70 shown in FIG. 3K is in a state where the drawing is rotated 180 degrees. Therefore, the moisture must move in the direction opposite to the direction of gravity through the slope shape (FIG. 17F). In other words, the slope shape suppresses the movement of moisture to the chip extraction electrode.
  • the respective volumes of the metal wiring (metal layer 330) in the slope shape (FIG. 17F) and the metal wiring (metal layer 330) in the step shape (FIG. 17E) are the same as the metal in FIG.
  • the volume of the wiring 360 is larger. Therefore, disconnection of the metal wiring due to corrosion can be suppressed.
  • a fourth embodiment of the present invention will be described. Differences from the third embodiment will be mainly described, and the third embodiment will be applied mutatis mutandis to the substantially overlapping portions.
  • a plurality of conductive regions for example, the wiring 404 and the chip extraction electrode 402 included in the wiring layer are formed on the main surface of the base layer 400, and are photosensitive so as to cover them.
  • An insulating resin 410 is formed.
  • An opening 412 is formed in the photosensitive insulating resin 410 by adjusting the light transmittance of the grating mask.
  • the opening 412 has a first region 412A having a depth reaching the chip extraction electrode 402, a second region 412B having a depth smaller than the depth of the first region 412A, and a depth smaller than the second region 412B. And a third region 412C.
  • the third region 412C is formed at a position overlapping with the wiring 404. Then, as shown in FIG. 19B, when the metal wiring 420 is formed, the metal wiring 420 is electrically connected to the chip extraction electrode 402 and is relatively thick between the wiring 404. The film thickness of the insulating resin 410 remains. Therefore, the parasitic capacitance Cp between the metal wiring 420 and the wiring 404 can be reduced.
  • a fifth embodiment of the present invention will be described. Differences from the third and fourth embodiments will be mainly described, and the third embodiment will be applied mutatis mutandis to the overlapping portions.
  • a conductive region 502 (wiring 502) is formed on the main surface of the base layer 500, and a photosensitive insulating resin 510 is formed so as to cover it.
  • tapers having various shapes are formed on the side surface 512A of the opening 512 of the photosensitive insulating resin 510. be able to.
  • a positive taper is formed on the side surface 512A.
  • a metal layer is formed on the entire surface, and the surface is flattened to form a metal wiring 520 having a reverse taper (inverted triangle) corresponding to the normal taper of the insulating resin 510 as shown in FIG. Is done.
  • the capacitive coupling area facing the conductive region 502 is reduced, and the parasitic capacitance Cp is reduced.
  • the width of the metal wiring 520 is increased upward along the taper, the current density of the metal wiring 520 can be improved and the resistance of the wiring 502 can be reduced.
  • the taper can be applied in various shapes such as a triangle, a trapezoid, a semicircle, and a semi-elliptical shape. Further, by controlling the light transmittance of the grating mask in, for example, a matrix shape or an array shape so as to realize a checker pattern, the taper line segment is further uneven, that is, the surface of the insulating resin 510 is uneven (patternedpatternindented). Surface) is also useful.
  • the surface of the metal wiring 520 that is in surface contact with the insulating resin 510 has an uneven shape corresponding to the uneven shape of the insulating resin 510. Thereby, both adhesiveness improves and the path
  • the surface treatment of the insulating resin 510 can be formed into a concavo-convex shape by chemical treatment such as dry etching.
  • the transmissive region may be formed while repeating a slight increase and decrease in an analog or digital manner in the light transmittance direction from (1) to (0.3). . Further, a minute increase / decrease is developed in the transmissive region in the X and Y directions, respectively, thereby realizing a minute layout pattern having a height difference as shown in FIG. 17A, for example.
  • FIG. 17A shows a checker pattern 310B (protruding positive dod array pattern 310B) in slope-shaped insulating resin 310A.
  • the corresponding metal wiring 332A in the slope shape also has a lattice shape (not shown) corresponding to the checker pattern 310B.
  • the uneven shape of the tapered line segment can also be applied to the step-shaped line segment shown in FIG.
  • the light transmittance is changed from (1) to (0.3) in steps (every (1), every (0.7), (0.5). ), And every (0.3)), the transmission region may be formed while repeating a minute increase / decrease in an analog or digital manner. Further, in the transmission region for each step, a minute increase / decrease is developed in the X and Y directions, thereby realizing a layout pattern similar to FIG. 17A for each step.
  • the positive dod array pattern 310B on the surface of the insulating resin may be a negative dod array pattern.
  • the uneven shape may be a geometric pattern, that is, not limited to a checker pattern, and may be a stripe pattern, for example.
  • FIG. 21A is a diagram corresponding to FIG. 4C described in the first embodiment. Differences from the first to fifth embodiments will be mainly described, and the first to fifth embodiments will be applied mutatis mutandis to the substantially overlapping portions.
  • selected chip take-out electrodes on the main surface on the substrate 12 are commonly connected by a metal layer.
  • FIG. 21B a relatively large amount of light L1 is applied to the regions that are respectively aligned with the two chip extraction electrodes that are to be commonly wired, and a relatively small amount of light L2 is applied to the region where other metal wirings are patterned.
  • the grating mask 40 is configured to irradiate. In the example shown in the figure, the light quantity L1 is applied to the regions that are respectively aligned with the chip extraction electrodes on both sides.
  • the photosensitive polyimide film 30 is developed to form openings 32 corresponding to the light amounts L1 and L2.
  • the opening 32 has a first region 32A that exposes the passivation layer 20 at a position corresponding to each of the chip extraction electrodes on both sides, and a second region that has a depth smaller than the first region 32A and has a predetermined film thickness. And a region 32B. In this state, both ends of the second region 32B are sandwiched between the first regions 32A.
  • the passivation layer 20 is etched using the photosensitive polyimide film 30 as an etching mask. Therefore, a contact hole for exposing the chip take-out electrode is formed at each position matching the plurality of first regions 32A of the passivation layer 20.
  • the subsequent steps are the same as those in the first embodiment.
  • the metal layer 40 is formed on the entire surface of the substrate, and then the surface having a height h1 from the main surface of the substrate 12 is formed. A flattening process is performed at K1.
  • a patterned metal wiring 42A is formed in the opening of the photosensitive polyimide film 30 as shown in FIG. Therefore, the metal wiring 42A electrically connects the chip extraction electrodes on both sides.
  • a semiconductor chip may be provided with a plurality of ground terminals or power supply terminals. In such a case, the two first regions 32A can be interconnected together by the metal wiring 42A.
  • the external terminals are formed without using the “formation of the opening 60A by the patterning of the solder resist” shown in FIG. FIG. 22A corresponds to FIG. 2D of the first embodiment.
  • the grating mask 40 includes a light transmission region where the light transmission amount is L1> L2> L3. However, these light transmission regions are formed continuously.
  • an opening 36 as shown in FIG. 22C is formed.
  • the opening 36 includes a first region 36A having a depth reaching the chip extraction electrode, a second region 36B having a depth smaller than the first region 36A and having a predetermined film thickness, and a second region 36B. And a third region 36C having a predetermined film thickness that is shallower than the region 36B.
  • a solder resist 60 is applied so as to cover the metal layer 50.
  • a planarization process is performed on a surface K1 having a height h1 from the main surface of the substrate 12.
  • the height h1 is a height at which a part of the metal layer 50 on the third region 36C remains and is exposed.
  • solder balls 70 as external terminals are formed on the metal wiring 52.
  • a bonding wire 71 using a bonder may be used instead of the solder ball 70.
  • the exposed region of the metal wiring 52 is substantially equal to the connection area between the solder ball 70 or the bonding wire 71 and the metal wiring 52.
  • the mold resin 73 is further applied so as to seal the bonding wire 71.
  • the mold resin 73 also covers the solder resist 62 and the polyimide film 30 (first insulating layer).
  • Reference numeral 72 denotes a metal material, and a part thereof is exposed to the outside of the semiconductor device 600.
  • the metal material 72 is electrically connected to the bonding wire 71 and thus is electrically connected to the chip extraction electrode 18.
  • the seventh embodiment since it is not necessary to pattern the solder resist by a photolithography process, the number of processes by WLP can be further reduced, and the manufacturing cost can be reduced.
  • the number of processes can be reduced, and reliability can be improved with respect to the insulating layer and the metal wiring layer applied to the upper layer of the passivation layer, which is a severe external environmental condition.
  • the volume amount (cross-sectional area amount) of the metal wiring can be arbitrarily set in consideration of electrical characteristics or reliability.
  • the shape of the opening of the insulating layer in which the metal layer is embedded can be arbitrarily set.
  • the present invention has been described in detail above, but the present invention is not limited to the specific embodiment, and various modifications can be made within the scope of the present invention described in the claims.
  • Deformation / change is possible.
  • the step structure for example, FIG. 17 (E)
  • the slope structure for example, FIG. 17 (F), FIG. 18 (D)
  • the parasitic capacitance Cp disclosed in the fourth embodiment are used.
  • the structure to be reduced for example, FIG. 19B
  • the structure to reduce the parasitic capacitance Cp disclosed in the fifth embodiment for example, FIG. 20B
  • the sixth embodiment for example, FIG. 21.
  • Each of (E)) can be applied to at least one of the structure of the first layer and the structure of the second layer in the structure of the two-layer wiring disclosed in the second embodiment (for example, FIG. 6E).
  • the structure disclosed in the seventh embodiment can be applied to the structure of the second layer in the structure of the two-layer wiring disclosed in the second embodiment (for example, FIG. 6E).
  • Each of the structures disclosed in the third to seventh embodiments includes a fan-in type CSP semiconductor device (for example, FIG. 11) and a fan-out type CSP semiconductor device (for example, FIG. 15D). Applicable to each.

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Abstract

This semiconductor device is provided with, for instance: a substrate (12) that includes a circuit element; a chip leading out electrode (18), which is electrically connected to the circuit element, and which is formed on the surface of the substrate; a passivation layer (20) that covers the chip leading out electrode; an insulating resin (30), which covers the passivation layer (20), and which has a first opening formed therein; metal wiring (52), which is formed in the first opening, and which is electrically connected to the chip leading out electrode; and an external terminal (70), which is formed on the surface of the metal wiring (52). The first opening includes a first region (52A) having a first depth, and a second region (52B) having a second depth, which is less than the first depth, and at which the photosensitive insulating resin (30) is left, and the metal wiring (52) is formed in the first and the second regions.

Description

半導体装置およびその製造方法Semiconductor device and manufacturing method thereof
　本発明は、半導体装置およびその製造方法に関し、特に、半導体装置の外部端子の構造および外部端子の形成方法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a structure of an external terminal of the semiconductor device and a method of forming the external terminal.
　電子機器の小型化、軽量化に伴い、そこに表面実装される半導体装置のスペースも制限されている。このため、半導体装置は、半導体チップをチップサイズでパッケージ化したチップサイズパッケージ（Chip Size Package:ＣＳＰ）で構成されるものが多い。典型的なＣＳＰは、半導体チップをリードフレームまたはインターポーポーザに搭載し、ボンディングワイヤまたはフリップチップにより電気的接続を行い、リードフレームまたはインターポーザを介してＢＧＡ（Ball
grid Array）またはＬＧＡ(Land Grid Array)などの外部端子が接続される。また、ＣＳＰの生産効率を向上させるため、ウエハーレベルパッケージ（Wafer
level Package：ＷＬＰ）による製造が行われている。 As electronic devices become smaller and lighter, space for semiconductor devices mounted on the surface of the electronic devices is also limited. For this reason, many semiconductor devices are configured by a chip size package (CSP) in which semiconductor chips are packaged in a chip size. In a typical CSP, a semiconductor chip is mounted on a lead frame or an interposer, and an electrical connection is made by a bonding wire or a flip chip.
External terminals such as grid array (LGA) or land grid array (LGA) are connected. In order to improve the production efficiency of CSP, wafer level package (Wafer
Level Package (WLP) is being manufactured.
　ＷＬＰの第１の製造形態は、パッシベーション膜が形成された半導体チップの集合体を、そのパッシベーション膜の開口部に対応するチップパッド（チップ取り出し電極）に電気的にカップリングする配線（再配線と呼ばれることもある）、外部端子（ソルダーボール、ボンディングワイヤ、等）、等を形成し、その後に、個々のＣＳＰを得るためにウエハーをダイシングして独立した複数の半導体装置を得る。ＷＬＰの第２の製造形態は、パッシベーション膜が形成された半導体チップの集合体をダイシングして独立した複数のチップを得、それら複数の半導体チップのそれぞれ周囲を絶縁樹脂で封止すると共に、夫々対応するパッシベーション膜の開口部に対応するチップパッドに電気的にカップリングする配線（再配線と呼ばれることもある）、外部端子、等を形成する。尚、半導体チップには、少なくとも、半導体基板（基板）、トランジスタ等の電子回路（回路素子）、電気回路に電源や信号を供給する内部配線、電子回路が含む複数の電気ノードや複数の内部配線の独立を保障する絶縁材、パッシベーション材、を含む。前記トランジスタは、半導体基板に含まれるか、半導体基板上に３次元構造として積層される。前記複数の内部配線は、主に半導体基板上に多層の配線層として形成される。前記パッシベーション材は、前記多層の配線層の最上層の更に上層に半導体チップを保護する絶縁層である。パッシベーションの機能は、半導体チップを、水分、可動イオン、等の汚染から保護してデバイスの信頼性を高める。 A first manufacturing form of WLP is a wiring (rewiring and rewiring) that electrically couples an assembly of semiconductor chips on which a passivation film is formed to a chip pad (chip take-out electrode) corresponding to the opening of the passivation film. In some cases, external terminals (solder balls, bonding wires, etc.) are formed, and then the wafer is diced to obtain individual semiconductor devices to obtain individual CSPs. In the second manufacturing form of WLP, an assembly of semiconductor chips on which a passivation film is formed is diced to obtain a plurality of independent chips, and each of the plurality of semiconductor chips is sealed with an insulating resin, respectively. A wiring (sometimes referred to as rewiring), an external terminal, and the like that are electrically coupled to the chip pad corresponding to the opening of the corresponding passivation film are formed. The semiconductor chip includes at least a semiconductor substrate (substrate), an electronic circuit (circuit element) such as a transistor, internal wiring for supplying power and signals to the electrical circuit, a plurality of electrical nodes and a plurality of internal wirings included in the electronic circuit. Insulation material that ensures independence, and passivation material. The transistor is included in a semiconductor substrate or stacked as a three-dimensional structure on the semiconductor substrate. The plurality of internal wirings are mainly formed as a multilayer wiring layer on a semiconductor substrate. The passivation material is an insulating layer that protects the semiconductor chip on the uppermost layer of the multilayer wiring layer. The passivation function increases the reliability of the device by protecting the semiconductor chip from contamination such as moisture and mobile ions.
　ＷＬＰにおいて、フォトリソ工程を用いて半田ボール等の外部端子を形成すると、製造コストが高くなるため、フォトリソ工程に代えてイオンプレーティング法により外部端子を形成する、安価な製造方法が開示されている（特許文献１、２、３）。 In WLP, if an external terminal such as a solder ball is formed using a photolithography process, the manufacturing cost increases. Therefore, an inexpensive manufacturing method is disclosed in which an external terminal is formed by an ion plating method instead of the photolithography process. ( Patent Documents 1, 2, and 3).
　平坦化の技術として、切削（特許文献４）、研削（特許文献５）、研磨（特許文献６）がそれぞれ開示されている。特許文献４については、発明を実施するための形態において、比較例として後述する。 Cutting (Patent Document 4), grinding (Patent Document 5), and polishing (Patent Document 6) are disclosed as flattening techniques. Patent Document 4 will be described later as a comparative example in the embodiment for carrying out the invention.
　多階調マスクには、グレイトーンマスク（特許文献７）とハーフトーンマスク（特許文献８）の２種類がある。グレイトーンマスクは、一例として露光機の限界解像度以下のスリット部を作り、そのスリット部が光の一部を遮り、中間露光を実現するものである。一方、ハーフトーンマスクは、一例として半透過の膜を利用し、中間露光を行うものである。いずれも、１回の露光で露光部分、中間露光部分、未露光部分の３つの露光レベルを表現し、現像後に２種類の厚さのレジスト膜を作ることができる。 There are two types of multi-tone masks, a gray tone mask (Patent Document 7) and a halftone mask (Patent Document 8). As an example, the gray tone mask creates a slit portion having a resolution lower than the limit resolution of the exposure machine, and the slit portion blocks a part of light to realize intermediate exposure. On the other hand, the halftone mask performs intermediate exposure using a semi-transmissive film as an example. In any case, three exposure levels of an exposed portion, an intermediate exposed portion, and an unexposed portion can be expressed by one exposure, and two types of resist films can be formed after development.
特許第４５８９４５０号Japanese Patent No. 4589450 特許第４７９９６７９号Japanese Patent No. 4799679 特許第４７３８５４１号Japanese Patent No. 4738541 欧州特許出願公開第２０７５８２５号European Patent Application No. 2075825 特開２０００－２７７６０８号公報JP 2000-277608 A 特開２００６－２１６７６８号公報JP 2006-216768 A 特開２００８－０８９８１７号公報（米国特許登録第７８２９２４７号）JP 2008-089817 A (US Patent Registration No. 7829247) 特表２０１０－５２７０２９号公報（米国特許登録第８１３３６４１号）　尚、特許文献１～８のそれぞれを本発明書に盛り込み、特許文献１～８のそれぞれが開示する内容を本明細書の開示の一部とする。JP 2010-527029 A (US Patent Registration No. 81333641) Each of Patent Documents 1 to 8 is incorporated in the present invention, and the contents disclosed by each of Patent Documents 1 to 8 are disclosed in the present specification. Part.
　本発明は、更なる製造コストを低減した半導体装置及びその製造方法を開示し、一つの実施形態として、半導体装置としてのウエハーレベルパッケージ及びその製造方法を開示する。 The present invention discloses a semiconductor device and a manufacturing method thereof with further reduced manufacturing costs, and discloses a wafer level package as a semiconductor device and a manufacturing method thereof as one embodiment.
　本発明に係る半導体装置は、例えば、回路素子を含む基板と、前記回路素子に電気的にカップリングする第１の金属配線を含み、前記基板の表面に形成される第１の金属層と、前記第１の金属層を覆う第１の絶縁材で形成されるパッシベーション層と、前記パッシベーション層を覆う第２の絶縁材で形成され、第１の開口部を含む第１の絶縁層と、前記第１の開口部に形成され、前記第１の金属配線に電気的にカップリングする第２の金属配線を含む第２の金属層と、前記第２の金属配線に電気的にカップリングし、前記第２の金属配線の表面に形成される外部端子と、を備え、前記第１の開口部は、第１の深度を有する第１の領域と、前記第１の深度よりも浅く前記第１の絶縁層を残存させる深度である第２の深度を有する第２の領域と、を含み、前記第２の金属配線は前記第１及び第２の領域に形成される。 A semiconductor device according to the present invention includes, for example, a substrate including a circuit element, a first metal wiring electrically coupled to the circuit element, and a first metal layer formed on the surface of the substrate; A passivation layer formed of a first insulating material covering the first metal layer; a first insulating layer formed of a second insulating material covering the passivation layer and including a first opening; A second metal layer including a second metal wiring formed in the first opening and electrically coupled to the first metal wiring; and electrically coupled to the second metal wiring; An external terminal formed on a surface of the second metal wiring, wherein the first opening has a first region having a first depth, and the first region is shallower than the first depth. A second region having a second depth that is a depth at which the insulating layer of the second layer remains. Wherein the second metal wiring is formed on the first and second regions.
　本発明に係る半導体装置の製造方法は、例えば、回路素子が形成された基板の表面に、前記回路素子に電気的にカップリングする第１の金属配線を含む第１の金属層を形成し、前記第１の金属層を覆う第１の絶縁材で形成されるパッシベーション層を形成し、前記パッシベーション層を覆う第２の絶縁材で形成され、第１の開口部を含む第１の絶縁層を形成し、前記第１の開口部に形成され、前記第１の金属配線に電気的にカップリングする第２の金属配線を含む第２の金属層を形成し、前記第２の金属配線に電気的にカップリングし、前記第２の金属配線の表面にカップリングする外部端子を形成し、前記第１の開口部の形成は、第１の深度を有する第１の領域と、前記第１の深度よりも浅く前記第１の絶縁層を残存させる深度である第２の深度を有する第２の領域と、を同時に形成し、前記第２の金属配線は、前記第１及び第２の領域に形成する。 In the method of manufacturing a semiconductor device according to the present invention, for example, a first metal layer including a first metal wiring electrically coupled to the circuit element is formed on the surface of the substrate on which the circuit element is formed. Forming a passivation layer formed of a first insulating material covering the first metal layer; forming a first insulating layer formed of a second insulating material covering the passivation layer and including a first opening; Forming a second metal layer including a second metal wiring formed in the first opening and electrically coupled to the first metal wiring, and electrically connecting the second metal wiring to the second metal wiring; An external terminal for coupling to the surface of the second metal wiring, and forming the first opening includes a first region having a first depth, A depth at which the first insulating layer remains to be shallower than a depth. A second region having a depth, and simultaneously forming the second metal wiring is formed in the first and second regions.
　本発明によれば、更なる製造コストを低減した半導体装置及びその製造方法を提供することができる。 According to the present invention, it is possible to provide a semiconductor device with a further reduced manufacturing cost and a manufacturing method thereof.
ＷＬＰにより構成された半導体パッケージの模式的な平面図である。It is a typical top view of the semiconductor package comprised by WLP. 図２（Ａ）ないし（Ｆ）は、本発明の第１の実施例によるＷＬＰの工程を説明する図１のＸ－Ｘ線断面図である。2A to 2F are cross-sectional views taken along the line XX of FIG. 1 for explaining the steps of the WLP according to the first embodiment of the present invention. 図３（Ｇ）ないし（Ｋ）は、本発明の第１の実施例によるＷＬＰの工程を説明する図１のＸ－Ｘ線断面図である。FIGS. 3G to 3K are cross-sectional views taken along the line XX of FIG. 1 for explaining the steps of the WLP according to the first embodiment of the present invention. 図４（Ａ）ないし（Ｆ）は、本発明の第１の実施例によるＷＬＰの他の工程を説明する図である。4A to 4F are diagrams for explaining other steps of the WLP according to the first embodiment of the present invention. 図５（Ａ）ないし（Ｄ）は、本発明の第２の実施例によるＷＬＰの工程を説明する断面図である。FIGS. 5A to 5D are cross-sectional views illustrating a process of WLP according to the second embodiment of the present invention. 図６（Ｅ）ないし（Ｇ）は、本発明の第２の実施例によるＷＬＰの工程を説明する断面図である。6E to 6G are cross-sectional views illustrating a process of WLP according to the second embodiment of the present invention. 本発明の第１および２の実施例によるＷＬＰの工程と従来のＷＬＰの工程と比較するフローである。5 is a flowchart comparing the WLP process according to the first and second embodiments of the present invention and the conventional WLP process. 図８（Ａ）は、ファンインタイプのＣＳＰの模式的な平面図、図８（Ｂ）、（Ｃ）は、本発明の第１または第２の実施例によるファンインタイプのＷＬＰの工程を説明する平面図とその断面図である。FIG. 8A is a schematic plan view of a fan-in type CSP, and FIGS. 8B and 8C are diagrams showing a process of a fan-in type WLP according to the first or second embodiment of the present invention. It is the top view to explain and its sectional drawing. 図９（Ａ）ないし（Ｄ）は、本発明の第１または第２の実施例によるファンインタイプのＷＬＰの工程を説明する平面図とその断面図である。FIGS. 9A to 9D are a plan view and a cross-sectional view for explaining a process of a fan-in type WLP according to the first or second embodiment of the present invention. 図１０（Ａ）ないし（Ｄ）は、本発明の第１または第２の実施例によるファンインタイプのＷＬＰの工程を説明する平面図とその断面図である。FIGS. 10A to 10D are a plan view and a cross-sectional view illustrating a process of fan-in type WLP according to the first or second embodiment of the present invention. 図１１（Ａ）、（Ｂ）は、本発明の第１または第２の実施例によるファンインタイプのＷＬＰの工程を説明する平面図とその断面図である。FIGS. 11A and 11B are a plan view and a cross-sectional view illustrating a process of fan-in type WLP according to the first or second embodiment of the present invention. 図１２（Ａ）ないし（Ｅ）は、本発明の第１または第２の実施例によるファンアウトタイプのＷＬＰ用基板の製造例を説明する断面図である。12A to 12E are cross-sectional views illustrating an example of manufacturing a fan-out type WLP substrate according to the first or second embodiment of the present invention. 図１３（Ａ）は、ファンアウトタイプのＣＳＰの模式的な平面図、図１３（Ｂ）、（Ｃ）は、本発明の第１または第２の実施例によるファンアウトタイプのＷＬＰの工程を説明する平面図とその断面図である。FIG. 13 (A) is a schematic plan view of a fan-out type CSP, and FIGS. 13 (B) and (C) show the steps of the fan-out type WLP according to the first or second embodiment of the present invention. It is the top view to explain and its sectional drawing. 図１４（Ａ）ないし（Ｄ）は、本発明の第１または第２の実施例によるファンアウトタイプのＷＬＰの工程を説明する平面図とその断面図である。FIGS. 14A to 14D are a plan view and a cross-sectional view illustrating a process of fan-out type WLP according to the first or second embodiment of the present invention. 図１５（Ａ）ないし（Ｄ）は、本発明の第１または第２の実施例によるファンアウトタイプのＷＬＰの工程を説明する平面図とその断面図である。FIGS. 15A to 15D are a plan view and a cross-sectional view for explaining a process of a fan-out type WLP according to the first or second embodiment of the present invention. 図１６（Ａ）ないし（Ｆ）は、本発明の第３の実施例によるＷＬＰの工程を説明する断面図である。FIGS. 16A to 16F are cross-sectional views for explaining a process of WLP according to the third embodiment of the present invention. 図１７（Ａ）ないし（Ｆ）は、本発明の第３の実施例によるＷＬＰの他の工程を説明する断面図である。17A to 17F are cross-sectional views illustrating other steps of WLP according to the third embodiment of the present invention. グレイティングマスクによる他のレイアウトパターンの例を示す図である。It is a figure which shows the example of the other layout pattern by a grating mask. 図１８（Ａ）ないし（Ｅ）は、本発明の第３の実施例による工程を用いたときの利点を説明する図である。FIGS. 18A to 18E are views for explaining advantages when using the process according to the third embodiment of the present invention. 図１９（Ａ）、（Ｂ）は、本発明の第４の実施例によるＷＬＰの工程を説明する断面図である。FIGS. 19A and 19B are cross-sectional views illustrating the process of WLP according to the fourth embodiment of the present invention. 図２０（Ａ）、（Ｂ）は、本発明の第５の実施例によるＷＬＰの工程を説明する断面図である。20A and 20B are cross-sectional views for explaining a process of WLP according to the fifth embodiment of the present invention. 図２１（Ａ）ないし（Ｅ）は、本発明の第６の実施例によるＷＬＰの工程を説明する断面図である。21A to 21E are cross-sectional views for explaining a process of WLP according to the sixth embodiment of the present invention. 図２２（Ａ）ないし（Ｄ）は、本発明の第７の実施例によるＷＬＰの工程を説明する断面図である。22A to 22D are cross-sectional views for explaining a process of WLP according to the seventh embodiment of the present invention. 図２３（Ｅ）ないし（Ｈ）は、本発明の第７の実施例によるＷＬＰの工程を説明する断面図である。FIGS. 23E to 23H are cross-sectional views for explaining a process of WLP according to the seventh embodiment of the present invention. 本発明の第１の実施例によるＷＬＰの工程を説明する図１のＹ－Ｙ線断面図の第１例である。FIG. 3 is a first example of a cross-sectional view taken along line YY of FIG. 1 for explaining a process of WLP according to the first embodiment of the present invention. 本発明の第１の実施例によるＷＬＰの工程を説明する図１のＹ－Ｙ線断面図の第２例である。FIG. 5 is a second example of the YY sectional view of FIG. 1 for explaining the process of WLP according to the first embodiment of the present invention. 本発明の各実施形態に利用する各種樹脂の一例および金属の一例のそれぞれの物性値を示す表である。It is a table | surface which shows each physical-property value of an example of various resin utilized for each embodiment of this invention, and an example of a metal. 絶縁性の感光性ポリイミド膜３０に生じるクレーズ（Craze）の例を示す模式図である。3 is a schematic view showing an example of craze generated in the insulating photosensitive polyimide film 30. FIG. 図２８（ａ）、（ｂ）は、各種樹脂の応力－歪み曲線を示すグラフである。28 (a) and 28 (b) are graphs showing stress-strain curves of various resins. 図２９（ａ）、（ｂ）は、図３（Ｇ）の高さｈ１における切削を斜視的に見た模式図である。FIGS. 29A and 29B are schematic views of the cutting at the height h1 in FIG.
　以下、本発明を実施するための形態を、図面を参照して説明する。好ましい形態では、本発明に係る半導体装置及びその製造方法の一例は、前述した第１又は第２の製造形態がそれぞれ含む複数の製造工程の少なくとも一部の製造工程に関連するＷＬＰに適用される。また、本発明に係る半導体装置の一例は、そのようなＷＬＰから得られる製造物である。但し、本発明は、必ずしもＷＬＰに関連する半導体装置、及びその製造方法に限定されるものではなく、ＷＬＰ以外の個々の半導体装置、及びそれを製造する方法であってもよい。つまり本発明は、半導体装置及びその製造方法に広く適用されるものである。なお、図面のスケール、及び各エレメント同士の比率は、発明の特徴を分かり易くするために強調されており、必ずしも実際のデバイスのスケール及び前記比率と同一ではないことに留意すべきである。 Hereinafter, modes for carrying out the present invention will be described with reference to the drawings. In a preferred embodiment, an example of a semiconductor device and a manufacturing method thereof according to the present invention is applied to a WLP related to at least a part of a plurality of manufacturing steps included in the first or second manufacturing mode described above. . An example of the semiconductor device according to the present invention is a product obtained from such WLP. However, the present invention is not necessarily limited to the semiconductor device related to WLP and the manufacturing method thereof, and may be an individual semiconductor device other than WLP and a method of manufacturing the same. That is, the present invention is widely applied to semiconductor devices and manufacturing methods thereof. It should be noted that the scale of the drawing and the ratio of each element are emphasized for easy understanding of the features of the invention, and are not necessarily the same as the actual device scale and the ratio.
　図１は、本発明の第１の実施例に係る製造方法を用いて構成された半導体装置に関連する半導体チップの概略平面図（半導体装置の外部端子から見た平面図）であり、ここには半導体ウエハー上の１つの半導体チップが例示されている。半導体ウェハ（不図示）は、複数の半導体チップを含む。ウエハー上の１つの半導体チップ１０（半導体装置１０）は、矩形状の外形１０Ａによって表される。半導体チップ１０は、シリコン基板１２を含み、シリコン基板１２の一方の主面１２Ａには複数の回路素子１４が形成されている。シリコン基板１２は、シリコン材に限られずその他の材料であってもよい。回路素子１４は、例示としてトランジスタ等の電子回路である。図１には、２つの回路素子１４が例示されている。シリコン基板１２の主面１２Ａには、単層もしくは多層の配線１６が形成され、配線１６は、回路素子１４とチップ取り出し電極１８との間の電気的経路を構成する。チップ取り出し電極１８は、所謂チップパッドである。チップ取り出し電極１８は、最上層の配線１６の一部の領域をパッシベーション層により露出することにより形成してもよいし、配線１６上に別途、金属層を形成するようにしてもよい。このような半導体チップ１０は、ウエハー上に多数形成されており、パッシベーション層（パッシベーション材）によって、シリコン基板１２及び配線１６が保護される。これまでの構造が、所謂半導体の前工程で製造される。この後、これらの半導体チップの主面１２Ａに、後述するようにＷＬＰの工程により金属パターン５２および外部端子７０が形成される。外部端子７０は、ソルダーボール、ボンディングワイヤ、等であり、それらの形状、材質は、問わない。つまり、ＷＬＰの工程は、前工程で製造されたチップ取り出し電極１８（チップパッド）を、半導体装置としての外部端子７０へ、再配線としての金属パターン５２によって電気的に接続する。 FIG. 1 is a schematic plan view of a semiconductor chip related to a semiconductor device configured by using the manufacturing method according to the first embodiment of the present invention (plan view seen from an external terminal of the semiconductor device). 1 illustrates one semiconductor chip on a semiconductor wafer. A semiconductor wafer (not shown) includes a plurality of semiconductor chips. One semiconductor chip 10 (semiconductor device 10) on the wafer is represented by a rectangular outer shape 10A. The semiconductor chip 10 includes a silicon substrate 12, and a plurality of circuit elements 14 are formed on one main surface 12 </ b> A of the silicon substrate 12. The silicon substrate 12 is not limited to a silicon material and may be other materials. The circuit element 14 is an electronic circuit such as a transistor as an example. FIG. 1 illustrates two circuit elements 14. A single-layer or multi-layer wiring 16 is formed on the main surface 12A of the silicon substrate 12, and the wiring 16 constitutes an electrical path between the circuit element 14 and the chip extraction electrode 18. The chip extraction electrode 18 is a so-called chip pad. The chip extraction electrode 18 may be formed by exposing a partial region of the uppermost wiring 16 with a passivation layer, or a metal layer may be separately formed on the wiring 16. A large number of such semiconductor chips 10 are formed on a wafer, and the silicon substrate 12 and the wiring 16 are protected by a passivation layer (passivation material). The structure so far is manufactured in a so-called semiconductor pre-process. Thereafter, the metal pattern 52 and the external terminal 70 are formed on the main surface 12A of these semiconductor chips by a WLP process as will be described later. The external terminals 70 are solder balls, bonding wires, etc., and their shapes and materials are not limited. That is, in the WLP process, the chip extraction electrode 18 (chip pad) manufactured in the previous process is electrically connected to the external terminal 70 as the semiconductor device by the metal pattern 52 as the rewiring.
　図２および図３は、本発明の第１の実施例に係るＷＬＰの製造工程を説明する概略断面図であり、図１のＸ－Ｘ線断面を表している。図２（Ａ）を参照すると、シリコン基板１２（基板）は、シリコン材１２－１と多層配線部１２－２を含んで構成される。シリコン材１２－１は、回路素子１４を含む。多層配線部１２－２は、回路素子１４と配線１６を電気的に接続する互いに積層する複数の内部配線（複数の内部配線層）、及び前記複数の内部配線を電気的に絶縁する絶縁材（絶縁層）を含む多層構造である。図示においては簡素化して表記している。これら多層構造においては、周知のダマシン（Damascene）技術が用いられてもよい。チップ取り出し電極１８、配線１６は、同一の配線層（第１の金属層）に含まれる。前記同一の配線層は、前記複数の内部配線層に最上層の配線層として位置づけられる。前記複数の内部配線層は、前記多層配線部１２－２に含まれる。この明細書においては、発明の特徴を構成する複数のエレメントのうちの一つのエレメントである前記同一の配線層（チップ取り出し電極１８及び配線１６）を、シリコン基板１２の主面１２Ａに表記している。つまり、発明を実現する実施例の構造を理解しやすいように、簡素化して表記している。シリコン基板１２の主面１２Ａには、上記したように、チップ取り出し電極１８、配線１６が形成されている。チップ取り出し電極１８は、例えば、Ａｌ、Ａｕ、Ｃｕ等の導電性金属材料から構成される。以降の図面においては、シリコン材１２－１、多層配線部１２－２、内部配線、及び回路素子１４は、図示が省略される。次いで、図２（Ｂ）に示すように、基板全面に、窒化シリコン（Ｓｉ３Ｎ４）などからなるパッシベーション層２０が所定の膜厚で形成される。図面においては、パッシベーション層２０が凹凸（convex-concave）の形状であるが、平坦化されたパッシベーション層２０であってもよい。次いで、図２（Ｃ）に示すように、公知のフォトリソ工程を用いてチップ取り出し電極１６を露出させる開口２０Ａが形成される。 2 and 3 are schematic cross-sectional views for explaining a process for manufacturing a WLP according to the first embodiment of the present invention, and represent a cross section taken along line XX of FIG. Referring to FIG. 2A, the silicon substrate 12 (substrate) includes a silicon material 12-1 and a multilayer wiring part 12-2. The silicon material 12-1 includes the circuit element 14. The multilayer wiring portion 12-2 includes a plurality of internal wirings (a plurality of internal wiring layers) that are stacked to electrically connect the circuit elements 14 and the wirings 16, and an insulating material that electrically insulates the plurality of internal wirings ( Insulating layer). In the drawing, the description is simplified. In these multilayer structures, a well-known damascene technique may be used. The chip extraction electrode 18 and the wiring 16 are included in the same wiring layer (first metal layer). The same wiring layer is positioned as the uppermost wiring layer in the plurality of internal wiring layers. The plurality of internal wiring layers are included in the multilayer wiring portion 12-2. In this specification, the same wiring layer (chip take-out electrode 18 and wiring 16), which is one of a plurality of elements constituting the features of the invention, is represented on the main surface 12A of the silicon substrate 12. Yes. That is, in order to make it easy to understand the structure of the embodiment for realizing the invention, it is simplified and described. As described above, the chip extraction electrode 18 and the wiring 16 are formed on the main surface 12A of the silicon substrate 12. The chip extraction electrode 18 is made of a conductive metal material such as Al, Au, or Cu, for example. In the subsequent drawings, illustration of the silicon material 12-1, the multilayer wiring portion 12-2, the internal wiring, and the circuit element 14 is omitted. Next, as shown in FIG. 2B, a passivation layer 20 made of silicon nitride (Si 3 N 4 ) or the like is formed on the entire surface of the substrate with a predetermined film thickness. In the drawing, the passivation layer 20 has a convex-concave shape, but may be a planarized passivation layer 20. Next, as shown in FIG. 2C, an opening 20A for exposing the chip extraction electrode 16 is formed by using a known photolithography process.
　次に、図２（Ｄ）に示すように、パッシベーション層２０を覆うように基板全面に、スピンコート等により絶縁性の感光性ポリイミド膜３０（第２の絶縁材であり、第１の絶縁層）が塗布される。感光性ポリイミド膜３０は、ポジ型またはネガ型のいずれであってもよいが、図に示す例は、ポジ型を示している。膜３０は、ポリイミド材に限られず、例えば、フェノール樹脂、不飽和ポリエステル樹脂、メラミン樹脂またはユレア樹脂を主成分とする材料であってもよい。後述する図３（Ｇ）において詳述する。 Next, as shown in FIG. 2D, an insulating photosensitive polyimide film 30 (second insulating material, which is a first insulating layer, is formed on the entire surface of the substrate so as to cover the passivation layer 20 by spin coating or the like. ) Is applied. The photosensitive polyimide film 30 may be either a positive type or a negative type, but the example shown in the figure shows a positive type. The film 30 is not limited to a polyimide material, and may be a material mainly composed of a phenol resin, an unsaturated polyester resin, a melamine resin, or a urea resin, for example. This will be described in detail with reference to FIG.
　次に、図２（Ｅ）に示すように、透過される光量を変化させることができるグレイティングマスク（ハーフトーンマスク）４０を用いて感光性ポリイミド膜３０を露光する。グレイティングマスク４０は、例えば、日立化成ＨＤ－８９１０を用いることができ、透過光量を異ならせることで、感光性ポリイミド膜３０にグレイスケール（段階的）な露光を行うことができ、これにより、現像された感光性ポリイミド膜３０には、露光量に応じた膜厚が残存される。すなわち、より露光量が大きな領域では、残膜厚が小さく、露光量が小さな領域では、残膜厚が厚くなる。 Next, as shown in FIG. 2 (E), the photosensitive polyimide film 30 is exposed using a grating mask (halftone mask) 40 capable of changing the amount of transmitted light. For example, Hitachi Kasei HD-8910 can be used as the grating mask 40, and the photosensitive polyimide film 30 can be subjected to grayscale (stepwise) exposure by varying the amount of transmitted light. In the developed photosensitive polyimide film 30, a film thickness corresponding to the exposure amount remains. That is, the remaining film thickness is small in the region where the exposure amount is larger, and the remaining film thickness is thick in the region where the exposure amount is small.
　図２（Ｅ）の例では、グレイティングマスク４０は、光量Ｌ１を透過する領域、光量Ｌ１よりも小さな光量Ｌ２を透過する領域、遮光領域４０Ａを含み、光量Ｌ１は、パッシベーション層２０の開口２０Ａと整合する領域を露光する。光量Ｌ２は、開口２０Ａから側方に連続する領域であり、後に金属層が形成される領域を露光する。光量Ｌ１は、現像したときにポリイミド膜３０を完全に除去するのに十分な値であり、光量Ｌ２は、ポリイミド膜３０に所定の膜厚を残存させる値である。 In the example of FIG. 2E, the grating mask 40 includes a region that transmits the light amount L1, a region that transmits a light amount L2 that is smaller than the light amount L1, and a light shielding region 40A. The light amount L1 is the opening 20A of the passivation layer 20. Expose areas that are aligned with. The light quantity L2 is an area that continues laterally from the opening 20A, and exposes an area in which a metal layer will be formed later. The light amount L1 is a value sufficient to completely remove the polyimide film 30 when developed, and the light amount L2 is a value that leaves a predetermined film thickness on the polyimide film 30.
　次に、感光性ポリイミド膜３０が現像される。図２（Ｆ）に示すように、感光性ポリイミド膜３０には、光量に応じて段差のある開口部３２が形成される。開口部３２は、パッシベーション層２０の開口２０Ａと整合する位置に開口２０Ａに到達する深度を有する第１の領域３２Ａと、第１の領域３２Ａよりも深度が小さく第１の領域３２Ａから側方に一定の深さで延在する第２の領域３２Ｂとを有する。好ましくは、第１の領域３２Ａのサイズは、パッシベーション層２０の開口部２０Ａと同程度である。 Next, the photosensitive polyimide film 30 is developed. As shown in FIG. 2 (F), the photosensitive polyimide film 30 is formed with an opening 32 having a step according to the amount of light. The opening 32 has a first region 32A having a depth reaching the opening 20A at a position aligned with the opening 20A of the passivation layer 20, and a depth smaller than the first region 32A and laterally from the first region 32A. And a second region 32B extending at a certain depth. Preferably, the size of the first region 32 </ b> A is approximately the same as the opening 20 </ b> A of the passivation layer 20.
　次に、図３（Ｇ）に示すように、導電性金属材料からなる金属層５０（第２の金属層）が基板全面に成膜される。金属層５０は、必ずしも単一の層に限らず、多層であってもよい。好ましい例では、第１例としてＴｉ、Ｃｕ等のシードメタルを形成し、その後、電界めっきによりＣｕを形成する。第２例としてスパッタ、イオンプレーティング等の物理気相成長によって、Ｔｉ、Ｃｕ等のバリアメタルを成膜し、その後、Ｃｕを成膜してもよい。金属層５０は、パッシベーション層２０の開口２０Ａおよび感光性ポリイミド膜３０の第１の領域３２Ａの開口を充填するのに十分な厚さを有する。 Next, as shown in FIG. 3G, a metal layer 50 (second metal layer) made of a conductive metal material is formed over the entire surface of the substrate. The metal layer 50 is not necessarily a single layer and may be a multilayer. In a preferred example, a seed metal such as Ti or Cu is formed as a first example, and then Cu is formed by electroplating. As a second example, a barrier metal such as Ti or Cu may be formed by physical vapor deposition such as sputtering or ion plating, and then Cu may be formed. The metal layer 50 has a thickness sufficient to fill the opening 20 </ b> A of the passivation layer 20 and the opening of the first region 32 </ b> A of the photosensitive polyimide film 30.
　次に、平坦化処理が行われ、同時に金属層５０がパターンニングされる。金属層５０は、下地の凹凸を反映し、その表面には段差が形成されている。平坦化処理は、研削（grinding）、研磨（polishing）、及び切削（cutting）の少なくともいずれか一つを用いて、金属層５０とその下地のポリイミド膜３０の一部を除去する。研削（grinding）は、砥石などで「物質を削る」。研磨（polishing）は、砥粒などで「物質を磨き削る」。切削（cutting）は、鋭利な刃等で「物質を切り取る」。ＣＭＰ（Chemical
Mechanical Polishing）は、研磨の技術範囲である。研削及び研磨は、ポリイミド膜３０及び金属層５０の上方向から下方向に向かって、面で削る。切削は、ポリイミド膜３０及び金属層５０の側面を視点に（例えば、左から右方向へ）、面で切削する。言い換えれば、基板１２の主面を水平方向に走査される切削刃（bit(beitel)
or a cutting tool）を用いて、切削が行われる。切削刃による場合は、切削刃が面Ｋ１に位置決めされ、それより上のポリイミド膜３０および金属層５０が除去される。したがって、切削刃の高さは、切削工程にわたって一定に保たれる。切削刃による場合は、切削刃が面Ｋ１に位置決めされそれより上のポリイミド膜３０および金属層５０がカッティングされる。高さｈ１の基準点は、基板１２の主面に限られず、シリコン基板の下線（裏面）であってもよい。他方、「研削」・「研磨」は、例えば砥粒を粘結剤で固めた砥石を回転させ、工作物を「削る」、あるいは「磨き削る」ことによって行われます。したがって、砥石の高さは、研削工程にわたって変化する。「研削」・「研磨」による場合は、基板１２の主面から一定の高さｈ１に到達する面Ｋ１まで、金属層５０およびポリイミド膜３０がポリッシングされる。この様に、最終的に同様の工作物が完成するとしても、治具である切削刃および砥石の動き及び削る原理、並びに治具の摩耗原理は、全く異なる。 Next, a planarization process is performed, and the metal layer 50 is patterned at the same time. The metal layer 50 reflects the unevenness of the base, and a step is formed on the surface thereof. In the planarization process, at least one of grinding, polishing, and cutting is used to remove the metal layer 50 and a part of the underlying polyimide film 30. Grinding is “shaving the substance” with a grindstone. Polishing is “polishing material” with abrasive grains. Cutting is “cutting out the substance” with a sharp blade or the like. CMP (Chemical
Mechanical Polishing) is the technical range of polishing. In the grinding and polishing, the polyimide film 30 and the metal layer 50 are cut by a surface from the upper side to the lower side. The cutting is performed by using the side surfaces of the polyimide film 30 and the metal layer 50 as viewpoints (for example, from left to right). In other words, a cutting blade (bit (beitel)) that scans the main surface of the substrate 12 in the horizontal direction.
or a cutting tool). In the case of using a cutting blade, the cutting blade is positioned on the surface K1, and the polyimide film 30 and the metal layer 50 above it are removed. Therefore, the height of the cutting blade is kept constant throughout the cutting process. In the case of using a cutting blade, the cutting blade is positioned on the surface K1, and the polyimide film 30 and the metal layer 50 above it are cut. The reference point of the height h1 is not limited to the main surface of the substrate 12, but may be an underline (back surface) of the silicon substrate. On the other hand, “grinding” and “polishing” are performed, for example, by rotating a grindstone in which abrasive grains are hardened with a binder to “shave” or “shave” the workpiece. Accordingly, the height of the grindstone varies over the grinding process. In the case of “grinding” and “polishing”, the metal layer 50 and the polyimide film 30 are polished from the main surface of the substrate 12 to the surface K1 reaching a certain height h1. In this way, even if a similar workpiece is finally completed, the principles of movement and cutting of the cutting blade and the grindstone, which are jigs, and the wear principle of the jigs are completely different.
　切削（cutting）の技術を適用する場合、膜３０（第２の絶縁材であり、第１の絶縁層）は、ポリイミド材に限られず、例えば、フェノール樹脂、不飽和ポリエステル樹脂、メラミン樹脂またはユレア樹脂を主成分とする材料が好ましい。これら材を適用すれば、切削刃による切削時に切削刃の劣化を抑止する（切削刃の寿命を延ばす）非常に優れた効果を奏する。詳細には、切削刃が面Ｋ１に沿って切削する時（例えば、切削刃が、左から右方向へ走査する時）、切削される材料（工作物）が切削刃に抵抗感を受ける。よって切削刃が磨耗する原因は、第１に、切削される材料の硬度があり、第２に、材料の粘り（すなわち弾性伸びの大きさ）、がある。切削刃が粘りのある材料（工作物）を切削すると、切削刃は、切れていない材料を引きずってしまうためである。この視点において、フェノール樹脂のほか、不飽和ポリエステル樹脂、メラミン樹脂またはユレア樹脂を主成分とする切削される材料（工作物）は、有用である。切削刃による切削は切削時の局部発熱で塑性変形を起こさない、また、切削刃の切れ味を良くするためには、膜３０は、適度な弾性率を持ち、限界応力に対する歪みが小さく強度が比較的低い樹脂が良好と考えるからである。 In the case of applying the cutting technique, the film 30 (second insulating material, first insulating layer) is not limited to the polyimide material, and for example, phenol resin, unsaturated polyester resin, melamine resin, or urea. A material mainly composed of a resin is preferable. When these materials are applied, the cutting blade is prevented from deteriorating (extending the life of the cutting blade) at the time of cutting with the cutting blade. Specifically, when the cutting blade cuts along the surface K1 (for example, when the cutting blade scans from the left to the right), the material to be cut (workpiece) receives a sense of resistance on the cutting blade. Therefore, the cause of wear of the cutting blade is firstly the hardness of the material to be cut, and secondly, the stickiness of the material (that is, the magnitude of elastic elongation). This is because when the cutting blade cuts a sticky material (workpiece), the cutting blade drags an uncut material. In this respect, a material to be cut (workpiece) mainly composed of unsaturated polyester resin, melamine resin or urea resin in addition to phenol resin is useful. Cutting with a cutting blade does not cause plastic deformation due to local heat generation during cutting, and in order to improve the sharpness of the cutting blade, the film 30 has an appropriate elastic modulus, a small distortion with respect to a limit stress, and a strength comparison. This is because a low resin is considered good.
　図２４及び図２５は、切削（cutting）に好ましい実施例のそれぞれの例示として、図１のＹ－Ｙ線断面を表している。 FIG. 24 and FIG. 25 show the YY line cross section of FIG. 1 as an example of each preferred embodiment for cutting.
　図２４において、グレイティングマスク（ハーフトーンマスク）４０を用いてフェノール樹脂４６０を露光する。その後、現像工程にてフェノール樹脂４６０に対応する溝４６２（それは開口部３２に対応する）を形成する。溝４６２に隣接する第１の樹脂４６０（フェノール樹脂４６０）の断面を、基板４５０の面に対してほぼ垂直な長方形とした。かかる第１の樹脂４６０および溝４６２に、金属層５０（第２の金属層）の形成として多層である２層の金属層（相対的に硬度の高い第１の金属４７０と、相対的に硬度の低い第２の金属４８０）を物理気相成長によって成膜した。その結果、図２４に示す成膜状態が得られる。 24, the phenolic resin 460 is exposed using a grating mask (halftone mask) 40. Thereafter, a groove 462 (which corresponds to the opening 32) corresponding to the phenol resin 460 is formed in the development process. The cross section of the first resin 460 (phenol resin 460) adjacent to the groove 462 is a rectangle substantially perpendicular to the surface of the substrate 450. In the first resin 460 and the groove 462, the metal layer 50 (second metal layer) is formed as a multi-layered two-layer metal layer (the first metal 470 having relatively high hardness and the relative hardness. Second metal 480) having a low thickness was deposited by physical vapor deposition. As a result, the film formation state shown in FIG. 24 is obtained.
　第１の金属４７０は、Ｔｉ、Ｃｒ、ＴａまたはＰｄとしてよく、第２の金属４８０は、ＣｕまたはＡｌとしてよい。これら材質から分かるように、バリアメタルとして用いられる第１の金属４７０と、配線メタルとして用いられる第２の金属４８０との間には、硬度の差がある。 The first metal 470 may be Ti, Cr, Ta, or Pd, and the second metal 480 may be Cu or Al. As can be seen from these materials, there is a difference in hardness between the first metal 470 used as a barrier metal and the second metal 480 used as a wiring metal.
　次に、図３（Ｇ）と同様に図２４のバイト４８０の設置を行う。設置工程では、図２４の溝４６２の側面（第１の樹脂４６０の側壁）に成膜された第１の金属４７０が成膜されていない、つまり厚みがゼロの場所に該当する高さである高さＨ０に、切削刃４９０を設置して第１の樹脂４６０および第２の金属４８０を切削する。その結果、図３（Ｈ）に示す中間体が得られる。 Next, the byte 480 in FIG. 24 is installed in the same manner as in FIG. In the installation process, the first metal 470 formed on the side surface (side wall of the first resin 460) of the groove 462 in FIG. 24 is not formed, that is, the height corresponds to a place where the thickness is zero. The cutting blade 490 is installed at the height H0 to cut the first resin 460 and the second metal 480. As a result, the intermediate shown in FIG. 3 (H) is obtained.
　図２４に示すように、第１の樹脂４６０の上面から溝４６２の側面の上部までは、相対的に硬度の高い第１の金属４７０が成膜される。しかし更に下方にゆくに従って第１の樹脂４６０の側面に成膜される第１の金属４７０の厚みは次第に小さくなってゆき、やがてゼロとなる。溝４６２の底と、第１の樹脂４６０の上面と、溝４６２の側面の上部とに成膜された第１の金属４７０の上に、第２の金属４８０が成膜されている。尚、第２の金属４８０は、図３の金属層５０の様に、溝４６２を埋めるように第２の金属４８０を成膜してもよい。尚、第１の樹脂４６０の上面に成膜された第１の金属４７０の厚さと、溝４６２の底部に成膜された第１の金属４７０の厚さとは、ほぼ同じ厚さである。 As shown in FIG. 24, a first metal 470 having a relatively high hardness is formed from the upper surface of the first resin 460 to the upper part of the side surface of the groove 462. However, as it goes further downward, the thickness of the first metal 470 formed on the side surface of the first resin 460 gradually decreases and eventually becomes zero. A second metal 480 is formed on the first metal 470 formed on the bottom of the groove 462, the upper surface of the first resin 460, and the upper part of the side surface of the groove 462. Note that the second metal 480 may be formed to fill the groove 462 like the metal layer 50 in FIG. Note that the thickness of the first metal 470 formed on the upper surface of the first resin 460 and the thickness of the first metal 470 formed on the bottom of the groove 462 are substantially the same.
　（第１の金属が成膜されていない所を切削刃で切削）
　この切削の特徴は、図２４において、第１の金属４７０が成膜されていない、厚みがゼロの場所に該当する高さＨ０の切削ラインに沿って切削刃４９０を設置し、基板４５０の表面に沿って切削刃４９０を走査することによって切削を行うことである。したがって切削刃４９０が切削するのは、最も軟らかい第１の樹脂４６０と、第１の金属４７０よりも相対的に硬度の低い第２の金属４８０の２種類だけである。尚、第２の金属４８０の成膜の厚さは任意であり、切削刃４９０の設置高さＨとは直接的な関連はない。例えば、第２の金属４８０の成膜の厚さが薄い場合、高さＨ０の切削ラインで切削刃４９０が切削するのは、第１の樹脂４６０だけの場合もある。例えば、第２の金属４８０の成膜の厚さが薄い場合、高さＨ１の切削ラインは、溝４６２に形成された第２の金属４８０の表面である場合もある。尚、「最も軟らかい」とは、切削される対象の複数の材料のうちで最も軟らかい材質であるという意味である。尚、切削刃４９０を固定して基板４５０を走査する、または両者をそれぞれ独立して走査する、ことも本願の一つの技術範囲に含まれる。 (Cutting with a cutting blade where the first metal is not deposited)
In FIG. 24, the cutting feature is that a cutting blade 490 is installed along a cutting line having a height H0 corresponding to a place where the thickness of the first metal 470 is not formed and the thickness is zero. The cutting is performed by scanning the cutting blade 490 along the line. Therefore, the cutting blade 490 cuts only the two types of the first resin 460 that is the softest and the second metal 480 that is relatively harder than the first metal 470. It should be noted that the thickness of the second metal 480 is arbitrary and is not directly related to the installation height H of the cutting blade 490. For example, when the film thickness of the second metal 480 is thin, the cutting blade 490 may cut only the first resin 460 on the cutting line having the height H0. For example, when the film thickness of the second metal 480 is thin, the cutting line having the height H1 may be the surface of the second metal 480 formed in the groove 462. Note that “softest” means the softest material among a plurality of materials to be cut. In addition, it is also included in one technical scope of the present application to scan the substrate 450 with the cutting blade 490 fixed, or to scan both of them independently.
　上記の高さＨ０よりも高い位置で切削する場合、相対的に硬度の高い第１の金属４７０が溝４６２の側面にも成膜されている。そのため、第１の金属４７０も含めた３種類の材料を切削することとなる。かかる場合と比較すると、本実施形態は切削刃４９０の磨耗の程度が最も小さく、切削刃４９０の寿命を最も延ばすことが可能である。 When cutting at a position higher than the height H0, the first metal 470 having a relatively high hardness is also formed on the side surface of the groove 462. Therefore, three types of materials including the first metal 470 are cut. Compared with such a case, in the present embodiment, the degree of wear of the cutting blade 490 is the smallest, and the life of the cutting blade 490 can be maximized.
　（第１の金属の成膜厚さが小さい所を切削刃で切削）
　ただし、バイト４８０の設置工程および切削工程では、溝４６２の側面に成膜された最も硬度の高い第１の金属４７０の厚さが小さければ、その高さを狙って切削してもよい。例えば図２４の領域Ａ拡大図に示すように、高さＨ１では、第１の金属４７０の成膜厚さＴ１は、第１の樹脂４６０の上面に成膜された同じ第１の金属４７０の厚みＴ２（図１９の領域Ｂ拡大図参照）よりも薄くなっている。この高さＨ１の切削ラインで切削してもよい。この条件によれば、切削刃４９０は、第１の金属４７０、第２の金属４８０および第１の樹脂４６０の３種類を切削することとなるものの、第１の金属４７０の成膜厚みＴ１は、上記の条件を満たすほど小さい。これを、上記の高さＨ１よりも更に高い位置で切削する場合と比較すれば、切削刃４９０の磨耗の程度は小さく、切削刃４９０の寿命を延ばすことが可能である。 (Cutting with a cutting blade where the first metal film thickness is small)
However, in the installation process and cutting process of the cutting tool 480, if the thickness of the first metal 470 having the highest hardness formed on the side surface of the groove 462 is small, the cutting may be performed aiming at the height. For example, as shown in the enlarged view of region A in FIG. 24, at the height H1, the film thickness T1 of the first metal 470 is the same as that of the same first metal 470 formed on the upper surface of the first resin 460. It is thinner than the thickness T2 (see the enlarged view of region B in FIG. 19). You may cut with this cutting line of height H1. According to this condition, the cutting blade 490 cuts three types of the first metal 470, the second metal 480, and the first resin 460, but the film thickness T1 of the first metal 470 is It is small enough to satisfy the above conditions. Compared with the case of cutting at a position higher than the height H1, the degree of wear of the cutting blade 490 is small, and the life of the cutting blade 490 can be extended.
　（比較例）
　特許文献４を比較例として本発明の一つの実施形態と比較する。特許文献４の技術では、溝の側壁の任意の位置に切削刃を当接させ、Ｘ方向に切削することを開示するものの、メタルの硬度と切削刃の劣化（摩耗）についての課題は一切開示されておらず、切削刃の劣化抑止を視点とした切削刃の高さについての検討は一切されておらず、開示も示唆もない。更に絶縁膜の材質と切削刃の関係の検討についても、一切開示も示唆もされていない。 (Comparative example)
Patent Document 4 is compared with one embodiment of the present invention as a comparative example. Although the technique of Patent Document 4 discloses that the cutting blade is brought into contact with an arbitrary position on the side wall of the groove and is cut in the X direction, there is no disclosure about the hardness of the metal and the deterioration (wear) of the cutting blade. The height of the cutting blade from the viewpoint of suppressing the deterioration of the cutting blade has not been studied, and there is no disclosure or suggestion. Furthermore, there is no disclosure or suggestion regarding the examination of the relationship between the material of the insulating film and the cutting blade.
　一方、本発明の一つの実施形態では、切削刃の設定高さと第１の金属４７０との関係を厳密に規定することによって切削刃の磨耗を抑制し、切削性能も向上可能になるという顕著な効果を有する。更に、本発明では、後述する電気的な絶縁としての第１の樹脂４６０の材質と切削刃との関係を厳密に規定することによって切削刃の磨耗を抑制し、切削性能も向上可能になるという顕著な効果を有する。 On the other hand, in one embodiment of the present invention, it is possible to suppress the wear of the cutting blade and to improve the cutting performance by strictly defining the relationship between the set height of the cutting blade and the first metal 470. Has an effect. Furthermore, according to the present invention, by precisely defining the relationship between the material of the first resin 460 as electrical insulation described later and the cutting blade, it is possible to suppress cutting blade wear and improve cutting performance. Has a noticeable effect.
　（本発明によって切削刃の磨耗が抑制される理由）
　既に述べたように、相対的に硬度の高い第１の金属４７０をより多く切削するほど、言い換えれば、切削ラインの線分長に占める第１の金属４７０の線分長の比率が大きいほど、切削刃４９０の磨耗が激しいため、第１の金属４７０の厚みが、より薄い所あるいはゼロになる所を狙って切削し、第１の金属４７０の切削量を可能な限り抑制するのが本発明の各実施形態の一つの特徴である。以下、物理定数と切削刃４９０の磨耗に関して考察する。 (Reason why wear of the cutting blade is suppressed by the present invention)
As already described, the more the first metal 470 having a relatively high hardness is cut, in other words, the larger the ratio of the line segment length of the first metal 470 to the line segment length of the cutting line is, Since the cutting blade 490 is heavily worn, the present invention is to cut the first metal 470 as much as possible by cutting the first metal 470 so that the thickness of the first metal 470 becomes thinner or zero. This is one feature of each of the embodiments. Hereinafter, the physical constant and the wear of the cutting blade 490 will be considered.
　図２６は、切削刃を利用した本発明の一つの実施形態に好ましい各種樹脂および金属の物性値を示す表である。図２６は、第１の樹脂４６０として用いることのできる素材の代表として、フェノール樹脂を含んでいる。また、第１の金属４７０として使用可能な金属の代表としてＴｉを、第２の金属４８０として使用可能な金属の代表としてＣｕまたはＡｌを含んでいる。尚、ポリイミド樹脂は、フェノール樹脂の比較例である。 FIG. 26 is a table showing physical properties of various resins and metals preferable for one embodiment of the present invention using a cutting blade. FIG. 26 includes a phenol resin as a representative material that can be used as the first resin 460. Further, Ti is included as a representative metal that can be used as the first metal 470, and Cu or Al is included as a representative metal that can be used as the second metal 480. Polyimide resin is a comparative example of phenol resin.
　切削刃４９０で切削する時、切削される材料が切削刃４９０に抵抗感を受け、よって切削刃４９０が磨耗する原因は、第１に、切削される材料の硬度があり、第２に、材料の粘り（すなわち弾性伸びの大きさ）、がある。切削刃４９０が粘りのある材料を切削すると、切削刃４９０は、切れていない材料を引きずってしまうためである。Ｔｉは上記の硬度・粘りの両方が高いため、とりわけ切削刃４９０を摩耗する材料である。 When cutting with the cutting blade 490, the material to be cut receives resistance to the cutting blade 490, and the cause of the wear of the cutting blade 490 is firstly the hardness of the material to be cut, and secondly, the material There is stickiness (that is, the size of elastic elongation). This is because when the cutting blade 490 cuts a sticky material, the cutting blade 490 drags an uncut material. Ti is a material that wears the cutting blade 490 in particular because of its high hardness and stickiness.
　しかし、切削刃を利用した本発明の一つの実施形態は、Ｔｉに代表される硬度の高い第１の金属４７０が成膜されていない所、あるいはその厚みが薄い所に該当する高さを切削する。これにより、第１の金属４７０の切削量を抑制した。したがって、切削刃４９０の磨耗を抑制し、その寿命を大幅に延長可能である。 However, in one embodiment of the present invention using a cutting blade, a height corresponding to a place where the first metal 470 having a high hardness represented by Ti is not formed or where the thickness is thin is cut. To do. Thereby, the cutting amount of the first metal 470 was suppressed. Therefore, the wear of the cutting blade 490 can be suppressed, and its life can be greatly extended.
　また、フェノール樹脂はポリマー構成に必要な官能アルキル基、水酸基などのネットワーク形成基が一般に多く、ポリイミドのイミド基などのネットワーク形成基に比べて、密な三次元構造をとる。そのため、弾性率は比較的高く、硬度も高く、塑性変形(クレーズ変形)範囲が小さい。特にフェノール樹脂は環状構造が主体のため、切削刃に切削対象物が付着して加工性能が劣化するなどの問題が生じず、切削加工しやすい。このように切削上の金属との特性上の差が小さくなることで、加工上の問題が排除される。 Also, phenolic resins generally have many network-forming groups such as functional alkyl groups and hydroxyl groups necessary for polymer construction, and have a dense three-dimensional structure compared to network-forming groups such as polyimide imide groups. Therefore, the elastic modulus is relatively high, the hardness is high, and the plastic deformation (craze deformation) range is small. In particular, the phenolic resin is mainly composed of an annular structure, so that it is easy to perform cutting work without causing problems such as a cutting object adhering to the cutting blade and deterioration in processing performance. Thus, the problem in processing is eliminated by reducing the difference in characteristics from the metal on cutting.
　（本発明によって切削性能が向上する理由：第１の樹脂の素材）
　既に述べたように、第１の樹脂４６０は、フェノール樹脂のほか、不飽和ポリエステル樹脂、メラミン樹脂またはユレア樹脂を主成分としてもよい。切削刃による切削は切削時の局部発熱で塑性変形を起こさない、熱硬化樹脂が望ましいからである。また、切削刃の切れ味を良くするためには、第１の樹脂４６０は、適度な弾性率を持ち、限界応力に対する歪みが小さく強度が比較的低い樹脂が良好と考えられるからである。少なくとも、第１の樹脂の破断に至る塑性変形の範囲が、ポリイミドの塑性変形の範囲よりも小さい、ことが好ましい。また、第１の樹脂の破断強度（tensile strength）は、ポリイミドの破断強度よりも小さい、ことが好ましい。具体的な数値としては、第１の樹脂は、応力に対して破断に到達する歪みが１０パーセント未満であることが好ましい。また、第１の樹脂の破断強度（tensile
strength）は、８０ＭＰａ以下であることが好ましい。 (Reason why cutting performance is improved by the present invention: first resin material)
As already described, the first resin 460 may contain an unsaturated polyester resin, melamine resin, or urea resin as a main component in addition to the phenol resin. This is because cutting with a cutting blade is preferably a thermosetting resin that does not cause plastic deformation due to local heat generation during cutting. Moreover, in order to improve the sharpness of the cutting blade, the first resin 460 is considered to be a resin having an appropriate elastic modulus, a small distortion with respect to a limit stress, and a relatively low strength. It is preferable that at least the range of plastic deformation leading to fracture of the first resin is smaller than the range of plastic deformation of polyimide. Further, the tensile strength of the first resin is preferably smaller than that of polyimide. As a specific numerical value, it is preferable that the first resin has less than 10% of strain to reach rupture with respect to stress. In addition, the tensile strength of the first resin (tensile
strength) is preferably 80 MPa or less.
　図２７は、図２４（切削刃を利用した本発明の一つの実施形態）の第１の樹脂４６０としては適さない樹脂（ポリイミド樹脂等）に生じるクレーズ（Craze）の例を示す模式図である。クレーズとは、２次元絡み合い原子鎖の２次元鎖が整列し、切れ難くなる状態を言う。図２７に示すように、プラスチックの袋を開封しようとするときに力Ｆを加えると、有機物バルク部４９２と、伸びて白濁する部分がクレーズ４９４とに別れ、非常に強く抵抗する現象である。白濁して見えるクレーズ４９４は、微小繊維であるフィブリル（fibril）４９６と、空隙部分であるボイド（void）４９８とを含む。 FIG. 27 is a schematic diagram showing an example of craze generated in a resin (polyimide resin or the like) that is not suitable as the first resin 460 in FIG. 24 (one embodiment of the present invention using a cutting blade). . Craze means a state in which two-dimensional chains of two-dimensional entangled atomic chains are aligned and difficult to break. As shown in FIG. 27, when a force F is applied when trying to open a plastic bag, the organic bulk part 492 and the part that expands and becomes cloudy separates into a craze 494, which is a phenomenon of extremely strong resistance. Craze 494 that appears cloudy includes fibrils 496 that are microfibers and voids 498 that are voids.
　図２８は各種樹脂の応力－歪み曲線を示すグラフである。第１の樹脂４６０としては、応力に対する歪みが数％以下の樹脂が好ましく、かかる樹脂はクレーズが生じにくい、切削刃への絡み付きが少ない材料である。図２８（ｂ）に示すように、上述のフェノール樹脂、不飽和ポリエステル樹脂、メラミン樹脂またはユレア樹脂はいずれも、かかる条件を満たしている。固く伸びが少ないπ型環状基を含有しているからである。 FIG. 28 is a graph showing stress-strain curves of various resins. As the first resin 460, a resin having a strain with respect to stress of several percent or less is preferable, and the resin is a material that hardly causes craze and has little entanglement with the cutting blade. As shown in FIG. 28 (b), the above-mentioned phenol resin, unsaturated polyester resin, melamine resin, or urea resin all satisfy such conditions. This is because it contains a π-type cyclic group that is hard and has little elongation.
　一方、図２８（ａ）に示すように、ポリイミド樹脂は、応力に対する歪みが数十％にも及ぶ強度の高い樹脂であり、図２７に示したクレーズを発生し易い。したがって第１の樹脂４６０の素材としては、切削刃４９０による切削性能を低下させるおそれがあるため、ポリイミド樹脂は不適当である。但し、切削以外の「研削」、「研磨」の技術を利用した本発明の第１の実施例においては、絶縁材として、感光性ポリイミド膜３０は好適であることは、言うまでもない。 On the other hand, as shown in FIG. 28 (a), the polyimide resin is a resin having a high strength in which the strain with respect to the stress reaches several tens of percent, and the crazing shown in FIG. 27 is likely to occur. Accordingly, as the material of the first resin 460, polyimide resin is inappropriate because there is a possibility that the cutting performance by the cutting blade 490 may be deteriorated. However, it goes without saying that the photosensitive polyimide film 30 is suitable as an insulating material in the first embodiment of the present invention using techniques of “grinding” and “polishing” other than cutting.
　ここでフェノール樹脂、不飽和ポリエステル樹脂、メラミン樹脂またはユレア樹脂を「主成分とする」という文言の定義を説明する。 Here, the definition of the phrase “mainly composed of phenol resin, unsaturated polyester resin, melamine resin or urea resin” will be explained.
　フェノール樹脂には、フェノールとホルムアルデヒドを混合し、酸触媒で縮合重合し、高分子化したノボラック型と呼ばれる樹脂と、アルカリ触媒で縮合重合したレゾール型と呼ばれる樹脂とがある。前者はそのままでは熱可塑性であり、低分子状態では液体である。これにヘキサメチレンテトラミンなどを１～２０重量％硬化剤として混合すると、縮合重合し熱硬化樹脂となる。後者はそれ自体が自己反応性活性基を有するため、加熱されることで熱硬化する。 There are two types of phenolic resins: phenolic and formaldehyde mixed, polymerized by acid catalyst, polymerized novolak type, and resin called resol type, polymerized by alkali catalyst. The former is thermoplastic as it is, and is liquid in the low molecular state. When hexamethylenetetramine or the like is mixed with this as 1 to 20% by weight of a curing agent, it undergoes condensation polymerization and becomes a thermosetting resin. Since the latter itself has a self-reactive active group, it is cured by heating.
　電子部品用途に関しては、熱硬化重合反応が制御しやすいノボラック型が主に使われている。本願で永久レジストと呼んでいるものはノボラック型であり、フォトレジストとして加工される場合、ノボラック型フェノール樹脂は１００％がこの成分で占められている。フォトレジスト以外の、例えば塗布材料として用いられる場合には、様々な強度が強いマクロモノマー、例えばセルローズなどの充填剤や顔料（特に黒色顔料など）やフィラー（シリカガラス微粒子）などが添加物総量で０．１～５０重量％程度混入されることもある。 For electronic component applications, the novolak type that allows easy control of the thermosetting polymerization reaction is mainly used. What is referred to as a permanent resist in the present application is a novolak type, and when processed as a photoresist, 100% of the novolak type phenol resin is occupied by this component. When used as a coating material other than a photoresist, for example, macromonomers having various strengths such as fillers such as cellulose, pigments (particularly black pigments), fillers (silica glass fine particles), etc., are used as the total amount of additives. About 0.1 to 50% by weight may be mixed.
　フェノール樹脂は、図２８（ａ）の応力ひずみ曲線からも分かるように伸びが少なく、強度もそれほど高くないため、電子材料としてはもろい。多少強度を上げたいなどの要求に応じてエポキシ変性フェノール樹脂（変性をした部分すなわち、混合％に応じてエポキシの性質が強くなる）にしたり、耐熱性に劣ることからポリビニルアセタール変性フェノール樹脂にしたりすることができる。また、熱サイクル信頼性を向上させるためニトリルゴム変性フェノール樹脂にしたり、印刷性を高めるためロジン変性フェノール樹脂にしたりするなど、さまざまな性質改善のために変性が行われている。その変性樹脂の混合比は１％から５０重量％のレベルで行われている。したがって本文では「フェノール樹脂を主成分とする」とは、フェノール樹脂５０重量％以上であることと定義する。 The phenolic resin is fragile as an electronic material because it has little elongation and high strength, as can be seen from the stress-strain curve in FIG. Depending on requirements such as a slight increase in strength, an epoxy-modified phenolic resin (modified part, that is, the epoxy properties become stronger depending on the mixing percentage) or a polyvinyl acetal-modified phenolic resin due to poor heat resistance can do. Modifications have been made to improve various properties, such as using a nitrile rubber-modified phenol resin to improve thermal cycle reliability, or using a rosin-modified phenol resin to improve printability. The mixing ratio of the modified resin is 1% to 50% by weight. Therefore, in the present text, “having a phenol resin as a main component” is defined as 50% by weight or more of a phenol resin.
　メラミン樹脂はメラミンとホルムアルデヒドの縮合反応で得られるメチロールメラミンを重合縮合反応させ合成するが、窒素環状基を作るため、尿素樹脂より衝撃強度が強い。一般にはメチロールメラミンを繊維などに含浸させて、強化プラスチックを作るが、電子部品としてはセルローズ添加剤が５～４０重量％加えられて使われる。もちろん１００％樹脂としての使用にも耐える。エポキシやユレア樹脂との変性加工は合成時にエポキシモノマーや尿素を適量加えることで自由に行える。また、混合することで中間的性質をもつ樹脂ができる。本文では「メラミン樹脂を主成分とする」とは、５０重量％以上であることをここでは定義する。 Melamine resin is synthesized by polymerization condensation reaction of methylolmelamine obtained by condensation reaction of melamine and formaldehyde, but has a higher impact strength than urea resin because it forms a nitrogen cyclic group. Generally, reinforced plastics are made by impregnating methylol melamine into fibers and the like, but as an electronic component, 5 to 40% by weight of a cellulose additive is added. Of course, it can withstand use as 100% resin. Modification with epoxy or urea resin can be done freely by adding appropriate amounts of epoxy monomer and urea during synthesis. Further, by mixing, a resin having intermediate properties can be obtained. In the present text, “having melamine resin as a main component” is defined herein to be 50% by weight or more.
　不飽和ポリエステル樹脂は無水マレイン酸、イソフタル酸系などの不飽和ポリエステルとエチレングリコールなどの多価アルコールの縮合重合で作られる熱硬化性の樹脂であり、無水マレイン酸もスチレンも環状基のため、機械的強度が強いことが特徴である。したがって１００％樹脂も使用できる。特に繊維に含浸させる強化プラスチックとしての用途に優れている。各種のエステル化合物で無数の種類が作れるが、異種樹脂による変性樹脂として表面の平滑性を保つため、合成時ペンタジエンなどを混ぜた変性や、相溶性のあるアクリルウレタンなど混ぜ透明性や光による黄変防止の変性などが考えられている。一般的に合成時に混ぜて作る反応基としてフェノール、エポキシ、ウレタンがあり、自由な配合ができるが、本文では「不飽和ポリエステル樹脂を主成分とする」とは、５０重量％以上であることと定義する。 Unsaturated polyester resin is a thermosetting resin made by condensation polymerization of unsaturated polyesters such as maleic anhydride and isophthalic acid and polyhydric alcohols such as ethylene glycol, both maleic anhydride and styrene are cyclic groups, It is characterized by high mechanical strength. Therefore, 100% resin can also be used. In particular, it is excellent for use as a reinforced plastic impregnated into fibers. A myriad of different types of ester compounds can be made, but in order to maintain the smoothness of the surface as a modified resin with different types of resins, modification by mixing pentadiene during synthesis, mixing with compatible acrylic urethane, and yellowing due to light Modifications to prevent alteration are considered. Generally, there are phenol, epoxy and urethane as reactive groups to be mixed at the time of synthesis, and they can be blended freely. However, in the text, “based on unsaturated polyester resin” means 50% by weight or more. Define.
　ユレア樹脂（尿素樹脂）は尿素とホルムアルデヒドを縮合反応させ合成されるもので、環状化合物をもたない直鎖のネットワークのため、破壊靱性が落ちる。そのため、１００％樹脂を使用することは少なく、破壊靱性を増すために環状化合物であるビスフェノールＡ骨格を持つグリシン化合物０．５～３０重量％を合成時に入れて変性することなどが考えられている。また充填剤としてセルローズがよく用いられ、５～４０重量％入れることで機械的性質を調整できる。メラミン樹脂やフェノール樹脂との整合性もよく、反応時にメラミンやフェノールを加えることで、お互いの性質の中間的な性質が生まれる。本文では「ユレア樹脂を主成分とする」とは、５０重量％以上であることと定義する。 Urea resin (urea resin) is synthesized by condensation reaction of urea and formaldehyde, and because it is a linear network without cyclic compounds, fracture toughness decreases. Therefore, it is rare to use 100% resin, and in order to increase fracture toughness, it is considered that 0.5 to 30% by weight of a glycine compound having a bisphenol A skeleton, which is a cyclic compound, is added and modified during synthesis. . Cellulose is often used as a filler, and the mechanical properties can be adjusted by adding 5 to 40% by weight. Good consistency with melamine resin and phenol resin, and by adding melamine and phenol during the reaction, intermediate properties between each other are born. In the present text, “based on urea resin” is defined as 50% by weight or more.
　図２９は、図２４の高さＨ０における切削後の樹脂と金属を断面から見た模式図である。図２９（ａ）は図２４の素材をそのまま用いていて、第１の樹脂４６０（フェノール樹脂等）と、第２の金属４８０（ＣｕやＡｌ）とが交互に切削される場合を示している。一方図２９（ｂ）は、図１９の第１の樹脂４６０を仮にポリイミド樹脂４６１に変更した場合を示している。図２４の素材をそのまま用いた場合は、図２９（ａ）に示すように、切削は問題なく行われる。第１の樹脂４６０は、固くて伸びが少ない特性を有することから、切削される際、一緒に切断される隣接する第２の金属４８０との間に空隙を生じにくい。また、基板４５０からも第１の樹脂４６０は剥離しにくい。そのため配線を形成する金属の配線パターンが歪むことが防止されるという顕著な効果を有する。 FIG. 29 is a schematic view of the resin and metal after cutting at the height H0 in FIG. 24 as seen from the cross section. FIG. 29A shows a case where the material of FIG. 24 is used as it is, and the first resin 460 (phenol resin or the like) and the second metal 480 (Cu or Al) are alternately cut. . On the other hand, FIG. 29B shows a case where the first resin 460 of FIG. 19 is temporarily changed to a polyimide resin 461. When the material of FIG. 24 is used as it is, cutting is performed without any problem as shown in FIG. Since the first resin 460 is hard and has a low elongation property, when the first resin 460 is cut, a gap is not easily generated between the adjacent second metals 480 that are cut together. Further, the first resin 460 is hardly peeled from the substrate 450. Therefore, there is a remarkable effect that the metal wiring pattern forming the wiring is prevented from being distorted.
　しかし、図２９（ｂ）のように、第１の樹脂４６０に代えてポリイミド樹脂４６１を使用すると、その強度の高さゆえに、切削刃に押されてポリイミド樹脂４６１が歪み、先行して切削される第２の金属４８０（左側）との間に空隙４６３を生じてしまうし、基板４５０からの剥離４６７も生じてしまう。また、ポリイミド樹脂４６１が歪むと、その後続の切削対象である第２の金属４８０（右側）をも歪ませてしまい、第２の金属４８０の基板４５０からの剥離４６９も生じてしまう。 However, when polyimide resin 461 is used instead of the first resin 460 as shown in FIG. 29B, due to its high strength, the polyimide resin 461 is distorted by the cutting blade and is cut in advance. A gap 463 is formed between the second metal 480 and the second metal 480 (left side), and peeling 467 from the substrate 450 is also generated. In addition, when the polyimide resin 461 is distorted, the second metal 480 (right side) that is a subsequent cutting target is also distorted, and peeling 469 of the second metal 480 from the substrate 450 is also generated.
　上記の空隙及び剥離が発生すると、配線・樹脂パターンが歪んでしまうおそれがある。すなわち、金属の脱落、樹脂の脱落、内部ボイド等が発生しやすく、配線の断線、配線のショートが発生する可能性がある。特に配線密度の高い配線の場合、樹脂と金属、金属と基板、樹脂と基板、の接着面積がもともと小さいことから、上記のような金属からの剥離（例えば空隙４６３）、基板からの剥離（例えば剥離４６７、４６９）が起きやすい。よって、図２９（ａ）のように切削しやすい第１の樹脂４６０を使用することが重要である。 If the above gaps and separation occur, the wiring / resin pattern may be distorted. In other words, metal dropout, resin dropout, internal voids, and the like are likely to occur, and there is a possibility that wiring breaks and wiring shorts may occur. Particularly in the case of wiring with a high wiring density, the adhesion area between the resin and the metal, the metal and the substrate, and the resin and the substrate is originally small. Peeling 467, 469) is likely to occur. Therefore, it is important to use the first resin 460 that is easy to cut as shown in FIG.
　（本発明によって切削性能が向上する理由：パッシベーション膜）
　図２４に示すように、基板４５０は、少なくともその表面の一部にパッシベーション膜４４４を有し、パッシベーション膜４４４が第１の樹脂４６０と接している。パッシベーション膜４４４と第１の樹脂４６０とが接することによって第１の樹脂４６０の密着性（接着力）が向上し、切削性能がより向上する。 (Reason why cutting performance is improved by the present invention: passivation film)
As shown in FIG. 24, the substrate 450 has a passivation film 444 on at least a part of its surface, and the passivation film 444 is in contact with the first resin 460. When the passivation film 444 and the first resin 460 are in contact with each other, the adhesion (adhesive force) of the first resin 460 is improved, and the cutting performance is further improved.
　本実施形態のパッシベーション膜４４４は、ポリイミド樹脂を主成分としている。パッシベーション膜４４４に接する第１の樹脂４６０として用いられるフェノール樹脂、不飽和ポリエステル樹脂、メラミン樹脂、ユレア樹脂のいずれかは、ポリイミド樹脂に接着する感光性樹脂であり、接着力が強く、切削しやすい性能を有する。これは、上記の第１の樹脂４６０の材料が、パッシベーション膜４４４の材料であるポリイミド樹脂の反応基である、カルボキシル基やイミド基と反応性のあるカルボキシル基、水酸基、イミド基を比較的多く含み、主鎖や副鎖にちりばめられているからである。 The passivation film 444 of this embodiment is mainly composed of polyimide resin. Any of a phenol resin, an unsaturated polyester resin, a melamine resin, and a urea resin used as the first resin 460 in contact with the passivation film 444 is a photosensitive resin that adheres to a polyimide resin, and has a strong adhesive force and is easy to cut. Has performance. This is because the material of the first resin 460 has a relatively large number of carboxyl groups, hydroxyl groups, and imide groups that are reactive with the carboxyl groups and imide groups, which are reactive groups of the polyimide resin that is the material of the passivation film 444. This is because it is included in the main chain and sub-chain.
　再び、図２および図３の説明（第１の実施例に係るＷＬＰの製造工程）に戻る。図３（Ｇ）において、樹脂３０及び金属層層５０が、上面から高さｈ１に到達する面Ｋ１まで、研削または研磨される。または、樹脂３０及び金属層層５０が、高さｈ１に設置された切削刃によって側面から面Ｋ１に沿って切削される。 Again, the description returns to the description of FIGS. 2 and 3 (the manufacturing process of the WLP according to the first embodiment). In FIG. 3G, the resin 30 and the metal layer 50 are ground or polished from the upper surface to the surface K1 reaching the height h1. Alternatively, the resin 30 and the metal layer 50 are cut from the side surface along the surface K1 by the cutting blade installed at the height h1.
　図３（Ｈ）は、平坦化処理された状態を示している。ポリイミド膜３０の表面３２および金属層５０の表面は、ほぼ同一の高さを有し、ポリイミド膜３０の開口部３２内には、金属パターン（金属配線）５２が形成される。金属パターン５２は、第２の金属層である。金属パターン５２は、ポリイミド膜３０の開口部３２（図２（Ｆ））に対応する形状を有し、従って、金属パターン５２は、パッシベーション２０の開口２０Ａ（図２（Ｃ））を介してチップ取り出し電極１８に接続された第１の領域５２Ａと、当該第１の領域５２Ａから側方に延在する第２の領域５２Ｂとを有する。 FIG. 3 (H) shows a state after flattening. The surface 32 of the polyimide film 30 and the surface of the metal layer 50 have substantially the same height, and a metal pattern (metal wiring) 52 is formed in the opening 32 of the polyimide film 30. The metal pattern 52 is a second metal layer. The metal pattern 52 has a shape corresponding to the opening 32 (FIG. 2F) of the polyimide film 30, and therefore the metal pattern 52 is chipped through the opening 20A of the passivation 20 (FIG. 2C). A first region 52A connected to the extraction electrode 18 and a second region 52B extending laterally from the first region 52A.
　次に、図３（Ｉ）に示すように、基板全面にソルダーレジスト６０が塗布され、例えば公知のフォトリソ工程により露光、現像が行われ、図３（Ｊ）に示すように、金属パターン５２の平坦な表面を有する第２の領域５２Ｂを露出するようなソルダーレジスト６０の開口６０Ａが形成される。尚、ソルダーレジストは、フォトリソグラフィー製法に代えて、レーザ製法で開口６０Ａを形成してもよい。次に、図３（Ｋ）に示すように、開口６０Ａを介して半田ボール７０（外部端子７０）が形成される。こうして、ＷＬＰプロセスが行われ、この後、基板をダイシングすることで個々のＣＳＰの半導体チップを得ることができる。 Next, as shown in FIG. 3 (I), a solder resist 60 is applied to the entire surface of the substrate, and exposure and development are performed by, for example, a known photolithography process. As shown in FIG. An opening 60A of the solder resist 60 is formed so as to expose the second region 52B having a flat surface. Note that the solder resist may form the opening 60A by a laser manufacturing method instead of the photolithography manufacturing method. Next, as shown in FIG. 3K, solder balls 70 (external terminals 70) are formed through the openings 60A. Thus, the WLP process is performed, and thereafter, the substrate is diced to obtain individual CSP semiconductor chips.
　ソルダーレジスト材料は、例えば、ノボラック型シアネート樹脂、ビスフェノールＡ型シアネート樹脂、ビスフェノールＥ型シアネート樹脂、テトラメチルビスフェノールＦ型シアネート樹脂等のビスフェノール型シアネート樹脂等のシアネート樹脂；フェノールノボラック樹脂、クレゾールノボラック樹脂、ビスフェノールＡノボラック樹脂等のノボラック型フェノール樹脂、未変性のレゾールフェノール樹脂、桐油、アマニ油、クルミ油等で変性した油変性レゾールフェノール樹脂等のレゾール型フェノール樹脂等のフェノール樹脂；ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、ビスフェノールＳ型エポキシ樹脂、ビスフェノールＥ型エポキシ樹脂、ビスフェノールＭ型エポキシ樹脂、ビスフェノールＰ型エポキシ樹脂、ビスフェノールＺ型エポキシ樹脂等のビスフェノール型エポキシ樹脂；フェノールノボラック型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂等のノボラック型エポキシ樹脂；ビフェニル型エポキシ樹脂、ビフェニルアラルキル型エポキシ樹脂、アリールアルキレン型エポキシ樹脂、ナフタレン型エポキシ樹脂、アントラセン型エポキシ樹脂、フェノキシ型エポキシ樹脂、ジシクロペンタジエン型エポキシ樹脂、ノルボルネン型エポキシ樹脂、アダマンタン型エポキシ樹脂、フルオレン型エポキシ樹脂等のエポキシ樹脂；ユリア（尿素）樹脂、メラミン樹脂等のトリアジン環を有する樹脂；不飽和ポリエステル樹脂、ビスマレイミド樹脂、ポリウレタン樹脂、ジアリルフタレート樹脂、シリコーン樹脂、ベンゾオキサジン環を有する樹脂、ポリイミド樹脂、ポリアミドイミド樹脂、ベンゾシクロブテン樹脂、等が挙げられる。本発明においては、これらの中の１種類を単独で用いてもよいし、２種類以上を併用してもよい。また、同じ種類の樹脂の異なる重量平均分子量を有するものを併用してもよい。さらに、上記の１種類または２種類以上とそれらのプレポリマーとを併用してもよい。前記熱硬化性樹脂の含有量としては特に限定されないが、樹脂組成物全体の５０－１００重量％であることが好ましい。 Solder resist materials include, for example, novolak type cyanate resins, bisphenol A type cyanate resins, bisphenol E type cyanate resins, cyanate resins such as bisphenol type cyanate resins such as tetramethylbisphenol F type cyanate resin; phenol novolac resins, cresol novolac resins, Phenolic resins such as bisphenol A novolac resins, novolac type phenolic resins, unmodified resole phenolic resins, oil-modified resol phenolic resins modified with tung oil, linseed oil, walnut oil, etc .; bisphenol A type epoxy resins Bisphenol F type epoxy resin, bisphenol S type epoxy resin, bisphenol E type epoxy resin, bisphenol M type epoxy resin, bisphenol P type epoxy resin Bisphenol type epoxy resins such as xyphenol resin and bisphenol Z type epoxy resin; Novolak type epoxy resins such as phenol novolac type epoxy resin and cresol novolak type epoxy resin; Biphenyl type epoxy resin, biphenyl aralkyl type epoxy resin, arylalkylene type epoxy resin, Epoxy resins such as naphthalene type epoxy resin, anthracene type epoxy resin, phenoxy type epoxy resin, dicyclopentadiene type epoxy resin, norbornene type epoxy resin, adamantane type epoxy resin, fluorene type epoxy resin; urea (urea) resin, melamine resin, etc. Resin having a triazine ring: unsaturated polyester resin, bismaleimide resin, polyurethane resin, diallyl phthalate resin, silicone resin, benzoxazine Resins having, polyimide resin, polyamideimide resin, benzocyclobutene resin, and the like. In the present invention, one of these may be used alone, or two or more may be used in combination. Moreover, you may use together what has different weight average molecular weights of the same kind of resin. Furthermore, you may use together the said 1 type, or 2 or more types, and those prepolymers. The content of the thermosetting resin is not particularly limited, but is preferably 50 to 100% by weight based on the entire resin composition.
　上記の例では、パッシベーション層２０に開口２０Ａを形成した後に、パッシベーション層２０の上層の感光性ポリイミド膜３０に開口２０Ａに通じる開口部３２を形成したが、開口２０Ａと開口部３２とを連続的に形成するようにしてもよい。その工程を図４に示す。図４（Ａ）に示すように、基板１２の主面１２Ａには、チップ取り出し電極１８や配線１６が形成され、次いで図４（Ｂ）示すように、基板全面にパッシベーション層２０が形成される。次に、図４（Ｃ）に示すように、パッシベーション層２０を覆うように基板全面に感光性ポリイミド膜３０が塗布され、次に、図４（Ｄ）に示すようにグレイティングマスク４０を用いて感光性ポリイミド膜３０を露光する。グレイティングマスク４０は、図２（Ｅ）のときと同様に、光量Ｌ１を透過する領域、光量Ｌ１よりも小さな光量Ｌ２を透過する領域、遮光領域４０Ａを有する。 In the above example, after the opening 20A is formed in the passivation layer 20, the opening 32 leading to the opening 20A is formed in the upper photosensitive polyimide film 30 of the passivation layer 20, but the opening 20A and the opening 32 are continuously formed. You may make it form in. The process is shown in FIG. As shown in FIG. 4A, chip takeout electrodes 18 and wirings 16 are formed on the main surface 12A of the substrate 12, and then a passivation layer 20 is formed on the entire surface of the substrate as shown in FIG. 4B. . Next, as shown in FIG. 4C, a photosensitive polyimide film 30 is applied to the entire surface of the substrate so as to cover the passivation layer 20, and then a grating mask 40 is used as shown in FIG. 4D. Then, the photosensitive polyimide film 30 is exposed. As in the case of FIG. 2E, the grating mask 40 includes a region that transmits the light amount L1, a region that transmits a light amount L2 smaller than the light amount L1, and a light shielding region 40A.
　次に、図４（Ｅ）に示すように、感光性ポリイミド膜３０を現像することで、感光性ポリイミド膜３０には、光量Ｌ１、Ｌ２に応じた形状の開口部３２が形成され、当該開口部３２は、パッシベーション層２０に到達する深度を有する第１の領域３２Ａと、当該第１の領域３２Ａよりも深度が浅い深度を有しかつ側方に一定の深さで延在する第２の領域３２Ｂとを有する。引き続き、図４（Ｆ）に示すように、感光性ポリイミド膜３０を用い、第１の領域３２Ａによって露出されたパッシベーション層２０をエッチングにより除去することで、チップ取り出し電極１８の開口２０Ａが形成される。 Next, as shown in FIG. 4E, by developing the photosensitive polyimide film 30, openings 32 having shapes corresponding to the light amounts L1 and L2 are formed in the photosensitive polyimide film 30, and the openings The part 32 includes a first region 32A having a depth reaching the passivation layer 20, and a second region having a depth shallower than the first region 32A and extending laterally at a constant depth. And a region 32B. Subsequently, as shown in FIG. 4F, the photosensitive polyimide film 30 is used, and the passivation layer 20 exposed by the first region 32A is removed by etching, whereby the opening 20A of the chip extraction electrode 18 is formed. The
　次に、本発明の第２の実施例のＷＬＰの工程を説明する。第１の実施例では、単層配線により半田ボール７０を形成する例を示したが、第２の実施例は、２層配線により半田ボール７０を形成する例を図５および図６示す。尚、単層配線は、例えば絶縁層を挟まない２つの金属層を含む。例えば、第１の実施例で開示したバリアメタル層と銅層である。２層配線とは、絶縁層を挟んだ２つの金属層である。第１の実施例と異なる点を中心に説明し、ほぼ重複する部分は第１の実施例を準用する。 Next, the WLP process of the second embodiment of the present invention will be described. In the first embodiment, an example in which the solder ball 70 is formed by single-layer wiring is shown. However, in the second embodiment, an example in which the solder ball 70 is formed by two-layer wiring is shown in FIGS. The single-layer wiring includes, for example, two metal layers that do not sandwich an insulating layer. For example, the barrier metal layer and the copper layer disclosed in the first embodiment. The two-layer wiring is two metal layers sandwiching an insulating layer. Differences from the first embodiment will be mainly described, and the first embodiment will be applied mutatis mutandis.
　図３（Ｈ）において、金属層５０の平坦化処理を行って金属パターン５２を形成した後、次に、図５（Ａ）に示すように、平坦化された金属パターン５２およびポリイミド膜３０を覆うように基板全面に感光性ポリイミド膜８０が塗布される。ポリイミド膜３０及びポリイミド膜８０は、共に絶縁層である。次いで、図５（Ｂ）に示すように、グレイティングマスク４２を用いて感光性ポリイミド膜８０が露光される。グレイティングマスク４２は、光量Ｌ１を透過する領域、光量Ｌ１よりも少ない光量Ｌ２を透過する領域、および遮光領域４２Ａを含み、光量Ｌ１は、感光性ポリイミド膜８０をすべて除去するのに十分な値であり、光量Ｌ２は、感光性ポリイミド８０に所定の膜厚を残存させる値である。 In FIG. 3H, after the metal layer 50 is planarized to form the metal pattern 52, the planarized metal pattern 52 and the polyimide film 30 are then formed as shown in FIG. A photosensitive polyimide film 80 is applied to the entire surface of the substrate so as to cover it. Both the polyimide film 30 and the polyimide film 80 are insulating layers. Next, as shown in FIG. 5B, the photosensitive polyimide film 80 is exposed using the grating mask 42. The grating mask 42 includes a region that transmits the light amount L1, a region that transmits a light amount L2 less than the light amount L1, and a light shielding region 42A. The light amount L1 is a value sufficient to remove all of the photosensitive polyimide film 80. The light quantity L2 is a value that leaves a predetermined film thickness on the photosensitive polyimide 80.
　次に、図５（Ｃ）に示すように、ポリイミド膜８０が現像されると、そこには光量Ｌ１、Ｌ２に応じた膜厚を有する開口部８２が形成される。開口８２は、下地の金属パターン５２に至る深度を有する第１の領域８２Ａと、第１の領域８２Ａの深度よりも浅い深度を有し側方に一定の深さで延在する第２の領域８２Ｂとを有する。 Next, as shown in FIG. 5C, when the polyimide film 80 is developed, an opening 82 having a film thickness corresponding to the light amounts L1 and L2 is formed there. The opening 82 includes a first region 82A having a depth reaching the underlying metal pattern 52, and a second region having a depth shallower than that of the first region 82A and extending laterally at a certain depth. 82B.
　次に、図５（Ｄ）に示すように、ポリイミド膜８０を覆うように基板前面に金属層９０が形成される。金属層９０は、第１の実施例と同様に単層または多層のいずれであってもよい。金属層９０の形成後、平坦化処理が行われる。平坦化処理は、第１の実施例のときと同様に、研削、研磨、及び切削の少なくともいずれか一つを用いて行われる。ここでは、基板１２の主面から高さｈ２となる面Ｋ２で平坦化処理を行うことで、金属層９０およびポリイミド膜８０の一部が除去される。切削の技術を適用する場合、第１の実施例と同様に、膜８０は、ポリイミド材に限られず、例えば、フェノール樹脂、不飽和ポリエステル樹脂、メラミン樹脂またはユレア樹脂を主成分とする材料が好ましい。平坦化処理により、図６（Ｅ）に示すように、ポリイミド膜８０の表面とほぼ同一の表面を有する金属パターン９２が形成される。金属パターン９２は、開口部８２の第１および第２の領域８２Ａ、８２Ｂにそれぞれ対応する第１および第２の領域９２Ａ、９２Ｂを有する。次に、図６（Ｆ）に示すように、ソルダーレジスト６２が塗布され、フォトリソ工程により金属パターン９２の第２の領域９２Ｂを露出するような開口が形成され、図６（Ｇ）に示すように金属パターン９２に電気的に結合された半田ボール７０が形成される。 Next, as shown in FIG. 5D, a metal layer 90 is formed on the front surface of the substrate so as to cover the polyimide film 80. The metal layer 90 may be either a single layer or a multilayer as in the first embodiment. After the formation of the metal layer 90, a planarization process is performed. The flattening process is performed using at least one of grinding, polishing, and cutting, as in the first embodiment. Here, a part of the metal layer 90 and the polyimide film 80 is removed by performing a planarization process on a surface K2 having a height h2 from the main surface of the substrate 12. When the cutting technique is applied, the film 80 is not limited to the polyimide material as in the first embodiment, and for example, a material mainly composed of a phenol resin, an unsaturated polyester resin, a melamine resin, or a urea resin is preferable. . By the planarization process, as shown in FIG. 6E, a metal pattern 92 having a surface substantially the same as the surface of the polyimide film 80 is formed. The metal pattern 92 has first and second regions 92A and 92B corresponding to the first and second regions 82A and 82B of the opening 82, respectively. Next, as shown in FIG. 6F, a solder resist 62 is applied, and an opening is formed so as to expose the second region 92B of the metal pattern 92 by a photolithography process, as shown in FIG. 6G. A solder ball 70 electrically connected to the metal pattern 92 is formed.
　図７は、ＷＬＰの配線形成に関連する本実施例による製造方法と従来の製造方法とを対比するものである。外部端子の形成方法は、省略している。従来のＷＬＰの製造方法は、図２（Ｃ）に示す状態から、感光性樹脂を塗布し（Ｓ１）、所定のマスクパターンを用いて露光し（Ｓ２）、感光性樹脂を現像し（Ｓ３）、スパッタリングによりＴｉ等のシードメタルを形成し（Ｓ４）、次いで、再び、感光性レジストの塗布（Ｓ５）、露光（Ｓ６）、および現像（Ｓ７）によるフォトリソ工程を行い、電解めっきによりＣｕ等の金属配線を形成し（Ｓ８）、レジストを剥離し（Ｓ９）、シードメタルをエッチングする（Ｓ１０）という工程を含む。これに対し、本実施例のＷＬＰの製造方法は、上記したように、図２（Ｃ）に示す状態から、感光性ポリイミド樹脂を塗布し（Ｓ１０１：図２（Ｄ））、グレイティングマスクを用いた露光を行い（Ｓ１０２：図２（Ｅ））、現像し（Ｓ１０３：図２（Ｆ））、物理気相成長や電解めっきによる金属配線を成膜し（Ｓ１０４：図３（Ｇ））、表面研削（Ｓ１０５：図３（Ｈ））の工程を含むものであり、従来の製造方法と比べて大幅に工程数を削減することができる。表面研削（Ｓ１０５）は、表面切削であってもよい。また、本実施例の製造方法では、感光性ポリイミド樹脂は永久レジストとして残存するため、感光性ポリイミド樹脂を除去する工程は不要であり、このことも工程数の削減に寄与する。 FIG. 7 compares the manufacturing method according to this embodiment related to the formation of the WLP wiring and the conventional manufacturing method. The method for forming the external terminals is omitted. In the conventional WLP manufacturing method, from the state shown in FIG. 2C, a photosensitive resin is applied (S1), exposed using a predetermined mask pattern (S2), and the photosensitive resin is developed (S3). Then, a seed metal such as Ti is formed by sputtering (S4), and then a photolithographic process is again performed by applying a photosensitive resist (S5), exposure (S6), and development (S7), and by electroplating, Cu or the like It includes steps of forming metal wiring (S8), stripping the resist (S9), and etching the seed metal (S10). On the other hand, in the manufacturing method of the WLP of this example, as described above, the photosensitive polyimide resin is applied from the state shown in FIG. 2C (S101: FIG. 2D), and the grating mask is applied. Exposure is performed (S102: FIG. 2E), development is performed (S103: FIG. 2F), and metal wiring is formed by physical vapor deposition or electrolytic plating (S104: FIG. 3G). The method includes surface grinding (S105: FIG. 3H), and the number of steps can be significantly reduced as compared with the conventional manufacturing method. The surface grinding (S105) may be surface cutting. Moreover, in the manufacturing method of a present Example, since the photosensitive polyimide resin remains as a permanent resist, the process of removing the photosensitive polyimide resin is unnecessary, and this also contributes to the reduction of the number of processes.
　なお、上記実施例の製造方法により得られるＣＳＰは、外部端子として半田ボールが形成されたＢＧＡとなるが、外部端子は、平面形状を有するようなＬＧＡであってよい。または、外部端子は、図２３（Ｈ）に示される様にボンダーによるボンディングワイヤ７１であってもよい。さらに、グレイティングマスクにより露光される感光性樹脂は、ポジ型、ネガ型のいずれであってもよく、その材料もポリイミド系に限るものではない。さらにグレイティングマスクは、光の透過量を調節することができものであれば、その形態を問うものではなく、例えばハーフトーンマスク等であってよい。 The CSP obtained by the manufacturing method of the above embodiment is a BGA in which solder balls are formed as external terminals. However, the external terminals may be LGA having a planar shape. Alternatively, the external terminal may be a bonding wire 71 using a bonder as shown in FIG. Further, the photosensitive resin exposed by the grating mask may be either a positive type or a negative type, and the material is not limited to the polyimide type. Furthermore, the grating mask is not limited in its form as long as the amount of light transmission can be adjusted, and may be a halftone mask, for example.
　次に、本発明の実施例に係る製造方法を、パッシベーション層より上層の配線層が２層構造を有するＦａｎ－ｉｎ　ＷＬＰに適用したときの例を、図８ないし図１１に示す。前述の第１及び第２の実施例を引用している。図８（Ａ）は、ＷＬＰにより外部端子１１０Ａ～１１０ＤがＣＳＰの表面に形成された状態のファンインタイプのＣＳＰの模式的な平面図を表している。ファンインタイプのＣＳＰ１００は、半導体チップの外形１００Ａより内側の面内に複数の外部端子１１０（１１０Ａ～１１０Ｄ）を形成している。外部端子１１０Ａは、パッシベーション層より上層の１層目の配線１２０Ａを介して基板主面に形成されたチップパッド（チップ取り出し電極）１３０Ａに接続され、外部端子１１０Ｃは、１層目の配線１２０Ｃにより基板主面に形成されたチップパッド（チップ取り出し電極）１３０Ｃに接続される。また、外部端子１１０Ｂは、パッシベーション層より上層かつ１層目より上層の２層目の配線１２０Ｂを介して基板主面のチップパッド（チップ取り出し電極）１３０Ｂに接続され、外部端子１１０Ｄは、２層目の配線１２０Ｄによりチップパッド（チップ取り出し電極）１３０Ｄに接続される。配線１２０Ａおよび１２０Ｃと、配線１２０Ｂおよび１２０Ｄは、交差するため、パッシベーション層より上層の配線層は、少なくとも２層構造を必要とする。 Next, an example in which the manufacturing method according to the embodiment of the present invention is applied to Fan-in WLP in which the wiring layer above the passivation layer has a two-layer structure is shown in FIGS. The first and second embodiments described above are cited. FIG. 8A shows a schematic plan view of a fan-in type CSP in which external terminals 110A to 110D are formed on the surface of the CSP by WLP. The fan-in type CSP 100 has a plurality of external terminals 110 (110A to 110D) formed on the surface inside the outer shape 100A of the semiconductor chip. The external terminal 110A is connected to a chip pad (chip take-out electrode) 130A formed on the main surface of the substrate via a first layer wiring 120A above the passivation layer, and the external terminal 110C is connected to the first layer wiring 120C. It is connected to a chip pad (chip take-out electrode) 130C formed on the main surface of the substrate. The external terminal 110B is connected to a chip pad (chip take-out electrode) 130B on the main surface of the substrate via a second layer wiring 120B above the passivation layer and above the first layer, and the external terminal 110D has two layers. The wiring 120D is connected to a chip pad (chip extraction electrode) 130D. Since the wirings 120A and 120C and the wirings 120B and 120D intersect, the wiring layer above the passivation layer needs to have at least a two-layer structure.
　図８（Ｂ）は、１層目の配線１２０Ａ、１２０Ｃが終了したときの平面図、図８（Ｃ）は、そのＸ－Ｘ線断面を表している。基板１４０の主面上には、チップパッド１３０Ａ～１３０Ｄが形成され、チップパッド１３０Ａ～１３０Ｄ以外の領域はパッシベーション層１５０によって被覆されている。１層目の配線１２０Ａは、その一方の端部がチップパッド１３０Ａに接続され、その他方の端部が対角線方向に延在するようにパターンニングされ、配線１２０Ｃは、その一方の端部がチップパッド１３０Ｃに接続され、その他方の端部が対角線方向に延在するようにパターンニングされている。また、チップパッド１３０Ｂ、１３０Ｄ上にも、１層目のコンタクトパッド１２２Ｂ、１２２Ｄが同時に形成される。尚、１層目の配線１２０Ａ、１２０Ｃ、１２２Ｂ、１２２Ｄは、上記した第１の実施例（図２（Ａ）ないし図３（Ｈ））までの工程を用いて形成してもよいし、あるいは、図７に示した従来の方法による工程を用いて形成してもよい。ここでの１層目の配線は、シードメタルとその上に電解めっきされた金属の積層にて構成される例を示している。つまり、少なくとも２層目の配線を形成するにあたって、本実施例の製造方法が用いられる。 FIG. 8B is a plan view when the wirings 120A and 120C in the first layer are finished, and FIG. 8C shows a cross section taken along line XX. Chip pads 130A to 130D are formed on the main surface of the substrate 140, and regions other than the chip pads 130A to 130D are covered with a passivation layer 150. The wiring 120A of the first layer is patterned so that one end thereof is connected to the chip pad 130A and the other end extends in a diagonal direction, and the wiring 120C has one end connected to the chip. It is connected to the pad 130C and patterned so that the other end extends in a diagonal direction. In addition, the first contact pads 122B and 122D are simultaneously formed on the chip pads 130B and 130D. The first- layer wirings 120A, 120C, 122B, and 122D may be formed using the steps up to the first embodiment (FIGS. 2A to 3H), or Alternatively, it may be formed by using the conventional method shown in FIG. Here, the first-layer wiring is an example constituted by a stack of a seed metal and a metal electroplated thereon. In other words, the manufacturing method of this embodiment is used for forming at least the second-layer wiring.
　次に、２層目の配線を形成する。前述の第２の実施例（図５ないし図６）を引用している。図９（Ａ）、（Ｂ）に示すように、基板全面に感光性絶縁樹脂１６０が塗布され、次に、図９（Ｃ）、（Ｄ）に示すように、グレイティングマスクを用いて感光性絶縁樹脂１６０が露光される。図９（Ｃ）では、露光される領域１６０Ａ、１６０Ｂが実線で示されている。１層目のコンタクトパッド１２２Ｂ、１２２Ｄに整合する感光性絶縁樹脂１６０の領域は、コンタクトパッド１２２Ｂ、１２２Ｄへの開口が形成されるように比較的大きな光量で露光され、２層目の配線１２０Ｂ（図８（Ａ））、１２０Ｄ（図８（Ａ））が形成される領域１６０Ａは、感光性絶縁樹脂１６０の所定の膜厚が残存されるように比較的小さな光量で露光される。１層目の配線１２０Ａ、１２０Ｃのそれぞれの端部に整合する２つの領域１６０Ｂも同様に、１層目の配線１２０Ａ、１２０Ｃへの開口が形成されるように比較的大きな光量で露光される。 Next, the second layer wiring is formed. The second embodiment described above (FIGS. 5 to 6) is cited. As shown in FIGS. 9A and 9B, a photosensitive insulating resin 160 is applied to the entire surface of the substrate. Next, as shown in FIGS. 9C and 9D, exposure is performed using a grating mask. The conductive insulating resin 160 is exposed. In FIG. 9C, the exposed areas 160A and 160B are indicated by solid lines. The region of the photosensitive insulating resin 160 aligned with the first contact pads 122B and 122D is exposed with a relatively large amount of light so as to form openings to the contact pads 122B and 122D, and the second layer wiring 120B ( 8A) and 120D (FIG. 8A) are exposed with a relatively small amount of light so that a predetermined film thickness of the photosensitive insulating resin 160 remains. Similarly, the two regions 160B aligned with the respective ends of the first- layer wirings 120A and 120C are also exposed with a relatively large amount of light so as to form openings to the first- layer wirings 120A and 120C.
　次に、図１０（Ａ）、（Ｂ）に示すように、感光性絶縁樹脂１６０の露光領域１６０Ａ、１６０Ｂに対応する１６２、１６４の領域が現像され、これにより、感光性絶縁樹脂１６０には、光量に応じた膜厚の開口部１６２、１６４が形成される。開口部１６２は、コンタクトパッド１２２Ｂ、１２２Ｄに至る深度を有する第１の領域１６２Ａと、第１の領域１６２Ａの深度よりも浅い深度を有し対角線状に一定深さで延在する第２の領域１６２Ｂとを有する。開口部１６４は、１層目の配線１２０Ａ、１２０Ｃに至る第１の領域１６２Ａの深度とほぼ同一な深度を有する。 Next, as shown in FIGS. 10A and 10B, the areas 162 and 164 corresponding to the exposed areas 160A and 160B of the photosensitive insulating resin 160 are developed. The openings 162 and 164 having a film thickness corresponding to the light amount are formed. The opening 162 includes a first region 162A having a depth reaching the contact pads 122B and 122D, and a second region having a depth shallower than that of the first region 162A and extending diagonally at a constant depth. 162B. The opening 164 has substantially the same depth as the depth of the first region 162A reaching the first- layer wirings 120A and 120C.
　次に、図１０（Ｃ）、（Ｄ）に示すように、開口部１６２を含む基板全面に２層目の金属層１７０が形成される。金属層１７０は、ＴｉまたはＣｕ等のシードメタルとその上に電解めっきされたＣｕ金属を含んで構成される。 Next, as shown in FIGS. 10C and 10D, a second metal layer 170 is formed on the entire surface of the substrate including the opening 162. The metal layer 170 includes a seed metal such as Ti or Cu and a Cu metal electrolytically plated thereon.
　次に、図１１（Ａ）、（Ｂ）に示すように、表面の平坦化処理が行われる。平坦化処理は、第１及び第２の実施例のときと同様に、研削、研磨、及び切削の少なくともいずれか一つを用いて行われる。ここでの平坦化処理は、基板主面から一定の高さ以上に存在する金属層１７０および感光性絶縁樹脂１６０が除去される。これにより、感光性絶縁樹脂１６０の開口部１６２内にパターンニングされた２層目の配線１２０Ｂ、１２０Ｄが形成される。配線１２０Ｂ、１２０Ｄは、開口部１６２の形状を転写した形状を含み、第１の領域１６２Ａ（（図１０（Ａ）））に対応する領域においてコンタクトパッド１２２Ｂ、１２２Ｄに接続する。配線１２０Ｂ、１２０Ｄは、第２の領域１６２Ｂに対応する領域において、ほぼ一定の膜厚で延在する。また、開口部１６４（図１０（Ａ））内には、１層目の配線１２０Ａ、１２０Ｃの端部に接続される２層目のコンタクトパッド１２２Ａ、１２２Ｃが形成される。以後、第１の実施例のときと同様にソルダーレジストが形成される。外部端子１１０Ａ１１０Ｃが、夫々対応する開口部１６４の２層目の金属層１７０を介して１層目の配線１２０Ａ、１２０Ｃ、及びチップパッド１３０Ａ、１３０Ｃに電気的に接続する。外部端子１１０Ｂ、１１０Ｄが、夫々対応する２層目の配線１２０Ｂ、１２０Ｄ、及びチップパッド１３０Ｂ、１３０Ｄに電気的に接続する。 Next, as shown in FIGS. 11A and 11B, the surface is flattened. The flattening process is performed using at least one of grinding, polishing, and cutting as in the first and second embodiments. In the planarization process here, the metal layer 170 and the photosensitive insulating resin 160 existing at a certain height or more from the main surface of the substrate are removed. As a result, patterned second layer wirings 120 </ b> B and 120 </ b> D are formed in the opening 162 of the photosensitive insulating resin 160. The wirings 120B and 120D include a shape obtained by transferring the shape of the opening 162, and are connected to the contact pads 122B and 122D in a region corresponding to the first region 162A ((FIG. 10A)). The wirings 120B and 120D extend with a substantially constant film thickness in a region corresponding to the second region 162B. In the opening 164 (FIG. 10A), second-layer contact pads 122A and 122C connected to the ends of the first- layer wirings 120A and 120C are formed. Thereafter, a solder resist is formed in the same manner as in the first embodiment. The external terminals 110A110C are electrically connected to the first wirings 120A and 120C and the chip pads 130A and 130C through the second metal layer 170 of the corresponding opening 164. The external terminals 110B and 110D are electrically connected to the corresponding second- layer wirings 120B and 120D and chip pads 130B and 130D, respectively.
　次に、本発明の実施例に係る製造方法を、パッシベーション層より上層の配線層が２層構造を有するＦａｎ－ｏｕｔ　ＷＬＰに適用したときの例を、図１２ないし図１５に示す。前述の第１及び第２の実施例を引用している。ファンアウトタイプのＣＳＰは、半導体チップと、半導体チップよりも大きな外形を有し当該半導体チップを支持する絶縁樹脂とを有し、外部端子は、半導体チップの外形を超えて絶縁樹脂上に形成されるものである。このタイプは、ファンインタイプよりも多数の外部端子を形成することができる。 Next, an example in which the manufacturing method according to the embodiment of the present invention is applied to Fan-out WLP in which the wiring layer above the passivation layer has a two-layer structure is shown in FIGS. The first and second embodiments described above are cited. The fan-out type CSP has a semiconductor chip and an insulating resin that has a larger outer shape than the semiconductor chip and supports the semiconductor chip, and the external terminals are formed on the insulating resin beyond the outer shape of the semiconductor chip. Is. This type can form a larger number of external terminals than the fan-in type.
　図１２は、ファンアウトタイプのＷＬＰ用基板の製造例を示している。図１２（Ａ）に示すように、パッシベーション層２４４が形成された半導体ウエハーＷを、砥石Ｓまたはレーザを用いてダイシングし、個々の半導体チップに分離し、次いで、図１２（Ｂ）に示すように、各半導体チップ２００を、チップ固定テープ２１０上に整列させる。チップ固定テープ２１０の表面には、接着層２１０Ａが形成されており、半導体チップ２００の主面が接着層２１０Ａにより固定される。半導体チップ２００の主面は、回路素子１４、チップ取り出し電極１８、及び配線１６（図２）が形成されている面である。次に、図１２（Ｃ）に示すように、チップ固定テープ２１０上の各半導体チップ２００の周囲（背面（裏面）、側面）を絶縁樹脂２２０により封止し、図１２（Ｄ）に示すように、チップ固定テープ２１０を接着層２１０Ａと共に剥離することで、ファンアウトＷＬＰ用基板２３０が完成される。 FIG. 12 shows an example of manufacturing a fan-out type WLP substrate. As shown in FIG. 12A, the semiconductor wafer W on which the passivation layer 244 is formed is diced using a grindstone S or a laser, separated into individual semiconductor chips, and then as shown in FIG. 12B. Next, the semiconductor chips 200 are aligned on the chip fixing tape 210. An adhesive layer 210A is formed on the surface of the chip fixing tape 210, and the main surface of the semiconductor chip 200 is fixed by the adhesive layer 210A. The main surface of the semiconductor chip 200 is a surface on which the circuit element 14, the chip extraction electrode 18, and the wiring 16 (FIG. 2) are formed. Next, as shown in FIG. 12C, the periphery (back surface (back surface), side surface) of each semiconductor chip 200 on the chip fixing tape 210 is sealed with an insulating resin 220, as shown in FIG. Then, the chip fixing tape 210 is peeled off together with the adhesive layer 210A, whereby the fan-out WLP substrate 230 is completed.
　図１２（Ｅ）は、ファンアウトＷＬＰ用基板２３０に含まれる１つの半導体チップ２００の拡大断面図である。紙面及び説明の都合上、図１２（Ｄ）の図面に対して天地（主面、裏面）を逆に図示している。半導体チップ２００が示す基板２４０の側面および裏面は、絶縁樹脂２２０によって封止され、その主面が絶縁樹脂２２０から露出される。基板２４０の主面には、チップパッド（チップ取り出し電極）２４２が形成され、チップパッドを除く領域がパッシベーション層２４４によって保護されている。 FIG. 12E is an enlarged cross-sectional view of one semiconductor chip 200 included in the fan-out WLP substrate 230. For the convenience of the drawing and the description, the top and bottom (the main surface and the back surface) are shown opposite to the drawing of FIG. The side surface and the back surface of the substrate 240 indicated by the semiconductor chip 200 are sealed with the insulating resin 220, and the main surface is exposed from the insulating resin 220. A chip pad (chip extraction electrode) 242 is formed on the main surface of the substrate 240, and a region excluding the chip pad is protected by the passivation layer 244.
　本実施例に係る製造方法においてファンアウトＷＬＰ用基板を用いたときの工程は、外部端子が絶縁樹脂２２０上に形成される点を除き、図８ないし図１１に示したファンインＷＬＰ用基板を用いたときの工程と実質的に同様である。このため、参照番号は図８ないし図１１と同一のものを用いて説明する。 The process when the fan-out WLP substrate is used in the manufacturing method according to the present embodiment is performed by using the fan-in WLP substrate shown in FIGS. 8 to 11 except that the external terminals are formed on the insulating resin 220. This is substantially the same as the process used. Therefore, the same reference numerals as those in FIGS. 8 to 11 are used for explanation.
　図１３（Ａ）は、外部端子１１０Ａ～１１０ＤがＣＳＰの表面に形成された状態のファンアウトタイプのＣＳＰの模式的な平面図を表している。外部端子１１０Ａ～１１０Ｄは、半導体チップの外形１００Ａより外側に存在する絶縁樹脂２２０の領域に形成される。外部端子１１０Ａ、１１０Ｃは、パッシベーション層より上層の１層目の配線１２０Ａ、１２０Ｃを介して基板主面上に形成されたチップパッド（チップ取り出し電極）１３０Ａ、１３０Ｂにそれぞれ接続され、外部端子１１０Ｂ、１１０Ｄは、パッシベーション層より上層かつ１層目より上層の２層目の配線１２０Ｂ、１２０Ｄを介して基板主面上に形成されたチップパッド１３０Ｂ、１３０Ｄにそれぞれ接続される。 FIG. 13A shows a schematic plan view of a fan-out type CSP in which external terminals 110A to 110D are formed on the surface of the CSP. The external terminals 110A to 110D are formed in a region of the insulating resin 220 existing outside the outer shape 100A of the semiconductor chip. The external terminals 110A and 110C are respectively connected to chip pads (chip take-out electrodes) 130A and 130B formed on the main surface of the substrate via wirings 120A and 120C in the first layer above the passivation layer. 110D is connected to chip pads 130B and 130D formed on the main surface of the substrate via wirings 120B and 120D in the second layer above the passivation layer and above the first layer, respectively.
　図１３（Ｂ）、（Ｃ）は、基板１４０（図１２（Ｅ）では２４０）および絶縁樹脂２２０の主面上に１層目の配線１２０Ａ、１２０Ｃ、コンタクトパッド１２２Ｂ、１２２Ｄを形成した後に、感光性絶縁樹脂１６０を塗布した状態を示している。図１３（Ｃ）は、図１３（Ｂ）で示すＸ－Ｘ線断面を表している。次に、図１４（Ａ）、（Ｂ）に示すように、グレイティングマスクを用いて感光性絶縁樹脂１６０を露光する。露光領域は、半導体チップの外形１００Ａを跨ぐ領域１６０Ａ、半導体チップの外形１００Ａの外周である領域１６０Ｂの実線で示す範囲である。次に、図１４（Ｃ）、（Ｄ）に示すように、感光性絶縁樹脂１６０が現像され、領域１６０Ａ、１６０Ｂに対応した開口部１６２、１６４が形成される。開口部１６２は、コンタクトパッド１２２Ｂ、１２２Ｄに至る深度の第１の領域１６２Ａと、第１の領域１６２Ａの深度よりも浅い深度を有し感光性絶縁樹脂１６０の所定の膜厚が残存された第２の領域１６２Ｂとを含む。また、開口部１６４は、１層目の配線１２０Ａ、１２０Ｃの端部に至る第１の領域１６２Ａの深度とほぼ同一な深度を有する。次に、図１５（Ａ）、（Ｂ）に示すように、シードメタルおよび電解めっきによる２層目の金属層１７０が基板全面に成膜され、次に、図１５（Ｃ）、（Ｄ）に示すように、金属層および感光性絶縁樹脂１６０の平坦化処理が行われ、２層目の配線１２０Ｂ、１２０Ｄがパターンニングされる。金属層１７０の形成は、第１及び第２の実施例のときと同様に、物理気相成長を用いてもよい。平坦化処理は、第１及び第２の実施例のときと同様に、研削、研磨、及び切削の少なくともいずれか一つを用いて行われる。その後、外部端子１１０Ａ～１１０Ｄが絶縁樹脂２２０の主面上に形成される。 FIGS. 13B and 13C illustrate a case where the first wirings 120A and 120C and the contact pads 122B and 122D are formed on the main surface of the substrate 140 (240 in FIG. 12E) and the insulating resin 220. The state where the photosensitive insulating resin 160 is applied is shown. FIG. 13C shows a cross section taken along line XX shown in FIG. Next, as shown in FIGS. 14A and 14B, the photosensitive insulating resin 160 is exposed using a grating mask. The exposure region is a range indicated by a solid line of a region 160A straddling the outer shape 100A of the semiconductor chip and a region 160B that is the outer periphery of the outer shape 100A of the semiconductor chip. Next, as shown in FIGS. 14C and 14D, the photosensitive insulating resin 160 is developed to form openings 162 and 164 corresponding to the regions 160A and 160B. The opening 162 has a first region 162A having a depth reaching the contact pads 122B and 122D and a depth shallower than that of the first region 162A, and a predetermined thickness of the photosensitive insulating resin 160 remains. 2 regions 162B. In addition, the opening 164 has a depth substantially the same as the depth of the first region 162A that reaches the ends of the first- layer wirings 120A and 120C. Next, as shown in FIGS. 15A and 15B, a second metal layer 170 by seed metal and electrolytic plating is formed on the entire surface of the substrate, and then FIGS. 15C and 15D. As shown in FIG. 3, the metal layer and the photosensitive insulating resin 160 are planarized, and the second- layer wirings 120B and 120D are patterned. For the formation of the metal layer 170, physical vapor deposition may be used as in the first and second embodiments. The flattening process is performed using at least one of grinding, polishing, and cutting as in the first and second embodiments. Thereafter, the external terminals 110A to 110D are formed on the main surface of the insulating resin 220.
　次に、本発明の第３の実施例について説明する。第１及び第２の実施例と異なる点を中心に説明し、ほぼ重複する部分は第１及び第２の実施例を準用する。図１６は、本発明の第３の実施例による製造方法を説明する図である。図１６（Ａ）に示すように、ＷＬＰ等に用いられる基板もしくは配線層などの下地層３００上に感光性絶縁樹脂３１０が塗布される。例えば、下地層３００は、図２（Ｃ）が示すシリコン基板１２、配線層（チップ取り出し電極１８及び配線１６）、及びパッシベーション層２０を含む。次に、図１６（Ｂ）に示すように、グレイティングマスク３２０を用いて感光性絶縁樹脂３１０を露光する。第３の実施例では、グレイティングマスク３２０は、光透過率を異にする複数の透過領域を備える。図の例では、それぞれの光透過率が（０）、（０．３）、（０．５）、（０．７）、（１）となる複数の領域がグレイティングマスク３２０に形成されている。光透過率が（０）とは、感光性絶縁樹脂３１０が実質的に感光しない、ということである。感光性絶縁樹脂３１０を現像すると、図１６（Ｃ）に示すように、感光性絶縁樹脂３１０には、それぞれの露光量に応じて絶縁樹脂の膜厚が異なる複数の開口部３１２が形成される。次に、図１６（Ｄ）に示すように、感光性絶縁樹脂３２０を覆うように金属層３３０を形成し、その後、下地層３００の主面から高さｈ１の面Ｋ１で平坦化処理を行うことで、図１６（Ｆ）に示すような膜厚を異にする複数の金属配線３３２を得ることができる。金属配線３３２の膜厚を可変することで、複数の金属配線３３２それぞれの配線抵抗値を調整することができる。配線抵抗値は、線幅が同一であれば、断面積に依存するからである。金属配線３３２の膜厚は、使用する環境（複数の金属配線３３２の夫々が求められる電気特性スペック及び信頼性スペック）に応じて適宜選択される。尚、グレイティングマスク３２０は、ハーフトーンマスクに置き換えることが出来る。尚、金属層３３０の形成は、第１及び第２の実施例と同様に物理気相成長や電解めっきを用いて行われる。尚、平坦化処理は、研削、研磨、及び切削の少なくともいずれか一つを用いて行われる。絶縁樹脂３１０の材料は、第１及び第２の実施例で開示したすべての材料が適用できる。 Next, a third embodiment of the present invention will be described. Differences from the first and second embodiments will be mainly described, and the first and second embodiments will be applied mutatis mutandis to the substantially overlapping portions. FIG. 16 is a diagram for explaining a manufacturing method according to the third embodiment of the present invention. As shown in FIG. 16A, a photosensitive insulating resin 310 is applied on a base layer 300 such as a substrate or a wiring layer used for WLP or the like. For example, the base layer 300 includes the silicon substrate 12 illustrated in FIG. 2C, the wiring layer (the chip extraction electrode 18 and the wiring 16), and the passivation layer 20. Next, as shown in FIG. 16B, the photosensitive insulating resin 310 is exposed using a grating mask 320. In the third embodiment, the grating mask 320 includes a plurality of transmission regions having different light transmittances. In the example shown in the figure, a plurality of regions having respective light transmittances of (0), (0.3), (0.5), (0.7), and (1) are formed on the grating mask 320. Yes. The light transmittance of (0) means that the photosensitive insulating resin 310 is not substantially exposed to light. When the photosensitive insulating resin 310 is developed, as shown in FIG. 16C, a plurality of openings 312 having different thicknesses of the insulating resin are formed in the photosensitive insulating resin 310 in accordance with the respective exposure amounts. . Next, as shown in FIG. 16D, a metal layer 330 is formed so as to cover the photosensitive insulating resin 320, and thereafter, a planarization process is performed on a surface K1 having a height h1 from the main surface of the base layer 300. Thus, a plurality of metal wirings 332 having different film thicknesses as shown in FIG. By varying the film thickness of the metal wiring 332, the wiring resistance value of each of the plurality of metal wirings 332 can be adjusted. This is because the wiring resistance value depends on the cross-sectional area if the line width is the same. The film thickness of the metal wiring 332 is appropriately selected according to the environment to be used (electric characteristic specifications and reliability specifications for which each of the plurality of metal wirings 332 is required). The grating mask 320 can be replaced with a halftone mask. The formation of the metal layer 330 is performed using physical vapor deposition or electrolytic plating as in the first and second embodiments. The flattening process is performed using at least one of grinding, polishing, and cutting. As the material of the insulating resin 310, all materials disclosed in the first and second embodiments can be applied.
　図１７は、本発明の第３の実施例の変形例を説明する図である。図１７（Ａ）に示すように、ＷＬＰ等に用いられる基板もしくは配線層などの下地層３００上に感光性絶縁樹脂３１０Ａが塗布され、次に、図１７（Ｂ）に示すように、グレイティングマスク３２０Ａを用いて感光性絶縁樹脂３１０Ａが露光される。当該変形例では、グレイティングマスク３２０Ａは、光透過率が異なる透過領域が連続的に形成されている。図の例では、感光性絶縁樹脂３１０が実質的に感光する領域の視点において、光透過率が右方向へ（１）、（０．７）、（０．５）、（０．３）となる複数の領域が連続して形成され、かつ光透過率が一方向に大きく（または小さく）なるように配列されている。つまり、光透過率が（１）から（０）、または（０）から（１）に向かってデジタル値またはアナログ値として連続的に変化する一体化された一つの領域である。ここにおいては、光透過率がデジタル方式の事例である。次に、感光性絶縁樹脂３１０Ａを現像すると、図１７（Ｃ）に示すように、感光性絶縁樹脂３１０Ａには、膜厚が段階的（ステップ状）に変化するような開口部３１４が形成される。次に、図１７（Ｄ）に示すように金属層３３０を形成し、下地層３００の主面から高さｈ１の面Ｋ１で平坦化処理を行うことで、図１７（Ｅ）に示すように開口部３１４内に膜厚が異なる金属配線３３２Ａを形成することができる。金属層３３２Ａの形成は、第１及び第２の実施例のときと同様に、物理気相成長を用いてもよい。平坦化処理は、第１及び第２の実施例のときと同様に、研削、研磨、及び切削の少なくともいずれか一つを用いて行われる。その後、ソルダーレジストを形成し、その後、外部端子が金属層３３２Ａに接続するように、例えば図１７（Ｅ）に記述される符号３３２Ａの付近に形成される。また、グレイティングマスク３２０Ａの光透過率が線形（アナログ値；アナログ方式）に変化するように構成すれば、図１７（Ｆ）に示すように、開口部３１４の残存する膜厚を線形（スロープ状）に傾斜させることができ、対応する金属配線３３２Ａの膜厚もより線形に変化させることができる。更に、金属層３３２Ａの形成の高さを、高さｈ１よりも低く制御すれば、金属配線３３２Ａの膜厚を一定にしつつ線形の傾斜とすることが出来る。 FIG. 17 is a diagram for explaining a modification of the third embodiment of the present invention. As shown in FIG. 17A, a photosensitive insulating resin 310A is applied on a base layer 300 such as a substrate or a wiring layer used for WLP or the like. Next, as shown in FIG. The photosensitive insulating resin 310A is exposed using the mask 320A. In the modification, the grating mask 320A is continuously formed with transmissive regions having different light transmittances. In the example of the figure, the light transmittance is (1), (0.7), (0.5), (0.3) in the right direction from the viewpoint of the region where the photosensitive insulating resin 310 is substantially exposed. Are arranged in such a manner that the light transmittance is increased (or decreased) in one direction. That is, it is an integrated region in which the light transmittance continuously changes as a digital value or an analog value from (1) to (0) or from (0) to (1). Here, the light transmittance is an example of a digital system. Next, when the photosensitive insulating resin 310A is developed, as shown in FIG. 17C, the photosensitive insulating resin 310A is formed with an opening 314 whose film thickness changes stepwise. The Next, as shown in FIG. 17E, a metal layer 330 is formed as shown in FIG. 17D, and planarization is performed on the surface K1 having a height h1 from the main surface of the base layer 300, as shown in FIG. Metal wirings 332A having different film thicknesses can be formed in the openings 314. For the formation of the metal layer 332A, physical vapor deposition may be used as in the first and second embodiments. The flattening process is performed using at least one of grinding, polishing, and cutting as in the first and second embodiments. Thereafter, a solder resist is formed, and then, for example, it is formed in the vicinity of reference numeral 332A described in FIG. 17E so that the external terminal is connected to the metal layer 332A. If the light transmittance of the grating mask 320A changes linearly (analog value; analog method), the remaining film thickness of the opening 314 is linear (slope) as shown in FIG. The film thickness of the corresponding metal wiring 332A can be changed more linearly. Furthermore, if the formation height of the metal layer 332A is controlled to be lower than the height h1, the thickness of the metal wiring 332A can be made constant while being linear.
　図１８（Ａ）は、図１７（Ｆ）に対応し、第３の実施例のようなグレイティングマスク３２０Ａを用いて感光性絶縁樹脂３１０Ａを露光したときに得られる金属配線３３２Ｂを立体的な斜視図で表している。図１８（Ｂ）に示すように、感光性絶縁樹脂３５０に形成された開口部３５２が、下地層３４０の主面に形成された導電領域３４２に至るコンタクトホール３５２Ａと、当該コンタクトホール３５２Ａに繋がる配線を形成する溝３５２Ｂとを有するとき、溝３５２Ｂが一様な深度であれば、コンタクトホール３５３Ａとの境界には、ほぼ直角の段差が形成される。この場合、金属配線３６０は、図１８（Ｃ）に示すように、ほぼ直角の段差コーナー部分に直角の段差に倣った膜厚が形成される。例えば、ポリイミド等の感光性絶縁樹脂３５０は、ベーキングにより体積を収縮させるため、金属配線３６０のコーナー部分３６２には、Ｘ方向の応力Ｐｘ、Ｙ方向の応力Ｐｙが合成された応力Ｐが生ずる。よって、信頼性の視点から合力Ｐに関連する「金属配線３６０の断線または絶縁樹脂３５０の破壊、若しくは金属配線３６０と絶縁樹脂３５０の密着性の劣化」を吟味しなければならない。一方、図１８（Ｄ）、（Ｆ）は、本実施例のように感光性絶縁樹脂３１０Ａの開口部の側面（断面）の少なくとも一部に傾斜を持たせることで、コーナー部分の傾斜をなだらかにすることができ、コーナー部分に生じる応力Ｐを低減することができる。図１７（Ｅ）の形状においても、応力Ｐを低減することができる。更に、金属配線３６０の形状に関連して、図１７（Ｅ）のステップ状、図１７（Ｆ）、図１８（Ａ）及び図１８（Ｄ）のスロープ状の形状は、耐湿性の視点からの信頼性をも向上させる。例えば、図１７（Ｆ）の符号３３２Ｂが記載される場所には、図３（Ｋ）に示す外部端子７０と同様に外部端子（不図示）が形成される。その外部端子以外の領域には、図３（Ｉ）に示されるソルダーレジスト６０と同様に、基板全面にソルダーレジストが形成される。ここで、水分は外部端子または外部端子と、ソルダーレジストとの境界部から侵入し、金属配線（金属層３３０）と絶縁樹脂３１０Ａと境界に沿ってチップ取り出し電極（不図示。図２（Ａ）に示すチップ取り出し電極１８と同様）へ進行する。そして、最終的にはチップ取り出し電極を腐食させる。本願の半導体装置は、その外部端子が大地側のマザーボードに向いて接続されるのが一般的である。例えば、図３（Ｋ）に示す外部端子７０が、その図面を１８０度回転させた状態である。よって、水分は、スロープ状（図１７（Ｆ））の形状を介して重力方向と反対方向へ移動しなければならない。言い換えれば、スロープ形状は、水分のチップ取り出し電極への移動を抑制する。図１７（Ｅ）のステップ形状においても同様である。更に、スロープ状（図１７（Ｆ））の金属配線（金属層３３０）及びステップ状（図１７（Ｅ））の金属配線（金属層３３０）の夫々の体積は、図１８（Ｂ）の金属配線３６０の体積よりも大きい。よって、腐食による金属配線の断線も抑止できる。 FIG. 18A corresponds to FIG. 17F, and shows a three-dimensional view of the metal wiring 332B obtained when the photosensitive insulating resin 310A is exposed using the grating mask 320A as in the third embodiment. It is represented by a perspective view. As shown in FIG. 18B, the opening 352 formed in the photosensitive insulating resin 350 is connected to the contact hole 352A reaching the conductive region 342 formed in the main surface of the base layer 340 and the contact hole 352A. If the groove 352B has a uniform depth when the groove 352B for forming the wiring is provided, a substantially perpendicular step is formed at the boundary with the contact hole 353A. In this case, as shown in FIG. 18C, the metal wiring 360 is formed with a film thickness that follows the step at a right angle at a substantially right step corner portion. For example, since the photosensitive insulating resin 350 such as polyimide shrinks its volume by baking, a stress P obtained by combining the stress Px in the X direction and the stress Py in the Y direction is generated in the corner portion 362 of the metal wiring 360. Therefore, from the viewpoint of reliability, “disconnection of the metal wiring 360 or destruction of the insulating resin 350 or deterioration of the adhesion between the metal wiring 360 and the insulating resin 350” related to the resultant force P must be examined. On the other hand, in FIGS. 18D and 18F, the inclination of the corner portion is made gentle by providing an inclination to at least a part of the side surface (cross section) of the opening of the photosensitive insulating resin 310A as in this embodiment. And the stress P generated in the corner portion can be reduced. Also in the shape of FIG. 17E, the stress P can be reduced. Further, in relation to the shape of the metal wiring 360, the step shape of FIG. 17 (E) and the slope shape of FIG. 17 (F), FIG. 18 (A) and FIG. 18 (D) are from the viewpoint of moisture resistance. Also improve the reliability. For example, an external terminal (not shown) is formed at the place where the reference numeral 332B in FIG. 17F is described, similarly to the external terminal 70 shown in FIG. Similar to the solder resist 60 shown in FIG. 3I, a solder resist is formed on the entire surface of the substrate other than the external terminals. Here, moisture enters from the boundary between the external terminal or the external terminal and the solder resist, and the chip take-out electrode (not shown; To the chip take-out electrode 18 shown in FIG. Finally, the chip takeout electrode is corroded. The semiconductor device of the present application is generally connected with its external terminals facing the mother board on the ground side. For example, the external terminal 70 shown in FIG. 3K is in a state where the drawing is rotated 180 degrees. Therefore, the moisture must move in the direction opposite to the direction of gravity through the slope shape (FIG. 17F). In other words, the slope shape suppresses the movement of moisture to the chip extraction electrode. The same applies to the step shape of FIG. Further, the respective volumes of the metal wiring (metal layer 330) in the slope shape (FIG. 17F) and the metal wiring (metal layer 330) in the step shape (FIG. 17E) are the same as the metal in FIG. The volume of the wiring 360 is larger. Therefore, disconnection of the metal wiring due to corrosion can be suppressed.
　次に、本発明の第４の実施例について説明する。第３の実施例と異なる点を中心に説明し、ほぼ重複する部分は第３の実施例を準用する。図１９（Ａ）に示すように、下地層４００の主面には、配線層に含まれる複数の導電領域（例えば、配線４０４やチップ取り出し電極４０２）が形成され、それを覆うように感光性絶縁樹脂４１０が形成される。グレイティングマスクの光透過率を調整することで、感光性絶縁樹脂４１０には、開口部４１２が形成される。開口部４１２は、チップ取り出し電極４０２に至る深度を有する第１の領域４１２Ａと、第１の領域４１２Ａの深度よりも浅い深度の第２の領域４１２Ｂと、第２の領域４１２Ｂよりも深度が浅い第３の領域４１２Ｃとを有する。第３の領域４１２Ｃは、配線４０４と重複する位置に形成される。そして、図１９（Ｂ）に示すように、金属配線４２０が形成されたとき、金属配線４２０は、チップ取り出し電極４０２に電気的に接続されるとともに、配線４０４との間には、比較的厚い絶縁樹脂４１０の膜厚が残存される。よって、金属配線４２０と配線４０４との間の寄生容量Ｃｐを削減することができる。 Next, a fourth embodiment of the present invention will be described. Differences from the third embodiment will be mainly described, and the third embodiment will be applied mutatis mutandis to the substantially overlapping portions. As shown in FIG. 19A, a plurality of conductive regions (for example, the wiring 404 and the chip extraction electrode 402) included in the wiring layer are formed on the main surface of the base layer 400, and are photosensitive so as to cover them. An insulating resin 410 is formed. An opening 412 is formed in the photosensitive insulating resin 410 by adjusting the light transmittance of the grating mask. The opening 412 has a first region 412A having a depth reaching the chip extraction electrode 402, a second region 412B having a depth smaller than the depth of the first region 412A, and a depth smaller than the second region 412B. And a third region 412C. The third region 412C is formed at a position overlapping with the wiring 404. Then, as shown in FIG. 19B, when the metal wiring 420 is formed, the metal wiring 420 is electrically connected to the chip extraction electrode 402 and is relatively thick between the wiring 404. The film thickness of the insulating resin 410 remains. Therefore, the parasitic capacitance Cp between the metal wiring 420 and the wiring 404 can be reduced.
　次に、本発明の第５の実施例について説明する。第３及び第４の実施例と異なる点を中心に説明し、ほぼ重複する部分は第３の実施例を準用する。図２０（Ａ）に示すように、下地層５００の主面には、導電領域５０２（配線５０２）が形成され、それを覆うように感光性絶縁樹脂５１０が形成される。ここで、図１７（Ｂ）に示したようにグレイティングマスクの光透過率を連続的に変化させることで、感光性絶縁樹脂５１０の開口部５１２の側面５１２Ａに様々な形状のテーパを形成することができる。例えば、同図に示すように、開口部５１２が導電領域５０２とオーバラップするとき、側面５１２Ａに正テーパを形成する。次いで、全面に金属層が形成され、表面の平坦化処理を行うことで、図２０（Ｂ）に示すように絶縁樹脂５１０の正テーパに対応した逆テーパ（逆三角形）の金属配線５２０が形成される。金属配線５２０は、開口部５１２の側面の正テーパによって、導電領域５０２と対向する容量結合面積が小さくなり、寄生容量Ｃｐが低減される。さらに、金属配線５２０の幅は、テーパにならって上方に向けて拡大されるため、金属配線５２０の電流密度を向上させることができ、配線５０２の低抵抗化を図ることができる。テーパの形状は、三角形、台形、半円形、半楕円形、等様々に適用できる。更に、グレイティングマスクの光透過率を、例えばチェッカーパターンを実現する様にマトリックス状またはアレイ状に制御することによって、テーパの線分を更に凹凸に、つまり絶縁樹脂５１０の表面を凹凸（patterned indented surface）に形成することも有用である。絶縁樹脂５１０と面接触する金属配線５２０の表面は、絶縁樹脂５１０の凹凸形状に対応した凸凹形状となる。これにより、両者の密着性が向上し、且つ水分の浸水路の経路総長が長くなり耐湿性が向上する。絶縁樹脂５１０の表面の処理は、ドライエッチ等の化学的処理によっても凹凸形状に形成できる。 Next, a fifth embodiment of the present invention will be described. Differences from the third and fourth embodiments will be mainly described, and the third embodiment will be applied mutatis mutandis to the overlapping portions. As shown in FIG. 20A, a conductive region 502 (wiring 502) is formed on the main surface of the base layer 500, and a photosensitive insulating resin 510 is formed so as to cover it. Here, as shown in FIG. 17B, by continuously changing the light transmittance of the grating mask, tapers having various shapes are formed on the side surface 512A of the opening 512 of the photosensitive insulating resin 510. be able to. For example, as shown in the figure, when the opening 512 overlaps the conductive region 502, a positive taper is formed on the side surface 512A. Next, a metal layer is formed on the entire surface, and the surface is flattened to form a metal wiring 520 having a reverse taper (inverted triangle) corresponding to the normal taper of the insulating resin 510 as shown in FIG. Is done. In the metal wiring 520, due to the positive taper of the side surface of the opening 512, the capacitive coupling area facing the conductive region 502 is reduced, and the parasitic capacitance Cp is reduced. Furthermore, since the width of the metal wiring 520 is increased upward along the taper, the current density of the metal wiring 520 can be improved and the resistance of the wiring 502 can be reduced. The taper can be applied in various shapes such as a triangle, a trapezoid, a semicircle, and a semi-elliptical shape. Further, by controlling the light transmittance of the grating mask in, for example, a matrix shape or an array shape so as to realize a checker pattern, the taper line segment is further uneven, that is, the surface of the insulating resin 510 is uneven (patternedpatternindented). Surface) is also useful. The surface of the metal wiring 520 that is in surface contact with the insulating resin 510 has an uneven shape corresponding to the uneven shape of the insulating resin 510. Thereby, both adhesiveness improves and the path | route total length of the water immersion path becomes long, and moisture resistance improves. The surface treatment of the insulating resin 510 can be formed into a concavo-convex shape by chemical treatment such as dry etching.
　このテーパの線分の凹凸形状は、図１７（Ｆ）が示すスロープ状の線分にも適用できる。図１７（Ｂ）に示すグレイティングマスク３２０Ａにおいて、その光透過率が（１）から（０．３）の方向へ、微小な増減をアナログ的またはデジタル的に繰り返しながら透過領域を形成すればよい。更に、その透過領域において微小な増減をＸ及びＹ方向にそれぞれ展開することで、例えば図１７Ａに示されるように微小な高低差のレイアウトパターンを実現する。図１７Ａは、スロープ状の絶縁樹脂３１０Ａにおけるチェッカーパターン３１０Ｂ（突起状のポジティブなドッドアレイパターン３１０Ｂ）を示す。スロープ状における対応する金属配線３３２Ａも、チェッカーパターン３１０Ｂに対応して格子状（不図示）となる。他方、このテーパの線分の凹凸形状は、図１７（Ｅ）が示すステップ状の線分にも適用できる。図１７（Ｂ）に示すグレイティングマスク３２０Ａにおいて、その光透過率が（１）から（０．３）の方向へ、ステップ毎（（１）毎、（０．７）毎、（０．５）毎、（０．３）毎）に微小な増減をアナログ的またはデジタル的に繰り返しながら透過領域を形成すればよい。更に、ステップ毎の透過領域において、微小な増減をＸ及びＹ方向にそれぞれ展開することで、ステップ毎に図１７Ａと同様なレイアウトパターンを実現する。尚、絶縁樹脂の表面のポジティブなドッドアレイパターン３１０Ｂは、ネガティブなドッドアレイパターンであってもよい。凹凸形状は、幾何学模様なパターンであればよく、つまりチェッカーパターンに限られず例えばストライプパターンであってもよい。 The uneven shape of this taper line segment can also be applied to the slope-shaped line segment shown in FIG. In the grating mask 320A shown in FIG. 17B, the transmissive region may be formed while repeating a slight increase and decrease in an analog or digital manner in the light transmittance direction from (1) to (0.3). . Further, a minute increase / decrease is developed in the transmissive region in the X and Y directions, respectively, thereby realizing a minute layout pattern having a height difference as shown in FIG. 17A, for example. FIG. 17A shows a checker pattern 310B (protruding positive dod array pattern 310B) in slope-shaped insulating resin 310A. The corresponding metal wiring 332A in the slope shape also has a lattice shape (not shown) corresponding to the checker pattern 310B. On the other hand, the uneven shape of the tapered line segment can also be applied to the step-shaped line segment shown in FIG. In the grating mask 320A shown in FIG. 17B, the light transmittance is changed from (1) to (0.3) in steps (every (1), every (0.7), (0.5). ), And every (0.3)), the transmission region may be formed while repeating a minute increase / decrease in an analog or digital manner. Further, in the transmission region for each step, a minute increase / decrease is developed in the X and Y directions, thereby realizing a layout pattern similar to FIG. 17A for each step. The positive dod array pattern 310B on the surface of the insulating resin may be a negative dod array pattern. The uneven shape may be a geometric pattern, that is, not limited to a checker pattern, and may be a stripe pattern, for example.
　次に、本発明の第６の実施例について説明する。図２１（Ａ）は、第１の実施例で説明した図４（Ｃ）に対応する図である。第１～第５の実施例と異なる点を中心に説明し、ほぼ重複する部分は第１～第５の実施例を準用する。第６の実施例では、基板１２上の主面上の選択されたチップ取り出し電極間を金属層で共通接続するものである。図２１（Ｂ）に示すように、共通配線すべき２つのチップ取り出し電極にそれぞれ整合する領域に比較的大きな光量Ｌ１を照射し、それ以外の金属配線をパターンニングする領域に比較的小さな光量Ｌ２を照射するようにグレイティングマスク４０が構成される。図の例では、両側にあるチップ取り出し電極にそれぞれ整合する領域に、光量Ｌ１が照射される。 Next, a sixth embodiment of the present invention will be described. FIG. 21A is a diagram corresponding to FIG. 4C described in the first embodiment. Differences from the first to fifth embodiments will be mainly described, and the first to fifth embodiments will be applied mutatis mutandis to the substantially overlapping portions. In the sixth embodiment, selected chip take-out electrodes on the main surface on the substrate 12 are commonly connected by a metal layer. As shown in FIG. 21B, a relatively large amount of light L1 is applied to the regions that are respectively aligned with the two chip extraction electrodes that are to be commonly wired, and a relatively small amount of light L2 is applied to the region where other metal wirings are patterned. The grating mask 40 is configured to irradiate. In the example shown in the figure, the light quantity L1 is applied to the regions that are respectively aligned with the chip extraction electrodes on both sides.
　次に、図２１（Ｃ）に示すように、感光性ポリイミド膜３０が現像され、光量Ｌ１、Ｌ２に応じた開口部３２が形成される。開口部３２は、両側のチップ取り出し電極にそれぞれ対応する位置でパッシベーション層２０を露出させる第１の領域３２Ａと、第１の領域３２Ａよりも深度が浅く所定の膜厚を残存させた第２の領域３２Ｂとを有する。第２の領域３２Ｂの両端が第１の領域３２Ａによって挟まれた状態である。 Next, as shown in FIG. 21C, the photosensitive polyimide film 30 is developed to form openings 32 corresponding to the light amounts L1 and L2. The opening 32 has a first region 32A that exposes the passivation layer 20 at a position corresponding to each of the chip extraction electrodes on both sides, and a second region that has a depth smaller than the first region 32A and has a predetermined film thickness. And a region 32B. In this state, both ends of the second region 32B are sandwiched between the first regions 32A.
　感光性ポリイミド膜３０をエッチングマスクに用いてパッシベーション層２０をエッチングする。よって、パッシベーション層２０の複数の第１の領域３２Ａに整合するそれぞれの位置に、チップ取り出し電極を露出させるコンタクトホールが形成される。以後の工程は、第１の実施例のときと同様であり、図２１（Ｄ）に示すように金属層４０が基板全面に成膜され、次いで、基板１２の主面から高さｈ１の面Ｋ１で平坦化処理が行われる。その結果、図２１（Ｅ）に示すように感光性ポリイミド膜３０の開口部内にパターニングされた金属配線４２Ａが形成される。よって、金属配線４２Ａは、両側のチップ取り出し電極を電気的に接続する。例えば、半導体チップには、複数のグランド端子または電源供給端子が設けられることがあり、このような場合に金属配線４２Ａにより、２つの第１の領域３２Ａを一括に、相互接続することができる。 The passivation layer 20 is etched using the photosensitive polyimide film 30 as an etching mask. Therefore, a contact hole for exposing the chip take-out electrode is formed at each position matching the plurality of first regions 32A of the passivation layer 20. The subsequent steps are the same as those in the first embodiment. As shown in FIG. 21D, the metal layer 40 is formed on the entire surface of the substrate, and then the surface having a height h1 from the main surface of the substrate 12 is formed. A flattening process is performed at K1. As a result, a patterned metal wiring 42A is formed in the opening of the photosensitive polyimide film 30 as shown in FIG. Therefore, the metal wiring 42A electrically connects the chip extraction electrodes on both sides. For example, a semiconductor chip may be provided with a plurality of ground terminals or power supply terminals. In such a case, the two first regions 32A can be interconnected together by the metal wiring 42A.
　次に、本発明の第７の実施例について説明する。第１～第６の実施例と異なる点を中心に説明し、ほぼ重複する部分は第１～第６の実施例を準用する。第７の実施例は、図３（Ｊ）に示された「ソルダーレジストのパターニングによる開口６０Ａの形成」を用いないで、外部端子の形成を行うものである。図２２（Ａ）は、第１の実施例の図２（Ｄ）に対応する。図２２（Ｂ）に示すように、グレイティングマスク４０は、光透過量がＬ１＞Ｌ２＞Ｌ３となる光透過領域をもって構成される。但し、これらの光透過領域は連続して形成される。感光性ポリイミド膜３０は、光量Ｌ１、Ｌ２、Ｌ３で露光され、現像されたとき、図２２（Ｃ）に示すような開口部３６が形成される。すなわち、開口部３６は、チップ取り出し電極に至る深度を有する第１の領域３６Ａと、第１の領域３６Ａよりも深度が浅く所定の膜厚が残存された第２の領域３６Ｂと、更に第２の領域３６Ｂよりも深度が浅く所定の膜厚が残存された第３の領域３６Ｃとを有する。 Next, a seventh embodiment of the present invention will be described. Differences from the first to sixth embodiments will be mainly described, and the first to sixth embodiments will be applied mutatis mutandis to the substantially overlapping portions. In the seventh embodiment, the external terminals are formed without using the “formation of the opening 60A by the patterning of the solder resist” shown in FIG. FIG. 22A corresponds to FIG. 2D of the first embodiment. As shown in FIG. 22B, the grating mask 40 includes a light transmission region where the light transmission amount is L1> L2> L3. However, these light transmission regions are formed continuously. When the photosensitive polyimide film 30 is exposed and developed with the light amounts L1, L2, and L3, an opening 36 as shown in FIG. 22C is formed. That is, the opening 36 includes a first region 36A having a depth reaching the chip extraction electrode, a second region 36B having a depth smaller than the first region 36A and having a predetermined film thickness, and a second region 36B. And a third region 36C having a predetermined film thickness that is shallower than the region 36B.
　次に、図２２（Ｄ）に示すように、ポリイミド膜３０の開口部３６に関連する金属層５０がほぼ一定の膜厚で感光性ポリイミド膜３０の表面の基準線を越えない様に基板全面に形成され、次に、図２３（Ｅ）に示すように、金属層５０を覆うようにソルダーレジスト６０が塗布される。次に、基板１２の主面から高さｈ１の面Ｋ１で平坦化処理が行われる。この高さｈ１は、第３の領域３６Ｃ上の金属層５０の一部が残存され露出される高さである。これにより、図２３（Ｆ）に示すように、開口部３６の第１の領域３６Ａには金属層５０の一部及びソルダーレジスト６２が残存し、第２の領域３６Ｂには金属層５０の一部及びソルダーレジスト６２が存し、第３の領域３６Ｃは金属配線５２が残存し且つソルダーレジスト６０が残存しない。つまり、金属配線５２は、ソルダーレジスト６２と感光性ポリイミド膜３０によって露出された状態となる。次に、図２３（Ｇ）に示すように、金属配線５２上に外部端子としての半田ボール７０が形成される。尚、図２３（Ｈ）に示される様に、半田ボール７０に代えて、ボンダーによるボンディングワイヤ７１であってもよい。露出された金属配線５２の領域は、実質的に半田ボール７０またはボンディングワイヤ７１と、金属配線５２との接続面積に等しい。ボンディングワイヤ７１を適用する場合、更に、モールドレジン７３がボンディングワイヤ７１を封止するように適用される。モールドレジン７３は、ソルダーレジスト６２及びポリイミド膜３０（第１の絶縁層）をもカバーする。尚、符号７２は金属材であり、半導体装置６００の外部にその一部を露出する。金属材７２は、ボンディングワイヤ７１に電気的に接続し、よってチップ取り出し電極１８に電気的に接続する。 Next, as shown in FIG. 22D, the entire surface of the substrate so that the metal layer 50 associated with the opening 36 of the polyimide film 30 does not exceed the reference line on the surface of the photosensitive polyimide film 30 with a substantially constant film thickness. Next, as shown in FIG. 23E, a solder resist 60 is applied so as to cover the metal layer 50. Next, a planarization process is performed on a surface K1 having a height h1 from the main surface of the substrate 12. The height h1 is a height at which a part of the metal layer 50 on the third region 36C remains and is exposed. Thus, as shown in FIG. 23F, a part of the metal layer 50 and the solder resist 62 remain in the first region 36A of the opening 36, and one part of the metal layer 50 remains in the second region 36B. And the solder resist 62, the metal wiring 52 remains in the third region 36C, and the solder resist 60 does not remain. That is, the metal wiring 52 is exposed by the solder resist 62 and the photosensitive polyimide film 30. Next, as shown in FIG. 23G, solder balls 70 as external terminals are formed on the metal wiring 52. As shown in FIG. 23H, a bonding wire 71 using a bonder may be used instead of the solder ball 70. The exposed region of the metal wiring 52 is substantially equal to the connection area between the solder ball 70 or the bonding wire 71 and the metal wiring 52. When the bonding wire 71 is applied, the mold resin 73 is further applied so as to seal the bonding wire 71. The mold resin 73 also covers the solder resist 62 and the polyimide film 30 (first insulating layer). Reference numeral 72 denotes a metal material, and a part thereof is exposed to the outside of the semiconductor device 600. The metal material 72 is electrically connected to the bonding wire 71 and thus is electrically connected to the chip extraction electrode 18.
　第７の実施例によれば、ソルダーレジストをフォトリソ工程によりパターニングする必要がなくなるので、ＷＬＰによる工程数をさらに削減することができ、製造コストを低減することが可能になる。 According to the seventh embodiment, since it is not necessary to pattern the solder resist by a photolithography process, the number of processes by WLP can be further reduced, and the manufacturing cost can be reduced.
　第１～７の実施例の開示によれば、工程数を削減できると共に、過酷な外部環境条件であるパッシベーション層の更なる上層に適用される絶縁層及び金属配線層に対して、信頼性を向上させる。例えば、電気的特性または信頼性を考慮して、金属配線の体積量（断面積量）を任意に設定できる。その金属層を埋設する絶縁層の開口部の形状を任意に設定できる。 According to the disclosure of the first to seventh embodiments, the number of processes can be reduced, and reliability can be improved with respect to the insulating layer and the metal wiring layer applied to the upper layer of the passivation layer, which is a severe external environmental condition. Improve. For example, the volume amount (cross-sectional area amount) of the metal wiring can be arbitrarily set in consideration of electrical characteristics or reliability. The shape of the opening of the insulating layer in which the metal layer is embedded can be arbitrarily set.
　以上、本発明の好ましい実施の形態について詳述したが、本発明は、特定の実施形態に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。例えば、第３の実施例で開示したステップ構造（例えば図１７（Ｅ））及びスロープ構造（例えば図１７（Ｆ）、図１８（Ｄ））、第４の実施例で開示した寄生容量Ｃｐを削減する構造（例えば図１９（Ｂ））、第５の実施例で開示した寄生容量Ｃｐを削減する構造（例えば図２０（Ｂ））、及び第６の実施例で開示した構造（例えば図２１（Ｅ））のそれぞれは、第２の実施例で開示した２層配線の構造（例えば、図６（Ｅ））において、少なくとも１層目の構造及び２層目の構造のいずれかに適用できる。また、第７の実施例で開示した構造は、第２の実施例で開示した２層配線の構造（例えば、図６（Ｅ））において、２層目の構造に適用できる。尚、第３～第７の実施例で開示したそれぞれの構造は、ファンインタイプのＣＳＰの半導体装置（例えば、図１１）及びファンアウトタイプのＣＳＰの半導体装置（例えば、図１５（Ｄ））にそれぞれ適用できる。 The preferred embodiment of the present invention has been described in detail above, but the present invention is not limited to the specific embodiment, and various modifications can be made within the scope of the present invention described in the claims. Deformation / change is possible. For example, the step structure (for example, FIG. 17 (E)) and the slope structure (for example, FIG. 17 (F), FIG. 18 (D)) disclosed in the third embodiment, and the parasitic capacitance Cp disclosed in the fourth embodiment are used. The structure to be reduced (for example, FIG. 19B), the structure to reduce the parasitic capacitance Cp disclosed in the fifth embodiment (for example, FIG. 20B), and the structure disclosed in the sixth embodiment (for example, FIG. 21). Each of (E)) can be applied to at least one of the structure of the first layer and the structure of the second layer in the structure of the two-layer wiring disclosed in the second embodiment (for example, FIG. 6E). . The structure disclosed in the seventh embodiment can be applied to the structure of the second layer in the structure of the two-layer wiring disclosed in the second embodiment (for example, FIG. 6E). Each of the structures disclosed in the third to seventh embodiments includes a fan-in type CSP semiconductor device (for example, FIG. 11) and a fan-out type CSP semiconductor device (for example, FIG. 15D). Applicable to each.
１０：半導体チップ
１２：シリコン基板
１２Ａ：主面
１４：回路素子
１６：配線
１８：チップ取り出し電極
２０：パッシベーション層
２０Ａ：開口
３０：感光性ポリイミド膜
３２：開口部
３２Ａ：第１の領域
３２Ｂ：第２の領域
４０：グレイティングマスク
４０Ａ：遮光領域
５０：金属層
５２：金属パターン
５２Ａ：第１の領域
５２Ｂ：第２の領域
６０：ソルダーレジスト
６０Ａ：開口
７０：半田ボール 10: Semiconductor chip 12: Silicon substrate 12A: Main surface 14: Circuit element 16: Wiring 18: Chip extraction electrode 20: Passivation layer 20A: Opening 30: Photosensitive polyimide film 32: Opening 32A: First region 32B: First 2 area 40: grating mask 40A: light shielding area 50: metal layer 52: metal pattern 52A: first area 52B: second area 60: solder resist 60A: opening 70: solder ball

Claims (42)

  1. 回路素子を含む基板と、
    　前記回路素子に電気的にカップリングする第１の金属配線を含み、前記基板の表面に形成される第１の金属層と、
    　前記第１の金属層を覆う第１の絶縁材で形成されるパッシベーション層と、
    　前記パッシベーション層を覆う第２の絶縁材で形成され、第１の開口部を含む第１の絶縁層と、
    　前記第１の開口部に形成され、前記第１の金属配線に電気的にカップリングする第２の金属配線を含む第２の金属層と、
    　前記第２の金属配線に電気的にカップリングし、前記第２の金属配線の表面に形成される外部端子と、を備え、
    　前記第１の開口部は、第１の深度を有する第１の領域と、前記第１の深度よりも浅く前記第１の絶縁層を残存させる深度である第２の深度を有する第２の領域と、を含み、前記第２の金属配線は前記第１及び第２の領域に形成される、半導体装置。     A substrate including circuit elements;
    A first metal layer including a first metal wiring electrically coupled to the circuit element and formed on a surface of the substrate;
    A passivation layer formed of a first insulating material covering the first metal layer;
    A first insulating layer formed of a second insulating material covering the passivation layer and including a first opening;
    A second metal layer including a second metal wiring formed in the first opening and electrically coupled to the first metal wiring;
    An external terminal electrically coupled to the second metal wiring and formed on a surface of the second metal wiring;
    The first opening has a first region having a first depth and a second region having a second depth that is a depth that is shallower than the first depth and leaves the first insulating layer. And the second metal wiring is formed in the first and second regions.
  2. 半導体装置はさらに、少なくとも前記第１の絶縁層を覆い、前記第１の絶縁層に直接接する、ソルダーレジスト又はモールドレジンを備える、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, further comprising a solder resist or a mold resin that covers at least the first insulating layer and is in direct contact with the first insulating layer.
  3. 前記第１の絶縁材は、ＳｉＮ系の材料を主成分とする、請求項１または２に記載の半導体装置。 The semiconductor device according to claim 1, wherein the first insulating material includes a SiN-based material as a main component.
  4. 前記第２の絶縁材は、感光性の性質を有する、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the second insulating material has a photosensitive property.
  5. 前記第２の絶縁材は、イミド系の材料を主成分とする、請求項１または４に記載の半導体装置。 The semiconductor device according to claim 1, wherein the second insulating material includes an imide-based material as a main component.
  6. 前記外部端子は、前記第２の領域において、前記第２の金属配線に電気的にカップリングする、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the external terminal is electrically coupled to the second metal wiring in the second region.
  7. 前記第２の金属配線の表面の少なくとも一部の表面は、前記第２の絶縁材の表面と同一である、請求項１または６に記載の半導体装置。 The semiconductor device according to claim 1, wherein at least a part of the surface of the second metal wiring is the same as the surface of the second insulating material.
  8. 前記第２の絶縁材は、前記第２の領域において、互いに深度が異なる複数の前記第２の深度を有する、請求項１ないし７いずれか１つに記載の半導体装置。 The semiconductor device according to claim 1, wherein the second insulating material has a plurality of the second depths having different depths in the second region.
  9. 前記第２の絶縁材は、前記第２の領域において、その厚みが前記基板に向かって薄く形成され、前記第２の金属配線は、前記第２の領域において、その厚みが前記基板に向かって厚く形成される、請求項１ないし７いずれか１つに記載の半導体装置。 The thickness of the second insulating material is reduced toward the substrate in the second region, and the thickness of the second metal wiring is toward the substrate in the second region. The semiconductor device according to claim 1, wherein the semiconductor device is formed thick.
  10. 前記第２の領域における前記第２の絶縁材の少なくとも一部の表面は、凹凸（patterned indented surface）である、請求項８または９に記載の半導体装置。 10. The semiconductor device according to claim 8, wherein a surface of at least a part of the second insulating material in the second region is a pattern (indented surface).
  11. 前記第２の領域における前記第２の絶縁材の少なくとも一部の表面は、幾何学模様パターンである、請求項８または９に記載の半導体装置。 The semiconductor device according to claim 8, wherein at least a part of the surface of the second insulating material in the second region is a geometric pattern.
  12. 前記第２の絶縁材の少なくとも一部の表面に対応する前記第２の金属配線の表面は、前記第２の絶縁材の一部の表面の形状に対応する転写パターンである、請求項１０または１１に記載の半導体装置。 The surface of the second metal wiring corresponding to at least a part of the surface of the second insulating material is a transfer pattern corresponding to the shape of the part of the surface of the second insulating material. 11. The semiconductor device according to 11.
  13. 半導体装置はさらに、
    　前記パッシベーション層と前記第１の絶縁層との間に形成され、第３の絶縁材で形成され、かつ第２の開口部を含む第２の絶縁層と、
    　前記第２の開口部に形成され、前記第１及び第２の金属配線を電気的に接続する第３の金属配線を含む第３の金属配線層と、を含む請求項１に記載の半導体装置。     Semiconductor devices further
    A second insulating layer formed between the passivation layer and the first insulating layer, formed of a third insulating material, and including a second opening;
    2. The semiconductor device according to claim 1, further comprising: a third metal wiring layer including a third metal wiring formed in the second opening and electrically connecting the first and second metal wirings. .
  14. 前記第２の開口部は、第３の深度を有する第３の領域と、前記第３の深度よりも浅く前記第２の絶縁層を残存させる深度である第４の深度を含む第４の領域と、を含み、前記第３の金属配線は前記第３及び第４の領域に形成される、請求項１３に記載の半導体装置。 The second opening includes a third region having a third depth and a fourth region including a fourth depth that is a depth that is shallower than the third depth and leaves the second insulating layer. The semiconductor device according to claim 13, wherein the third metal wiring is formed in the third and fourth regions.
  15. 前記第３の金属配線は、前記第３の領域において前記第１の金属配線に電気的にカップリングし、前記第１及び第４の領域において前記第２の金属配線にカップリングする、請求項１４に記載の半導体装置。 The third metal wiring is electrically coupled to the first metal wiring in the third region, and is coupled to the second metal wiring in the first and fourth regions. 14. The semiconductor device according to 14.
  16. 前記第４の領域は、互いに深度が異なる複数の前記第４の深度を有する、請求項１４または１５に記載の半導体装置。 The semiconductor device according to claim 14, wherein the fourth region has a plurality of the fourth depths having different depths.
  17. 前記第３の絶縁材は、前記第４の領域において、その厚みが前記基板に向かって薄く形成され、よって前記第２の金属配線領域は、前記第４の領域において、その厚みが前記基板に向かって厚く形成される、請求項１４または１５に記載の半導体装置。 The thickness of the third insulating material is reduced toward the substrate in the fourth region. Therefore, the thickness of the second metal wiring region in the fourth region is the same as that of the substrate. The semiconductor device according to claim 14, wherein the semiconductor device is formed thicker toward the surface.
  18. 前記第２の領域における前記第２の絶縁材の少なくとも一部の表面は、凹凸（patterned indented surface）である、請求項１６または１７に記載の半導体装置。 18. The semiconductor device according to claim 16, wherein a surface of at least a part of the second insulating material in the second region is an uneven surface.
  19. 前記第２の領域における前記第２の絶縁材の少なくとも一部の表面は、幾何学模様パターンである、請求項１６または１７に記載の半導体装置。 The semiconductor device according to claim 16, wherein at least a part of the surface of the second insulating material in the second region is a geometric pattern.
  20. 前記第２の絶縁材の少なくとも一部の表面に対応する前記第２の金属配線の表面は、前記第２の絶縁材の一部の表面の形状に対応する転写パターンである、請求項１８または１９に記載の半導体装置。 The surface of the second metal wiring corresponding to at least a part of the surface of the second insulating material is a transfer pattern corresponding to the shape of the part of the surface of the second insulating material. 19. The semiconductor device according to 19.
  21. 半導体装置は更に、
    　前記基板を保持するように前記基板の領域外に設けられた絶縁性の保持材を備え、
    　前記第２の絶縁材、前記第２の領域及びそれに対応する前記第２の金属配線は、前記基板の領域、及び前記基板の側面に延在する前記保持材の領域に配置され、
    　前記外部端子は、前記基板の領域外に配置される、請求項１ないし２０いずれか１つに記載の半導体装置。     Semiconductor devices further
    An insulating holding material provided outside the area of the substrate so as to hold the substrate;
    The second insulating material, the second region, and the second metal wiring corresponding to the second insulating material are disposed in the region of the substrate and the region of the holding material extending to the side surface of the substrate,
    21. The semiconductor device according to claim 1, wherein the external terminal is disposed outside a region of the substrate.
  22. 前記外部端子は、前記基板の領域内に配置される、請求項１ないし２０いずれか１つに記載の半導体装置。 21. The semiconductor device according to claim 1, wherein the external terminal is disposed in a region of the substrate.
  23. 回路素子が形成された基板の表面に、前記回路素子に電気的にカップリングする第１の金属配線を含む第１の金属層を形成し、
    　前記第１の金属層を覆う第１の絶縁材で形成されるパッシベーション層を形成し、
    　前記パッシベーション層を覆う第２の絶縁材で形成され、第１の開口部を含む第１の絶縁層を形成し、
    　前記第１の開口部に形成され、前記第１の金属配線に電気的にカップリングする第２の金属配線を含む第２の金属層を形成し、
    　前記第２の金属配線に電気的にカップリングし、前記第２の金属配線の表面にカップリングする外部端子を形成し、
    　前記第１の開口部の形成は、第１の深度を有する第１の領域と、前記第１の深度よりも浅く前記第１の絶縁層を残存させる深度である第２の深度を有する第２の領域と、を同時に形成し、
    前記第２の金属配線は、前記第１及び第２の領域に形成する、半導体装置の製造方法。     Forming a first metal layer including a first metal wiring electrically coupled to the circuit element on a surface of the substrate on which the circuit element is formed;
    Forming a passivation layer formed of a first insulating material covering the first metal layer;
    Forming a first insulating layer formed of a second insulating material covering the passivation layer and including a first opening;
    Forming a second metal layer including a second metal wiring formed in the first opening and electrically coupled to the first metal wiring;
    Forming an external terminal electrically coupled to the second metal wiring and coupled to a surface of the second metal wiring;
    The formation of the first opening includes a first region having a first depth, and a second region having a second depth which is a depth that leaves the first insulating layer shallower than the first depth. Are simultaneously formed,
    The method of manufacturing a semiconductor device, wherein the second metal wiring is formed in the first and second regions.
  24. 前記製造方法は更に、
    　前記第１の絶縁層および前記第２の金属層を平坦化する、請求項２３に記載の半導体装置の製造方法。     The manufacturing method further includes:
    24. The method of manufacturing a semiconductor device according to claim 23, wherein the first insulating layer and the second metal layer are planarized.
  25. 前記平坦化は、前記基板から一定の高さで、前記第１の絶縁層および前記第２の金属層を切削する、請求項２４に記載の半導体装置の製造方法。 25. The method of manufacturing a semiconductor device according to claim 24, wherein the planarization is performed by cutting the first insulating layer and the second metal layer at a certain height from the substrate.
  26. 前記第１の絶縁層は、フェノール樹脂、不飽和ポリエステル樹脂、メラミン樹脂、またはユレア樹脂を主成分とする、請求項２５に記載の半導体装置の製造方法。 26. The method of manufacturing a semiconductor device according to claim 25, wherein the first insulating layer is mainly composed of a phenol resin, an unsaturated polyester resin, a melamine resin, or a urea resin.
  27. 前記第１の樹脂は、応力に対して破断に到達する歪みが１０パーセント未満である、ことを特徴とする請求項２５または２６に記載の半導体装置の製造方法。 27. The method of manufacturing a semiconductor device according to claim 25, wherein the first resin has less than 10% strain to reach fracture with respect to stress.
  28. 前記第１の樹脂の破断に至る塑性変形の範囲が、ポリイミドの塑性変形の範囲よりも小さい、ことを特徴とする請求項２５ないし２７のいずれか１つに記載の半導体装置の製造方法。 28. The method of manufacturing a semiconductor device according to claim 25, wherein a range of plastic deformation leading to breakage of the first resin is smaller than a range of plastic deformation of polyimide.
  29. 前記第１の樹脂の破断強度（tensile strength）は、８０ＭＰａ以下である、ことを特徴とする請求項２５ないし２８のいずれか１つに記載の半導体装置の製造方法。 29. The method of manufacturing a semiconductor device according to claim 25, wherein the first resin has a tensile strength of 80 MPa or less.
  30. 前記第１の樹脂の破断強度（tensile strength）は、ポリイミドの破断強度よりも小さい、ことを特徴とする請求項２５ないし２９いずれか１つに記載の半導体装置の製造方法。 30. The method of manufacturing a semiconductor device according to claim 25, wherein the breaking strength of the first resin is smaller than the breaking strength of polyimide.
  31. 前記製造方法は更に、
    　少なくとも前記第１の絶縁層を覆い、前記第１の絶縁層に直接接するソルダーレジスト又はモールドレジンを形成する、請求項２３ないし３０いずれか１つに記載の半導体装置の製造方法。     The manufacturing method further includes:
    31. The method of manufacturing a semiconductor device according to claim 23, wherein a solder resist or a mold resin that covers at least the first insulating layer and is in direct contact with the first insulating layer is formed.
  32. 前記製造方法は更に、
    　前記パッシベーション層に前記第１の金属層を露出するコンタクトホールを形成し、
    　前記第１の開口部は、前記コンタクトホールに対応して形成される、請求項２３ないし３１いずれか１つに記載の半導体装置の製造方法。     The manufacturing method further includes:
    Forming a contact hole exposing the first metal layer in the passivation layer;
    32. The method of manufacturing a semiconductor device according to claim 23, wherein the first opening is formed corresponding to the contact hole.
  33. 前記製造方法は更に、
    　前記第１の開口部を介して前記パッシベーション層に前記第１の金属層を露出するコンタクトホールを形成する、請求項２３ないし３１いずれか１つに記載の半導体装置の製造方法。     The manufacturing method further includes:
    32. The method of manufacturing a semiconductor device according to claim 23, wherein a contact hole that exposes the first metal layer is formed in the passivation layer through the first opening.
  34. 前記製造方法は更に、
    　感光性の性質を有する前記第２の絶縁材を前記第１及び第２の領域にそれぞれ対応する互いに異なる光量で同時に露光し、露光された第２の絶縁材を現像することで前記第１の開口部を形成する、請求項２３ないし３３いずれか１つに記載の半導体装置の製造方法。     The manufacturing method further includes:
    The second insulating material having a photosensitive property is simultaneously exposed with different light amounts corresponding to the first and second regions, and the exposed second insulating material is developed to develop the first insulating material. 34. The method for manufacturing a semiconductor device according to claim 23, wherein the opening is formed.
  35. 前記第１及び第２の領域が連続する一つの領域として、前記第１の開口部を形成する、請求項２３ないし３４いずれか１つに記載の半導体装置の製造方法。 35. The method of manufacturing a semiconductor device according to claim 23, wherein the first opening is formed as one region where the first and second regions are continuous.
  36. 前記製造方法は更に、
    　前記第２の領域における前記第２の絶縁材の少なくとも一部の表面に、凹凸（patterned indented surface）を形成する、請求項２３ないし３５いずれか１つに記載の半導体装置の製造方法。     The manufacturing method further includes:
    36. The method of manufacturing a semiconductor device according to claim 23, wherein a patterned indented surface is formed on at least a part of the surface of the second insulating material in the second region.
  37. 前記製造方法は更に、
    　前記第２の領域における前記第２の絶縁材の少なくとも一部の表面に、幾何学模様パターンを形成する、請求項２３ないし３５いずれか１つに記載の半導体装置の製造方法。     The manufacturing method further includes:
    36. The method for manufacturing a semiconductor device according to claim 23, wherein a geometric pattern is formed on a surface of at least a part of the second insulating material in the second region.
  38. 前記製造方法は更に、
    　前記第２の絶縁材の少なくとも一部の表面に対応する前記第２の金属配線の表面に、前記第２の絶縁材の一部の表面の形状に対応する転写パターンを形成する、請求項３６または３７に記載の半導体装置の製造方法。     The manufacturing method further includes:
    37. A transfer pattern corresponding to a shape of a part of the surface of the second insulating material is formed on a surface of the second metal wiring corresponding to at least a part of the surface of the second insulating material. Or 37. A method of manufacturing a semiconductor device according to 37.
  39. 前記第１の領域における前記第２の絶縁材の露光と現像と同時に、前記第２の絶縁材の少なくとも一部の表面の露光と現像を行う、請求項３６ないし３８いずれか１つに記載の半導体装置の製造方法。 39. The exposure and development of at least a part of the surface of the second insulating material are performed simultaneously with the exposure and development of the second insulating material in the first region. A method for manufacturing a semiconductor device.
  40. 前記製造方法は更に、
    　前記パッシベーション層と前記第１の絶縁層との間に、第３の絶縁材で形成されかつ第２の開口部を含む第２の絶縁層を形成し、
    　前記第２の開口部において、前記第１及び第２の金属配線を電気的に接続する第３の金属配線を含む第３の金属配線層を形成する、請求項２３ないし３９いずれか１つに記載の半導体装置の製造方法。     The manufacturing method further includes:
    Forming a second insulating layer formed of a third insulating material and including a second opening between the passivation layer and the first insulating layer;
    The third metal wiring layer including a third metal wiring that electrically connects the first and second metal wirings is formed in the second opening. 40. The manufacturing method of the semiconductor device of description.
  41. 前記第３の絶縁材は、感光性の性質を有し、
    　前記製造方法は更に、前記第３の絶縁材を露光し、露光された第３の絶縁材を現像することで前記第２の開口部を形成する、請求項４０に記載の半導体装置の製造方法。     The third insulating material has a photosensitive property,
    41. The method of manufacturing a semiconductor device according to claim 40, wherein the manufacturing method further includes exposing the third insulating material and developing the exposed third insulating material to form the second opening. .
  42. 前記製造方法は更に、
    　前記基板の領域外に、前記基板を保持するように絶縁性の保持材を形成し、
    　前記第１の絶縁層及び前記第２の金属配線は、前記基板の領域及び前記保持材の領域に渡って形成し、
    　前記外部端子は、前記基板の領域外に形成する、請求項２３ないし４１いずれか１つに記載の半導体装置の製造方法。     The manufacturing method further includes:
    An insulating holding material is formed outside the area of the substrate so as to hold the substrate;
    The first insulating layer and the second metal wiring are formed over the region of the substrate and the region of the holding material,
    42. The method of manufacturing a semiconductor device according to claim 23, wherein the external terminal is formed outside a region of the substrate.
PCT/JP2012/060347 2012-04-17 2012-04-17 Semiconductor device and method for manufacturing same WO2013157080A1 (en)

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CN113169166A (en) * 2018-11-20 2021-07-23 凸版印刷株式会社 Semiconductor package substrate and method of manufacturing the same

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JP2006287095A (en) * 2005-04-04 2006-10-19 Seiko Epson Corp Semiconductor device and manufacturing method therefor
JP2008233844A (en) * 2007-03-22 2008-10-02 Samsung Sdi Co Ltd Semiconductor device and method of manufacturing the same

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* Cited by examiner, † Cited by third party
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JP2021501459A (en) * 2017-10-05 2021-01-14 日本テキサス・インスツルメンツ合同会社 Structures and methods for semiconductor packaging
CN113169166A (en) * 2018-11-20 2021-07-23 凸版印刷株式会社 Semiconductor package substrate and method of manufacturing the same

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