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WO2013012195A2 - Method for manufacturing substrate and method or manufacturing electronic device using same - Google Patents

Method for manufacturing substrate and method or manufacturing electronic device using same Download PDF

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Publication number
WO2013012195A2
WO2013012195A2 PCT/KR2012/005466 KR2012005466W WO2013012195A2 WO 2013012195 A2 WO2013012195 A2 WO 2013012195A2 KR 2012005466 W KR2012005466 W KR 2012005466W WO 2013012195 A2 WO2013012195 A2 WO 2013012195A2
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WO
WIPO (PCT)
Prior art keywords
substrate
metal layer
forming
manufacturing
nano
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Application number
PCT/KR2012/005466
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French (fr)
Korean (ko)
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WO2013012195A3 (en
Inventor
이종람
유철종
김기수
손준호
Original Assignee
포항공과대학교 산학협력단
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Publication of WO2013012195A2 publication Critical patent/WO2013012195A2/en
Publication of WO2013012195A3 publication Critical patent/WO2013012195A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Definitions

  • the present invention relates to a method for manufacturing a substrate for forming an electronic device, and more specifically, a method for selectively reducing nanodimples on a patterned metal layer at a low cost, thereby greatly reducing a manufacturing cost of an electronic device substrate. It is about.
  • the fine pattern fabrication technique using nanoimprint can overcome the limitation of resolution of photolithography to form an ultra high resolution pattern, but in the case of a mother substrate having an ultra fine pattern, it is formed by lithography using an electron beam and thus has various patterns. In order to secure the mother substrate there is a problem that requires a very expensive cost and equipment.
  • the present invention is to solve the problems of the prior art as described above, it is an object of the present invention to provide a substrate for an electronic device and a method of manufacturing an electronic device using the same and simpler and lower cost than the conventional method.
  • the present invention (1), (a) forming a metal layer on the substrate; (b) forming a mask layer having a predetermined pattern formed on the metal layer; (c) immersing the substrate in an acid solution and applying a voltage to form a metal oxide having self-aligned nano holes in the exposed metal layer; And (d) forming nano dimples on the metal layer by etching and removing the metal oxides.
  • it may further comprise the step of removing the mask layer before the step (d).
  • the present invention (2), (a) forming a metal layer of a predetermined pattern on the substrate; (b) forming an insulating layer on a portion of the metal layer to which the substrate is exposed; (c) immersing the substrate in an acid solution and applying a voltage to form a metal oxide having self-aligned nano holes in the exposed metal layer; And (d) etching and removing the metal oxide, thereby forming nano dimples on the metal layer.
  • the present invention (3) comprises the steps of: (a) forming an insulating layer of a predetermined pattern on the substrate; (b) forming a metal layer on a portion of the insulating layer to which the substrate is exposed; (c) immersing the substrate in an acid solution and applying a voltage to form a metal oxide having self-aligned nano holes in the exposed metal layer; And (d) etching and removing the metal oxide, thereby forming nano dimples on the metal layer.
  • the metal layer may include at least one of Al, Ti, Ta, Mg, Nb, Hf, Zn.
  • the mask layer may be formed using one or more of photolithography or nanoimprinting.
  • the mask layer may be made of one or more selected from titanium oxide, aluminum oxide, silicon oxide, photoresist, polyimide, PDMS, PMMA, thermosetting resin or ultraviolet curable resin.
  • the metal layer of the predetermined pattern is formed by forming a mask layer on a substrate by a photolithography method or a nanoimprint method, and depositing a metal layer on the substrate by thermal evaporation or sputtering, and then lift-off. off) may be formed by a method of removing the mask layer.
  • the acid solution in the step (c) comprises at least one selected from sulfuric acid, oxalic acid, phosphoric acid, and controls the size of the nano-holes formed through the concentration control of the components Can be.
  • step (c) it can adjust the size of the nano-holes formed by adjusting the applied voltage within the range of 20V ⁇ 200V.
  • the substrate may be a conductive substrate, and the conductive substrate is preferably made of a semiconductor, ITO, AZO, GZO, stainless steel sheet or Invar steel sheet.
  • the insulating layer is a metal oxide, metal nitride, photoresist. It may be made of one or more selected from thermosetting resins, ultraviolet curable resins, polyimides, PMMA or PDMS.
  • This invention (4) provides the manufacturing method of the electronic device characterized by forming an electronic device on the nano dimple of the board
  • the electronic device may be at least one selected from an organic light emitting diode, a liquid crystal display, an electrophoretic device, a plasma display panel, a thin film transistor, a microprocessor, a RAM, an organic solar cell, and a thin film solar cell.
  • Conventional anodization uses metal oxides with self-aligning nano holes formed on the metal surface. Metal oxides having such nano-holes are used to improve the characteristics of each device by forming a regular pattern by deposition of additional metals or combinations of organic materials.
  • the present invention provides nano-structures regularly formed in the metal layer when the self-aligned metal oxides are removed. Dimples can be obtained, and these nano dimples can be immediately applied to an electrode substrate.
  • the method for manufacturing a substrate according to the present invention is a low cost electron compared to a method of forming a predetermined metal pattern using photolithography, nanoimprint, or metal mask and anodizing method using only photolithography or nanoimprint.
  • the substrate for an element can be manufactured.
  • the method for manufacturing a substrate according to the present invention can form self-aligning nano dimples in a selective region of a large area structure, thereby enabling the manufacture of electronic devices efficiently without additional separation between devices.
  • the substrate and the electronic device manufacturing method using the same according to the present invention can manufacture an electronic device substrate having additional nano dimples without changing the infrastructure used in the existing industrial structure, thereby reducing the manufacturing cost and improving the manufacturing efficiency You can expect.
  • FIG. 1 is a flowchart of a method of manufacturing a substrate and an electronic device according to the first embodiment of the present invention.
  • FIG. 2 is a flowchart of a method of manufacturing a substrate and an electronic device according to a second embodiment of the present invention.
  • FIG 3 is a manufacturing process diagram of the substrate and the electronic device according to the first embodiment of the present invention.
  • FIG. 4 is a manufacturing process chart of the substrate and the electronic device according to the second embodiment of the present invention.
  • FIG. 5 is a photograph of a substrate on which nanodimples are prepared according to the first embodiment of the present invention.
  • FIG. 1 and 3 show a flowchart and a manufacturing process diagram of a method for manufacturing a substrate and an electronic device according to the first embodiment of the present invention, respectively.
  • the substrate according to the first embodiment of the present invention and the method for manufacturing an electronic device using the substrate include a substrate preparation step (S100), a metal layer forming step (S110), and a mask layer forming step (S120). ), Anodizing step (S130), metal oxide removal step (S140) and the electronic device forming step (S150).
  • the preparing step (S100) of the substrate is a step of preparing in a state capable of depositing a metal layer on the substrate, and means a cleaning process for removing impurities that may exist on the surface of the substrate.
  • the cleaning process is a method of immersing in a solution of 1: 1 mixed sulfuric acid and hydrogen peroxide for more than 10 minutes and then neutralized by immersing in deionized water for 5 minutes and using the solution according to the type of substrate If it is difficult to clean by using the ultrasonic vibration equipment can be used for 3 to 5 minutes in acetone solution, 3 to 5 minutes or more in IPA solution and then immersed in deionized water for 3 to 5 minutes or more.
  • a semiconductor, ITO, AZO, GZO, stainless steel or Invar steel sheet or the like can be used as the conductive substrate capable of forming an electronic device in the present invention.
  • the metal layer forming step (S110) may be formed by a known method such as thermal evaporation or sputtering. Particularly, in order to deposit a high purity thin film, the vacuum of the deposition equipment proceeds at a high vacuum of 10 ⁇ 6 torr or less, and the metal layer may be Al, It may include one or more selected from Ti, Ta, Mg, Nb, Hf, Zn. Specifically, in the case of depositing by thermal evaporation, when the metal material to be deposited is placed on the tungsten boat and a current is applied, the metal material is melted and deposited on the substrate.
  • thermal evaporation when the metal material to be deposited is placed on the tungsten boat and a current is applied, the metal material is melted and deposited on the substrate.
  • the thickness of the deposited metal is checked in real time through a crystal thickness monitor installed in the equipment, and the thickness of the deposited metal layer is preferably 1 ⁇ m or more.
  • the amount of Ar gas is fixed to 25 sccm in the equipment, and a plasma is formed at a process pressure of 3 mTorr to deposit a metal material to be deposited on the upper substrate as a target.
  • the substrate is rotated at a constant speed to form a uniform metal layer on the upper substrate.
  • the mask layer forming step (S120) may form a mask layer by a photolithography or nanoimprint method, the mask layer is titanium oxide, aluminum oxide, silicon oxide, photoresist, polyimide, PDMS, PMMA, thermosetting resin Or one or more selected from ultraviolet curable resins.
  • the photolithography method after the photoresist is coated on the substrate using a spin coater, a mask having a specific pattern is contacted on the photoresist, and a predetermined pattern is transferred using an ultraviolet photosensitive device. A mask layer having a predetermined pattern is formed through the phosphorus developing process.
  • thermosetting or ultraviolet curing resin is coated on the substrate on which the metal layer is formed, and a mold having a specific pattern is applied at a pressure of about 3 bar at a vacuum of 10 -3 Torr or less.
  • a mask layer having a predetermined pattern can be formed by applying a curing temperature or higher or ultraviolet rays.
  • the mask layer is preferably made of one or more selected from titanium oxide, aluminum oxide, silicon oxide, photoresist, polyimide, PDMS, PMMA, thermosetting resin or ultraviolet curable resin.
  • the anodizing step (S130) is a step of forming self-aligning nano holes in the metal layer exposed from the mask layer formed in the mask layer forming step (S120). Specifically, in the anodic oxidation step, a platinum or carbon electrode is provided as an anode in an electrolyte, the metal layer is used as an anode, and the anode and the anode are 5 to 10 cm apart, and each electrode is immersed in an electrolyte to perform anodization. do.
  • sulfuric acid, oxalic acid, phosphoric acid, and the like may be used as the electrolyte, and the acid solution used for such an electrolyte may have a concentration of 0.04 to 0.3M and a liquid temperature of 0 to 50 ° C, at an applied voltage of 20 to 200V. Will proceed.
  • the range of applied voltage to be used is determined according to the acid solution used, it is preferable to use an electrolyte containing sulfuric acid in the range of 20 ⁇ 40V, oxalic acid in the range of 40 ⁇ 80V, phosphoric acid in the range of 80 ⁇ 200V.
  • the nano-dimples formed under the metal oxide layer that is, the nano-holes formed by adjusting the acid solution used as the electrolyte and the applied voltage, can be adjusted within the range of 50 to 500 nm.
  • the metal oxide removal step (S140) is a process of removing the metal oxides in which the nano holes are formed, and when the mixed solution of chromic acid 1.8% by weight and phosphoric acid 6% by weight is removed by immersion under a liquid temperature of 60 to 70 ° C. As shown in FIG. 5, nano dimples of various sizes may be formed on the metal layer.
  • the electronic device forming step (S150) is a step of forming an electronic device on the nano dimple, and the electronic device that can be formed includes an organic light emitting diode (OLED) and a liquid crystal display (LCD). ), Electrophoretic display (EPD), plasma display panel (PDP), thin-film transistor (TFT), microprocessor, random access memory (RAM), organic Solar cell (Organic Solar cell), thin film solar cell (a-Si, CIGS) is possible.
  • OLED organic light emitting diode
  • LCD liquid crystal display
  • EPD Electrophoretic display
  • PDP plasma display panel
  • TFT thin-film transistor
  • RAM random access memory
  • organic Solar cell Organic Solar cell
  • a-Si, CIGS thin film solar cell
  • the mask layer when manufacturing the electronic device, the mask layer may be maintained as needed, or the electronic device may be manufactured after removing the mask layer through the mask layer removing step (S145).
  • FIGS. 2 and 4 show a flowchart and a manufacturing process diagram for the method for manufacturing the substrate and the electronic device according to the second embodiment of the present invention, respectively.
  • the substrate according to the second embodiment of the present invention and the method of manufacturing an electronic device using the substrate the substrate preparation step (S200), patterned metal layer forming step (S210), insulating layer forming step (S220), anodizing (S230), removing a metal oxide (S240), and forming an electronic device (S250). Since the dual substrate preparation step (S200), anodization step (S230), metal oxide removal step (S240), and electronic device forming step (S250) are the same as in the first embodiment, the patterned metal layer forming step (S210) and Only the insulation layer forming step S220 will be described.
  • a process of forming an insulating layer after forming a patterned metal layer is described first.
  • the same effect can be achieved by using a method of forming a metal layer after forming a patterned insulating layer. You can get it.
  • the patterned metal layer forming step (S210) may be used a variety of well-known pattern forming method, such as a photographing method or an imprint method. For example, after forming a mask layer on the substrate by a photolithography method or a nano imprint method and depositing a metal layer on the surface and the mask layer exposed to the substrate by thermal evaporation or sputtering, a lift-off process is performed. The patterned metal layer may be formed by removing the mask layer and the metal layer formed on the mask layer.
  • the insulating layer forming step (S220) is a step of filling a non-electrically insulating layer between the metal of the patterned metal layer, as shown in Figure 4, the method of filling the insulating layer is thermal vapor deposition, chemical vapor deposition method Can be formed by a known method, such as sputtering method, and the insulating layer is a metal oxide, metal nitride, photoresist. At least one selected from thermosetting resins, ultraviolet curable resins, polyimides, PMMA, or PDMS can be used.

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Abstract

The present invention relates to a method for significantly reduce manufacturing cost of an electronic device by selectively forming a nano-dimple on a metal layer that is patterned at a low cost. The method, according to the present invention comprises the steps of: (a) forming the metal layer on a substrate; (b) forming a mask layer, which is provided with a predetermined pattern, on the metal layer; (c) forming a metal oxide having self-alignment nano-holes on the metal layer, which is exposed, by submerging the substrate in an acid solution and applying a voltage; and (d) forming the nano-dimple on the metal layer by removing the metal oxide by means of etching.

Description

기판의 제조방법 및 이를 이용한 전자소자의 제조방법Substrate manufacturing method and electronic device manufacturing method using the same
본 발명은 전자소자를 형성하기 위한 기판의 제조방법에 관한 것으로, 보다 구체적으로는 저비용으로 패터닝된 금속층에 선택적으로 나노 딤플을 형성할 수 있어 전자소자용 기판의 제조비용을 크게 절감할 수 있는 방법에 관한 것이다.The present invention relates to a method for manufacturing a substrate for forming an electronic device, and more specifically, a method for selectively reducing nanodimples on a patterned metal layer at a low cost, thereby greatly reducing a manufacturing cost of an electronic device substrate. It is about.
미세 패턴의 제작과 관련된 기술은 포토리소그래피가 가지는 막대한 산업적 파급효과에 힘입어 다양하게 개발되어 왔다. 특히 지난 십 수년간 놀라운 집적도의 향상을 거듭하여, 수십nm ~ 수nm 크기의 패턴도 공업적으로 생산 가능해지기에 이르러 있다. Techniques related to the production of fine patterns have been developed variously due to the enormous industrial ripple effect of photolithography. In particular, in the last decades, there has been a remarkable increase in density, resulting in industrial production of patterns ranging in size from tens of nanometers to several nanometers.
하지만 포토리소그래피 기반의 패턴 제조 기술은 복합적인 형태의 패턴을 구현하기 위해 복잡한 공정이 필요하여 장시간이 소요됨은 물론 잘 설계된 마스크가 요구된다. 또한 포토리소그래피의 해상도는 장비에 구비되는 자외선 램프의 파장에 의존하므로 초미세 패턴을 형성함에 있어서 일정한 한계를 가진다.However, photolithography-based pattern manufacturing technology requires a complicated process to realize a complex pattern, which requires a long time and a well-designed mask. In addition, since the resolution of photolithography depends on the wavelength of the ultraviolet lamp provided in the equipment, there is a certain limit in forming the ultra fine pattern.
나노 임프린트를 이용한 미세 패턴 제조 기술은 포토리소그래피가 가지는 해상도의 한계를 극복하여 초고해상도의 패턴을 형성할 수 있지만, 초미세패턴을 갖는 모기판의 경우 전자빔을 이용한 리소그래피로 형성하기 때문에 다양한 패턴을 가지는 모기판을 확보하기 위해서는 매우 고가의 비용과 설비가 필요한 문제점이 있다.The fine pattern fabrication technique using nanoimprint can overcome the limitation of resolution of photolithography to form an ultra high resolution pattern, but in the case of a mother substrate having an ultra fine pattern, it is formed by lithography using an electron beam and thus has various patterns. In order to secure the mother substrate there is a problem that requires a very expensive cost and equipment.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위한 것으로, 종래의 방법에 비해 간소하면서도 저비용으로 전자소자용 기판과 이를 이용한 전자소자의 제조하는 방법을 제공하는 것을 목적으로 한다.The present invention is to solve the problems of the prior art as described above, it is an object of the present invention to provide a substrate for an electronic device and a method of manufacturing an electronic device using the same and simpler and lower cost than the conventional method.
상기 과제를 해결하기 위한 수단으로, 본 발명 (1)은, (a) 기판에 금속층을 형성하는 단계; (b) 상기 금속층 상에 소정의 패턴이 형성된 마스크 층을 형성하는 단계; (c) 상기 기판을 산 용액에 침지하고 전압을 인가하여, 노출된 금속층에 자가정렬 나노 홀을 갖는 금속 산화물을 형성하는 단계; 및 (d) 상기 금속 산화물을 식각하여 제거함으로써 상기 금속층에 나노 딤플이 형성되도록 하는 단계;를 포함하는 기판의 제조방법을 제공한다.As a means for solving the above problems, the present invention (1), (a) forming a metal layer on the substrate; (b) forming a mask layer having a predetermined pattern formed on the metal layer; (c) immersing the substrate in an acid solution and applying a voltage to form a metal oxide having self-aligned nano holes in the exposed metal layer; And (d) forming nano dimples on the metal layer by etching and removing the metal oxides.
상기 발명 (1)에 있어서, 상기 (d) 단계 전에 상기 마스크층을 제거하는 단계를 추가로 포함할 수 있다.In the invention (1), it may further comprise the step of removing the mask layer before the step (d).
본 발명 (2)는, (a) 기판에 소정 패턴의 금속층을 형성하는 단계; (b) 상기 금속층 중 기판이 노출된 부분에 절연층을 형성하는 단계; (c) 상기 기판을 산 용액에 침지하고 전압을 인가하여, 노출된 금속층에 자가정렬 나노 홀을 갖는 금속 산화물을 형성하는 단계; 및 (d) 상기 금속 산화물을 식각하여 제거함으로써, 상기 금속층에 나노 딤플이 형성되도록 하는 단계;를 포함하는 것을 특징으로 하는 기판의 제조방법을 제공한다.The present invention (2), (a) forming a metal layer of a predetermined pattern on the substrate; (b) forming an insulating layer on a portion of the metal layer to which the substrate is exposed; (c) immersing the substrate in an acid solution and applying a voltage to form a metal oxide having self-aligned nano holes in the exposed metal layer; And (d) etching and removing the metal oxide, thereby forming nano dimples on the metal layer.
본 발명 (3)은, (a) 기판에 소정 패턴의 절연층을 형성하는 단계; (b) 상기 절연층 중 기판이 노출된 부분에 금속층을 형성하는 단계; (c) 상기 기판을 산 용액에 침지하고 전압을 인가하여, 노출된 금속층에 자가정렬 나노 홀을 갖는 금속 산화물을 형성하는 단계; 및 (d) 상기 금속 산화물을 식각하여 제거함으로써, 상기 금속층에 나노 딤플이 형성되도록 하는 단계;를 포함하는 것을 특징으로 하는 기판의 제조방법을 제공한다.The present invention (3) comprises the steps of: (a) forming an insulating layer of a predetermined pattern on the substrate; (b) forming a metal layer on a portion of the insulating layer to which the substrate is exposed; (c) immersing the substrate in an acid solution and applying a voltage to form a metal oxide having self-aligned nano holes in the exposed metal layer; And (d) etching and removing the metal oxide, thereby forming nano dimples on the metal layer.
상기 발명 (1) 내지 (3)에 있어서, 상기 금속층은 Al, Ti, Ta, Mg, Nb, Hf, Zn 중 적어도 하나 이상을 포함할 수 있다.In the above inventions (1) to (3), the metal layer may include at least one of Al, Ti, Ta, Mg, Nb, Hf, Zn.
상기 발명 (1)에 있어서, 상기 마스크 층은 포토리소그라피법 또는 나노임프린트법 중의 하나 이상을 사용하여 형성될 수 있다.In the above invention (1), the mask layer may be formed using one or more of photolithography or nanoimprinting.
상기 발명 (1)에 있어서, 상기 마스크 층은 티타늄 산화물, 알루미늄 산화물, 실리콘 산화물, 포토레지스트, 폴리이미드, PDMS, PMMA, 열경화성 수지 또는 자외성 경화형 수지 중 선택된 1종 이상으로 이루어질 수 있다.In the invention (1), the mask layer may be made of one or more selected from titanium oxide, aluminum oxide, silicon oxide, photoresist, polyimide, PDMS, PMMA, thermosetting resin or ultraviolet curable resin.
상기 발명 (3)에 있어서, 상기 소정 패턴의 금속층은, 포토리소그라피법 또는 나노임프린트법으로 기판상에 마스크층을 형성하고, 그 위에 열증착법 또는 스퍼터링법으로 금속층을 증착한 후 리프트오프(lift-off) 과정을 거쳐 상기 마스크층을 제거하는 방법으로 형성될 수 있다.In the invention (3), the metal layer of the predetermined pattern is formed by forming a mask layer on a substrate by a photolithography method or a nanoimprint method, and depositing a metal layer on the substrate by thermal evaporation or sputtering, and then lift-off. off) may be formed by a method of removing the mask layer.
상기 발명 (1) 내지 (3)에 있어서, 상기 (c) 단계에서 산 용액은, 황산, 옥살산, 인산 중에서 선택된 1종 이상을 포함하며, 상기 성분의 농도 조절을 통해 형성되는 나노 홀의 크기를 조절할 수 있다.In the invention (1) to (3), the acid solution in the step (c) comprises at least one selected from sulfuric acid, oxalic acid, phosphoric acid, and controls the size of the nano-holes formed through the concentration control of the components Can be.
상기 발명 (1) 내지 (3)에 있어서, 상기 (c) 단계에서 20V~200V 범위 내에서 인가전압을 조절하여 형성되는 나노 홀의 크기를 조절할 수 있다.In the invention (1) to (3), in the step (c) it can adjust the size of the nano-holes formed by adjusting the applied voltage within the range of 20V ~ 200V.
상기 발명 (1) 내지 (3)에 있어서, 상기 기판은 전도성 기판일 수 있고, 상기 전도성 기판은, 반도체, ITO, AZO, GZO, 스테인리스 강판 또는 인바 강판으로 이루어진 것이 바람직하다.In the above inventions (1) to (3), the substrate may be a conductive substrate, and the conductive substrate is preferably made of a semiconductor, ITO, AZO, GZO, stainless steel sheet or Invar steel sheet.
상기 발명 (2) 또는 (3)에 있어서, 상기 절연층은 금속 산화물, 금속 질화물, 포토레지스트. 열경화성 수지, 자외선 경화형 수지, 폴리이미드, PMMA 또는 PDMS 중에서 선택된 1종 이상으로 이루어질 수 있다.In the invention (2) or (3), the insulating layer is a metal oxide, metal nitride, photoresist. It may be made of one or more selected from thermosetting resins, ultraviolet curable resins, polyimides, PMMA or PDMS.
본 발명 (4)는 상기 발명 (1) 내지 (3)에 기재된 방법에 의해 제조된 기판의 나노 딤플 상에 전자소자를 형성하는 것을 특징으로 하는 전자소자의 제조방법을 제공한다.This invention (4) provides the manufacturing method of the electronic device characterized by forming an electronic device on the nano dimple of the board | substrate manufactured by the method as described in said invention (1)-(3).
상기 발명 (4)에 있어서, 상기 전자소자는 유기발광다이오드, 액정표시장치, 전기영동장치, 플라스마 디스플레이패널, 박막 트랜지스터, 마이크로프로세서, 램, 유기 태양전지 및 박막 태양전지 중에서 선택된 하나 이상일 수 있다.In the invention (4), the electronic device may be at least one selected from an organic light emitting diode, a liquid crystal display, an electrophoretic device, a plasma display panel, a thin film transistor, a microprocessor, a RAM, an organic solar cell, and a thin film solar cell.
통상의 양극산화법은 금속 표면에 형성된 자가정렬 나노 홀을 갖는 금속산화물을 사용한다. 이러한 나노 홀을 갖는 금속산화물은 추가적인 금속의 증착이나 유기물의 조합으로 규칙적인 패턴을 형성하여 각 소자의 특성향상을 위해 이용하지만, 본 발명은 자가정렬 금속산화물을 제거할 경우 금속층에 규칙적으로 형성된 나노 딤플을 얻을 수 있고, 이 나노 딤플은 전극 기판으로도 즉시 적용이 가능하다.Conventional anodization uses metal oxides with self-aligning nano holes formed on the metal surface. Metal oxides having such nano-holes are used to improve the characteristics of each device by forming a regular pattern by deposition of additional metals or combinations of organic materials. However, the present invention provides nano-structures regularly formed in the metal layer when the self-aligned metal oxides are removed. Dimples can be obtained, and these nano dimples can be immediately applied to an electrode substrate.
본 발명에 따른 기판의 제조방법은 포토리소그래피, 나노 임프린트, 또는 금속마스크를 이용한 소정의 금속패턴을 형성하는 방법과 양극산화법을 적절하게 조합하여 포토리소그래피나 나노 임프린트만을 이용하는 방법에 비해, 저비용으로 전자소자용 기판을 제조할 수 있게 된다.The method for manufacturing a substrate according to the present invention is a low cost electron compared to a method of forming a predetermined metal pattern using photolithography, nanoimprint, or metal mask and anodizing method using only photolithography or nanoimprint. The substrate for an element can be manufactured.
또한, 본 발명에 따른 기판의 제조방법은, 대면적 구조의 선택적 영역에 자가정렬 나노 딤플을 형성할 수 있기 때문에, 추가적인 소자 간의 분리 과정 없이 효율적으로 전자소자의 제조가 가능하게 된다.In addition, the method for manufacturing a substrate according to the present invention can form self-aligning nano dimples in a selective region of a large area structure, thereby enabling the manufacture of electronic devices efficiently without additional separation between devices.
따라서, 본 발명에 따른 기판과 이를 이용한 전자소자 제조방법은, 기존 산업구조에서 사용하는 인프라의 변화 없이 추가적으로 나노 딤플을 갖는 전자소자 기판을 제작할 수 있고 이로 인해 제조비용의 절감과 제조 효율의 향상 효과를 기대할 수 있다.Therefore, the substrate and the electronic device manufacturing method using the same according to the present invention can manufacture an electronic device substrate having additional nano dimples without changing the infrastructure used in the existing industrial structure, thereby reducing the manufacturing cost and improving the manufacturing efficiency You can expect.
도 1은 본 발명의 제1 실시형태에 따른 기판 및 전자소자의 제조방법에 대한 흐름도이다.1 is a flowchart of a method of manufacturing a substrate and an electronic device according to the first embodiment of the present invention.
도 2는 본 발명의 제2 실시형태에 따른 기판 및 전자소자의 제조방법에 대한 흐름도이다.2 is a flowchart of a method of manufacturing a substrate and an electronic device according to a second embodiment of the present invention.
도 3은 본 발명의 제1 실시형태에 따른 기판 및 전자소자의 제조 공정도이다.3 is a manufacturing process diagram of the substrate and the electronic device according to the first embodiment of the present invention.
도 4는 본 발명의 제2 실시형태에 따른 기판 및 전자소자의 제조 공정도이다.4 is a manufacturing process chart of the substrate and the electronic device according to the second embodiment of the present invention.
도 5는 본 발명의 제1 실시형태에 따라 제조한 나노딤플이 형성된 기판의 사진이다.5 is a photograph of a substrate on which nanodimples are prepared according to the first embodiment of the present invention.
이하에서는, 본 발명의 바람직한 실시예에 기초하여 본 발명을 보다 구체적으로 설명한다. 그러나 하기 실시예는 본 발명의 이해를 돕기 위한 일 예에 불과한 것으로 이에 의해 본 발명의 권리범위가 축소 및 한정되는 것은 아니다.Hereinafter, the present invention will be described in more detail based on the preferred embodiments of the present invention. However, the following examples are merely examples to help the understanding of the present invention, whereby the scope of the present invention is not reduced or limited.
도 1 및 3은 각각 본 발명의 제1 실시형태에 따른 기판 및 전자소자의 제조방법에 대한 흐름도와 제조 공정도를 나타낸 것이다.1 and 3 show a flowchart and a manufacturing process diagram of a method for manufacturing a substrate and an electronic device according to the first embodiment of the present invention, respectively.
이들 도면에 도시된 바와 같이, 본 발명의 제1 실시형태에 따른 기판과 이 기판을 이용한 전자소자의 제조방법은, 기판 준비단계(S100), 금속층 형성단계(S110), 마스크층 형성단계(S120), 양극산화 단계(S130), 금속산화물 제거단계(S140) 및 전자소자 형성단계(S150)을 포함하여 이루어진다.As shown in these drawings, the substrate according to the first embodiment of the present invention and the method for manufacturing an electronic device using the substrate include a substrate preparation step (S100), a metal layer forming step (S110), and a mask layer forming step (S120). ), Anodizing step (S130), metal oxide removal step (S140) and the electronic device forming step (S150).
상기 기판의 준비단계(S100)는 기판에 금속층을 증착시킬 수 있는 상태로 준비하는 단계로, 기판의 표면에 존재할 수 있는 불순물을 제거하는 세정 공정을 의미한다. 구체적으로, 상기 세정 공정은 황산과 과산화수소수를 1:1로 혼합한 용액에 10분 이상 침지한 후 탈 이온수에서 5분 동안 침지하여 중화시키는 방법을 사용하며 기판의 종류에 따라 상기의 용액을 이용하여 세정이 어려울 경우 초음파 진동 장비를 이용하여 아세톤 용액에서 3 ~ 5분, IPA 용액에서 3 ~ 5분 이상을 처리한 후 탈 이온수에서 3 ~ 5분 이상을 침지하여 세정하는 방법을 사용할 수 있다. 본 발명에서 전자소자를 형성할 수 있는 전도성 기판으로는, 반도체, ITO, AZO, GZO, 스테인리스 강판 또는 인바 강판 등으로 이루어진 것이 사용될 수 있다.The preparing step (S100) of the substrate is a step of preparing in a state capable of depositing a metal layer on the substrate, and means a cleaning process for removing impurities that may exist on the surface of the substrate. Specifically, the cleaning process is a method of immersing in a solution of 1: 1 mixed sulfuric acid and hydrogen peroxide for more than 10 minutes and then neutralized by immersing in deionized water for 5 minutes and using the solution according to the type of substrate If it is difficult to clean by using the ultrasonic vibration equipment can be used for 3 to 5 minutes in acetone solution, 3 to 5 minutes or more in IPA solution and then immersed in deionized water for 3 to 5 minutes or more. As the conductive substrate capable of forming an electronic device in the present invention, a semiconductor, ITO, AZO, GZO, stainless steel or Invar steel sheet or the like can be used.
상기 금속층 형성단계(S110)는 열증착법 또는 스퍼터링법과 같은 공지의 방법으로 형성할 수 있고, 특히 고순도 박막의 증착을 위해서 증착 장비의 진공은 10-6torr 이하의 고진공에서 진행하며, 금속층은 Al, Ti, Ta, Mg, Nb, Hf, Zn 중에서 선택된 1종 이상을 포함할 수 있다. 구체적으로 열증착법을 이용하여 증착할 경우, 텅스텐 보트 위에 증착하려는 금속물질을 위치하고 전류를 인가하면 금속물질이 녹아 기판 상에 증착된다. 증착된 금속의 두께는 장비에 설치된 크리스탈 두께 모니터를 통해 실시간으로 확인하며, 증착된 금속층의 두께는 1㎛ 이상이 되도록 함이 바람직하다. 스퍼터링을 이용하여 금속층을 형성할 경우, 장비 내에 Ar 가스의 양을 25sccm으로 고정하고 공정압력 3mTorr에서 플라즈마를 형성하여 증착하려는 금속 물질을 타켓으로 해서 상부의 기판에 증착하게 된다. 이때 상부의 기판에 균일한 금속층을 형성하기 위해 일정한 속도록 기판을 회전시켜준다. The metal layer forming step (S110) may be formed by a known method such as thermal evaporation or sputtering. Particularly, in order to deposit a high purity thin film, the vacuum of the deposition equipment proceeds at a high vacuum of 10 −6 torr or less, and the metal layer may be Al, It may include one or more selected from Ti, Ta, Mg, Nb, Hf, Zn. Specifically, in the case of depositing by thermal evaporation, when the metal material to be deposited is placed on the tungsten boat and a current is applied, the metal material is melted and deposited on the substrate. The thickness of the deposited metal is checked in real time through a crystal thickness monitor installed in the equipment, and the thickness of the deposited metal layer is preferably 1 μm or more. In the case of forming a metal layer using sputtering, the amount of Ar gas is fixed to 25 sccm in the equipment, and a plasma is formed at a process pressure of 3 mTorr to deposit a metal material to be deposited on the upper substrate as a target. At this time, the substrate is rotated at a constant speed to form a uniform metal layer on the upper substrate.
상기 마스크층 형성단계(S120)는 포토리소그래피 또는 나노임프린트의 방법으로 마스크층을 형성할 수 있으며, 상기 마스크층은 티타늄 산화물, 알루미늄 산화물, 실리콘 산화물, 포토레지스트, 폴리이미드, PDMS, PMMA, 열경화성 수지 또는 자외성 경화형 수지 중 선택된 1종 이상으로 이루어지는 것이 바람직하다. 구체적으로 포토리소그래피법을 사용하는 경우, 포토레지스트를 스핀코터를 이용하여 기판 상부에 코팅을 한 후 특정한 패턴을 갖는 마스크를 포토레지스트 상부에 접촉시키고 자외선 감광기를 이용하여 소정을 패턴을 전사한 후 통상적인 현상공정을 통해 소정의 패턴을 가지는 마스크 층을 형성한다. 특히 포토레지스트를 이용한 포토리소그래피의 경우 추가적으로 다른 물질을 증착하여 아세톤에 5분 이상 침지하게 되면 포토레지스트가 형성된 부분의 물질은 녹아나가면서 새로운 물질을 이용하여 또 다른 패턴을 가지는 마스크 층을 형성할 수 있다. 또한 나노임프린트법을 사용하는 경우, 금속층이 형성된 기판상에 열경화형 혹은 자외선 경화형 수지 중 선택된 1종의 물질을 코팅하고, 특정 패턴을 가지는 몰드를 10-3Torr 이하의 진공에서 3bar 정도의 압력을 인가하면서 사용되는 수지의 특성에 따라 경화온도 이상 혹은 자외선을 인가하면 소정의 패턴을 갖는 마스크층을 형성할 수 있다. 상기 마스크층은 티타늄 산화물, 알루미늄 산화물, 실리콘 산화물, 포토레지스트, 폴리이미드, PDMS, PMMA, 열경화성 수지 또는 자외성 경화형 수지 중 선택된 1종 이상으로 이루어지는 것이 바람직하다.The mask layer forming step (S120) may form a mask layer by a photolithography or nanoimprint method, the mask layer is titanium oxide, aluminum oxide, silicon oxide, photoresist, polyimide, PDMS, PMMA, thermosetting resin Or one or more selected from ultraviolet curable resins. Specifically, in the case of using the photolithography method, after the photoresist is coated on the substrate using a spin coater, a mask having a specific pattern is contacted on the photoresist, and a predetermined pattern is transferred using an ultraviolet photosensitive device. A mask layer having a predetermined pattern is formed through the phosphorus developing process. Particularly in the case of photolithography using photoresist, if another material is deposited and immersed in acetone for 5 minutes or more, the material of the photoresist formed portion is melted and a mask layer having another pattern can be formed using a new material. have. In addition, in the case of using the nanoimprinting method, one material selected from thermosetting or ultraviolet curing resin is coated on the substrate on which the metal layer is formed, and a mold having a specific pattern is applied at a pressure of about 3 bar at a vacuum of 10 -3 Torr or less. According to the properties of the resin used while applying, a mask layer having a predetermined pattern can be formed by applying a curing temperature or higher or ultraviolet rays. The mask layer is preferably made of one or more selected from titanium oxide, aluminum oxide, silicon oxide, photoresist, polyimide, PDMS, PMMA, thermosetting resin or ultraviolet curable resin.
상기 양극산화 단계(S130)는 상기 마스크층 형성단계(S120)에서 형성된 마스크층으로부터 노출된 금속층에 자가정렬 나노 홀을 형성하는 단계이다. 구체적으로 상기 양극 산화 단계는 전해질 내에 백금 또는 탄소 전극을 음극으로 구비하고, 상기 금속층을 양극으로 하여, 음극과 양극 사이가 5 ~ 10cm가 되도록 하고 각각의 전극을 전해질에 침지하여 양극 산화 과정을 진행한다. 좀 더 구체적으로 전해질로는 황산, 옥살산, 인산 등을 이용할 수 있고, 이러한 전해질에 대하여 사용되는 산 용액의 농도는 0.04 ~ 0.3M, 액온은 0 ~ 50℃의 조건으로 인가전압 20 ~ 200V 사이에서 진행하게 된다. 특히 사용되는 인가전압의 범위는 사용되는 산 용액에 따라 정해지게 되며 20 ~ 40V 범위 내에서는 황산, 40 ~ 80V 범위 내에서는 옥살산, 80 ~ 200V 범위 내에서는 인산을 포함하는 전해질을 사용함이 바람직하다. 전해질로 사용되는 산용액과 인가전압을 조절함으로써 형성되는 나노 홀 즉 금속산화물 층 하부에 형성되는 나노 딤플을 크기를 50 ~ 500nm 범위 내에서 조절할 수 있다. The anodizing step (S130) is a step of forming self-aligning nano holes in the metal layer exposed from the mask layer formed in the mask layer forming step (S120). Specifically, in the anodic oxidation step, a platinum or carbon electrode is provided as an anode in an electrolyte, the metal layer is used as an anode, and the anode and the anode are 5 to 10 cm apart, and each electrode is immersed in an electrolyte to perform anodization. do. More specifically, sulfuric acid, oxalic acid, phosphoric acid, and the like may be used as the electrolyte, and the acid solution used for such an electrolyte may have a concentration of 0.04 to 0.3M and a liquid temperature of 0 to 50 ° C, at an applied voltage of 20 to 200V. Will proceed. In particular, the range of applied voltage to be used is determined according to the acid solution used, it is preferable to use an electrolyte containing sulfuric acid in the range of 20 ~ 40V, oxalic acid in the range of 40 ~ 80V, phosphoric acid in the range of 80 ~ 200V. The nano-dimples formed under the metal oxide layer, that is, the nano-holes formed by adjusting the acid solution used as the electrolyte and the applied voltage, can be adjusted within the range of 50 to 500 nm.
상기 금속산화물 제거단계(S140)는 나노 홀이 형성된 금속산화물을 제거하는 공정으로, 크롬산 1.8중량%, 인산 6중량%의 혼합용액을, 액온 60 ~ 70℃의 조건으로 침지하는 방법으로 제거하게 되면, 도 5에 보여진 바와 같이, 금속층의 상부에 다양한 크기의 나노 딤플을 형성할 수 있다.The metal oxide removal step (S140) is a process of removing the metal oxides in which the nano holes are formed, and when the mixed solution of chromic acid 1.8% by weight and phosphoric acid 6% by weight is removed by immersion under a liquid temperature of 60 to 70 ° C. As shown in FIG. 5, nano dimples of various sizes may be formed on the metal layer.
상기 전자소자 형성단계(S150)는 상기 나노 딤플 상에 전자소자를 형성하는 단계로, 형성할 수 있는 전자소자는 유기 발광 다이오드(oganic light emitting diode: OLED), 액정 표시 장치(liquid crystal display: LCD), 전기영동장치(Electrophoretic display: EPD), 플라스마 디스플레이 패널(plasma display panel: PDP), 박막 트랜지스터(thin-film transistor: TFT), 마이크로프로세서(microprocessor), 램(Random access memory: RAM), 유기 태양전지 (Organic Solar cell), 박막 태양전지 (a-Si, CIGS) 등이 가능하다.The electronic device forming step (S150) is a step of forming an electronic device on the nano dimple, and the electronic device that can be formed includes an organic light emitting diode (OLED) and a liquid crystal display (LCD). ), Electrophoretic display (EPD), plasma display panel (PDP), thin-film transistor (TFT), microprocessor, random access memory (RAM), organic Solar cell (Organic Solar cell), thin film solar cell (a-Si, CIGS) is possible.
한편, 도 1 및 3에 도시된 바와 같이, 전자소자의 제조시 필요에 따라 마스크층을 그대로 유지하거나, 아니면 마스크층 제거단계(S145)를 통해 마스크층을 제거한 후 전자소자를 제조할 수도 있다.On the other hand, as shown in Figures 1 and 3, when manufacturing the electronic device, the mask layer may be maintained as needed, or the electronic device may be manufactured after removing the mask layer through the mask layer removing step (S145).
도 2 및 4는 각각 본 발명의 제2 실시형태에 따른 기판 및 전자소자의 제조방법에 대한 흐름도와 제조 공정도를 나타낸 것이다.2 and 4 show a flowchart and a manufacturing process diagram for the method for manufacturing the substrate and the electronic device according to the second embodiment of the present invention, respectively.
이들 도면에 도시된 바와 같이, 본 발명의 제2 실시형태에 따른 기판과 이 기판을 이용한 전자소자의 제조방법은, 기판 준비단계(S200), 패턴된 금속층 형성단계(S210), 절연층 형성단계(S220), 양극산화 단계(S230), 금속산화물 제거단계(S240) 및 전자소자 형성단계(S250)을 포함하여 이루어진다. 이중 기판 준비단계(S200), 양극산화 단계(S230), 금속산화물 제거단계(S240) 및 전자소자 형성단계(S250)은 제1 실시형태와 동일하므로, 이하에서는 패턴된 금속층 형성단계(S210) 및 절연층 형성단계(S220)에 대해서만 설명한다.As shown in these figures, the substrate according to the second embodiment of the present invention and the method of manufacturing an electronic device using the substrate, the substrate preparation step (S200), patterned metal layer forming step (S210), insulating layer forming step (S220), anodizing (S230), removing a metal oxide (S240), and forming an electronic device (S250). Since the dual substrate preparation step (S200), anodization step (S230), metal oxide removal step (S240), and electronic device forming step (S250) are the same as in the first embodiment, the patterned metal layer forming step (S210) and Only the insulation layer forming step S220 will be described.
한편, 본 발명의 제2 실시형태에서는 먼저 패턴된 금속층을 형성한 후 절연층을 형성하는 과정을 설명하였으나, 역으로 패턴된 절연층을 형성한 후 금속층을 형성하는 방법을 사용하여도 동일한 효과를 얻을 수 있다.Meanwhile, in the second embodiment of the present invention, a process of forming an insulating layer after forming a patterned metal layer is described first. However, the same effect can be achieved by using a method of forming a metal layer after forming a patterned insulating layer. You can get it.
상기 패턴된 금속층 형성단계(S210)은 포토그래피법이나 임프린트법과 같이 공지된 다양한 패턴 형성방법이 사용될 수 있다. 일 예로, 기판상에 포토리소그래피법 또는 나노 임프린트법으로 마스크층을 형성하고 열증착 또는 스퍼터를 이용하여 기판이 노출된 면과 마스크층에 금속층을 증착한 후, 리프트오프(Lift-off) 과정을 통해 마스크층과 상기 마스크층에 형성된 금속층을 제거하는 방법을 통해 패턴된 금속층을 형성할 수 있다.The patterned metal layer forming step (S210) may be used a variety of well-known pattern forming method, such as a photographing method or an imprint method. For example, after forming a mask layer on the substrate by a photolithography method or a nano imprint method and depositing a metal layer on the surface and the mask layer exposed to the substrate by thermal evaporation or sputtering, a lift-off process is performed. The patterned metal layer may be formed by removing the mask layer and the metal layer formed on the mask layer.
상기 절연층 형성단계(S220)는 도 4에 도시된 바와 같이, 패턴된 금속층의 금속 사이에 전기를 통하지 않는 절연층을 채우는 단계로, 절연층을 채울 수 있는 방법으로는 열증착법, 화학기상증착법, 스퍼터링법과 같은 공지의 방법으로 형성할 수 있으며 수 있으며, 절연층으로는 금속 산화물, 금속 질화물, 포토레지스트. 열경화성 수지, 자외선 경화형 수지, 폴리이미드, PMMA 또는 PDMS 중에서 선택된 1종 이상을 사용할 수 있다.The insulating layer forming step (S220) is a step of filling a non-electrically insulating layer between the metal of the patterned metal layer, as shown in Figure 4, the method of filling the insulating layer is thermal vapor deposition, chemical vapor deposition method Can be formed by a known method, such as sputtering method, and the insulating layer is a metal oxide, metal nitride, photoresist. At least one selected from thermosetting resins, ultraviolet curable resins, polyimides, PMMA, or PDMS can be used.

Claims (15)

  1. (a) 기판에 금속층을 형성하는 단계;(a) forming a metal layer on the substrate;
    (b) 상기 금속층 상에 소정의 패턴이 형성된 마스크 층을 형성하는 단계;(b) forming a mask layer having a predetermined pattern formed on the metal layer;
    (c) 상기 기판을 산 용액에 침지하고 전압을 인가하여, 노출된 금속층에 자가정렬 나노 홀을 갖는 금속 산화물을 형성하는 단계; 및(c) immersing the substrate in an acid solution and applying a voltage to form a metal oxide having self-aligned nano holes in the exposed metal layer; And
    (d) 상기 금속 산화물을 식각하여 제거함으로써, 상기 금속층에 나노 딤플이 형성되도록 하는 단계;를 포함하는 것을 특징으로 하는 기판의 제조방법.and (d) etching and removing the metal oxide to form nano dimples in the metal layer.
  2. 제 1 항에 있어서, The method of claim 1,
    상기 (d) 단계 전에 상기 마스크층을 제거하는 단계를 추가로 포함하는 것을 특징으로 하는 기판의 제조방법.And removing the mask layer before the step (d).
  3. (a) 기판에 소정 패턴의 금속층을 형성하는 단계;(a) forming a metal layer of a predetermined pattern on the substrate;
    (b) 상기 금속층 중 기판이 노출된 부분에 절연층을 형성하는 단계;(b) forming an insulating layer on a portion of the metal layer to which the substrate is exposed;
    (c) 상기 기판을 산 용액에 침지하고 전압을 인가하여, 노출된 금속층에 자가정렬 나노 홀을 갖는 금속 산화물을 형성하는 단계;(c) immersing the substrate in an acid solution and applying a voltage to form a metal oxide having self-aligned nano holes in the exposed metal layer;
    (d) 상기 금속 산화물을 식각하여 제거함으로써, 상기 금속층에 나노 딤플이 형성되도록 하는 단계;를 포함하는 것을 특징으로 하는 기판의 제조방법.and (d) etching and removing the metal oxide to form nano dimples in the metal layer.
  4. (a) 기판에 소정 패턴의 절연층을 형성하는 단계;(a) forming an insulating layer having a predetermined pattern on the substrate;
    (b) 상기 절연층 중 기판이 노출된 부분에 금속층을 형성하는 단계;(b) forming a metal layer on a portion of the insulating layer to which the substrate is exposed;
    (c) 상기 기판을 산 용액에 침지하고 전압을 인가하여, 노출된 금속층에 자가정렬 나노 홀을 갖는 금속 산화물을 형성하는 단계;(c) immersing the substrate in an acid solution and applying a voltage to form a metal oxide having self-aligned nano holes in the exposed metal layer;
    (d) 상기 금속 산화물을 식각하여 제거함으로써, 상기 금속층에 나노 딤플이 형성되도록 하는 단계;를 포함하는 것을 특징으로 하는 기판의 제조방법.and (d) etching and removing the metal oxide to form nano dimples in the metal layer.
  5. 제 1 항 내지 제 4 항 중 어느 한 항에 있어서, The method according to any one of claims 1 to 4,
    상기 금속층은 Al, Ti, Ta, Mg, Nb, Hf, Zn 중 적어도 하나 이상을 포함하는 것을 특징으로 하는 기판의 제조방법.The metal layer is a method of manufacturing a substrate, characterized in that it comprises at least one of Al, Ti, Ta, Mg, Nb, Hf, Zn.
  6. 제 1 항에 있어서, The method of claim 1,
    상기 마스크 층은 포토리소그라피법 또는 나노임프린트법 중의 하나 이상을 사용하여 형성되는 것을 특징으로 하는 기판의 제조방법.And said mask layer is formed using at least one of photolithography or nanoimprinting.
  7. 제 1 항에 있어서, The method of claim 1,
    상기 마스크 층은 티타늄 산화물, 알루미늄 산화물, 실리콘 산화물, 포토레지스트, 폴리이미드, PDMS, PMMA, 열경화성 수지 또는 자외성 경화형 수지 중 선택된 1종 이상으로 이루어지는 것을 특징으로 하는 기판의 제조방법.The mask layer is a substrate manufacturing method, characterized in that made of at least one selected from titanium oxide, aluminum oxide, silicon oxide, photoresist, polyimide, PDMS, PMMA, thermosetting resin or ultraviolet curable resin.
  8. 제 4 항에 있어서, The method of claim 4, wherein
    상기 소정 패턴의 금속층은, The metal layer of the predetermined pattern,
    포토리소그라피법 또는 나노임프린트법으로 기판상에 마스크층을 형성하고, 그 위에 열증착법 또는 스퍼터링법으로 금속층을 증착한 후 리프트오프(lift-off) 과정을 거쳐 상기 마스크층을 제거함으로써, 형성되는 것을 특징으로 하는 기판의 제조방법.It is formed by forming a mask layer on a substrate by a photolithography method or a nanoimprint method, depositing a metal layer thereon by thermal evaporation or sputtering, and then removing the mask layer through a lift-off process. A method of manufacturing a substrate, characterized in that.
  9. 제 1 항 내지 제 4 항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4,
    상기 (c) 단계에서 산 용액은, 황산, 옥살산, 인산 중에서 선택된 1종 이상을 포함하며, 상기 성분의 농도 조절을 통해 형성되는 나노 홀의 크기를 조절하는 것을 특징으로 하는 기판의 제조방법.The acid solution in the step (c) comprises at least one selected from sulfuric acid, oxalic acid, phosphoric acid, the method of manufacturing a substrate, characterized in that for adjusting the size of the nano-holes formed by adjusting the concentration of the component.
  10. 제 1 항 내지 제 4 항 중 어느 한 항에 있어서, The method according to any one of claims 1 to 4,
    상기 (c) 단계에서 20V~200V 범위 내에서 인가전압을 조절하여 형성되는 나노 홀의 크기를 조절하는 것을 특징으로 하는 기판의 제조방법.The method of manufacturing a substrate, characterized in that in the step (c) adjusting the size of the nano-holes formed by adjusting the applied voltage within the range of 20V ~ 200V.
  11. 제 1 항 내지 제 4 항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4,
    상기 기판은 전도성 기판인 것을 특징으로 하는 기판의 제조방법.The substrate is a method of manufacturing a substrate, characterized in that the conductive substrate.
  12. 제 11 항에 있어서,The method of claim 11,
    상기 전도성 기판은, 반도체, ITO, AZO, GZO, 스테인리스 강판 또는 인바 강판으로 이루어진 것을 특징으로 하는 기판의 제조방법.The conductive substrate is a semiconductor, ITO, AZO, GZO, stainless steel sheet or Inba steel sheet manufacturing method, characterized in that consisting of a steel sheet.
  13. 제 3 항 또는 제 4 항에 있어서, The method according to claim 3 or 4,
    상기 절연층은 금속 산화물, 금속 질화물, 포토레지스트. 열경화성 수지, 자외선 경화형 수지, 폴리이미드, PMMA 또는 PDMS 중에서 선택된 1종 이상으로 이루어진 것을 특징으로 하는 기판의 제조방법.The insulating layer is a metal oxide, metal nitride, photoresist. Method for producing a substrate, characterized in that consisting of at least one selected from thermosetting resins, ultraviolet curable resins, polyimide, PMMA or PDMS.
  14. 제 1 항 내지 제 4 항 중 어느 한 항에 기재된 방법에 의해 제조된 기판의 나노 딤플 상에 전자소자를 형성하는 것을 특징으로 하는 전자소자의 제조방법.An electronic device is formed on a nano dimple of a substrate produced by the method according to any one of claims 1 to 4.
  15. 제 14 항에 있어서,The method of claim 14,
    상기 전자소자는 유기발광다이오드, 액정표시장치, 전기영동장치, 플라스마 디스플레이패널, 박막 트랜지스터, 마이크로프로세서, 램, 유기 태양전지 및 박막 태양전지 중에서 선택된 하나 이상인 것을 특징으로 하는 전자소자의 제조방법.The electronic device is an organic light emitting diode, a liquid crystal display, an electrophoretic device, a plasma display panel, a thin film transistor, a microprocessor, a RAM, an organic solar cell and a thin film solar cell manufacturing method of an electronic device, characterized in that at least one.
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