KR101243635B1 - Method of manufacturing a substrate and method of manufacturing an electronic device using the same - Google Patents
Method of manufacturing a substrate and method of manufacturing an electronic device using the same Download PDFInfo
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- KR101243635B1 KR101243635B1 KR20110071331A KR20110071331A KR101243635B1 KR 101243635 B1 KR101243635 B1 KR 101243635B1 KR 20110071331 A KR20110071331 A KR 20110071331A KR 20110071331 A KR20110071331 A KR 20110071331A KR 101243635 B1 KR101243635 B1 KR 101243635B1
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- substrate
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- 239000002253 acid Substances 0.000 claims abstract description 14
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- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 10
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 10
- 229920001187 thermosetting polymer Polymers 0.000 claims description 8
- 239000004642 Polyimide Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 239000004205 dimethyl polysiloxane Substances 0.000 claims description 7
- 235000013870 dimethyl polysiloxane Nutrition 0.000 claims description 7
- CXQXSVUQTKDNFP-UHFFFAOYSA-N octamethyltrisiloxane Chemical compound C[Si](C)(C)O[Si](C)(C)O[Si](C)(C)C CXQXSVUQTKDNFP-UHFFFAOYSA-N 0.000 claims description 7
- 238000004987 plasma desorption mass spectroscopy Methods 0.000 claims description 7
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 claims description 7
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 7
- 229920001721 polyimide Polymers 0.000 claims description 7
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 7
- 239000010409 thin film Substances 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 5
- 238000002207 thermal evaporation Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 4
- 235000006408 oxalic acid Nutrition 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052735 hafnium Inorganic materials 0.000 claims description 3
- 239000004973 liquid crystal related substance Substances 0.000 claims description 3
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- 150000004767 nitrides Chemical class 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 229910001220 stainless steel Inorganic materials 0.000 claims description 3
- 239000010935 stainless steel Substances 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229910052725 zinc Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 229910000831 Steel Inorganic materials 0.000 claims 2
- 239000010959 steel Substances 0.000 claims 2
- 239000000243 solution Substances 0.000 description 12
- 239000003792 electrolyte Substances 0.000 description 6
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- 238000007743 anodising Methods 0.000 description 4
- 238000002048 anodisation reaction Methods 0.000 description 3
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- KRVSOGSZCMJSLX-UHFFFAOYSA-L chromic acid Substances O[Cr](O)(=O)=O KRVSOGSZCMJSLX-UHFFFAOYSA-L 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- AWJWCTOOIBYHON-UHFFFAOYSA-N furo[3,4-b]pyrazine-5,7-dione Chemical compound C1=CN=C2C(=O)OC(=O)C2=N1 AWJWCTOOIBYHON-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
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- 229910052698 phosphorus Inorganic materials 0.000 description 1
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- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Thin Film Transistor (AREA)
- Electroluminescent Light Sources (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a method capable of selectively forming nano dimples on a patterned metal layer at low cost, thereby greatly reducing the manufacturing cost of an electronic device substrate.
The method according to the invention comprises the steps of (a) forming a metal layer on a substrate; (b) forming a mask layer having a predetermined pattern formed on the metal layer; (c) immersing the substrate in an acid solution and applying a voltage to form a metal oxide having self-aligned nano holes in the exposed metal layer; And (d) etching and removing the metal oxide to form nano dimples in the metal layer.
Description
The present invention relates to a method for manufacturing a substrate for forming an electronic device, and more specifically, a method for selectively reducing nanodimples on a patterned metal layer at a low cost, thereby greatly reducing a manufacturing cost of an electronic device substrate. It is about.
Techniques related to the production of fine patterns have been developed variously due to the enormous industrial ripple effect of photolithography. In particular, in the last decades, there has been a remarkable increase in density, resulting in industrial production of patterns ranging in size from tens of nanometers to several nanometers.
However, photolithography-based pattern manufacturing technology requires a complicated process to realize a complex pattern, which requires a long time and a well-designed mask. In addition, since the resolution of photolithography depends on the wavelength of the ultraviolet lamp provided in the equipment, there is a certain limit in forming the ultra fine pattern.
The fine pattern manufacturing technology using nanoimprint can overcome the limitations of the resolution of photolithography to form an ultra high resolution pattern. In order to secure the mother substrate there is a problem that requires a very expensive cost and equipment.
The present invention is to solve the problems of the prior art as described above, it is an object of the present invention to provide a substrate for an electronic device and a method of manufacturing an electronic device using the same and simpler and lower cost than the conventional method.
As a means for solving the above problems, the present invention (1), (a) forming a metal layer on the substrate; (b) forming a mask layer having a predetermined pattern formed on the metal layer; (c) immersing the substrate in an acid solution and applying a voltage to form a metal oxide having self-aligned nano holes in the exposed metal layer; And (d) forming nano dimples on the metal layer by etching and removing the metal oxides.
In the invention (1), it may further comprise the step of removing the mask layer before the step (d).
The present invention (2), (a) forming a metal layer of a predetermined pattern on the substrate; (b) forming an insulating layer on a portion of the metal layer to which the substrate is exposed; (c) immersing the substrate in an acid solution and applying a voltage to form a metal oxide having self-aligned nano holes in the exposed metal layer; And (d) etching and removing the metal oxide, thereby forming nano dimples on the metal layer.
The present invention (3) comprises the steps of: (a) forming an insulating layer of a predetermined pattern on the substrate; (b) forming a metal layer on a portion of the insulating layer to which the substrate is exposed; (c) immersing the substrate in an acid solution and applying a voltage to form a metal oxide having self-aligned nano holes in the exposed metal layer; And (d) etching and removing the metal oxide, thereby forming nano dimples on the metal layer.
In the above inventions (1) to (3), the metal layer may include at least one of Al, Ti, Ta, Mg, Nb, Hf, Zn.
In the above invention (1), the mask layer may be formed using one or more of photolithography or nanoimprinting.
In the invention (1), the mask layer may be made of one or more selected from titanium oxide, aluminum oxide, silicon oxide, photoresist, polyimide, PDMS, PMMA, thermosetting resin or ultraviolet curable resin.
In the invention (3), the metal layer of the predetermined pattern is formed by forming a mask layer on a substrate by a photolithography method or a nanoimprint method, and depositing a metal layer on the substrate by thermal evaporation or sputtering, and then lift-off. off) may be formed by a method of removing the mask layer.
In the invention (1) to (3), the acid solution in the step (c) comprises at least one selected from sulfuric acid, oxalic acid, phosphoric acid, the size of the nano-holes formed through the concentration control of the acid solution I can regulate it.
In the invention (1) to (3), in the step (c) it can adjust the size of the nano-holes formed by adjusting the applied voltage within the range of 20V ~ 200V.
In the above inventions (1) to (3), the substrate may be a conductive substrate, and the conductive substrate is preferably made of a semiconductor, ITO, AZO, GZO, stainless steel sheet or Invar steel sheet.
In the invention (2) or (3), the insulating layer is a metal oxide, metal nitride, photoresist. It may be made of one or more selected from a thermosetting resin, ultraviolet curable resin, polyimide, PMMA or PDMS.
This invention (4) provides the manufacturing method of the electronic device characterized by forming an electronic device on the nano dimple of the board | substrate manufactured by the method as described in said invention (1)-(3).
In the invention (4), the electronic device may be at least one selected from an organic light emitting diode, a liquid crystal display, an electrophoretic device, a plasma display panel, a thin film transistor, a microprocessor, a RAM, an organic solar cell, and a thin film solar cell.
Conventional anodization uses metal oxides with self-aligning nano holes formed on the metal surface. Metal oxides having such nano-holes are used to improve the characteristics of each device by forming a regular pattern by deposition of additional metals or combinations of organic materials. However, the present invention provides nano-structures regularly formed in the metal layer when the self-aligned metal oxides are removed. Dimples can be obtained, and these nano dimples can be immediately applied to an electrode substrate.
The method for manufacturing a substrate according to the present invention is a low cost electron compared to a method of forming a predetermined metal pattern using photolithography, nanoimprint, or metal mask and anodizing method using only photolithography or nanoimprint. The substrate for an element can be manufactured.
In addition, the method for manufacturing a substrate according to the present invention can form self-aligning nano dimples in a selective region of a large area structure, thereby enabling the manufacture of electronic devices efficiently without additional separation between devices.
Therefore, the substrate and the electronic device manufacturing method using the same according to the present invention can manufacture an electronic device substrate having additional nano dimples without changing the infrastructure used in the existing industrial structure, thereby reducing the manufacturing cost and improving the manufacturing efficiency You can expect.
1 is a flowchart of a method of manufacturing a substrate and an electronic device according to the first embodiment of the present invention.
2 is a flowchart of a method of manufacturing a substrate and an electronic device according to a second embodiment of the present invention.
3 is a manufacturing process diagram of the substrate and the electronic device according to the first embodiment of the present invention.
4 is a manufacturing process chart of the substrate and the electronic device according to the second embodiment of the present invention.
5 is a photograph of a substrate on which nanodimples are prepared according to the first embodiment of the present invention.
Hereinafter, the present invention will be described in more detail based on the preferred embodiments of the present invention. However, the following examples are merely examples to help the understanding of the present invention, whereby the scope of the present invention is not reduced or limited.
1 and 3 show a flowchart and a manufacturing process diagram of a method for manufacturing a substrate and an electronic device according to the first embodiment of the present invention, respectively.
As shown in these drawings, the substrate according to the first embodiment of the present invention and the method for manufacturing an electronic device using the substrate include a substrate preparation step (S100), a metal layer forming step (S110), and a mask layer forming step (S120). ), Anodizing step (S130), metal oxide removal step (S140) and the electronic device forming step (S150).
The preparing step (S100) of the substrate is a step of preparing in a state capable of depositing a metal layer on the substrate, and means a cleaning process for removing impurities that may exist on the surface of the substrate. Specifically, the cleaning process is a method of immersing in a solution of 1: 1 mixed sulfuric acid and hydrogen peroxide for more than 10 minutes and then neutralized by immersing in deionized water for 5 minutes and using the solution according to the type of substrate If it is difficult to clean by using the ultrasonic vibration equipment can be used for 3 to 5 minutes in acetone solution, 3 to 5 minutes or more in IPA solution and then immersed in deionized water for 3 to 5 minutes or more. As the conductive substrate capable of forming an electronic device in the present invention, a semiconductor, ITO, AZO, GZO, stainless steel or Invar steel sheet or the like can be used.
The metal layer forming step (S110) may be formed by a known method such as thermal deposition or sputtering. In particular, in order to deposit a high purity thin film, the vacuum of the deposition equipment proceeds at a high vacuum of 10 −6 torr or less, and the metal layer may be Al, It may include one or more selected from Ti, Ta, Mg, Nb, Hf, Zn. Specifically, in the case of depositing by thermal evaporation, the metal material to be deposited is placed on the tungsten boat, and when the current is applied, the metal material is melted and deposited on the substrate. The thickness of the deposited metal is checked in real time through a crystal thickness monitor installed in the equipment, and the thickness of the deposited metal layer is preferably 1 μm or more. In the case of forming a metal layer using sputtering, the amount of Ar gas is fixed to 25 sccm in the equipment, and a plasma is formed at a process pressure of 3 mTorr to deposit a metal material to be deposited on the upper substrate as a target. At this time, the substrate is rotated at a constant speed to form a uniform metal layer on the upper substrate.
The mask layer forming step (S120) may form a mask layer by photolithography or nanoimprint, and the mask layer may include titanium oxide, aluminum oxide, silicon oxide, photoresist, polyimide, PDMS, PMMA, and thermosetting resin. Or it consists of 1 or more types chosen from ultraviolet curable resin. Specifically, in the case of using the photolithography method, after the photoresist is coated on the substrate using a spin coater, a mask having a specific pattern is contacted on the photoresist, and a predetermined pattern is transferred using an ultraviolet photosensitive device. A mask layer having a predetermined pattern is formed through the phosphorus developing process. Particularly in the case of photolithography using photoresist, if another material is deposited and immersed in acetone for 5 minutes or more, the material of the photoresist formed portion is melted and a mask layer having another pattern can be formed using a new material. have. In addition, in the case of using the nanoimprint method, one of the thermosetting resin or the ultraviolet curable resin is coated on the substrate on which the metal layer is formed, and the mold having a specific pattern is applied at a pressure of about 3 bar at a vacuum of 10 -3 Torr or less. Depending on the properties of the resin used while applying, a mask layer having a predetermined pattern can be formed by applying a curing temperature or higher or ultraviolet rays. The mask layer is preferably made of one or more selected from titanium oxide, aluminum oxide, silicon oxide, photoresist, polyimide, PDMS, PMMA, thermosetting resin or ultraviolet curable resin.
The anodizing step (S130) is a step of forming self-aligning nano holes in the metal layer exposed from the mask layer formed in the mask layer forming step (S120). Specifically, in the anodic oxidation step, a platinum or carbon electrode is provided as an anode in an electrolyte, the metal layer is used as an anode, and a distance between the cathode and the anode is 5 to 10 cm, and each electrode is immersed in an electrolyte to proceed with anodization. do. More specifically, sulfuric acid, oxalic acid, phosphoric acid, and the like may be used as the electrolyte, and the acid solution used for such an electrolyte may have a concentration of 0.04 to 0.3M and a liquid temperature of 0 to 50 ° C, at an applied voltage of 20 to 200V. Will proceed. In particular, the range of applied voltage to be used is determined according to the acid solution used, it is preferable to use an electrolyte containing sulfuric acid in the range of 20 ~ 40V, oxalic acid in the range of 40 ~ 80V, phosphoric acid in the range of 80 ~ 200V. By adjusting the concentration of the acid solution used as the electrolyte and the applied voltage, nano-dimples formed under the metal oxide layer, that is, the nano-holes formed under the size, can be controlled within a range of 50 to 500 nm.
The metal oxide removal step (S140) is a process of removing the metal oxides in which the nano holes are formed, and when the mixed solution of chromic acid 1.8% by weight and phosphoric acid 6% by weight is removed by immersion under a liquid temperature of 60 to 70 ° C. As shown in FIG. 5, nano dimples of various sizes may be formed on the metal layer.
The electronic device forming step (S150) is a step of forming an electronic device on the nano dimple, and the electronic device that can be formed includes an organic light emitting diode (OLED) and a liquid crystal display (LCD). ), Electrophoretic display (EPD), plasma display panel (PDP), thin-film transistor (TFT), microprocessor, random access memory (RAM), organic Solar cell (Organic Solar cell), thin film solar cell (a-Si, CIGS) is possible.
On the other hand, as shown in Figures 1 and 3, when manufacturing the electronic device, the mask layer may be maintained as needed, or the electronic device may be manufactured after removing the mask layer through the mask layer removing step (S145).
2 and 4 show a flowchart and a manufacturing process diagram for the method for manufacturing the substrate and the electronic device according to the second embodiment of the present invention, respectively.
As shown in these figures, the substrate according to the second embodiment of the present invention and the method of manufacturing an electronic device using the substrate, the substrate preparation step (S200), patterned metal layer forming step (S210), insulating layer forming step (S220), anodizing (S230), removing a metal oxide (S240), and forming an electronic device (S250). Since the dual substrate preparation step (S200), anodization step (S230), metal oxide removal step (S240), and electronic device forming step (S250) are the same as in the first embodiment, the patterned metal layer forming step (S210) and Only the insulation layer forming step S220 will be described.
Meanwhile, in the second embodiment of the present invention, a process of forming an insulating layer after forming a patterned metal layer is described first. However, the same effect can be achieved by using a method of forming a metal layer after forming a patterned insulating layer. You can get it.
The patterned metal layer forming step (S210) may be used a variety of well-known pattern forming method, such as a photographing method or an imprint method. For example, after forming a mask layer on the substrate by a photolithography method or a nano imprint method and depositing a metal layer on the surface and the mask layer exposed to the substrate by thermal evaporation or sputtering, a lift-off process is performed. The patterned metal layer may be formed by removing the mask layer and the metal layer formed on the mask layer.
The insulating layer forming step (S220) is a step of filling a non-electrically insulating layer between the metal of the patterned metal layer, as shown in Figure 4, the method of filling the insulating layer is thermal vapor deposition, chemical vapor deposition method Can be formed by a known method, such as sputtering method, and the insulating layer is a metal oxide, metal nitride, photoresist. At least one selected from thermosetting resins, ultraviolet curable resins, polyimides, PMMA, or PDMS can be used.
Claims (15)
(b) forming a mask layer having a predetermined pattern formed on the metal layer;
(c) immersing the substrate in an acid solution and applying a voltage to form a metal oxide having self-aligned nano holes in the exposed metal layer; And
and (d) etching and removing the metal oxide to form nano dimples in the metal layer.
And removing the mask layer before the step (d).
(b) forming an insulating layer on a portion of the metal layer to which the substrate is exposed;
(c) immersing the substrate in an acid solution and applying a voltage to form a metal oxide having self-aligned nano holes in the exposed metal layer;
and (d) etching and removing the metal oxide to form nano dimples in the metal layer.
(b) forming a metal layer on a portion of the insulating layer to which the substrate is exposed;
(c) immersing the substrate in an acid solution and applying a voltage to form a metal oxide having self-aligned nano holes in the exposed metal layer;
and (d) etching and removing the metal oxide to form nano dimples in the metal layer.
The metal layer is a method of manufacturing a substrate, characterized in that it comprises at least one of Al, Ti, Ta, Mg, Nb, Hf, Zn.
And said mask layer is formed using at least one of photolithography or nanoimprinting.
The mask layer is a substrate manufacturing method, characterized in that made of at least one selected from titanium oxide, aluminum oxide, silicon oxide, photoresist, polyimide, PDMS, PMMA, thermosetting resin or ultraviolet curable resin.
The metal layer of the predetermined pattern,
It is formed by forming a mask layer on a substrate by a photolithography method or a nanoimprint method, depositing a metal layer thereon by thermal evaporation or sputtering, and then removing the mask layer through a lift-off process. A method of manufacturing a substrate, characterized in that.
The acid solution in step (c) comprises at least one selected from sulfuric acid, oxalic acid, phosphoric acid, the method of manufacturing a substrate, characterized in that for adjusting the size of the nano-holes formed by adjusting the concentration of the acid solution.
The method of manufacturing a substrate, characterized in that in the step (c) adjusting the size of the nano-holes formed by adjusting the applied voltage within the range of 20V ~ 200V.
The substrate is a method of manufacturing a substrate, characterized in that the conductive substrate.
The conductive substrate is a semiconductor, ITO, AZO, GZO, stainless steel sheet or Inba steel sheet manufacturing method, characterized in that consisting of a steel sheet.
The insulating layer is a metal oxide, metal nitride, photoresist. A method for producing a substrate, comprising at least one selected from thermosetting resins, ultraviolet curable resins, polyimides, PMMA or PDMS.
The electronic device is an organic light emitting diode, a liquid crystal display, an electrophoretic device, a plasma display panel, a thin film transistor, a microprocessor, a RAM, an organic solar cell and a thin film solar cell manufacturing method of an electronic device, characterized in that at least one.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20110071331A KR101243635B1 (en) | 2011-07-19 | 2011-07-19 | Method of manufacturing a substrate and method of manufacturing an electronic device using the same |
| PCT/KR2012/005466 WO2013012195A2 (en) | 2011-07-19 | 2012-07-10 | Method for manufacturing substrate and method or manufacturing electronic device using same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20110071331A KR101243635B1 (en) | 2011-07-19 | 2011-07-19 | Method of manufacturing a substrate and method of manufacturing an electronic device using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20130010603A KR20130010603A (en) | 2013-01-29 |
| KR101243635B1 true KR101243635B1 (en) | 2013-03-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR20110071331A KR101243635B1 (en) | 2011-07-19 | 2011-07-19 | Method of manufacturing a substrate and method of manufacturing an electronic device using the same |
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| Country | Link |
|---|---|
| KR (1) | KR101243635B1 (en) |
| WO (1) | WO2013012195A2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101585788B1 (en) * | 2014-08-28 | 2016-01-15 | 주식회사 포스코 | Method for manufacturing substrate for electronic device and thin film solar cell |
| KR101683796B1 (en) * | 2015-06-11 | 2016-12-08 | 한국과학기술연구원 | Method for curing polymer by using intense pulsed white light and method for manufacturing organic thin film transistor using the same |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10767143B2 (en) * | 2014-03-06 | 2020-09-08 | Sage Electrochromics, Inc. | Particle removal from electrochromic films using non-aqueous fluids |
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| KR101785468B1 (en) * | 2016-02-05 | 2017-10-16 | 호서대학교 산학협력단 | Method of manufacturing semiconductor thin film transistor and semiconductor thin film transistor manufactured by the method |
| US20180363125A1 (en) * | 2017-06-20 | 2018-12-20 | Board Of Trustees Of The University Of Arkansas | Method of forming high surface area metal oxide nanostructures and applications of same |
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| KR20110034710A (en) * | 2009-09-29 | 2011-04-06 | 광주과학기술원 | Method of forming pattern |
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| KR20090005889A (en) * | 2007-07-10 | 2009-01-14 | 호서대학교 산학협력단 | Method for fabricating nano particle |
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| KR101585788B1 (en) * | 2014-08-28 | 2016-01-15 | 주식회사 포스코 | Method for manufacturing substrate for electronic device and thin film solar cell |
| KR101683796B1 (en) * | 2015-06-11 | 2016-12-08 | 한국과학기술연구원 | Method for curing polymer by using intense pulsed white light and method for manufacturing organic thin film transistor using the same |
Also Published As
| Publication number | Publication date |
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| KR20130010603A (en) | 2013-01-29 |
| WO2013012195A3 (en) | 2013-03-14 |
| WO2013012195A2 (en) | 2013-01-24 |
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