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WO2013054917A1 - Semiconductor element and manufacturing method thereof - Google Patents

Semiconductor element and manufacturing method thereof Download PDF

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Publication number
WO2013054917A1
WO2013054917A1 PCT/JP2012/076519 JP2012076519W WO2013054917A1 WO 2013054917 A1 WO2013054917 A1 WO 2013054917A1 JP 2012076519 W JP2012076519 W JP 2012076519W WO 2013054917 A1 WO2013054917 A1 WO 2013054917A1
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WIPO (PCT)
Prior art keywords
substrate
main surface
wafer
semiconductor
dicing
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PCT/JP2012/076519
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French (fr)
Japanese (ja)
Inventor
勝 滝沢
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株式会社タムラ製作所
株式会社光波
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Publication of WO2013054917A1 publication Critical patent/WO2013054917A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present invention relates to a semiconductor device using a substrate made of gallium oxide and a method for manufacturing the same.
  • a sapphire substrate or a SiC substrate has been used as a base substrate of such a light emitting element.
  • the sapphire substrate does not have conductivity, the sapphire substrate has a structural restriction that the electrode structure of the light emitting element is a horizontal type.
  • the SiC substrate has poor crystallinity of the single crystal wafer and has so-called micropipe defects penetrating in the vertical direction of the single crystal, the n-type layer and the p-type layer are formed by cutting out the micropipe defects. There is a problem of having to.
  • III-V group compound semiconductor has light transmittance in the entire wavelength range of the light emitting region, particularly in the ultraviolet region, has relatively small lattice mismatch with GaN, and can obtain a good quality bulk single crystal.
  • a Ga 2 O 3 substrate as a light emitting element material in a blue or short wavelength region (see, for example, Patent Document 1).
  • this Ga 2 O 3 substrate particularly the ⁇ -Ga 2 O 3 substrate, has an extremely high cleavage property on the (100) plane, and the device is diced from the wafer in the manufacturing process of the light emitting device. Since the substrate is peeled off in the cleavage direction when cutting out, there is a problem that it is difficult to make an element.
  • Patent Document 2 a method for manufacturing a light-emitting element in which peeling due to cleavage of the substrate is prevented and the element is divided into element units has been proposed (see, for example, Patent Document 2).
  • a semiconductor wafer in which a light emitting element is formed on a substrate made of gallium oxide (Ga 2 O 3 ) is formed, and grooving is performed with a dicing blade from the front side of the semiconductor wafer.
  • the first method in which the light emitting elements are individually divided by grooving with a dicing blade and the dicing blade having the first thickness is grooved from the surface direction of the semiconductor wafer, and the first thickness is obtained.
  • an object of the present invention is to provide a semiconductor device that can be easily positioned when the device is cut out from a wafer and can suppress damage such as peeling and cracking due to cleavage of the substrate, and a method for manufacturing the same.
  • a substrate made of gallium oxide which is parallel to the first and second main surfaces located on opposite sides, and the first main surface and the cleavage surface.
  • a substrate having a first side surface parallel to an arbitrary direction and a second side surface intersecting the first side surface; a semiconductor layer formed on the first main surface of the substrate;
  • a semiconductor device provided with a recess formed at a corner portion between the first or second main surface and the second side surface and suppressing separation when the substrate is divided into device units.
  • a substrate made of gallium oxide and having a first main surface and a second main surface positioned on opposite sides is prepared.
  • a plurality of recesses along the second direction are formed in one main surface of the first and second main surfaces between the semiconductor elements, and the other main surface of the first and second main surfaces is formed.
  • a method for manufacturing a semiconductor device is provided, wherein the substrate is cut along the plurality of recesses from a surface, and the substrate is cut along the first direction to divide the plurality of semiconductor devices into device units.
  • FIG. 1A is a perspective view of a light emitting device according to a first embodiment of the present invention.
  • 1B is a cross-sectional view taken along line AA in FIG. 1A.
  • 1C is a view in the direction of arrow B in FIG. 1A.
  • FIG. 2A is a perspective view of the semiconductor wafer according to the first embodiment of the present invention.
  • 2B is a partial cross-sectional view showing a light emitting element portion of the semiconductor wafer of FIG. 2A.
  • FIG. 3 is a perspective view of the semiconductor wafer showing a state where it is mounted on the dicing frame.
  • FIG. 4 is a plan view of an essential part of the semiconductor wafer shown in FIG. FIG.
  • FIG. 5A is a fragmentary cross-sectional view showing a dicing process according to the first embodiment.
  • FIG. 5B is a plan view of FIG. 5A.
  • FIG. 5C is a fragmentary cross-sectional view showing the dicing process according to the first embodiment.
  • FIG. 5D is a plan view of FIG. 5C.
  • FIG. 5E is a cross-sectional view illustrating the main parts in the dicing process according to the first embodiment.
  • FIG. 5F is a plan view of FIG. 5E.
  • FIG. 6A is a perspective view of a light emitting device according to a second embodiment of the present invention.
  • 6B is a cross-sectional view taken along the line CC of FIG. 6A.
  • 6C is a view in the direction of arrow D in FIG.
  • FIG. 7A is a fragmentary cross-sectional view showing a dicing process according to the second embodiment.
  • FIG. 7B is a plan view of FIG. 7A.
  • FIG. 7C is a fragmentary cross-sectional view showing the dicing process according to the second embodiment.
  • FIG. 7D is a plan view of FIG. 7C.
  • FIG. 7E is a fragmentary cross-sectional view showing the dicing process according to the second embodiment.
  • FIG. 7F is a plan view of FIG. 7E.
  • FIG. 8A is a photograph of the example.
  • FIG. 8B is a photograph of a comparative example.
  • FIG. 1A is a perspective view of the light emitting device according to the first embodiment of the present invention
  • FIG. 1B is a cross-sectional view taken along line AA in FIG. 1A
  • FIG. 1C is a view in the direction of arrow B in FIG. 1A.
  • the light-emitting element 10 is an example of a semiconductor element, which is a substrate made of gallium oxide (Ga 2 O 3 ), and the first main surface 1a and the second main surface 1b located on opposite sides of each other, and Ga 2 O 3 substrate 11 having intersecting first side surface 1c and second side surface 1d, and GaN formed on first main surface 1a of Ga 2 O 3 substrate 11 via an AlN buffer layer (not shown).
  • the first side surface 1c is a surface parallel to the first main surface 1a and the direction parallel to the cleavage plane of the Ga 2 O 3 substrate 11 (the direction of the planned division line 4x described later).
  • the Ga 2 O 3 substrate 11 is damaged at the corners of the second main surface 1b and the second side surface 1d by peeling or cracking when the Ga 2 O 3 substrate 11 is divided into element units by a dicing blade.
  • the recessed part to suppress is formed.
  • the concave portion of the present embodiment is a step 15 constituted by a surface 111a intersecting with the second main surface 1b and a surface 111b intersecting with the second side surface 1d.
  • the “cleavage plane” of the Ga 2 O 3 substrate 11 is a (100) plane and a (001) plane.
  • the “concave portion” formed in the corner portion is used to include not only the concave portion formed in the corner between the main surface and the side surface but also the concave portion formed in the vicinity of the corner.
  • the plane orientation of the first main surface 1a and the second main surface 1b of the Ga 2 O 3 substrate 11 is the (101) or ( ⁇ 201) plane, and the second side surface 1d is (010). It is a surface.
  • the Ga 2 O 3 substrate 11 has a thickness of 100 to 200 ⁇ m, for example.
  • the (101) or ( ⁇ 201) surface is the main surface 1a or 1b is as follows.
  • a (100) surface is often used which provides a flat surface by cleavage and is easy to epitaxially grow a GaN-based semiconductor layer.
  • the (100) plane is a cleavage plane, there is a problem that cracks occur in the row direction parallel to the main surfaces 1a and 1b during division.
  • the principal surfaces 1a and 1b are (101) or ( ⁇ 201) planes that are non-cleavage surfaces and are surfaces on which the GaN-based semiconductor layer is likely to grow epitaxially.
  • the Ga 2 O 3 substrate 11 is based on ⁇ -Ga 2 O 3 , but one or more selected from the group consisting of Cu, Ag, Zn, Cd, Al, In, Si, Ge, and Sn are added. You may comprise with the oxide which has Ga as a main component. More specifically, for example, a gallium oxide represented by (Al x In y Ga (1-xy) ) 2 O 3 (where 0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) is used. Can be used.
  • the Ga 2 O 3 substrate 11 has an n-type conductivity type by oxygen defects or by being doped with impurities such as Si and Sn.
  • the Ga 2 O 3 substrate 11 is formed by cutting bulk Ga 2 O 3 produced by, for example, an EFG (Edge-defined Film-fed Growth) method or an FZ (Floating Zone) method into a desired dimension, A material that has been subjected to mechanical polishing or chemical polishing and further subjected to organic cleaning and acid cleaning can be used.
  • EFG Edge-defined Film-fed Growth
  • FZ Floating Zone
  • the GaN-based semiconductor layer 12 includes an Si-doped n-type GaN layer formed on the AlN buffer layer and an MQW (Multiple as an active layer formed on the n-type GaN layer and having an InGaN / GaN multiple quantum well structure. -Quantum Well) layer and an Mg-doped p-type GaN layer formed on the MQW layer.
  • the GaN system in the GaN-based semiconductor layer indicates that Ga and N are included in the constituent elements.
  • FIGS. 2A is a perspective view of the semiconductor wafer according to the first embodiment
  • FIG. 2B is a partial cross-sectional view showing a light emitting element portion of the semiconductor wafer of FIG. 2A.
  • Ga 2 O 3 Wafer Substrate A substrate made of gallium oxide (Ga 2 O 3 ), which is located on opposite sides of each other and has a (101) or ( ⁇ 201) plane orientation.
  • a disc-shaped Ga 2 O 3 wafer substrate 110 having two main surfaces 1a and 1b is prepared.
  • a plurality of light-emitting elements 10 are formed in a matrix in the row direction x and the column direction y orthogonal to each other on the Ga 2 O 3 wafer substrate 110.
  • the row direction x is a direction parallel to the first main surface 1 a and the cleavage plane of the Ga 2 O 3 substrate 11.
  • the column direction y is a direction that is parallel to the first main surface 1 a but is not parallel to the cleavage plane of the Ga 2 O 3 substrate 11.
  • an AlN buffer layer is formed on the first main surface 1a of the Ga 2 O 3 wafer substrate 110, and a GaN-based semiconductor layer 12 is epitaxially grown on the AlN buffer layer. Let it form. Then, the p-side electrode 13 is formed on the GaN-based semiconductor layer 12, and the n-side electrode 14 is formed on the second main surface 1 b of the Ga 2 O 3 wafer substrate 110.
  • MOCVD Metal-Organic Vapor Phase Epitaxy
  • FIG. 3 is a perspective view of the semiconductor wafer showing a state where it is mounted on the dicing frame.
  • the dicing tape 3 is attached to the back surface of the annular dicing frame 2, and the first main surface 1 a of the semiconductor wafer 1 is attached to the dicing tape 3.
  • FIG. 4 is a plan view of the main part of the semiconductor wafer 1.
  • the division lines 4x and 4y are set between the light emitting elements 10 so as to be orthogonal to each other.
  • the planned division line 4x is matched with the row direction x, and the planned division line 4y is matched with the column direction y.
  • FIGS. 5A, 5C, and 5E are cross-sectional views showing main parts of the dicing step according to the first embodiment
  • FIG. 5B is a plan view of FIG. 5A
  • FIG. 5D is a plan view of FIG.
  • FIG. 5F is a plan view of FIG. 5E.
  • the first main surface 1 a of the semiconductor wafer 1 is stuck on the dicing tape 3.
  • the width W 1 of the first dicing blade 5A is preferably, for example, 25 to 55 ⁇ m, and more preferably 35 to 45 ⁇ m. In the present embodiment, the width W 1 of the first dicing blade 5A is 40 ⁇ m.
  • the depth d of the groove 111 is preferably 20 to 50 ⁇ m, for example, and more preferably 30 to 40 ⁇ m. In the present embodiment, the depth d of the groove 111 is 35 ⁇ m.
  • the semiconductor wafer 1 is peeled off from the dicing tape 3, a new dicing tape 3 is attached to the dicing frame 2, the semiconductor wafer 1 is turned upside down, and the second main surface 1 b is placed on the new dicing tape 3. Adhere to.
  • the first dicing blade 5B having a width W 2 narrower than the width W 1 of the first dicing blade 5A is used to form the first of the Ga 2 O 3 wafer substrate 110. All the remaining thickness of the Ga 2 O 3 wafer substrate 110 is cut along the planned division line 4y from the main surface 1a side.
  • reference numeral 112 denotes a cut surface. The cutting is performed by aligning the center of the second dicing blade 5B with the center of the groove 111.
  • the width W 2 of the second dicing blade 5B is preferably 10 to 30 ⁇ m, and more preferably 15 to 25 ⁇ m.
  • the width W 2 of the second dicing blade 5B is 20 ⁇ m.
  • the first and second dicing blades 5A and 5B have a thin disk shape, and for example, a diamond blade having diamond abrasive grains in an abrasive layer is used.
  • the second dicing blade 5B is used to divide the Ga 2 O 3 wafer substrate 110 from the first main surface 1a side along the planned division line 4x parallel to the cleavage plane.
  • the entire thickness of the Ga 2 O 3 wafer substrate 110 is cut and divided into element units.
  • reference numeral 112 denotes a cut surface.
  • a rectangular Ga 2 O 3 substrate 11 is formed by dividing the element unit, and the light emitting element 10 shown in FIG. 1 is formed.
  • surfaces 111a and 111b are surfaces formed by the first dicing blade 5A.
  • the first side surface 1c and the second side surface 1d are surfaces formed by the second dicing blade 5B.
  • wax is applied to the surface of the plate glass on a hot plate set at 100 ° C., and the Ga 2 O 3 wafer substrate 110 is fixed on the plate glass.
  • the integrated plate glass and the Ga 2 O 3 wafer substrate 110 are fixed to a dicing tape.
  • the Ga 2 O 3 wafer substrate 110 is cut in the vertical direction from the planned dividing line 4x by the second dicing blade 5B.
  • the abrasive grains of the second dicing blade 5B have a larger particle diameter.
  • Table 1 shows the presence or absence of occurrence of oblique cracks when the Ga 2 O 3 wafer substrate 110 is cut for each median diameter of the diamond abrasive grains of the second dicing blade 5B.
  • the median diameter is a particle diameter at a 50% cumulative height in the particle size distribution of the abrasive grains.
  • Table 1 shows that oblique cracks along the cleavage direction of the Ga 2 O 3 wafer substrate 110 do not occur when the particle diameter of the abrasive grains of the second dicing blade 5B is large.
  • the Ga 2 O 3 wafer substrate 110 and the Ga 2 O 3 based semiconductor layer 12 are cut at once with a dicing blade, cracks are likely to occur in parallel along the cleavage direction.
  • the Ga 2 O 3 based semiconductor layer 12 is not diced, cracks and the like can be suppressed. Therefore, it is possible to divide into elements by suppressing damage such as peeling or cracking due to cleavage of the Ga 2 O 3 wafer substrate 110, and to provide a light emitting element 10 in which damage such as peeling or cracking due to cleavage of the substrate is suppressed. be able to.
  • FIG. 6A is a perspective view of a light emitting device according to a second embodiment of the present invention
  • FIG. 6B is a cross-sectional view taken along the line CC of FIG. 6A
  • FIG. 6C is a view taken in the direction of arrow D in FIG.
  • the stepped portion 15 is formed at the corner between the second main surface 1b and the second side surface 1d as a recess.
  • the second main surface 1b is used as a recess.
  • a groove 111 is formed at the corner with the second side surface 1d.
  • Emitting element 10 of this embodiment like the first embodiment, the first main surface 1a, the second main surface 1b, Ga 2 O having a first side surface 1c and a second side 1d 3 substrate 11, GaN-based semiconductor layer 12 formed on first main surface 1 a of Ga 2 O 3 substrate 11 via an AlN buffer layer (not shown), and p-side electrode formed on GaN-based semiconductor layer 12 13 and an n-side electrode 14 formed on the second main surface 1b of the Ga 2 O 3 substrate 11.
  • the groove 111 is formed about 5 to 20 ⁇ m away from the second side surface 1d.
  • the groove 111 may have a distance from the second side surface 1d of less than 5 ⁇ m.
  • one groove 111 is formed between the light emitting elements 10 on the second main surface 1b of the semiconductor wafer 1.
  • the two grooves 111 are formed with an interval s. The formed point is different from the first embodiment.
  • a Ga 2 O 3 wafer substrate 110 is prepared, and a plurality of light emitting elements 10 are matrixed in the row direction x and the column direction y on the Ga 2 O 3 wafer substrate 110.
  • the dicing tape 3 is attached to the back surface of the annular dicing frame 2, and the first main surface 1 a of the semiconductor wafer 1 is attached to the dicing tape 3.
  • FIG. 7A, 7C, and 7E are cross-sectional views showing the main part of the dicing process according to the second embodiment
  • FIG. 7B is a plan view of FIG. 7A
  • FIG. 7D is a plan view of FIG. 7C
  • FIG. 7E is a plan view of FIG. 7E.
  • the first main surface 1 a of the semiconductor wafer 1 is stuck on the dicing tape 3.
  • Forming a Ga 2 O 3 wafer second centered on dividing lines 4y main surface 1b is provided a distance s 2 two grooves 111 of the substrate 110 using a second dicing blade 5B of a width W 2.
  • the width W 2 of the second dicing blade 5B is preferably 10 to 30 ⁇ m, and more preferably 15 to 25 ⁇ m.
  • the width W 2 of the second dicing blade 5B is 20 ⁇ m.
  • the interval s is, for example, preferably 20 to 40 ⁇ m, and more preferably 25 to 35 ⁇ m.
  • the interval s is set to 30 ⁇ m.
  • the depth d of the groove 111 is preferably 20 to 50 ⁇ m, for example, and more preferably 30 to 40 ⁇ m. In the present embodiment, the depth d of the groove 111 is 35 ⁇ m.
  • the semiconductor wafer 1 is peeled off from the dicing tape 3, a new dicing tape 3 is attached to the dicing frame 2, the semiconductor wafer 1 is turned upside down, and the second main surface 1 b is placed on the new dicing tape 3. Adhere to.
  • the entire thickness of the Ga 2 O 3 wafer substrate 110 is cut along 4y.
  • reference numeral 112 denotes a cut surface. The cutting is performed by aligning the center of the second dicing blade 5B with the center between the grooves 111. Different dicing blades for grooves and dicing blades for cutting may be used.
  • FIG. 7E as shown in FIG. 7F, the 2 Ga 2 using a dicing blade 5B of the O 3 first 1 Ga 2 from the main surface 1a side along the dividing lines 4x of O 3 wafer wafer substrate 110
  • the entire thickness of the substrate 110 is cut and divided into element units.
  • reference numeral 112 denotes a cut surface.
  • a rectangular Ga 2 O 3 substrate 11 is formed by dividing the element unit, and the light emitting element 10 shown in FIG. 6 is formed.
  • the groove 111, the first side surface 1c, and the second side surface 1d are surfaces formed by the second dicing blade 5B.
  • Ga 2 O 3 wafer substrate 110 after forming the groove 111 has been cut Ga 2 O 3 wafer substrate 110 using a dicing blade may be cut Ga 2 O 3 wafer substrate 110 using a laser. That is, a groove 111 is formed on the planned dividing line 4y with a dicing blade, and the entire remaining thickness of the Ga 2 O 3 wafer substrate 110 is cut by the laser along the planned dividing line 4y. Next, the entire thickness of the Ga 2 O 3 wafer substrate 110 is cut by a laser along the planned dividing line 4x and divided into element units.
  • the Ga 2 O 3 wafer substrate 110 is cut using a dicing blade, but a part of the dicing scribe may be employed. That is, the groove 111 is formed on the planned division line 4y with a dicing blade, and all the remaining thickness of the Ga 2 O 3 wafer substrate 110 is cut along the planned division line 4y with the dicing blade. Next, a groove is formed by scribing on the planned dividing line 4x, stress is applied and breaking is performed, and the Ga 2 O 3 wafer substrate 110 is divided into element units.
  • FIG. 8 shows a main part of the semiconductor wafer 1 viewed from the second main surface 1b side
  • FIG. 8A is a photograph of the example
  • FIG. 8B is a photograph of the comparative example.
  • a region C shown in FIG. 8A is according to an example corresponding to the first embodiment. After forming the groove 111 in the Ga 2 O 3 wafer substrate 110 with a dicing blade having a width of 40 ⁇ m, the dicing blade having a width of 20 ⁇ m is formed. A case where the remaining thickness of the Ga 2 O 3 wafer substrate 110 is cut is shown. It can be seen from FIG. 8A that there is almost no peeling in the region C.
  • a region D shown in FIG. 8B is according to a comparative example, and shows a case where the entire thickness of the Ga 2 O 3 wafer substrate 110 is cut once with a dicing blade having a width of 20 ⁇ m without forming a groove. From FIG. 8B, it can be seen that in the region D, the peeling 113 occurs on the main surface on the side from which the dicing blade comes out.
  • this invention is not limited to the said embodiment, In the range which does not change the summary of invention, it can deform
  • the vertical type is described as the light emitting element, but the present invention can also be applied to a horizontal type.
  • the light-emitting element is described as a semiconductor element.
  • the present invention can also be applied to a semiconductor element such as a laser or a transistor.
  • the division lines are set to be orthogonal, but may be set to intersect in an oblique direction.
  • a diamond-shaped semiconductor element is formed.
  • the groove 111 is formed on the second main surface 1b on the side having a smaller electrode area.
  • the groove 111 may be formed on the first main surface 1a on the side having a larger electrode area.
  • the remaining thickness of the substrate is cut after forming a groove in the substrate, and the planned division line 4x parallel to the cleavage plane is cut.
  • the entire thickness of the substrate was cut without forming a groove in the substrate.
  • the groove was formed in the substrate and then the remaining thickness of the substrate was cut. You can do it.
  • a semiconductor element that can be easily positioned when cutting out an element from a wafer and can suppress damage such as peeling and cracking due to cleavage of the substrate, and a method for manufacturing the same.
  • SYMBOLS 1 Semiconductor wafer, 1a ... 1st main surface, 1b ... 2nd main surface, 1c ... 1st side surface, 1d ... 2nd side surface, 2 ... Dicing frame, 3 ... Dicing tape, 4x, 4y ... Divided Planned line, 5A ... first dicing blade, 5B ... second dicing blade, 10 ... light emitting element, 11 ... Ga 2 O 3 substrate, 12 ... GaN-based semiconductor layer, 13 ... p-side electrode, 14 ...

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  • Manufacturing & Machinery (AREA)
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  • Power Engineering (AREA)
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Abstract

Provided are a semiconductor element and manufacturing method thereof in which positioning is simple when cutting elements from a wafer and in which damage such as peeling and cracking due to cleavage of the substrate can be suppressed. A light-emitting element (10) is provided with: first and second primary surfaces (1a, 1b) positioned opposite of each other, and a first lateral surface (1c) parallel to a direction parallel with the first primary surface (1a) and the cleaved surface; a Ga2O3 substrate (11) having a second lateral surface (1d) which intersects with the first lateral surface (1c); a GaN-based semiconductor layer (12) formed on the first primary surface (1a) of the Ga2O3 substrate (11); and a step portion (15) which is formed at the corner of the second lateral surface (1d) and the second primary surface (1b) of the Ga2O3 substrate (11) and which is a depression that suppresses peeling when the Ga2O3 wafer substrate (11) is split into element units with a dicing blade.

Description

半導体素子及びその製造方法Semiconductor device and manufacturing method thereof
　本発明は、酸化ガリウムからなる基板を用いた半導体素子及びその製造方法に関する。 The present invention relates to a semiconductor device using a substrate made of gallium oxide and a method for manufacturing the same.
　従来、ＧａＮ系半導体を用いた青色や短波長領域の発光素子が知られている。このような発光素子の下地基板として、例えばサファイア基板やＳｉＣ基板が用いられてきた。しかし、サファイア基板は、導電性を有しないため、発光素子の電極構造が水平型となる構造上の制約を有している。また、ＳｉＣ基板は、単結晶ウエハの結晶性が悪く、単結晶の垂直方向に貫通するいわゆるマイクロパイプ欠陥が存在するため、マイクロパイプ欠陥を避けてｎ型層及びｐ型層を形成して切り出さなければならない等という問題がある。 Conventionally, light emitting elements of blue and short wavelength regions using GaN-based semiconductors are known. For example, a sapphire substrate or a SiC substrate has been used as a base substrate of such a light emitting element. However, since the sapphire substrate does not have conductivity, the sapphire substrate has a structural restriction that the electrode structure of the light emitting element is a horizontal type. In addition, since the SiC substrate has poor crystallinity of the single crystal wafer and has so-called micropipe defects penetrating in the vertical direction of the single crystal, the n-type layer and the p-type layer are formed by cutting out the micropipe defects. There is a problem of having to.
　そこで、III－V族系化合物半導体の発光領域の全波長範囲、特に紫外領域で光透過性を有し、ＧａＮに対する格子不整合が比較的小さく、また良質なバルク単結晶が得られるという特性から、青色や短波長領域の発光素子材料としてＧａ2Ｏ3基板を用いることが提案されている（例えば、特許文献１参照）。 Therefore, from the characteristics that III-V group compound semiconductor has light transmittance in the entire wavelength range of the light emitting region, particularly in the ultraviolet region, has relatively small lattice mismatch with GaN, and can obtain a good quality bulk single crystal. In addition, it has been proposed to use a Ga 2 O 3 substrate as a light emitting element material in a blue or short wavelength region (see, for example, Patent Document 1).
　しかし、このＧａ2Ｏ3基板、特にβ－Ｇａ2Ｏ3基板は、（１００）面に劈開性の極めて大なる特性を有しており、発光素子の製造工程においてウエハから素子をダイシング等によって切り出す際に基板が劈開方向に剥離してしまうため、素子化が難しいという問題がある。 However, this Ga 2 O 3 substrate, particularly the β-Ga 2 O 3 substrate, has an extremely high cleavage property on the (100) plane, and the device is diced from the wafer in the manufacturing process of the light emitting device. Since the substrate is peeled off in the cleavage direction when cutting out, there is a problem that it is difficult to make an element.
　このため、基板の劈開による剥離を防いで素子単位に分割する発光素子の製造方法が提案されている（例えば、特許文献２参照。）。この特許文献２には、酸化ガリウム（Ｇａ2Ｏ3）からなる基板上に発光素子を作り込んだ半導体ウエハを形成し、半導体ウエハの表方向からダイシングブレードで溝入れを行い、半導体ウエハの表裏を反転してダイシングブレードで溝入れを行って発光素子を個々に分割する第１の方法と、第１の厚さを有するダイシングブレードで半導体ウエハの表方向から溝入れを行い、第１の厚さよりも薄い第２の厚さを有するダイシングブレードで半導体ウエハの表方向から残りの部分を切断する第２の方法とが開示されている。 For this reason, a method for manufacturing a light-emitting element in which peeling due to cleavage of the substrate is prevented and the element is divided into element units has been proposed (see, for example, Patent Document 2). In this patent document 2, a semiconductor wafer in which a light emitting element is formed on a substrate made of gallium oxide (Ga 2 O 3 ) is formed, and grooving is performed with a dicing blade from the front side of the semiconductor wafer. The first method in which the light emitting elements are individually divided by grooving with a dicing blade and the dicing blade having the first thickness is grooved from the surface direction of the semiconductor wafer, and the first thickness is obtained. And a second method of cutting the remaining portion of the semiconductor wafer from the front direction with a dicing blade having a second thickness smaller than the first thickness.
特開２００６－３１０７６５号公報JP 2006-310765 A 特開２００７－２３４９０２号公報JP 2007-234902 A
　しかし、特許文献２に開示された第１の方法によると、表面に形成する溝と裏面に形成する溝との位置決めが難しいという問題がある。また、特許文献２に開示された第２の方法によると、ダイシングブレードが基板を抜け出るときに基板の劈開方向に沿って剥がれが生じやすいという問題がある。レーザで溝を形成した後、応力を加えて分割するダイシングスクライブでも同様の問題がある。 However, according to the first method disclosed in Patent Document 2, there is a problem that it is difficult to position the groove formed on the front surface and the groove formed on the back surface. Further, according to the second method disclosed in Patent Document 2, there is a problem that peeling is likely to occur along the cleavage direction of the substrate when the dicing blade exits the substrate. There is a similar problem in dicing scribe in which grooves are formed by laser and then divided by applying stress.
　したがって、本発明の目的は、ウエハから素子を切り出す際の位置決めが容易で、基板の劈開による剥がれや割れ等の損傷を抑制することができる半導体素子及びその製造方法を提供することにある。 Therefore, an object of the present invention is to provide a semiconductor device that can be easily positioned when the device is cut out from a wafer and can suppress damage such as peeling and cracking due to cleavage of the substrate, and a method for manufacturing the same.
　本発明の一態様は、上記目的を達成するため、酸化ガリウムからなる基板であって、互いに反対側に位置する第１及び第２の主面と、前記第１の主面及び劈開面に平行な方向に平行な第１の側面と、前記第１の側面と交差する第２の側面とを有する基板と、前記基板の前記第１の主面に形成された半導体層と、前記基板の前記第１又は第２の主面と前記第２の側面との角部に形成され、前記基板を素子単位に分割する際の剥離を抑制する凹部とを備えた半導体素子を提供する。 According to one embodiment of the present invention, in order to achieve the above object, a substrate made of gallium oxide, which is parallel to the first and second main surfaces located on opposite sides, and the first main surface and the cleavage surface. A substrate having a first side surface parallel to an arbitrary direction and a second side surface intersecting the first side surface; a semiconductor layer formed on the first main surface of the substrate; Provided is a semiconductor device provided with a recess formed at a corner portion between the first or second main surface and the second side surface and suppressing separation when the substrate is divided into device units.
　また、本発明の一態様は、上記目的を達成するため、酸化ガリウムからなる基板であって、互いに反対側に位置する第１及び第２の主面を有する基板を準備し、前記基板に複数の半導体素子を前記第１の主面及び前記基板の劈開面に平行な第１の方向と、前記第１の方向に交差する第２の方向に沿ってマトリクス状に形成し、前記基板の前記半導体素子間であって前記第１及び第２の主面のうち一方の主面に前記第２の方向に沿う複数の凹部を形成し、前記第１及び第２の主面のうち他方の主面から前記複数の凹部に沿って前記基板を切断し、前記第１の方向に沿って前記基板を切断して前記複数の半導体素子を素子単位に分割する半導体素子の製造方法を提供する。 In one embodiment of the present invention, in order to achieve the above object, a substrate made of gallium oxide and having a first main surface and a second main surface positioned on opposite sides is prepared. Are formed in a matrix form along a first direction parallel to the first main surface and the cleavage plane of the substrate and a second direction intersecting the first direction, A plurality of recesses along the second direction are formed in one main surface of the first and second main surfaces between the semiconductor elements, and the other main surface of the first and second main surfaces is formed. A method for manufacturing a semiconductor device is provided, wherein the substrate is cut along the plurality of recesses from a surface, and the substrate is cut along the first direction to divide the plurality of semiconductor devices into device units.
　本発明によれば、ウエハから素子を切り出す際の位置決めが容易で、基板の劈開による剥がれや割れ等の損傷を抑制することができる。 According to the present invention, positioning when cutting out an element from a wafer is easy, and damage such as peeling or cracking due to cleavage of the substrate can be suppressed.
図１Ａは、本発明の第１の実施の形態に係る発光素子の斜視図である。FIG. 1A is a perspective view of a light emitting device according to a first embodiment of the present invention. 図１Ｂは、図１ＡのＡ－Ａ線断面図である。1B is a cross-sectional view taken along line AA in FIG. 1A. 図１Ｃは、図１ＡのＢ方向矢視図である。1C is a view in the direction of arrow B in FIG. 1A. 図２Ａは、本発明の第１の実施の形態に係る半導体ウエハの斜視図である。FIG. 2A is a perspective view of the semiconductor wafer according to the first embodiment of the present invention. 図２Ｂは、図２Ａの半導体ウエハの発光素子の部分を示す部分断面図である。2B is a partial cross-sectional view showing a light emitting element portion of the semiconductor wafer of FIG. 2A. 図３は、ダイシングフレームに装着された状態を示す半導体ウエハの斜視図である。FIG. 3 is a perspective view of the semiconductor wafer showing a state where it is mounted on the dicing frame. 図４は、図３に示す半導体ウエハの要部平面図である。FIG. 4 is a plan view of an essential part of the semiconductor wafer shown in FIG. 図５Ａは、第１の実施の形態に係るダイシング工程を示す要部断面図である。FIG. 5A is a fragmentary cross-sectional view showing a dicing process according to the first embodiment. 図５Ｂは、図５Ａの平面図である。FIG. 5B is a plan view of FIG. 5A. 図５Ｃは、第１の実施の形態に係るダイシング工程を示す要部断面図である。FIG. 5C is a fragmentary cross-sectional view showing the dicing process according to the first embodiment. 図５Ｄは、図５Ｃの平面図である。FIG. 5D is a plan view of FIG. 5C. 図５Ｅは、第１の実施の形態に係るダイシング工程を示す要部断面図である。FIG. 5E is a cross-sectional view illustrating the main parts in the dicing process according to the first embodiment. 図５Ｆは、図５Ｅの平面図である。FIG. 5F is a plan view of FIG. 5E. 図６Ａは、本発明の第２の実施の形態に係る発光素子の斜視図である。FIG. 6A is a perspective view of a light emitting device according to a second embodiment of the present invention. 図６Ｂは、図６ＡのＣ－Ｃ線断面図である。6B is a cross-sectional view taken along the line CC of FIG. 6A. 図６Ｃは、図６ＡのＤ方向矢視図である。6C is a view in the direction of arrow D in FIG. 6A. 図７Ａは、第２の実施の形態に係るダイシング工程を示す要部断面図である。FIG. 7A is a fragmentary cross-sectional view showing a dicing process according to the second embodiment. 図７Ｂは、図７Ａの平面図である。FIG. 7B is a plan view of FIG. 7A. 図７Ｃは、第２の実施の形態に係るダイシング工程を示す要部断面図である。FIG. 7C is a fragmentary cross-sectional view showing the dicing process according to the second embodiment. 図７Ｄは、図７Ｃの平面図である。FIG. 7D is a plan view of FIG. 7C. 図７Ｅは、第２の実施の形態に係るダイシング工程を示す要部断面図である。FIG. 7E is a fragmentary cross-sectional view showing the dicing process according to the second embodiment. 図７Ｆは、図７Ｅの平面図である。FIG. 7F is a plan view of FIG. 7E. 図８Ａは、実施例の写真である。FIG. 8A is a photograph of the example. 図８Ｂは、比較例の写真である。FIG. 8B is a photograph of a comparative example.
　以下、本発明の実施の形態について図面を参照して説明する。なお、各図中、実質的に同一の機能を有する構成要素については、同一の符号を付してその重複した説明を省略する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in each figure, about the component which has the substantially same function, the same code | symbol is attached | subjected and the duplicate description is abbreviate | omitted.
［第１の実施の形態］
（第１の実施の形態の構成）
　図１Ａは、本発明の第１の実施の形態に係る発光素子の斜視図、図１Ｂは、図１ＡのＡ－Ａ線断面図、図１Ｃは、図１ＡのＢ方向矢視図である。 [First Embodiment]
(Configuration of the first embodiment)
1A is a perspective view of the light emitting device according to the first embodiment of the present invention, FIG. 1B is a cross-sectional view taken along line AA in FIG. 1A, and FIG. 1C is a view in the direction of arrow B in FIG. 1A.
　この発光素子１０は、半導体素子の一例であり、酸化ガリウム（Ｇａ2Ｏ3）からなる基板であって、互いに反対側に位置する第１の主面１ａ及び第２の主面１ｂと、互いに交差する第１の側面１ｃ及び第２の側面１ｄとを有するＧａ2Ｏ3基板１１と、Ｇａ2Ｏ3基板１１の第１の主面１ａに図示しないＡｌＮバッファ層を介して形成されたＧａＮ系半導体層１２と、ＧａＮ系半導体層１２上に形成されたＡｕ等からなるｐ側電極１３と、Ｇａ2Ｏ3基板１１の第２の主面１ｂに形成されたＡｕ等からなるｎ側電極１４とを有する。第１の側面１ｃは、第１の主面１ａ及びＧａ2Ｏ3基板１１の劈開面に平行な方向（後述する分割予定ライン４ｘの方向）に平行な面である。 The light-emitting element 10 is an example of a semiconductor element, which is a substrate made of gallium oxide (Ga 2 O 3 ), and the first main surface 1a and the second main surface 1b located on opposite sides of each other, and Ga 2 O 3 substrate 11 having intersecting first side surface 1c and second side surface 1d, and GaN formed on first main surface 1a of Ga 2 O 3 substrate 11 via an AlN buffer layer (not shown). A p-side electrode 13 made of Au or the like formed on the GaN-based semiconductor layer 12, and an n-side electrode made of Au or the like formed on the second main surface 1 b of the Ga 2 O 3 substrate 11. 14. The first side surface 1c is a surface parallel to the first main surface 1a and the direction parallel to the cleavage plane of the Ga 2 O 3 substrate 11 (the direction of the planned division line 4x described later).
（Ｇａ2Ｏ3基板）
　Ｇａ2Ｏ3基板１１は、第２の主面１ｂと第２の側面１ｄとの角部に、ダイシングブレードでＧａ2Ｏ3基板１１を素子単位に分割する際の剥がれや割れ等の損傷を抑制する凹部が形成されている。本実施の形態の凹部は、第２の主面１ｂと交差する面１１１ａ、及び第２の側面１ｄと交差する面１１１ｂから構成された段差部１５である。 (Ga 2 O 3 substrate)
The Ga 2 O 3 substrate 11 is damaged at the corners of the second main surface 1b and the second side surface 1d by peeling or cracking when the Ga 2 O 3 substrate 11 is divided into element units by a dicing blade. The recessed part to suppress is formed. The concave portion of the present embodiment is a step 15 constituted by a surface 111a intersecting with the second main surface 1b and a surface 111b intersecting with the second side surface 1d.
　本明細書において、Ｇａ2Ｏ3基板１１の「劈開面」は、（１００）面及び（００１）面である。また、本明細書において、角部に形成された「凹部」は、主面と側面との角そのものに形成された凹部だけでなく、角近傍に形成された凹部も含む意味で用いる。 In this specification, the “cleavage plane” of the Ga 2 O 3 substrate 11 is a (100) plane and a (001) plane. Further, in this specification, the “concave portion” formed in the corner portion is used to include not only the concave portion formed in the corner between the main surface and the side surface but also the concave portion formed in the vicinity of the corner.
　本実施の形態では、Ｇａ2Ｏ3基板１１の第１の主面１ａ及び第２の主面１ｂの面方位を（１０１）又は（－２０１）面とし、第２の側面１ｄを（０１０）面としている。Ｇａ2Ｏ3基板１１は、例えば１００～２００μｍの厚さを有する。 In the present embodiment, the plane orientation of the first main surface 1a and the second main surface 1b of the Ga 2 O 3 substrate 11 is the (101) or (−201) plane, and the second side surface 1d is (010). It is a surface. The Ga 2 O 3 substrate 11 has a thickness of 100 to 200 μm, for example.
　（１０１）又は（－２０１）面を主面１ａ、１ｂとしたのは、以下の理由による。主面として劈開により平坦な表面が得られ、かつＧａＮ系半導体層がエピタキシャル成長しやすい（１００）面を用いることが多い。しかし、（１００）面は劈開面のため、分割時に主面１ａ、１ｂと水平な行方向にクラックが入るという問題がある。このため、主面１ａ、１ｂは、非劈開面でかつＧａＮ系半導体層がエピタキシャル成長しやすい面である（１０１）又は（－２０１）面を用いることにした。 The reason why the (101) or (−201) surface is the main surface 1a or 1b is as follows. As the main surface, a (100) surface is often used which provides a flat surface by cleavage and is easy to epitaxially grow a GaN-based semiconductor layer. However, since the (100) plane is a cleavage plane, there is a problem that cracks occur in the row direction parallel to the main surfaces 1a and 1b during division. For this reason, the principal surfaces 1a and 1b are (101) or (−201) planes that are non-cleavage surfaces and are surfaces on which the GaN-based semiconductor layer is likely to grow epitaxially.
　このＧａ2Ｏ3基板１１は、β－Ｇａ2Ｏ3を基本とするが、Ｃｕ、Ａｇ、Ｚｎ、Ｃｄ、Ａｌ、Ｉｎ、Ｓｉ、Ｇｅ及びＳｎからなる群から選ばれる１種以上を添加したＧａを主成分とした酸化物で構成してもよい。より具体的には、例えば（ＡｌxＩｎyＧａ(1-x-y)）2Ｏ3（ただし、０≦ｘ＜１、０≦ｙ＜１、０≦ｘ＋ｙ＜１）で表わされるガリウム酸化物を用いることができる。 The Ga 2 O 3 substrate 11 is based on β-Ga 2 O 3 , but one or more selected from the group consisting of Cu, Ag, Zn, Cd, Al, In, Si, Ge, and Sn are added. You may comprise with the oxide which has Ga as a main component. More specifically, for example, a gallium oxide represented by (Al x In y Ga (1-xy) ) 2 O 3 (where 0 ≦ x <1, 0 ≦ y <1, 0 ≦ x + y <1) is used. Can be used.
　また、Ｇａ2Ｏ3基板１１は、酸素欠陥により、又はＳｉやＳｎ等の不純物がドーピングされることにより、ｎ型の導電型を有する。 The Ga 2 O 3 substrate 11 has an n-type conductivity type by oxygen defects or by being doped with impurities such as Si and Sn.
　上記のＧａ2Ｏ3基板１１は、例えばＥＦＧ（Edge-defined Film-fed Growth）法又はＦＺ（Floating Zone）法によって製造されたバルク状のＧａ2Ｏ3を所望の寸法に切り出し、その表面に機械的研磨又は化学的研磨を施し、さらに有機洗浄及び酸洗浄を行ったものを用いることができる。
  The Ga 2 O 3 substrate 11 is formed by cutting bulk Ga 2 O 3 produced by, for example, an EFG (Edge-defined Film-fed Growth) method or an FZ (Floating Zone) method into a desired dimension, A material that has been subjected to mechanical polishing or chemical polishing and further subjected to organic cleaning and acid cleaning can be used.
（ＧａＮ系半導体層）
　ＧａＮ系半導体層１２は、ＡｌＮバッファ層上に形成されたＳｉドープのｎ型ＧａＮ層と、ｎ型ＧａＮ層上に形成され、ＩｎＧａＮ／ＧａＮの多重量子井戸構造を有する活性層としてのＭＱＷ（Multiple-Quantum Well）層と、ＭＱＷ層上に形成されたＭｇドープのｐ型ＧａＮ層とを備えて構成されている。ＧａＮ系半導体層におけるＧａＮ系は、ＧａとＮを構成要素に含むことを示す。
  (GaN-based semiconductor layer)
The GaN-based semiconductor layer 12 includes an Si-doped n-type GaN layer formed on the AlN buffer layer and an MQW (Multiple as an active layer formed on the n-type GaN layer and having an InGaN / GaN multiple quantum well structure. -Quantum Well) layer and an Mg-doped p-type GaN layer formed on the MQW layer. The GaN system in the GaN-based semiconductor layer indicates that Ga and N are included in the constituent elements.
（第１の実施の形態の製造方法）
　次に、発光素子１０の製造方法の一例について図２～図５を参照して説明する。図２Ａは、第１の実施の形態に係る半導体ウエハの斜視図、図２Ｂは、図２Ａの半導体ウエハの発光素子の部分を示す部分断面図である。 (Manufacturing method of the first embodiment)
Next, an example of a method for manufacturing the light emitting element 10 will be described with reference to FIGS. 2A is a perspective view of the semiconductor wafer according to the first embodiment, and FIG. 2B is a partial cross-sectional view showing a light emitting element portion of the semiconductor wafer of FIG. 2A.
（１）Ｇａ2Ｏ3ウエハ基板の準備
　酸化ガリウム（Ｇａ2Ｏ3）からなる基板であって、互いに反対側に位置し面方位を（１０１）又は（－２０１）面とする第１及び第２の主面１ａ、１ｂを有する円盤状のＧａ2Ｏ3ウエハ基板１１０を準備する。 (1) Preparation of Ga 2 O 3 Wafer Substrate A substrate made of gallium oxide (Ga 2 O 3 ), which is located on opposite sides of each other and has a (101) or (−201) plane orientation. A disc-shaped Ga 2 O 3 wafer substrate 110 having two main surfaces 1a and 1b is prepared.
（２）発光素子の形成
　Ｇａ2Ｏ3ウエハ基板１１０に複数の発光素子１０を互いに直交する行方向ｘ及び列方向ｙにマトリクス状に形成する。ここで、行方向ｘは、第１の主面１ａ及びＧａ2Ｏ3基板１１の劈開面に平行な方向である。列方向ｙは、第１の主面１ａに平行であるが、Ｇａ2Ｏ3基板１１の劈開面に平行でない方向である。ＭＯＣＶＤ（Metal-Organic Vapor Phase Epitaxy）法等を用いて、Ｇａ2Ｏ3ウエハ基板１１０の第１の主面１ａ上にＡｌＮバッファ層を形成し、ＡｌＮバッファ層上にＧａＮ系半導体層１２をエピタキシャル成長させて形成する。そして、ＧａＮ系半導体層１２上にｐ側電極１３を形成し、Ｇａ2Ｏ3ウエハ基板１１０の第２の主面１ｂ上にｎ側電極１４を形成する。
  (2) Formation of Light-Emitting Elements A plurality of light-emitting elements 10 are formed in a matrix in the row direction x and the column direction y orthogonal to each other on the Ga 2 O 3 wafer substrate 110. Here, the row direction x is a direction parallel to the first main surface 1 a and the cleavage plane of the Ga 2 O 3 substrate 11. The column direction y is a direction that is parallel to the first main surface 1 a but is not parallel to the cleavage plane of the Ga 2 O 3 substrate 11. Using an MOCVD (Metal-Organic Vapor Phase Epitaxy) method or the like, an AlN buffer layer is formed on the first main surface 1a of the Ga 2 O 3 wafer substrate 110, and a GaN-based semiconductor layer 12 is epitaxially grown on the AlN buffer layer. Let it form. Then, the p-side electrode 13 is formed on the GaN-based semiconductor layer 12, and the n-side electrode 14 is formed on the second main surface 1 b of the Ga 2 O 3 wafer substrate 110.
（３）半導体ウエハのダイシングフレームへの装着
　図３は、ダイシングフレームに装着された状態を示す半導体ウエハの斜視図である。環状のダイシングフレーム２の裏面にダイシングテープ３を貼着し、半導体ウエハ１の第１の主面１ａをダイシングテープ３上に貼着する。 (3) Mounting of Semiconductor Wafer on Dicing Frame FIG. 3 is a perspective view of the semiconductor wafer showing a state where it is mounted on the dicing frame. The dicing tape 3 is attached to the back surface of the annular dicing frame 2, and the first main surface 1 a of the semiconductor wafer 1 is attached to the dicing tape 3.
　図４は、半導体ウエハ１の要部平面図である。発光素子１０間に分割予定ライン４ｘ、４ｙが互いに直交するように設定されている。分割予定ライン４ｘを行方向ｘに一致させ、分割予定ライン４ｙを列方向ｙに一致させている。 FIG. 4 is a plan view of the main part of the semiconductor wafer 1. The division lines 4x and 4y are set between the light emitting elements 10 so as to be orthogonal to each other. The planned division line 4x is matched with the row direction x, and the planned division line 4y is matched with the column direction y.
（４）ダイシング工程
　図５Ａ、図５Ｃ、図５Ｅは、第１の実施の形態に係るダイシング工程を示す要部断面図、図５Ｂは、図５Ａの平面図、図５Ｄは、図５Ｃの平面図、図５Ｆは、図５Ｅの平面図である。 (4) Dicing Step FIGS. 5A, 5C, and 5E are cross-sectional views showing main parts of the dicing step according to the first embodiment, FIG. 5B is a plan view of FIG. 5A, and FIG. 5D is a plan view of FIG. FIG. 5F is a plan view of FIG. 5E.
　図５Ａ、図５Ｂに示すように、半導体ウエハ１の第１の主面１ａをダイシングテープ３上に貼着する。幅Ｗ1の第１のダイシングブレード５Ａを用いてＧａ2Ｏ3ウエハ基板１１０の第２の主面１ｂの劈開面に平行でない分割予定ライン４ｙ上に溝１１１を形成する。第１のダイシングブレード５Ａの幅Ｗ1としては、例えば、２５～５５μｍが好ましく、３５～４５μｍがより好ましい。本実施の形態では、第１のダイシングブレード５Ａの幅Ｗ1を４０μｍとする。溝１１１の深さｄは、例えば、２０～５０μｍが好ましく、３０～４０μｍがより好ましい。本実施の形態では、溝１１１の深さｄを３５μｍとする。 As shown in FIGS. 5A and 5B, the first main surface 1 a of the semiconductor wafer 1 is stuck on the dicing tape 3. Forming a Ga 2 O 3 wafer second principal surface 1b groove 111 on the dividing line 4y not parallel to the cleavage plane of the substrate 110 using the first dicing blade 5A of the width W 1. The width W 1 of the first dicing blade 5A is preferably, for example, 25 to 55 μm, and more preferably 35 to 45 μm. In the present embodiment, the width W 1 of the first dicing blade 5A is 40 μm. The depth d of the groove 111 is preferably 20 to 50 μm, for example, and more preferably 30 to 40 μm. In the present embodiment, the depth d of the groove 111 is 35 μm.
　次に、半導体ウエハ１をダイシングテープ３から剥がして、新たなダイシングテープ３をダイシングフレーム２に貼着し、半導体ウエハ１を上下反転して第２の主面１ｂをその新たなダイシングテープ３上に貼着する。 Next, the semiconductor wafer 1 is peeled off from the dicing tape 3, a new dicing tape 3 is attached to the dicing frame 2, the semiconductor wafer 1 is turned upside down, and the second main surface 1 b is placed on the new dicing tape 3. Adhere to.
　次に、図５Ｃ、図５Ｄに示すように、第１のダイシングブレード５Ａの幅Ｗ1よりも狭い幅Ｗ2の第２のダイシングブレード５Ｂを用いてＧａ2Ｏ3ウエハ基板１１０の第１の主面１ａ側から分割予定ライン４ｙに沿ってＧａ2Ｏ3ウエハ基板１１０の残部の厚さ全てを切断する。図５Ｃ、図５Ｄ中、符号１１２は、切断面である。切断は、溝１１１の中心に第２のダイシングブレード５Ｂの中心を一致させて行う。第２のダイシングブレード５Ｂの幅Ｗ2としては、例えば、１０～３０μｍが好ましく、１５～２５μｍがより好ましい。本実施の形態では、第２のダイシングブレード５Ｂの幅Ｗ2を２０μｍとする。第１及び第２のダイシングブレード５Ａ、５Ｂは、薄肉円盤状を有し、例えば、ダイヤモンド砥粒を砥粒層に有するダイヤモンドブレードを用いる。 Next, as shown in FIG. 5C and FIG. 5D, the first dicing blade 5B having a width W 2 narrower than the width W 1 of the first dicing blade 5A is used to form the first of the Ga 2 O 3 wafer substrate 110. All the remaining thickness of the Ga 2 O 3 wafer substrate 110 is cut along the planned division line 4y from the main surface 1a side. 5C and 5D, reference numeral 112 denotes a cut surface. The cutting is performed by aligning the center of the second dicing blade 5B with the center of the groove 111. For example, the width W 2 of the second dicing blade 5B is preferably 10 to 30 μm, and more preferably 15 to 25 μm. In the present embodiment, the width W 2 of the second dicing blade 5B is 20 μm. The first and second dicing blades 5A and 5B have a thin disk shape, and for example, a diamond blade having diamond abrasive grains in an abrasive layer is used.
　次に、図５Ｅ、図５Ｆに示すように、第２のダイシングブレード５Ｂを用いてＧａ2Ｏ3ウエハ基板１１０の第１の主面１ａ側から劈開面に平行な分割予定ライン４ｘに沿ってＧａ2Ｏ3ウエハ基板１１０の厚さ全てを切断して素子単位に分割する。図５Ｅ、図５Ｆ中、符号１１２は、切断面である。素子単位の分割によって矩形のＧａ2Ｏ3基板１１が形成され、図１に示す発光素子１０が形成される。図１において、面１１１ａ、１１１ｂは、第１のダイシングブレード５Ａによって形成された面である。第１の側面１ｃ及び第２の側面１ｄは、第２のダイシングブレード５Ｂによって形成された面である。 Next, as shown in FIGS. 5E and 5F, the second dicing blade 5B is used to divide the Ga 2 O 3 wafer substrate 110 from the first main surface 1a side along the planned division line 4x parallel to the cleavage plane. The entire thickness of the Ga 2 O 3 wafer substrate 110 is cut and divided into element units. 5E and 5F, reference numeral 112 denotes a cut surface. A rectangular Ga 2 O 3 substrate 11 is formed by dividing the element unit, and the light emitting element 10 shown in FIG. 1 is formed. In FIG. 1, surfaces 111a and 111b are surfaces formed by the first dicing blade 5A. The first side surface 1c and the second side surface 1d are surfaces formed by the second dicing blade 5B.
　なお、分割予定ライン４ｘ上を垂直方向に切断する場合は、劈開方向に沿ったＧａ2Ｏ3ウエハ基板１１０の斜め割れに注意することが求められる。これらのＧａ2Ｏ3ウエハ基板１１０の斜め割れを防ぐために、次のような工程で切断を行うことが好ましい。 In the case of cutting the upper dividing line 4x vertically, it is necessary to note the diagonal cracking Ga 2 O 3 wafer substrate 110 along the cleavage direction. In order to prevent oblique cracking of these Ga 2 O 3 wafer substrates 110, it is preferable to perform cutting in the following steps.
　まず、１００℃に設定されたホットプレート上で板ガラスの表面にワックスを塗り、Ｇａ2Ｏ3ウエハ基板１１０を板ガラスの上に固定する。次に、一体となった板ガラスとＧａ2Ｏ3ウエハ基板１１０をダイシングテープに固定する。次に、第２のダイシングブレード５ＢでＧａ2Ｏ3ウエハ基板１１０を分割予定ライン４ｘから垂直方向に切断する。 First, wax is applied to the surface of the plate glass on a hot plate set at 100 ° C., and the Ga 2 O 3 wafer substrate 110 is fixed on the plate glass. Next, the integrated plate glass and the Ga 2 O 3 wafer substrate 110 are fixed to a dicing tape. Next, the Ga 2 O 3 wafer substrate 110 is cut in the vertical direction from the planned dividing line 4x by the second dicing blade 5B.
　また、Ｇａ2Ｏ3ウエハ基板１１０の劈開方向に沿った斜め割れを防ぐためには、第２のダイシングブレード５Ｂの砥粒の粒子径が大きい方が好ましい。表１は、第２のダイシングブレード５Ｂのダイヤモンド砥粒のメディアン径ごとの、Ｇａ2Ｏ3ウエハ基板１１０を切断したときの斜め割れの発生の有無を示す。ここで、メディアン径は、砥粒の粒度分布において累積高さ５０％点の粒子径である。表１は、第２のダイシングブレード５Ｂの砥粒の粒子径が大きい場合にＧａ2Ｏ3ウエハ基板１１０の劈開方向に沿った斜め割れが発生しないことを示している。 Further, in order to prevent oblique cracks along the cleavage direction of the Ga 2 O 3 wafer substrate 110, it is preferable that the abrasive grains of the second dicing blade 5B have a larger particle diameter. Table 1 shows the presence or absence of occurrence of oblique cracks when the Ga 2 O 3 wafer substrate 110 is cut for each median diameter of the diamond abrasive grains of the second dicing blade 5B. Here, the median diameter is a particle diameter at a 50% cumulative height in the particle size distribution of the abrasive grains. Table 1 shows that oblique cracks along the cleavage direction of the Ga 2 O 3 wafer substrate 110 do not occur when the particle diameter of the abrasive grains of the second dicing blade 5B is large.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
（第１の実施の形態の効果）
　第１の実施の形態によれば、以下の効果を奏する。
（ａ）Ｇａ2Ｏ3ウエハ基板１１０を劈開面に平行でない方向（分割予定ライン４ｙの方向）に沿ってダイシングブレードで切断する場合、ダイシングブレードが基板から抜け出るときに剥がれが起こりやすい。本実施の形態によれば、第２のダイシングブレード５ＢでＧａ2Ｏ3ウエハ基板１１０を切断する場合、第２のダイシングブレード５Ｂが抜け出る側の第２の主面１ｂに溝１１１が形成されているため、切断による剥がれが発生し難い。また、Ｇａ2Ｏ3ウエハ基板１１０とＧａ2Ｏ3系半導体層１２をダイシングブレードで一度に切断すると、劈開方向に沿って平行に割れが発生しやすい。本実施の形態によれば、Ｇａ2Ｏ3系半導体層１２をダイシングしないようにしているので、割れ等を抑制することができる。したがって、Ｇａ2Ｏ3ウエハ基板１１０の劈開による剥がれや割れ等の損傷を抑制して素子単位に分割することができ、基板の劈開による剥がれや割れ等の損傷を抑制した発光素子１０を提供することができる。
（ｂ）電極の面積が比較的小さいｎ側電極１４を形成した第２の主面１ｂに溝１１１を形成しているので、第１の主面１ａに溝を形成する場合と比べて基板への発光素子の実装密度が向上する。
（ｃ）第１のダイシングブレード５Ａを第２のダイシングブレード５Ｂの幅よりも広い幅のものを用いているので、第２のダイシングブレード５Ｂの位置決めを容易に行うことができる。したがって、ウエハから素子をダイシングによって切り出す際の切断位置の位置決めが容易になる。 (Effects of the first embodiment)
According to the first embodiment, the following effects are obtained.
(A) When the Ga 2 O 3 wafer substrate 110 is cut with a dicing blade along a direction that is not parallel to the cleavage plane (the direction of the division planned line 4y), peeling tends to occur when the dicing blade comes out of the substrate. According to the present embodiment, when the Ga 2 O 3 wafer substrate 110 is cut with the second dicing blade 5B, the groove 111 is formed on the second main surface 1b on the side from which the second dicing blade 5B comes out. Therefore, peeling due to cutting hardly occurs. Further, when the Ga 2 O 3 wafer substrate 110 and the Ga 2 O 3 based semiconductor layer 12 are cut at once with a dicing blade, cracks are likely to occur in parallel along the cleavage direction. According to this embodiment, since the Ga 2 O 3 based semiconductor layer 12 is not diced, cracks and the like can be suppressed. Therefore, it is possible to divide into elements by suppressing damage such as peeling or cracking due to cleavage of the Ga 2 O 3 wafer substrate 110, and to provide a light emitting element 10 in which damage such as peeling or cracking due to cleavage of the substrate is suppressed. be able to.
(B) Since the groove 111 is formed in the second main surface 1b on which the n-side electrode 14 having a relatively small electrode area is formed, the substrate is compared with the case where the groove is formed in the first main surface 1a. The mounting density of the light emitting element is improved.
(C) Since the first dicing blade 5A having a width wider than that of the second dicing blade 5B is used, the second dicing blade 5B can be easily positioned. Therefore, it becomes easy to position the cutting position when the element is cut out from the wafer by dicing.
［第２の実施の形態］
（第２の実施の形態の構成）
　図６Ａは、本発明の第２の実施の形態に係る発光素子の斜視図、図６Ｂは、図６ＡのＣ－Ｃ線断面図、図６Ｃは、図６ＡのＤ方向矢視図である。 [Second Embodiment]
(Configuration of Second Embodiment)
6A is a perspective view of a light emitting device according to a second embodiment of the present invention, FIG. 6B is a cross-sectional view taken along the line CC of FIG. 6A, and FIG. 6C is a view taken in the direction of arrow D in FIG.
　第１の実施の形態では、凹部として第２の主面１ｂと第２の側面１ｄとの角部に段差部１５を形成したが、本実施の形態は、凹部として第２の主面１ｂと第２の側面１ｄとの角部に溝１１１を形成したものである。本実施の形態の発光素子１０は、第１の実施の形態と同様に、第１の主面１ａ、第２の主面１ｂ、第１の側面１ｃ及び第２の側面１ｄを有するＧａ2Ｏ3基板１１と、Ｇａ2Ｏ3基板１１の第１の主面１ａに図示しないＡｌＮバッファ層を介して形成されたＧａＮ系半導体層１２と、ＧａＮ系半導体層１２上に形成されたｐ側電極１３と、Ｇａ2Ｏ3基板１１の第２の主面１ｂに形成されたｎ側電極１４とを有する。 In the first embodiment, the stepped portion 15 is formed at the corner between the second main surface 1b and the second side surface 1d as a recess. However, in the present embodiment, the second main surface 1b is used as a recess. A groove 111 is formed at the corner with the second side surface 1d. Emitting element 10 of this embodiment, like the first embodiment, the first main surface 1a, the second main surface 1b, Ga 2 O having a first side surface 1c and a second side 1d 3 substrate 11, GaN-based semiconductor layer 12 formed on first main surface 1 a of Ga 2 O 3 substrate 11 via an AlN buffer layer (not shown), and p-side electrode formed on GaN-based semiconductor layer 12 13 and an n-side electrode 14 formed on the second main surface 1b of the Ga 2 O 3 substrate 11.
　溝１１１は、第２の側面１ｄから５～２０μｍ程度離れて形成されている。なお、溝１１１は、第２の側面１ｄからの距離が５μｍ未満でもよい。 The groove 111 is formed about 5 to 20 μm away from the second side surface 1d. The groove 111 may have a distance from the second side surface 1d of less than 5 μm.
（第２の実施の形態の製造方法）
　第１の実施の形態では、半導体ウエハ１の第２の主面１ｂ上の発光素子１０間に１つの溝１１１を形成したが、本実施の形態では、間隔ｓを設けて２つの溝１１１を形成した点が第１の実施の形態と異なる。 (Manufacturing method of the second embodiment)
In the first embodiment, one groove 111 is formed between the light emitting elements 10 on the second main surface 1b of the semiconductor wafer 1. However, in the present embodiment, the two grooves 111 are formed with an interval s. The formed point is different from the first embodiment.
　本実施の形態は、第１の実施の形態と同様に、Ｇａ2Ｏ3ウエハ基板１１０を準備し、Ｇａ2Ｏ3ウエハ基板１１０に複数の発光素子１０を行方向ｘ及び列方向ｙにマトリクス状に形成する。次に、第１の実施の形態と同様に、環状のダイシングフレーム２の裏面にダイシングテープ３を貼着し、半導体ウエハ１の第１の主面１ａをダイシングテープ３上に貼着する。 In the present embodiment, similarly to the first embodiment, a Ga 2 O 3 wafer substrate 110 is prepared, and a plurality of light emitting elements 10 are matrixed in the row direction x and the column direction y on the Ga 2 O 3 wafer substrate 110. To form. Next, as in the first embodiment, the dicing tape 3 is attached to the back surface of the annular dicing frame 2, and the first main surface 1 a of the semiconductor wafer 1 is attached to the dicing tape 3.
　図７Ａ、図７Ｃ、図７Ｅは、第２の実施の形態に係るダイシング工程を示す要部断面図、図７Ｂは、図７Ａの平面図、図７Ｄは、図７Ｃの平面図、図７Ｆは、図７Ｅの平面図である。 7A, 7C, and 7E are cross-sectional views showing the main part of the dicing process according to the second embodiment, FIG. 7B is a plan view of FIG. 7A, FIG. 7D is a plan view of FIG. 7C, and FIG. FIG. 7E is a plan view of FIG. 7E.
　図７Ａ、図７Ｂに示すように、半導体ウエハ１の第１の主面１ａをダイシングテープ３上に貼着する。幅Ｗ2の第２のダイシングブレード５Ｂを用いてＧａ2Ｏ3ウエハ基板１１０の第２の主面１ｂの分割予定ライン４ｙを中心に間隔ｓを設けて２つの溝１１１を形成する。第２のダイシングブレード５Ｂの幅Ｗ2としては、例えば、１０～３０μｍが好ましく、１５～２５μｍがより好ましい。本実施の形態では、第２のダイシングブレード５Ｂの幅Ｗ2を２０μｍとする。間隔ｓは、例えば、２０～４０μｍが好ましく、２５～３５μｍがより好ましい。本実施の形態では、間隔ｓを３０μｍとする。溝１１１の深さｄは、例えば、２０～５０μｍが好ましく、３０～４０μｍがより好ましい。本実施の形態では、溝１１１の深さｄを３５μｍとする。 As shown in FIGS. 7A and 7B, the first main surface 1 a of the semiconductor wafer 1 is stuck on the dicing tape 3. Forming a Ga 2 O 3 wafer second centered on dividing lines 4y main surface 1b is provided a distance s 2 two grooves 111 of the substrate 110 using a second dicing blade 5B of a width W 2. For example, the width W 2 of the second dicing blade 5B is preferably 10 to 30 μm, and more preferably 15 to 25 μm. In the present embodiment, the width W 2 of the second dicing blade 5B is 20 μm. The interval s is, for example, preferably 20 to 40 μm, and more preferably 25 to 35 μm. In the present embodiment, the interval s is set to 30 μm. The depth d of the groove 111 is preferably 20 to 50 μm, for example, and more preferably 30 to 40 μm. In the present embodiment, the depth d of the groove 111 is 35 μm.
　次に、半導体ウエハ１をダイシングテープ３から剥がして、新たなダイシングテープ３をダイシングフレーム２に貼着し、半導体ウエハ１を上下反転して第２の主面１ｂをその新たなダイシングテープ３上に貼着する。 Next, the semiconductor wafer 1 is peeled off from the dicing tape 3, a new dicing tape 3 is attached to the dicing frame 2, the semiconductor wafer 1 is turned upside down, and the second main surface 1 b is placed on the new dicing tape 3. Adhere to.
　次に、図７Ｃ、図７Ｄに示すように、間隔ｓよりも狭い幅Ｗ2の第２のダイシングブレード５Ｂを用いてＧａ2Ｏ3ウエハ基板１１０の第１の主面１ａ側から分割予定ライン４ｙに沿ってＧａ2Ｏ3ウエハ基板１１０の厚さ全てを切断する。図７Ｃ、図７Ｄ中、符号１１２は、切断面である。切断は、溝１１１間の中心に第２のダイシングブレード５Ｂの中心を一致させて行う。なお、溝用のダイシングブレードと切断用のダイシングブレードで異なるものを用いてもよい。 Next, as shown in FIG. 7C and FIG. 7D, a line to be divided from the first main surface 1a side of the Ga 2 O 3 wafer substrate 110 using the second dicing blade 5B having a width W 2 narrower than the interval s. The entire thickness of the Ga 2 O 3 wafer substrate 110 is cut along 4y. 7C and 7D, reference numeral 112 denotes a cut surface. The cutting is performed by aligning the center of the second dicing blade 5B with the center between the grooves 111. Different dicing blades for grooves and dicing blades for cutting may be used.
　次に、図７Ｅ、図７Ｆに示すように、第２のダイシングブレード５Ｂを用いてＧａ2Ｏ3ウエハ基板１１０の第１の主面１ａ側から分割予定ライン４ｘに沿ってＧａ2Ｏ3ウエハ基板１１０の厚さ全てを切断して素子単位に分割する。図７Ｅ、図７Ｆ中、符号１１２は、切断面である。素子単位の分割によって矩形のＧａ2Ｏ3基板１１が形成され、図６に示す発光素子１０が形成される。図６において、溝１１１、第１の側面１ｃ及び第２の側面１ｄは、第２のダイシングブレード５Ｂによって形成された面である。 Next, FIG. 7E, as shown in FIG. 7F, the 2 Ga 2 using a dicing blade 5B of the O 3 first 1 Ga 2 from the main surface 1a side along the dividing lines 4x of O 3 wafer wafer substrate 110 The entire thickness of the substrate 110 is cut and divided into element units. 7E and 7F, reference numeral 112 denotes a cut surface. A rectangular Ga 2 O 3 substrate 11 is formed by dividing the element unit, and the light emitting element 10 shown in FIG. 6 is formed. In FIG. 6, the groove 111, the first side surface 1c, and the second side surface 1d are surfaces formed by the second dicing blade 5B.
（第２の実施の形態の効果）
　第２の実施の形態によれば、第２のダイシングブレード５Ｂでウエハ基板１１０を切断する場合、ダイシングブレード５Ｂがウエハ基板１１０から抜け出る側の第２の主面１ｂに分割予定ラインを挟んで一対の溝１１１が形成されているため、基板の剥がれが溝１１１から内側に及ばない。また、ＧａＮ系半導体層１２をダイシングしないようにしているので、割れ等を抑制することができる。したがって、Ｇａ2Ｏ3ウエハ基板１１０の劈開による剥がれや割れ等の損傷を抑制して素子単位に分割することができ、基板の劈開による剥がれや割れ等の損傷を抑制した発光素子１０を提供することができる。 (Effect of the second embodiment)
According to the second embodiment, when the wafer substrate 110 is cut by the second dicing blade 5B, a pair of the dicing blade 5B is sandwiched between the second main surface 1b on the side where the dicing blade 5B comes out of the wafer substrate 110, with the planned division line in between Since the groove 111 is formed, peeling of the substrate does not reach the inside from the groove 111. Moreover, since the GaN-based semiconductor layer 12 is not diced, cracks and the like can be suppressed. Therefore, it is possible to divide into elements by suppressing damage such as peeling or cracking due to cleavage of the Ga 2 O 3 wafer substrate 110, and to provide a light emitting element 10 in which damage such as peeling or cracking due to cleavage of the substrate is suppressed. be able to.
［変形例１］
　第１の実施の形態では、溝１１１を形成した後、ダイシングブレードを用いてＧａ2Ｏ3ウエハ基板１１０を切断したが、レーザを用いてＧａ2Ｏ3ウエハ基板１１０を切断してもよい。すなわち、分割予定ライン４ｙ上にダイシングブレードで溝１１１を形成し、分割予定ライン４ｙに沿ってＧａ2Ｏ3ウエハ基板１１０の残部の厚さ全てをレーザで切断する。次に、分割予定ライン４ｘに沿ってＧａ2Ｏ3ウエハ基板１１０の厚さ全てをレーザで切断して素子単位に分割する。 [Modification 1]
In the first embodiment, after forming the groove 111 has been cut Ga 2 O 3 wafer substrate 110 using a dicing blade may be cut Ga 2 O 3 wafer substrate 110 using a laser. That is, a groove 111 is formed on the planned dividing line 4y with a dicing blade, and the entire remaining thickness of the Ga 2 O 3 wafer substrate 110 is cut by the laser along the planned dividing line 4y. Next, the entire thickness of the Ga 2 O 3 wafer substrate 110 is cut by a laser along the planned dividing line 4x and divided into element units.
［変形例２］
　第１の実施の形態では、溝１１１を形成した後、ダイシングブレードを用いてＧａ2Ｏ3ウエハ基板１１０を切断したが、一部のダイシングスクライブを採用してもよい。すなわち、分割予定ライン４ｙ上にダイシングブレードで溝１１１を形成し、分割予定ライン４ｙに沿ってＧａ2Ｏ3ウエハ基板１１０の残部の厚さ全てをダイシングブレードで切断する。次に、分割予定ライン４ｘ上にスクライブにより溝を形成し、応力を加えてブレイキングしＧａ2Ｏ3ウエハ基板１１０を素子単位に分割する。 [Modification 2]
In the first embodiment, after forming the groove 111, the Ga 2 O 3 wafer substrate 110 is cut using a dicing blade, but a part of the dicing scribe may be employed. That is, the groove 111 is formed on the planned division line 4y with a dicing blade, and all the remaining thickness of the Ga 2 O 3 wafer substrate 110 is cut along the planned division line 4y with the dicing blade. Next, a groove is formed by scribing on the planned dividing line 4x, stress is applied and breaking is performed, and the Ga 2 O 3 wafer substrate 110 is divided into element units.
　図８は、第２の主面１ｂ側から見た半導体ウエハ１の要部を示し、図８Ａは、実施例の写真であり、図８Ｂは、比較例の写真である。図８Ａに示す領域Ｃは、第１の実施の形態に対応する実施例によるものであり、幅４０μｍのダイシングブレードでＧａ2Ｏ3ウエハ基板１１０に溝１１１を形成した後、幅２０μｍのダイシングブレードでＧａ2Ｏ3ウエハ基板１１０の残りの厚さを切断した場合を示す。図８Ａから領域Ｃには、ほとんど剥がれが生じていないことが分かる。 FIG. 8 shows a main part of the semiconductor wafer 1 viewed from the second main surface 1b side, FIG. 8A is a photograph of the example, and FIG. 8B is a photograph of the comparative example. A region C shown in FIG. 8A is according to an example corresponding to the first embodiment. After forming the groove 111 in the Ga 2 O 3 wafer substrate 110 with a dicing blade having a width of 40 μm, the dicing blade having a width of 20 μm is formed. A case where the remaining thickness of the Ga 2 O 3 wafer substrate 110 is cut is shown. It can be seen from FIG. 8A that there is almost no peeling in the region C.
　図８Ｂに示す領域Ｄは、比較例によるものであり、溝を形成せずに幅２０μｍのダイシングブレードでＧａ2Ｏ3ウエハ基板１１０の全ての厚さを１回で切断した場合を示す。図８Ｂから領域Ｄには、ダイシングブレードが抜け出た側の主面に剥がれ１１３が生じていることが分かる。 A region D shown in FIG. 8B is according to a comparative example, and shows a case where the entire thickness of the Ga 2 O 3 wafer substrate 110 is cut once with a dicing blade having a width of 20 μm without forming a groove. From FIG. 8B, it can be seen that in the region D, the peeling 113 occurs on the main surface on the side from which the dicing blade comes out.
　なお、本発明は、上記実施の形態に限定されず、発明の要旨を変更しない範囲内で種々に変形可能である。例えば、上記実施の形態で説明した製造方法のステップの入れ替え、追加、削除等は発明の要旨を変更しない範囲で可能である。 In addition, this invention is not limited to the said embodiment, In the range which does not change the summary of invention, it can deform | transform variously. For example, replacement, addition, deletion, etc. of the steps of the manufacturing method described in the above embodiment are possible without changing the gist of the invention.
　また、上記実施の形態では、発光素子として垂直型について説明したが、本発明は水平型にも適用可能である。 In the above embodiment, the vertical type is described as the light emitting element, but the present invention can also be applied to a horizontal type.
　また、上記実施の形態では、半導体素子として発光素子について説明したが、本発明は、レーザ、トランジスタ等の半導体素子にも適用可能である。 In the above embodiment, the light-emitting element is described as a semiconductor element. However, the present invention can also be applied to a semiconductor element such as a laser or a transistor.
　また、上記実施の形態では、分割予定ラインを直交するように設定したが、斜め方向に交差するように設定してもよい。この場合、菱形状の半導体素子が形成される。 In the above embodiment, the division lines are set to be orthogonal, but may be set to intersect in an oblique direction. In this case, a diamond-shaped semiconductor element is formed.
　また、上記実施の形態では、電極面積の小さい側の第２の主面１ｂに溝１１１を形成したが、電極面積の大きい側の第１の主面１ａに溝１１１を形成してもよい。 In the above embodiment, the groove 111 is formed on the second main surface 1b on the side having a smaller electrode area. However, the groove 111 may be formed on the first main surface 1a on the side having a larger electrode area.
　また、上記実施の形態では、劈開面に平行でない分割予定ライン４ｙに沿った切断においては基板に溝を形成してから基板の残りの厚さを切断し、劈開面に平行な分割予定ライン４ｘに沿った切断においては基板に溝を形成せずに基板の厚さ全てを切断したが、分割予定ライン４ｘに沿った切断においても基板に溝を形成してから基板の残りの厚さを切断してよい。 In the above embodiment, in the cutting along the planned division line 4y that is not parallel to the cleavage plane, the remaining thickness of the substrate is cut after forming a groove in the substrate, and the planned division line 4x parallel to the cleavage plane is cut. In the cutting along the substrate, the entire thickness of the substrate was cut without forming a groove in the substrate. However, in the cutting along the planned dividing line 4x, the groove was formed in the substrate and then the remaining thickness of the substrate was cut. You can do it.
　ウエハから素子を切り出す際の位置決めが容易で、基板の劈開による剥がれや割れ等の損傷を抑制することができる半導体素子及びその製造方法を提供する。 Provided are a semiconductor element that can be easily positioned when cutting out an element from a wafer and can suppress damage such as peeling and cracking due to cleavage of the substrate, and a method for manufacturing the same.
１…半導体ウエハ、１ａ…第１の主面、１ｂ…第２の主面、１ｃ…第１の側面、１ｄ…第２の側面、２…ダイシングフレーム、３…ダイシングテープ、４ｘ，４ｙ…分割予定ライン、５Ａ…第１のダイシングブレード、５Ｂ…第２のダイシングブレード、１０…発光素子、１１…Ｇａ2Ｏ3基板、１２…ＧａＮ系半導体層、１３…ｐ側電極、１４…ｎ側電極、１５…段差部、１１０…Ｇａ2Ｏ3ウエハ基板、１１１…溝、１１１ａ，１１１ｂ…面、１１２…切断面、１１３…剥がれ、ｄ…深さ、ｓ…間隔、Ｗ1，Ｗ2…幅、ｘ…行方向、ｙ…列方向 DESCRIPTION OF SYMBOLS 1 ... Semiconductor wafer, 1a ... 1st main surface, 1b ... 2nd main surface, 1c ... 1st side surface, 1d ... 2nd side surface, 2 ... Dicing frame, 3 ... Dicing tape, 4x, 4y ... Divided Planned line, 5A ... first dicing blade, 5B ... second dicing blade, 10 ... light emitting element, 11 ... Ga 2 O 3 substrate, 12 ... GaN-based semiconductor layer, 13 ... p-side electrode, 14 ... n-side electrode , 15, stepped portion, 110, Ga 2 O 3 wafer substrate, 111, groove, 111 a, 111 b, surface, 112, cut surface, 113, peeled, d, depth, s, spacing, W 1 , W 2, width. , X ... row direction, y ... column direction

Claims (10)

  1. 　酸化ガリウムからなる基板であって、互いに反対側に位置する第１及び第２の主面と、前記第１の主面及び劈開面に平行な方向に平行な第１の側面と、前記第１の側面と交差する第２の側面とを有する基板と、
    　前記基板の前記第１の主面に形成された半導体層と、
    　前記基板の前記第１又は第２の主面と前記第２の側面との角部に形成され、前記基板を素子単位に分割する際の剥離を抑制する凹部とを備えた半導体素子。     A substrate made of gallium oxide, the first and second main surfaces located on opposite sides of each other, the first side surface parallel to the first main surface and the direction parallel to the cleavage plane, and the first A substrate having a second side surface intersecting the side surface of
    A semiconductor layer formed on the first main surface of the substrate;
    A semiconductor device comprising: a recess formed at a corner between the first or second main surface and the second side surface of the substrate and suppressing separation when the substrate is divided into device units.
  2. 　前記劈開面は、（１００）面である請求項１に記載の半導体素子。 The semiconductor element according to claim 1, wherein the cleavage plane is a (100) plane.
  3. 　前記凹部は、前記主面と交差する面、及び前記側面と交差する面からなる段差部によって構成された請求項１又は２に記載の半導体素子。 3. The semiconductor element according to claim 1, wherein the concave portion is constituted by a step portion including a surface intersecting with the main surface and a surface intersecting with the side surface.
  4. 　前記凹部は、溝によって構成された請求項１又は２に記載の半導体素子。 3. The semiconductor element according to claim 1, wherein the recess is formed by a groove.
  5. 　前記半導体層は、前記基板の前記第１の主面の一部に形成された請求項１又は２に記載の半導体素子。 The semiconductor element according to claim 1, wherein the semiconductor layer is formed on a part of the first main surface of the substrate.
  6. 　前記第１及び第２の主面は、（１０１）又は（－２０１）面である請求項１又は２に記載の半導体素子。 3. The semiconductor element according to claim 1, wherein the first and second main surfaces are (101) or (−201) surfaces.
  7. 　酸化ガリウムからなる基板であって、互いに反対側に位置する第１及び第２の主面を有する基板を準備し、
    　前記基板に複数の半導体素子を前記第１の主面及び前記基板の劈開面に平行な第１の方向と、前記第１の方向に交差する第２の方向に沿ってマトリクス状に形成し、
    　前記基板の前記半導体素子間であって前記第１及び第２の主面のうち一方の主面に前記第２の方向に沿う複数の凹部を形成し、
    　前記第１及び第２の主面のうち他方の主面から前記複数の凹部に沿って前記基板を切断し、
    　前記第１の方向に沿って前記基板を切断して前記複数の半導体素子を素子単位に分割する半導体素子の製造方法。     Preparing a substrate made of gallium oxide and having first and second main surfaces located on opposite sides of each other;
    Forming a plurality of semiconductor elements on the substrate in a matrix along a first direction parallel to the first main surface and the cleavage plane of the substrate, and a second direction intersecting the first direction;
    Forming a plurality of recesses along the second direction on one main surface of the first and second main surfaces between the semiconductor elements of the substrate;
    Cutting the substrate along the plurality of recesses from the other main surface of the first and second main surfaces;
    A method for manufacturing a semiconductor element, wherein the substrate is cut along the first direction to divide the plurality of semiconductor elements into element units.
  8. 　前記劈開面は、（１００）面である請求項７に記載の半導体素子の製造方法。 The method of manufacturing a semiconductor element according to claim 7, wherein the cleavage plane is a (100) plane.
  9. 　前記複数の凹部の形成は、第１の幅を有する第１のダイシングブレードを用いて複数の溝を形成し、
    　前記複数の凹部に沿う前記基板の切断は、前記第１の幅よりも小さい第２の幅を有する第２のダイシングブレードを用いて前記溝の箇所で前記基板を切断する請求項７又は８に記載の半導体素子の製造方法。     The plurality of recesses are formed by forming a plurality of grooves using a first dicing blade having a first width,
    9. The cutting of the substrate along the plurality of recesses is performed by cutting the substrate at the groove using a second dicing blade having a second width smaller than the first width. The manufacturing method of the semiconductor element of description.
  10. 　前記複数の凹部の形成は、それぞれの前記半導体素子間に２本の溝を形成し、
    　前記複数の凹部に沿う前記基板の切断は、前記２本の溝間で前記基板を切断する請求項７に記載の半導体素子の製造方法。     The plurality of recesses are formed by forming two grooves between the semiconductor elements,
    The method for manufacturing a semiconductor device according to claim 7, wherein the cutting of the substrate along the plurality of recesses is performed by cutting the substrate between the two grooves.
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