JP5834952B2 - Manufacturing method of nitride semiconductor substrate - Google Patents

Description

  The present invention relates to a method for manufacturing a nitride semiconductor substrate.

In nitride semiconductors used as light emitting diodes (LEDs) and laser diodes (LDs), different substrates made of a material different from nitride semiconductors, such as sapphire and silicon carbide, are used as growth substrates for semiconductor layers. This is because it is difficult to obtain a bulk single crystal of a nitride semiconductor.
However, dislocation defects occur in the nitride semiconductor layer grown on the different substrate due to the difference in lattice constant between them and the coefficient of thermal expansion.
Therefore, various methods for obtaining a nitride semiconductor substrate (bulk single crystal layer) with few dislocation defects have been studied.

For example, a method is known in which a nitride semiconductor layer is formed on a heterogeneous substrate using lateral growth, and then the heterogeneous substrate is removed to obtain a nitride semiconductor substrate. By using this nitride semiconductor substrate as a growth substrate for the nitride semiconductor layer, a nitride semiconductor layer with fewer dislocation defects can be obtained as compared with the conventional one.
However, a nitride semiconductor layer grown on different substrates having different lattice constants and thermal expansion coefficients has a problem that stress is applied when the temperature is lowered after the growth and cracks are likely to occur in the nitride semiconductor layer. is there.

For this reason, a method for removing the heterogeneous substrate using the stress has been studied.
For example, the seed layer at the time of growth is partially left by erosion treatment to form an erosion debris, and the internal stress and external stress after growth are ruptured so as to act on the erosion debris intensively. A method for removing the substrate has been proposed (for example, Patent Documents 1 to 3).

JP 2003-163370 A JP 2002-241192 A JP 2010-163288 A

However, the methods described in Patent Document 1 and Patent Document 2 are arranged on a columnar protrusion formed on the surface of a different substrate because the height is relatively low at about 1 μm or less. The lateral growth from the seed layer is difficult, and at the same time crystals grow from the bottom. Therefore, a large number of crystal defects exist in the epitaxial layer grown from the bottom, and the obtained nitride semiconductor substrate does not actually reduce the crystal defects.
Further, although the method described in Patent Document 3 has a deep stripe depth of 25 μm, it corresponds to the stripe width and its period, the width of the region that can be lowered by lateral growth, and crystal defects during epitaxial growth. As a result, the area where crystal defects are generated still accounts for a considerable proportion of the total area formed by the epitaxial layer, because the latter is wide. As a result, crystal defects in the obtained nitride semiconductor substrate have not been reduced.

The present invention is shown below.
[1] A first step of forming a plurality of recesses on the surface of a different substrate made of a material different from that of a nitride semiconductor,
From the nitride semiconductor layer, a second step of growing a nitride semiconductor layer by lateral growth between the adjacent recesses and forming a gap between the bottom surface of the recess and the nitride semiconductor layer, and A method for manufacturing a nitride semiconductor substrate, comprising a third step of removing a heterogeneous substrate.
[2] The nitriding according to [1], wherein the heterogeneous substrate is a crystal substrate, and a bottom surface or a side surface of the concave portion is a surface in which any one of a C surface, an R surface, an A surface, and an M surface is inclined. Method for manufacturing a semiconductor substrate.
[3] The method for manufacturing a nitride semiconductor substrate according to [1] or [2], wherein the heterogeneous substrate is a sapphire substrate, and a bottom surface or a side surface of the recess is a surface having an inclined M surface.
[4] The method for manufacturing a nitride semiconductor substrate according to any one of [1] to [3], wherein an area of an upper surface between the recesses is 50% or less of an area of the entire surface of the different substrate.
[5] The method for manufacturing a nitride semiconductor substrate according to any one of [1] to [4], wherein the depth of the recess is in a range of 2 to 50 μm.
[6] The method for manufacturing a nitride semiconductor substrate according to any one of [1] to [5], wherein the plurality of recesses are formed as two or more types of recesses similar to each other in a planar shape.
[7] The method for manufacturing a nitride semiconductor substrate according to any one of [1] to [6], wherein the plurality of recesses are formed by being surrounded by a plurality of frames having a substantially equilateral triangular plane shape.
[8] The method for manufacturing a nitride semiconductor substrate according to [7], wherein the plurality of frames are regularly arranged so that only the apexes are shared with an adjacent frame.
[9] The plurality of frame bodies are arranged so that three vertices of the plurality of substantially equilateral triangles are respectively directed in the same direction from the center of the equilateral triangle, and adjacent substantially equilateral triangle frames are arranged only by the vertices. The method for producing a nitride semiconductor substrate according to [7], wherein the nitride semiconductor substrate is configured to be brought into contact with each other.

  According to the method for manufacturing a nitride semiconductor substrate of the present invention, a crystal defect can be reduced, and a nitride semiconductor layer can be naturally peeled from a heterogeneous substrate. Can be manufactured at cost.

It is a top view which shows the recessed part pattern of the principal part formed with the manufacturing method of the nitride semiconductor substrate of this invention. It is a top view which shows the whole arrangement | sequence of the recessed part pattern of FIG. It is a schematic sectional process drawing of the principal part for demonstrating the manufacturing method of the nitride semiconductor substrate of this invention. It is a schematic sectional process drawing of the principal part for demonstrating the manufacturing method of the nitride semiconductor substrate of this invention.

(First step)
In the nitride semiconductor substrate manufacturing method of the present invention, first, a plurality of recesses are formed on the surface of a different substrate made of a material different from that of the nitride semiconductor.
The substrate used here is not particularly limited as long as it is made of a material different from the nitride semiconductor and can grow the nitride semiconductor. For example, a crystal substrate is preferable. Specifically, sapphire, silicon, SiC, GaAs, ZnS, ZnO, or the like having any one of the C-plane, R-plane, A-plane, and M-plane as the main surface (surface that forms the recesses) can be given. Of these, a sapphire substrate is preferable. Note that an off angle of 10 ° or less (for example, 0.1 ° to 1 °) may be formed on the substrate.
For example, when the surface of the intended nitride semiconductor layer is (001) plane GaN, the main surface of the sapphire substrate used as the heterogeneous substrate preferably has a (0001) plane. Further, according to the intended crystal plane of the surface of the nitride semiconductor layer, it is possible to select a heterogeneous substrate and a crystal plane of the main surface of the heterogeneous substrate that are suitable for it. For example, when a sapphire substrate is used, the surface on which the concave portion is formed may be any one of (0001) plane, (11-20) plane, (1-100) plane, and the like.

Examples of a method for forming a plurality of recesses on the surface of a different substrate include a method using a photoresist and an etching process known in the art.
Specifically, as shown in FIG. 3A, an insulating film 2 such as silicon oxide (for example, about 0.1 to 5 μm, preferably about 0.3 to 2 μm) is formed on a heterogeneous substrate 1 by a CVD method or the like. ), A resist 3 is applied thereon, and a pattern having a predetermined shape is exposed on the resist 3. Thereafter, development processing is performed to form a resist 3 in a predetermined pattern shape (see FIG. 3B). Using this resist pattern, the insulating film 2 is patterned by subjecting it to an etching process such as wet etching using buffered hydrofluoric acid or the like or dry etching by RIE (see FIG. 3C). Further, a plurality of recesses can be formed by etching the heterogeneous substrate 1 using the patterned insulating film 2 as a mask (see FIG. 3D).

  Although the depth of a recessed part is not specifically limited, For example, about 2-50 micrometers is suitable, About 3-50 micrometers is preferable, About 9-48 micrometers is more preferable, About 17-25 micrometers is further more preferable. The deeper the recess, the more the crystal defects can be suppressed, the crystal growth from the bottom of the recess is more effectively suppressed, the contact between the heterogeneous substrate and the nitride semiconductor layer is less, and the heterogeneous substrate and the nitride are nitrided. Spontaneous peeling described later from the physical semiconductor layer can be promoted.

The plurality of recesses are preferably formed as two or more types of recesses having a similar shape in plan view (plan view). Examples of similar shapes here include polygons such as triangles, quadrangles, hexagons, and the like, and regular triangles are particularly preferable.
The plurality of recesses are preferably arranged regularly. Arranging regularly includes arranging a plurality of concave portions periodically in the vertical, horizontal, oblique directions, etc., and arranging them adjacently so as to contact each other.
In any case where the plurality of recesses are arranged periodically or adjacent to each other, for example, it is preferable that the plurality of recesses be surrounded by a plurality of frames having a substantially regular triangle, for example, a polygonal shape. The frame here is preferably a frame having a polygon, for example, an approximately equilateral triangular inner periphery and outer periphery.
In the case where the plurality of recesses are formed by the frame body, it is particularly preferable that the plurality of recesses are arranged adjacent to each other. Here, “adjacent” may be arranged such that one side of the frame is in contact with each other, or may be arranged so that the apex of the frame is in contact.

  When a plurality of substantially equilateral triangular frames are arranged, it is preferable that the three vertices of the equilateral triangular frames that are in contact with each other come in contact at one point and the sides do not come into contact with each other. In this respect, it can be distinguished from the concave shape formed by arranging the stripe-shaped convex portions so as to intersect at a predetermined angle (for example, 60 °). In this case, in three equilateral triangles in which the vertexes of the frame body come into contact with each other at one point, it is preferable that each vertex of the frame body is arranged in the same direction from the center of the equilateral triangle surrounded by the frame body. . In other words, it is preferable that three equilateral triangles are arranged with a period of 60 ° with one vertex in common. Furthermore, in other words, it is preferable that the triangular frame body has a substantially uniform thickness in the most part, with the apex part having a slightly thicker or less wide frame body. As a result, the contact area between the nitride semiconductor layer, which will be described later as a growth nucleus, and the heterogeneous substrate can be minimized. As a result, when facet growth is performed in the growth of a nitride semiconductor layer described later, dislocations can be prevented from propagating to the upper nitride semiconductor layer, and crystal defects can be reduced. In addition, natural peeling described later can be further promoted, and the manufacture of the nitride semiconductor substrate can be simplified.

Specifically, as shown in FIGS. 1 and 2, one unit of the plurality of recesses is formed by a plurality of substantially equilateral triangular frames 11 in a planar shape, and only the apexes P thereof are adjacent to each other. It arrange | positions and is comprised so that it may share with the frame 11 to do. That is, three concave portions A, B, and C are arranged by three equilateral triangle frames, respectively, and the apexes of the three frames are in contact at one point (vertex a2 of frame A, frame B Vertex b3, vertex c1) of frame C, and sides of each frame are not in contact.
Then, each of the concave portions A, B, C of the equilateral triangle surrounded by the frame body has the vertexes of the frame body in the same direction from their centers, that is, the vertices a1, b1, c1 are in the same direction, the vertices a2, b2, c2 is arranged in the same direction and vertices a3, b3, and c3 are arranged in the same direction, and each side of a plurality of equilateral triangles (in particular, the outer edges are arranged in a straight line).

When arranging equilateral triangular frames of the same size as described above, the side of the frame is sandwiched between the recesses A, B, C formed by being surrounded by one frame, and between the recesses A-B. Between the recesses B-C and between the recesses C-A, there are equilateral triangular recesses slightly larger than these recesses.
Accordingly, in such an arrangement of the plurality of recesses, a plurality of two types of recesses having similar shapes are regularly arranged. That is, as represented by W and Q in FIG. 2, all have the same or similar shapes. For example, the size of the recesses similar to each other can be adjusted in consideration of the thickness of the frame. For example, the recesses that are similar to each other are large between 150% and 50%. It is preferable to vary the thickness (area).
The frame body is preferably formed in a convex shape, and its side surface may be vertical (in this case, a surface other than the C surface is preferable), and a parabola that is concave on the inside or convex on the outside. For example, depending on the type of the different substrate, it is preferable that the C surface, the R surface, the A surface, or the M surface (particularly, the M surface) be inclined. That is, it is preferable that a surface different from the C surface, the R surface, the A surface, or the M surface is exposed. Moreover, when making it concave shape inside, it is more preferable that the bottom face is the surface which inclined one of the surfaces mentioned above. By providing such an inclined surface, GaN growth on the single crystal C surface can be made difficult. That is, providing the inclined surface is considered to be one factor for facilitating the formation of the gap.
Moreover, it is preferable that the convex part which comprises a frame is arrange | positioned along the crystal plane of a sapphire, when the dissimilar board | substrate is a sapphire substrate at least one part side surface. In particular, when the frame is formed in an equilateral triangle shape, one side surface on one side is preferably an M plane.

  In the present application, “contact only at the apex” means that the contact area strictly means “point”, but it is allowed to have a slight deviation in consideration of the pattern formation method of the recess, its accuracy, etc. To do. This deviation is, for example, a substantially circular area having a diameter of 1/2 or less of the thickness of a frame, which will be described later, or a polygonal area having one side, and 1/3 or less, 1/4 or less, 1/5 or less. , 1/8 or less, 1/10 or less can be a region having a diameter (or one side). In other words, it is preferable that the center lines of adjacent frames (frames themselves) do not intersect.

  The “triangle” is preferably a regular triangle or a substantially regular triangle, and the length of one side of the triangle is suitably about 30 to 150 μm, and more preferably about 50 to 120 μm. Moreover, when it has an inner periphery and an outer periphery as a frame, the range which the length of one side in an outer periphery mentioned above is suitable. The thickness of the triangular frame (t in FIG. 1) is 10 μm or less, preferably about 1 to 5 μm. Further, the thickness of the frame of the apex portion ((BA) / 2 in FIG. 1) is 10 μm or less, preferably about 1.5 to 6 μm. Thereby, the growth time of the nitride semiconductor layer described later can be shortened, and the density of dislocation defects in the obtained nitride semiconductor substrate can be minimized. In addition, it is possible to minimize the warpage of the substrate in the free standing state. In other words, as will be described later, it is possible to minimize warping after stacking semiconductor layers constituting elements such as LEDs and LDs.

  As described above, the plurality of recesses are preferably arranged regularly and uniformly. Thereby, the high density part of a dislocation defect can be made into a regular and the minimum area.

  The area of the upper surface between the recesses is preferably 50% or less, more preferably 30% or less, still more preferably 20% or less, and particularly preferably 5% or less of the total surface area of the different substrate. % Or less is more preferable. By setting the area of such an upper surface, it is possible to surely form a gap between the nitride semiconductor to be grown on the bottom surface and the bottom surface of the recess, and it is possible to further promote natural peeling described later by the cavity. It becomes.

(Second step)
Next, a nitride semiconductor layer is grown by lateral growth between adjacent recesses.
Nitride semiconductor layer means a layer made of a nitride semiconductor represented by the formula _{In x Al y Ga 1-xy} N (0 ≦ x, 0 ≦ y, 0 ≦ x + y ≦ 1). In addition to this, the composition may have a part of B as a group III element or a part of N as a group V element substituted with P or As. The nitride semiconductor layer is preferably grown as i-type. For example, as an n-type impurity, a group IV element such as Si, Ge, Sn, S, O, Ti, Zr, Cd, or a group VI element is used. Any one or more of the above may be contained.
Here, the nitride semiconductor layer may be any of a single crystal, a polycrystal, a mixed crystal state thereof, an amorphous layer, etc., but the growth proceeds from a portion in contact with the upper surface between the recesses, and from the amorphous state. A single crystal layer is preferable, and a single crystal structure layer is particularly preferable on the surface of the nitride semiconductor layer opposite to the heterogeneous substrate side.
Therefore, the nitride semiconductor layer grown between the recesses is not only laterally grown on the upper surface between the recesses, but also the lateral layer is formed through, for example, a so-called underlayer or buffer layer, intermediate layer, facet layer, etc. It suffices to grow between the recesses and above the upper surface between the recesses.
Here, “lateral growth” or “lateral layer” means a nitride semiconductor with an inclination angle within ± several tens of degrees (preferably within ± several degrees, more preferably approximately 0 °) with respect to the surface of a different substrate. It means that a layer grows or a grown layer, and may include growth of a buffer layer, an intermediate layer, a facet layer, etc., which will be described later. The facet layer means a layer in which a nitride semiconductor layer is grown at an inclination angle of 45 ± several degrees (preferably about 45 °) with respect to the surface of a different substrate.

The growth method of the nitride semiconductor is not particularly limited, but for example, MOVPE (metal organic chemical vapor deposition), MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor deposition), MBE (molecular beam epitaxy). Any method known as a method for growing a nitride semiconductor can be used. Of these, MOCVD or HVPE is preferable in consideration of the fact that a nitride semiconductor can be grown with good crystallinity, and HVPE is particularly preferable in the later stage of growth.
In the present invention, the nitride semiconductor crystal layer formed between a plurality of adjacent recesses on the surface of the different substrate may be a single layer, but is preferably formed as a laminated layer. For example, it is preferable that the stacked layers have the same or different compositions, such as the buffer layer, the intermediate layer, the facet layer, the lateral layer, and the like as described above.

  For example, first, as shown in FIG. 4A, a nitride semiconductor layer 12a is used as a base layer on a heterogeneous substrate having a plurality of recesses, particularly on the upper surface between the recesses arranged as the frame 11. A buffer layer, an intermediate layer, or the like may be formed. Examples of such a buffer layer include what is called a low-temperature buffer layer. For example, such a layer supplies a gas (for example, ammonia gas, TMG gas, etc.) containing an element constituting the nitride semiconductor layer to be obtained at a predetermined flow rate at a low temperature of about 450 to 600 ° C. A method is mentioned. The film thickness of the underlayer is 0.0 several μm to 0.00. It is preferably about several μm, more preferably about 0.1 ± 0.0 several μm.

  A nitride semiconductor layer may be further formed on the underlayer as an intermediate layer or the like (not shown in FIG. 4). Specifically, the nitride semiconductor layer supplies a gas (for example, ammonia gas, TMG gas, etc.) containing an element constituting the nitride semiconductor layer at a predetermined flow rate at a high temperature of about 950 to 1200 ° C. A method is mentioned. This nitride semiconductor layer can be formed with a film thickness of about several μm, for example. Thereby, the facet growth of the nitride semiconductor layer described later can be performed easily and reliably.

  When the heterogeneous substrate having a plurality of recesses on the surface described above is used, the underlayer, intermediate layer, etc. can be grown predominantly on the top surface between the recesses, and the nitride semiconductor is substantially formed on the bottom surface of the recesses. The layer does not grow (see FIG. 4A). This can be realized by forming a recess as described above.

Next, as shown in FIG. 4B, a so-called facet growth layer made of the nitride semiconductor layer 12b is formed on the nitride semiconductor layer 12a made of the underlayer or the like.
Examples of the growth method of the facet growth layer include the same method as the growth method of the nitride semiconductor layer described above.
In this facet growth, the nitride semiconductor layer grows with the upper surface of the underlying layer and / or the intermediate layer formed only on the upper surface between the recesses as the growth nucleus, so it grows by facet growth with the center of this upper surface as the apex. Can be made. Here, facet growth means growing in a direction different from the original or original growth direction of the nitride semiconductor layer (for example, the direction perpendicular to the upper surface of the heterogeneous substrate before forming the recesses). For example, if the upper surface of the concave portion of the heterogeneous substrate is a C plane, the nitride semiconductor layer is grown on a plane different from the C plane, preferably the (11-22) plane.
Such growth can be realized by controlling the flow rate of the source gas, the growth temperature, and the like.

The film thickness of the nitride semiconductor layer 12b to be facet grown is, for example, preferably about several μm to several tens of μm, more preferably about 5 μm to 30 μm, and further preferably about 10 ± several μm.
By continuing the growth of the facet growth layer by the nitride semiconductor layer 12b, the nitride semiconductor moves from the facet direction to the lateral direction and laterally grows, and the facet growth surface gradually changes to a flat surface. At this time, as shown in FIG. 4C, the growth of the nitride semiconductor layer is controlled in the recess formed in the different substrate, and the nitride semiconductor layer is not embedded in the recess.

  As a result, in this nitride semiconductor layer, a junction surface is formed at the apex of the facet growth (that is, the center point of the recess), and the progress of dislocation can be effectively prevented by the adhesion of the junction surface. Even if threading dislocations still exist or threading dislocations newly occur, threading dislocations can be advanced only immediately above the joined point. In this way, the nitride semiconductor layer can be laterally grown on the facet growth layer in a flat manner and horizontally on the surface of the heterogeneous substrate before the recess formation (for example, the entire surface is a c-plane). Thus, a cavity can be formed between the concave portion of the different substrate and the nitride semiconductor layer. Therefore, the nitride semiconductor layer stacked above the recesses of the different substrate substantially contacts and supports the nitride semiconductor layer only at the upper surface between the recesses.

Further, in the above-described series of growth of the nitride semiconductor layer, even if the nitride semiconductor layer on the upper surface between the recesses is not yet excellent in crystallinity or is in a crystal form, crystal defects are not observed. A nitride semiconductor layer having a better crystallinity due to the lateral growth, in which the crystal structure is gradually matched in the process of increasing the thickness of the nitride semiconductors 12b and 12c itself. 12c can be obtained.
The nitride semiconductor layer 12c by such lateral growth is preferably grown to a thickness of about 20 to 100 μm, about 30 to 70 μm, or about 30 to 50 μm, for example.
Note that, as described above, the thickness of the nitride semiconductor layer by lateral growth is not limited to a layer in which crystal growth strictly occurs at approximately 0 ° with respect to the surface of a different substrate, but also so-called buffer layers, intermediate layers, facet layers, and lateral layers. The thickness including etc. is meant.

Thereafter, the nitride semiconductor layer 12d is further grown in order to further stabilize the crystallinity of the nitride semiconductor layer 12c by the lateral growth described above and to ensure the strength as the nitride semiconductor substrate.
Examples of the method for growing the nitride semiconductor layer include the same method as the method for growing the nitride semiconductor layer described above.
As described above, even if threading dislocations exist, this nitride semiconductor layer can be concentrated in a predetermined region, and as a whole, a layer having substantially very few threading dislocations can be obtained. In the region where threading dislocations are extremely small here, for example, the dislocation density can be suppressed to about 1 × 10 ⁻⁷ pieces / cm ² or less.
The nitride semiconductor layer is preferably grown with a thickness of about 500 to 2000 μm and about 500 to 1000 μm.

  In this way, by growing the nitride semiconductor layer on the upper surface between the recesses of the heterogeneous substrate having a plurality of recesses, the gap 13 is formed between the bottom surface of the recesses and the nitride semiconductor layer, and finally the crystal It is possible to form a nitride semiconductor layer having good properties, that is, a substantially single crystal and a low dislocation density.

(Third step)
The nitride semiconductor layer obtained as described above is substantially in contact with only the upper surface between the recesses, and therefore, by applying a small external stress, the nitride semiconductor layer can be easily connected to a different substrate. Can be peeled off, and the dissimilar substrate can be removed.
The peeling / removal method in this case can be peeled off by utilizing the difference in coefficient of thermal expansion or the like by allowing the sapphire heterogeneous substrate and the nitride semiconductor layer to cool in a crystal growth apparatus, for example. . In other words, when a nitride semiconductor crystal is grown at a high temperature, the crystal structure such as the lattice constant is considered to be in a substantially similar state. It is considered that the lattice constant and the like with the physical semiconductor layer return to the original state at room temperature, and the difference is remarkably expressed and separated. In particular, by forming other recesses as described above and effectively arranging voids in the portions, it is possible to reduce the contact area between the heterogeneous substrate and the nitride semiconductor crystal, and to further promote natural peeling. it can.
Thereby, a free-standing nitride semiconductor substrate can be obtained.
However, instead of the stress load described above or together with the stress load, a method known in the art may be used for removing the dissimilar substrate. For example, polishing, etching, laser irradiation, etc. can be used.

  Thereafter, the obtained nitride semiconductor layer is arbitrarily removed by removing a part of the above-described buffer layer, intermediate layer, facet growth layer, lateral growth layer, and the nitride semiconductor layer formed on the lateral growth layer. Also good. As this removal method, for example, any one of polishing, etching, laser irradiation, and the like may be used.

  The thus obtained free-standing nitride semiconductor substrate (that is, a substrate from which a different type of substrate is removed) is usually warped (convex to the front). The warp in this case is suitably adjusted, for example, to about 300 μm or less (the difference in height of the warped substrate) by appropriately adjusting the film forming method, thickness, and the like of each nitride semiconductor layer described above. Thereby, when the nitride semiconductor layer which comprises LED, LD, etc. is laminated | stacked on this nitride semiconductor substrate, the curvature of nitride semiconductor layer itself can be offset or relieve | moderated by this board | substrate.

The best mode for carrying out the present invention will be described below with reference to the drawings. However, the form shown below is the illustration for materializing the technical idea of this invention, Comprising: It is not limited to the following.
Example 1
(First step)
First, a heterogeneous substrate 1 made of sapphire having a C surface as a main surface and an orientation flat surface as an A surface was prepared.
Next, as shown in FIG. 3A, a SiO ₂ film 2 having a thickness of 0.7 μm was formed on the sapphire heterogeneous substrate 1 using a CVD apparatus, and a resist 3 was applied thereon. The resist 3 was exposed to a mask pattern by a stepper. Thereafter, the resist 3 was developed to form a mask pattern with the resist 3 as shown in FIG.

Subsequently, as shown in FIG. 2C, the SiO ₂ film 2 was etched by RIE using this mask pattern to form a pattern. The mask pattern by resist is removed, and the sapphire substrate 1 is wet-etched at 300 ° C. for about 85 minutes (sapphire etching) using a mixed acid (phosphoric acid and sulfuric acid = 7: 3) using the SiO ₂ film 2 as a mask. The etching ratio was about 20 μm.
By removing the remaining SiO ₂ film 2, a pattern 10 having recesses W and Q was formed on the sapphire substrate 1 as shown in FIG.

As shown in FIG. 2, the pattern 10 has two concave portions Q and W that are similar in plan view and are surrounded by an equilateral triangular frame 11 to form an equilateral triangle. Here, the length B of one side of the outer periphery of the equilateral triangle was about 60 μm, the length A of one side of the inner circumference was about 50 μm, and the width t of the frame was about 3 μm. The height of the frame 11 was 20 μm.
As shown in FIG. 1, all equilateral triangular frames 11 have three vertices (for example, vertices a1 to a3 in the recess A, vertices b1 to b3 in the recess B, and vertices c1 to c3 in the recess C), They are arranged in the same direction from the center of the equilateral triangle.
In the pattern 10, the three equilateral triangular frames 11 adjacent to each other are in point contact only at the apex P, and are regularly and uniformly arranged in such a form.

(Second step)
A nitride semiconductor layer was grown on the sapphire heterogeneous substrate 1 having a plurality of recesses.
First, using a MOCVD apparatus on this sapphire heterogeneous substrate 1 at 500 ° C., supplying hydrogen as a carrier gas, source gas as NH ₃ at 8 slm, and TMG (trimethyl gallium) at 30 sccm at 760 torr. A nitride semiconductor layer 12a serving as a base (buffer) layer of GaN having a thickness of about 0.1 μm was grown (see FIG. 4A).
Next, in the same manner as described above, while supplying NH ₃ at 5.2 slm and TMG at 30 sccm at 950 ° C., the nitride semiconductor layer 12b made of GaN as a facet growth layer is about 10 μm at 760 torr. The film was grown with a film thickness (see FIG. 4B).

Subsequently, the obtained sapphire heterogeneous substrate 1 was transferred to an HVPE apparatus, and GaN was grown as a lateral growth layer 12c with a thickness of about 40 μm at 1020 ° C. while supplying HCl at 1 sccm and NH ₃ at 2 slm. . At this time, the progress of threading dislocation is prevented at the apex of the facet plane.
Subsequently, a nitride semiconductor layer 12d made of GaN having a thickness of about 830 μm was grown at 1012 ° C. while supplying HCl at 160 sccm and NH ₃ at 2 slm (see FIG. 4C).

  As a result, the facet surface grows while the surface of the nitride semiconductor layer gradually changes to the c-plane, and finally a gap is formed between the junction portion, that is, the bottom surface of the recess of the sapphire heterogeneous substrate and the nitride semiconductor layer. While forming 13, a flat surface was obtained.

  Thereafter, the sapphire heterogeneous substrate is removed by natural peeling caused by cooling in the apparatus, and the back surface side (the side in contact with the sapphire heterogeneous substrate) is polished to a nitride semiconductor having a thickness of about 370 μm. A substrate was obtained.

About the obtained nitride semiconductor substrate, while measuring the dislocation density and the absorption coefficient with respect to the light of a specific wavelength, the CL (cathode luminescence) image was image | photographed.
Here, the absorption coefficient can be calculated from the absorption and the thickness of the sample obtained by measuring the transmittance and the reflectance with a spectrophotometer.

  As can be seen from Table 1, in Example 1, since the joining by facet growth can be performed isotropically from three directions, the joining can be concentrated at the center point of the triangular recess. Therefore, even if threading dislocations exist, the dislocations themselves concentrate on the center point of the triangular recess, and the dislocation can be sufficiently reduced. Moreover, the warp (convex to the front) after peeling off the substrate could be suppressed as much as possible.

  Thus, when a nitride semiconductor layer (for example, about 30 to 1000 μm, preferably about 100 to 900 μm) is stacked on the obtained nitride semiconductor substrate to form a semiconductor element such as an LED or an LD, Since the warpage of the semiconductor layer itself can be offset or alleviated by this substrate, the shape stability of the nitride semiconductor substrate itself is improved, or the handling and stability of the semiconductor element formed on the substrate are improved, The yield of processes such as chip formation of semiconductor elements can be improved.

Example 2
The thickness of the SiO ₂ film shown in FIG. 3C is about 0.3 μm, and the etching depth of the sapphire heterogeneous substrate 1 shown in FIG. 3D is about 4 μm. A nitride semiconductor substrate was manufactured.
As a result, substantially the same effect as in the first embodiment can be obtained.

Example 3
A nitride semiconductor substrate was manufactured in the same manner as in Example 2 except that the patterning of the SiO ₂ film shown in FIG.
As a result, substantially the same effect as in the first embodiment can be obtained.

Example 4
A nitride semiconductor substrate was manufactured in the same manner as in Example 1 except that the nitride semiconductor layer 12a and the nitride semiconductor layer 12b shown in FIGS. 4A and 4B were both formed by the HVPE method. .
As a result, substantially the same effect as in the first embodiment can be obtained.

  The method for manufacturing a nitride semiconductor substrate of the present invention can be applied to the manufacture of all semiconductor devices using a nitride semiconductor.

DESCRIPTION OF SYMBOLS 1 Dissimilar board | substrate 10 Pattern 11 Frame 12a-12d Nitride semiconductor layer 13 Space | gap

Claims (8)

A first step of forming a plurality of recesses on a heterogeneous substrate surface made of a material different from a nitride semiconductor as two or more types of recesses similar to each other in a planar shape ;
From the nitride semiconductor layer, a second step of growing a nitride semiconductor layer by lateral growth between the adjacent recesses and forming a gap between the bottom surface of the recess and the nitride semiconductor layer, and A method for manufacturing a nitride semiconductor substrate, comprising a third step of removing a heterogeneous substrate. A first step of forming a plurality of recesses on a surface of a different substrate made of a material different from that of a nitride semiconductor by surrounding the plurality of recesses with a plurality of frames having a substantially equilateral triangle in plan view;
  A second step of growing a nitride semiconductor layer by lateral growth between the adjacent recesses, and forming a gap between the bottom surface of the recess and the nitride semiconductor layer;
  A method for producing a nitride semiconductor substrate, comprising a third step of removing the heterogeneous substrate from the nitride semiconductor layer. 3. The method for manufacturing a nitride semiconductor substrate according to claim 2, wherein the plurality of frames are regularly arranged so as to share only the apexes with the adjacent frames. 4. The plurality of frames are arranged such that three vertices of the plurality of substantially equilateral triangles are respectively directed in the same direction from the center of the equilateral triangle, and adjacent substantially equilateral triangle frames are brought into contact with only the vertices. The method for manufacturing a nitride semiconductor substrate according to claim 2, which is configured. The dissimilar substrate is a crystal substrate, the bottom surface or side surface of the recess, C plane, any one of claims 1-4 to R-plane, A plane and a plane tilted either side of the M face The manufacturing method of the nitride semiconductor substrate as described in any one of Claims 1-3. The heterologous substrate and sapphire substrate, a bottom surface or side surface of the recess, the nitride semiconductor substrate manufacturing method according to any one of claims 1-5 to a surface that is tilted M plane. The area of the upper surface between the recesses, the nitride semiconductor substrate manufacturing method according to any one of claims 1 to 6 to 50% or less of the area of the total surface of said foreign substrate. Method for manufacturing a nitride semiconductor substrate according to any one of claims 1 to 7 for the depth of the recess, in the range of 2 to 50 [mu] m.