WO2013054396A1

WO2013054396A1 - Method for manufacturing photovoltaic power apparatus, and photovoltaic power apparatus

Info

Publication number: WO2013054396A1
Application number: PCT/JP2011/073342
Authority: WO
Inventors: 剛彦佐藤; 秀一檜座; 雅酒井; 成人太田; 松野　繁
Original assignee: 三菱電機株式会社
Priority date: 2011-10-11
Filing date: 2011-10-11
Publication date: 2013-04-18
Also published as: CN103875082B; JPWO2013054396A1; JP5734447B2; CN103875082A

Abstract

This method for manufacturing a photovoltaic power apparatus includes: a first step wherein a recessed and projected structure is formed by forming recesses on one surface of a first conductivity-type or second conductivity-type crystalline semiconductor substrate; a second step wherein a first conductivity-type semiconductor film is formed on the one surface of the crystalline semiconductor substrate, said one surface including the insides of the recesses of the recessed and projected structure; a third step wherein an etching paste is applied to the insides of the recesses having the first conductivity-type semiconductor film formed therein, the surfaces of the recesses are exposed by removing, by etching, the first conductivity-type semiconductor film in the recesses, and first semiconductor bonded regions of the first conductivity-type semiconductor film and the crystalline semiconductor substrate are formed on the projections of the recessed and projected structure by leaving the first conductivity-type semiconductor film on the projections; a fourth step wherein the etching paste is removed; and a fifth step wherein second conductivity-type semiconductor films are formed in the exposed recesses, and second semiconductor bonded regions of the second conductivity-type semiconductor film and the crystalline semiconductor substrate are formed insides of the recesses.

Description

Photovoltaic device manufacturing method and photovoltaic device

The present invention relates to a method for manufacturing a back junction type photovoltaic device having a different conductive type semiconductor junction on the back side opposite to the light receiving surface, and the photovoltaic device.

In the formation of a current general crystalline silicon solar cell, a p-type crystalline silicon substrate having a thickness of about 200 μm is used to increase the surface texture, n-type impurity diffusion layer, antireflection film, and surface electrode ( For example, comb-shaped silver (Ag) electrodes) are sequentially formed on the light-receiving surface side of the p-type crystalline silicon substrate. Further, a back electrode (for example, an aluminum (Al) electrode) is formed on the non-light-receiving surface side (back surface side) of the p-type crystalline silicon substrate by screen printing. And the crystalline silicon solar cell is manufactured by baking these electrodes.

In this firing, the solvent content of the front electrode and the back electrode is volatilized, and the comb Ag electrode penetrates the antireflection film and is connected to the n-type impurity diffusion layer on the light-receiving surface side of the p-type crystal silicon substrate. Further, in this firing, a part of the Al electrode diffuses into the p-type crystalline silicon substrate on the non-light-receiving surface side of the p-type crystalline silicon substrate to form a back surface field layer (BSF: Back Surface Field). .

This BSF layer forms an internal electric field at the junction surface with the p-type crystalline silicon substrate, pushes minority carriers generated near the BSF layer back into the p-type crystalline silicon substrate, and recombines carriers near the Al electrode. It has a suppressing effect. However, the BSF layer formed by this diffusion has a thickness of several hundred nm to several μm when it is formed using a thermal process having an appropriate dopant concentration, and the open circuit voltage due to recombination within the BSF layer. This causes a decrease in short circuit current due to a decrease or light absorption.

For example, Patent Documents 1 to 3 describe the invention of a heterojunction solar cell in which a junction made of a thin impurity-doped silicon layer or a BSF layer is formed on a crystalline silicon substrate via a thin intrinsic semiconductor thin film (i layer). ing. By forming the impurity-doped silicon layer as a thin film, the impurity concentration distribution of the impurity-doped silicon layer can be freely set, and the recombination of carriers and light absorption in the film can be suppressed because the impurity-doped silicon layer is thin. And a large short-circuit current can be obtained. In addition, the intrinsic semiconductor layer inserted between the crystalline silicon substrate and the impurity-doped silicon layer suppresses impurity diffusion between heterojunctions and can form a junction with a steep impurity profile, thus forming a good junction interface. A higher open circuit voltage can be obtained. Furthermore, since the intrinsic semiconductor thin film and the impurity-doped silicon layer can be formed at a low temperature of about 200 ° C., even when the thickness of the crystalline silicon substrate is thin, stress generated in the crystalline silicon substrate due to heat and warpage of the crystalline silicon substrate can be reduced. Can do. In addition, it can be expected that a decrease in substrate quality can be suppressed even for a crystalline silicon substrate that is easily deteriorated by heat.

However, amorphous intrinsic silicon layers and impurity-doped silicon layers used in heterojunction solar cells have a large light absorption coefficient in the visible light region. For this reason, when the thickness of these layers is large, the amount of light entering the crystalline silicon substrate is reduced due to light absorption by these layers, and the short circuit current is reduced. On the other hand, when these amorphous silicon films are thinned to a total of several nanometers, the passivation effect at the substrate interface is lowered by the initial epitaxial growth layer on the crystalline silicon substrate, and the open circuit voltage is lowered.

On the other hand, Patent Document 4 discloses light reception by alternately arranging p-type and n-type impurity-doped thin films on the back surface of a semiconductor substrate and forming both emitter and base electrodes on the back surface side. A method for suppressing shadow loss due to the electrode on the surface side is shown (back junction solar cell). According to the back junction solar cell, in addition to suppressing shadow loss on the light receiving surface side, an insulating film having a light absorption rate smaller than that of the impurity doped layer can be used as an antireflection film on the light receiving surface. A solar cell having a high short-circuit current can be realized.

However, in the back junction solar cell, the pitch between the alternately arranged p-type regions (impurity-doped thin films) and n-type regions (impurity-doped thin films) greatly affects the characteristics. This is because when the positive and negative carriers generated in the semiconductor substrate when irradiated with light move to the p-type region and the n-type region, the distance moved in the semiconductor substrate depends on the pitch of each region. It is. A shorter pitch between the p-type region and the n-type region can suppress carrier recombination and improve solar cell characteristics.

Patent Document 4 discloses a method using a metal mask or a method using photoengraving as a method for patterning an impurity-doped thin film on the back surface of a semiconductor substrate. However, in the method using a metal mask, there is a wraparound under the metal mask when a thin film is formed by a chemical vapor deposition (CVD) method, and the wiring pitch cannot be reduced. Further, in the method using photolithography, it is possible to form each bonding region with a fine pitch, but the process becomes complicated and is not suitable for application to a mass production process.

Therefore, as a thin film patterning method applicable to mass production, a method using an etching paste can be considered. That is, by forming a thin film by screen printing, inkjet, dispenser or the like, applying an etching paste to an unnecessary area of this thin film and heating it, only the area where the etching paste is applied can be removed by etching.

Japanese Patent No. 2132527 Japanese Patent No. 2614561 Japanese Patent No. 3469729 Japanese Patent Application Laid-Open No. 2008-85374

However, the etching paste spreads during heating after coating and during etching. For this reason, a desired pattern cannot be etched with high accuracy, and when the pattern is reduced, adjacent patterns may overlap each other, and the wiring pitch of the p-type region, the n-type region, and the electrode may be reduced. There was a problem that it was difficult to reduce.

The present invention has been made in view of the above, and an object of the present invention is to provide a photovoltaic device manufacturing method and a photovoltaic device capable of manufacturing a back junction type photovoltaic device excellent in photoelectric conversion efficiency. And

In order to solve the above-described problems and achieve the object, a method for manufacturing a photovoltaic device according to the present invention includes forming a recess on one surface side of a crystalline semiconductor substrate of a first conductivity type or a second conductivity type. A first step of forming a concavo-convex structure; a second step of forming a first conductive type semiconductor film on one surface side of the crystalline semiconductor substrate including the inside of the concave portion of the concavo-convex structure; and the first conductive type semiconductor film An etching paste is applied to the recess in which the first conductive type is formed, and the first conductive type semiconductor film in the recess is removed by etching to expose the surface of the recess, and the first on the protrusion of the concavo-convex structure. A third step of forming a first semiconductor junction region between the first conductive type semiconductor film and the crystalline semiconductor substrate on the convex portion while leaving a conductive type semiconductor film; and a fourth step of removing the etching paste. And the exposed recess To include a fifth step of forming a second semiconductor junction region between the second conductivity type semiconductor layer to form a second conductivity type semiconductor layer in the recess and the crystalline semiconductor substrate.

According to the present invention, it is possible to produce a back junction type photovoltaic device excellent in photoelectric conversion efficiency.

FIG. 1-1 is a plan view schematically showing the back surface structure of the solar cell according to the first embodiment of the present invention. FIG. 1-2 is a diagram schematically showing a cross-sectional structure of the solar cell according to the first embodiment of the present invention, and is a main-portion cross-sectional view taken along line A-A 'in FIG. 1-1. FIG. 2 is a flowchart for explaining the solar cell manufacturing method according to the first embodiment. FIG. 3A is a cross-sectional view for explaining the method for manufacturing the solar cell according to the first embodiment. FIG. 3-2 is a cross-sectional view for explaining the method for manufacturing the solar cell according to the first embodiment. FIG. 3-3 is a sectional view for explaining the method for manufacturing the solar cell according to the first embodiment. FIG. 4: is principal part sectional drawing which shows typically the cross-section of the solar cell which is a photovoltaic apparatus concerning Embodiment 2 of this invention. FIG. 5 is a flowchart for explaining a method of manufacturing a solar cell according to the second embodiment of the present invention. FIG. 6-1 is a cross-sectional view for explaining the method for manufacturing the solar cell according to the second embodiment of the present invention. FIG. 6-2 is a cross-sectional view for explaining the method for manufacturing the solar cell according to the second embodiment of the present invention. FIG. 6-3 is a cross-sectional view for explaining the method for manufacturing the solar cell according to the second embodiment of the present invention. 6-4 is a cross-sectional view for explaining the method for manufacturing the solar cell according to the second embodiment of the present invention. FIG.

Hereinafter, a method for manufacturing a photovoltaic device and an embodiment of the photovoltaic device according to the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably. In the drawings shown below, the scale of each member may be different from the actual scale for easy understanding. The same applies between the drawings. Further, even a plan view may be hatched to make the drawing easy to see.

Embodiment 1 FIG.
FIG. 1-1 is a plan view schematically showing a back surface structure of a solar cell that is the photovoltaic device according to the first embodiment of the present invention. FIG. 1-2 is a diagram schematically showing a cross-sectional structure of the solar cell that is the photovoltaic device according to the first embodiment of the present invention, and is a cross-sectional view of a main part taken along line AA ′ in FIG. 1-1. FIG.

The solar cell according to the first embodiment includes an n-type semiconductor substrate 1 which is a first conductive type crystalline semiconductor substrate. On the surface of the n-type semiconductor substrate 1 on the light receiving surface side, a texture 2 made of fine irregularities is formed. On the texture 2, a passivation film 3 and an antireflection film 4 are laminated in this order. Instead of the passivation film 3, a stacked structure of an intrinsic silicon film and a silicon film having the same conductivity type as that of the crystalline semiconductor substrate may be provided.

On the surface (back surface) opposite to the light receiving surface of the n-type semiconductor substrate 1, a p-type semiconductor junction region 5 A having a conductivity type (p-type) opposite to the n-type semiconductor substrate 1 is the same as the n-type semiconductor substrate 1. The n-type semiconductor junction region 6A having the conductivity type (n-type) is formed in a comb shape. The p-type semiconductor junction region 5 </ b> A is provided in a groove portion 1 a formed on the back surface of the n-type semiconductor substrate 1. Then, on the back surface of the n-type semiconductor substrate 1, the p-type semiconductor junction region 5A and the n-type semiconductor junction region 6A are arranged so that the portions corresponding to the comb teeth in the comb shape are alternately meshed one by one. Yes. That is, one of the regions corresponding to the comb teeth in the p-type semiconductor junction region 5A and one of the regions corresponding to the comb teeth in the n-type semiconductor junction region 6A. They are arranged so that they mesh alternately.

In the p-type semiconductor junction region 5A, the p-type semiconductor layer 5 made of a thin film is formed in the groove 1a on the back surface of the n-type semiconductor substrate 1, and forms a pn junction with the back surface of the n-type semiconductor substrate 1. Further, in order to control the impurity profile at the interface between the n-type semiconductor substrate 1 and the p-type semiconductor layer 5 to be steep, an intrinsic silicon film (i layer) may be inserted between them. In this case, the n-type semiconductor substrate 1 and the p-type semiconductor layer 5 form a pn junction through the intrinsic silicon film.

A transparent conductive film 7 is formed on the p-type semiconductor layer 5. On the transparent conductive film 7 in the bottom region of the groove portion 1a, a p-type electrode for electrically coupling the regions in the p-type semiconductor junction region 5A and collecting the generated power from each region and taking it out. 9 is formed in a comb shape similar to the p-type semiconductor junction region 5A.

In the n-type semiconductor junction region 6A, an n-type semiconductor layer 6 made of a thin film is formed on the back surface of the n-type semiconductor substrate 1. The n-type semiconductor layer 6 is formed in a region where the p-type semiconductor layer 5 is not formed on the back surface of the n-type semiconductor substrate 1, that is, on the convex region 1 b between adjacent groove portions 1 a on the back surface of the n-type semiconductor substrate 1. The n-type dopant (for example, P) is contained at a higher concentration than the n-type semiconductor substrate 1. Further, in order to control the impurity profile at the interface between the n-type semiconductor substrate 1 and the n-type semiconductor layer 6 to be steep, an intrinsic silicon film (i layer) may be inserted between them.

A transparent conductive film 8 is formed on the n-type semiconductor layer 6. On the transparent conductive film 8, an n-type electrode 10 for electrically coupling the respective regions in the n-type semiconductor junction region 6 </ b> A and collecting the generated electric power from each region and taking it out is provided on the n-type semiconductor junction. It is formed in a comb shape similar to the region 6A.

In this solar cell, the antireflection film 4 side is the light receiving surface, and sunlight is incident. This solar cell is a heterojunction back junction solar cell in which the p-type electrode 9 and the n-type electrode 10 are arranged only on the back side of the solar cell. Thereby, the solar cell concerning Embodiment 1 suppresses the shadow loss by the side of a light-receiving surface, and the photoelectric conversion efficiency is improved.

The n-type semiconductor substrate 1 is a crystalline silicon substrate exhibiting an n-type conductivity type by being doped with, for example, an n-type dopant (for example, P (phosphorus)). The crystalline silicon substrate includes a single crystal silicon substrate and a polycrystalline silicon substrate. In this embodiment, an example in which a single crystal silicon substrate is used is described.

The passivation film 3 is formed so as to cover the light receiving surface of the n-type semiconductor substrate 1 and functions as a surface passivation layer that suppresses carrier recombination on the substrate surface on the light receiving surface side of the n-type semiconductor substrate 1. By forming such a passivation film 3, a passivation effect on the n-type semiconductor substrate 1 can be obtained, and an effect that an open circuit voltage and a short-circuit current density can be improved.

The antireflection film 4 is formed to cover the passivation film 3 and is a layer provided for the purpose of reducing reflection loss of light incident on the solar cell from the light receiving surface side. The antireflection film 4 also has a function as a protective layer for the n-type semiconductor substrate 1.

Next, an example of a method for manufacturing the solar cell according to the first embodiment will be described with reference to FIGS. 2, 3-1, and 3-2. FIG. 2 is a flowchart for explaining the solar cell manufacturing method according to the first embodiment. FIGS. 3A and 3B are cross-sectional views for explaining the method for manufacturing the solar cell according to the first embodiment.

First, a semiconductor substrate is prepared. In the present invention, the semiconductor substrate can be arbitrarily selected from, for example, n-type single crystal silicon or n-type polycrystalline silicon, or p-type single crystal silicon or p-type polycrystalline silicon. An example using an n-type semiconductor substrate 1 containing phosphorus (P) at a predetermined concentration is shown (FIG. 3A). If the n-type semiconductor substrate 1 is still sliced from the ingot, it is preferable to perform in advance a process for removing damage during slicing, a gettering process for removing impurities, and the like.

Next, a texture 2 made of fine irregularities is formed on the surface of one surface of the n-type semiconductor substrate 1 (FIG. 3-1 (b), step S101). At this time, the texture 2 may be formed on only one side or both sides of the n-type semiconductor substrate 1, but in this embodiment, the texture 2 is formed only on one side. The surface of the n-type semiconductor substrate 1 on which the texture 2 is formed becomes a light receiving surface when the solar cell is finally completed. Hereinafter, the surface on which the texture 2 is formed in the n-type semiconductor substrate 1 may be referred to as a light receiving surface.

For example, when a single crystal silicon substrate having a substrate orientation of (100) is used, the pyramid-shaped texture 2 can be formed by anisotropic etching with an alkaline solution. When a polycrystalline silicon substrate is used, the texture 2 can be formed by a method such as mixed acid or reactive ion etching (RIE). The shape of the texture 2 is not limited, but when the texture 2 is formed also on the back surface of the n-type semiconductor substrate 1, the texture is smaller than the laser digging depth when the groove 1a is formed by a laser in a later process to be described later. It is desired to be a size. Further, when the texture 2 is formed on one surface of the n-type semiconductor substrate 1, a protective film is formed in advance on the surface where the texture 2 is not formed.

Next, a groove 1a is formed by performing a digging process by laser scribing in a region where the p-type semiconductor junction region 5A on the other surface side of the n-type semiconductor substrate 1 is formed, and on the other surface side of the n-type semiconductor substrate 1 A step is formed (FIG. 3-1 (c), step S102). The surface of the n-type semiconductor substrate 1 where the groove 1a is formed becomes the back surface when the solar cell is finally completed. Hereinafter, the surface of the n-type semiconductor substrate 1 on which the groove 1a is formed may be referred to as the back surface.

The digging region for forming the groove 1a has a comb shape similar to the p-type semiconductor junction region 5A shown in FIG. 1-1, and the pitch between the portions corresponding to the comb teeth in the comb shape is about 500 μm to 2 mm. To be. That is, in the comb shape of the p-type electrode 9 formed in the digging region (p-type semiconductor junction region 5A), the groove portion 1a is formed so that the pitch between the portions corresponding to the comb teeth is about 500 μm to 2 mm. To do. Further, in the comb shape of the n-type electrode 10 formed on the convex region 1b, which is a region between the grooves 1a, the grooves 1a are formed so that the pitch between the portions corresponding to the comb teeth is about 500 μm to 2 mm. To do.

In the p-type electrode 9 formed in the p-type semiconductor junction region 5A, when the distance between the electrodes corresponding to the comb teeth is larger than 2 mm, the generated carriers move to the electrode when operating as a solar cell. This is because the carrier distance is increased and carrier recombination is likely to occur before the carrier reaches the electrode, and at the same time, the fill factor may be lowered depending on the resistance of the substrate. The same applies to the n-type electrode 10.

Further, the depth of the groove 1a (or the thickness of the convex region 1b) is about 5 μm to 100 μm, and preferably 5 μm to 20 μm. In the present invention, an etching paste or a resist is printed and applied to the groove 1a in a later step, and the thickness (application thickness) at that time is usually about 5 μm to 20 μm. Under this coating thickness condition, when the depth of the groove 1a is smaller than 5 μm, that is, smaller than the coating thickness of the liquid such as the etching paste or the resist, the spread of the liquid such as the applied etching paste or the resist is suppressed. Can not do it. Also, under this coating thickness condition, when the depth of the groove 1a is larger than 20 μm, that is, when it is larger than the coating thickness of a liquid such as a coated etching paste or resist, screen printing becomes difficult. When the coating thickness of these liquids is larger than 20 μm, an ink jet or a dispenser may be used.

In the present embodiment, a laser is used to form the groove 1a, but other methods may be used as long as the pattern formation accuracy is good. When laser damage remains in the laser irradiation portion, isotropic etching may be performed with an alkali or mixed acid after forming a pattern with a laser. However, by forming the groove portion 1a using a laser, the groove portion 1a can be formed without using a complicated process such as patterning of resist or the like and photolithography, so that the throughput is improved.

Next, the passivation film 3 and the antireflection film 4 are formed on the light receiving surface of the n-type semiconductor substrate 1 on which the texture 2 is formed (FIG. 3-1 (d), step S103, step S104). As the passivation film 3, a passivation effect is applied to an amorphous silicon film having the same conductivity type as that of the n-type semiconductor substrate 1 and doped with impurities at a higher concentration than the n-type semiconductor substrate 1, or an interface with the n-type semiconductor substrate 1. High silicon oxide film or silicon nitride film is used. As the antireflection film 4, a silicon oxide film or a silicon nitride film is used. Note that the passivation film 3 and the antireflection film 4 may be used as the same film as long as the film has both a passivation effect and an antireflection effect, such as a silicon oxide film and a silicon nitride film.

Next, the n-type semiconductor layer 6, the transparent conductive film 8, and the protective film 101 are sequentially formed on the back surface of the n-type semiconductor substrate 1 including the groove 1a (FIG. 3-2 (e), step S105, step S106, Step S107). As the n-type semiconductor layer 6, a silicon-based thin film is used. For example, an amorphous silicon film or microcrystalline silicon formed by a CVD method and doped with phosphorus (P) is used. Further, in order to control the impurity profile at the interface between the n-type semiconductor substrate 1 and the n-type semiconductor layer 6 to be steep, an intrinsic silicon film (i layer) may be inserted between them.

Further, before forming the n-type semiconductor layer 6 on the back surface of the n-type semiconductor substrate 1, chemical cleaning such as RCA cleaning for the purpose of cleaning the n-type semiconductor substrate 1, or the back surface of the n-type semiconductor substrate 1 and n Plasma processing may be performed for the purpose of controlling the interface state with the mold semiconductor layer 6.

The film thickness of the n-type semiconductor layer 6 is about 10 nm to 30 nm. If the film thickness of the n-type semiconductor layer 6 is within this range, unnecessary portions can be easily removed by an etch paste in a subsequent process, and recombination of carriers can be suppressed by the electric field effect on the n-type semiconductor substrate 1. it can.

As the transparent conductive film 8, an indium oxide film is formed by sputtering, for example, as a material that can be removed with an etching paste. As materials other than indium oxide used for the transparent conductive film 8, indium oxide (ITO) doped with 5% to 10% of tin, zinc oxide, tin oxide, or the like can be used. However, it is preferable to use a material that absorbs as little light as possible in the entire wavelength region where light absorption in silicon is present.

As the protective film 101, a silicon oxide film or a silicon nitride film having a thickness of about 20 nm to 100 nm is used as a film that can be removed with an etching paste. These films can be formed by a chemical vapor deposition method (PVD: Physical Vapor Deposition) such as a sputtering method. However, it is necessary to form the n-type semiconductor layer 6 at a temperature of 200 ° C. to 300 ° C. or lower which does not cause deterioration of characteristics due to hydrogen desorption from the silicon-based film. In addition, a material that can form silicon oxide by coating, such as a polysilazane material, can be used as long as it can be formed at a low temperature and can be removed by an etching paste.

Next, the etching paste 102 is applied in the groove 1a using a printing method (FIG. 3-2 (f), step S108). Thereafter, by heating the n-type semiconductor substrate 1 in an oven or the like, unnecessary portions of the three films of the protective film 101, the transparent conductive film 8, and the n-type semiconductor layer 6 are etched away with the etching paste 102. Further, the etching paste 102 is removed with pure water or a thin alkaline solution (FIG. 3-2 (g), step S109, step S110). Unnecessary portions of the three films are portions in the groove 1a. Therefore, by etching away unnecessary portions of the three films with the etching paste 102, the surface of the groove 1a is exposed, and the three films remain on the convex region 1b.

As the etching paste 102, for example, ISHCKISH from MERCK can be used. At this time, in the printing region of the etching paste 102, the width of the etching paste 102 needs to be printed narrower than the width of the groove 1a in consideration of the overlay accuracy with respect to the groove 1a. Further, it is necessary to adjust the emulsion thickness and printing conditions of the printing plate so that the printing thickness of the etching paste 102 does not greatly exceed the depth of the groove 1a. Further, the heating process after the application of the etching paste 102 requires heating at a temperature of 200 ° C. to 300 ° C. or less so as not to deteriorate the silicon-based film of the n-type semiconductor layer 6.

Further, the protective film 101, the transparent conductive film 8, and the n-type semiconductor layer 6 can be simultaneously etched with the etching paste 102 depending on the etching paste material and the type of each film to be etched. On the other hand, when these films cannot be etched at the same time, the protective film 101 is first removed with the etching paste 102, then the transparent conductive film 8 is removed with a liquid such as oxalic acid, and the n-type semiconductor layer 6 is further removed with an alkaline solution. A method such as removal can be used.

Next, the p-type semiconductor layer 5 and the transparent conductive film 7 are sequentially formed on the back surface of the n-type semiconductor substrate 1 including the exposed trench 1a (FIG. 3-2 (h), step S111, step S112). As the p-type semiconductor layer 5, a silicon-based thin film is used. For example, an amorphous silicon film or a microcrystalline silicon film formed by CVD and doped with boron is used. Further, in order to control the impurity profile at the interface between the n-type semiconductor substrate 1 and the p-type semiconductor layer 5 to be steep, an intrinsic silicon film (i layer) may be inserted between them.

In addition, before forming the p-type semiconductor layer 5, chemical film cleaning such as RCA cleaning for the purpose of cleaning the n-type semiconductor substrate 1 is performed by a method in which the protective film 101 on the convex region 1 b has resistance, or n-type. Plasma treatment may be performed for the purpose of controlling the interface state between the back surface of the semiconductor substrate 1 and the n-type semiconductor layer 6.

The film thickness of the p-type semiconductor layer 5 is about 10 nm to 30 nm. If the film thickness of the n-type semiconductor layer 6 is in this range, unnecessary portions can be easily removed by an etch paste in a later process, and a junction constituted by the n-type semiconductor substrate 1 and the p-type semiconductor layer 5 is formed. It can operate as a pn junction of a photovoltaic device.

As the transparent conductive film 7, an indium oxide film is formed by sputtering, for example, as a material that can be removed by etching. As a material other than indium oxide used for the transparent conductive film 7, indium oxide (ITO) doped with 5% to 10% tin, zinc oxide, tin oxide, or the like can be used. However, it is preferable to use a material that absorbs as little light as possible in the entire wavelength region where light absorption in silicon is present.

Next, a protective resist 103 is applied by printing in the groove 1a where the p-type semiconductor layer 5 and the transparent conductive film 7 are formed (FIG. 3-3 (i), step S113). As the protective resist 103, for example, an alkali resistant resist is used. Thereafter, using the protective resist 103 as an etching mask, the transparent conductive film 7 other than the groove 1a is etched away with a transparent conductive film removing liquid such as oxalic acid, and the p-type semiconductor layer 5 other than the groove 1a is further removed with an alkaline solution or the like. Then, the protective resist 103 is removed by a resist remover (FIG. 3-3 (j), step S114, step S115). In FIG. 3-3 (i) and FIG. 3-3 (j), the back surface of the n-type semiconductor substrate 1 faces downward. Processing is performed.

The thickness of the protective resist 103 is such that the p-type semiconductor layer 5 and the transparent conductive film 7 to be removed by etching and the n-type semiconductor layer 6 and the transparent conductive film 8 on the convex region 1b are not overlapped. The printing is performed so that the thickness (depth) is the same as the step 1b (depth of the groove 1a) or slightly smaller than the step (depth of the groove 1a) of the convex region 1b. Further, the transparent conductive film 7 and the p-type semiconductor layer 5 may be removed by vapor phase etching such as RIE or plasma etching.

Next, the protective film 101 remaining on the convex region 1b is removed (FIG. 3-3 (k), step S116). In the case where a silicon oxide film or a silicon nitride film is used as the protective film 101, the protective film 101 can be removed using hydrofluoric acid. Thereby, the n-type semiconductor layer 6 and the transparent conductive film 8 remain on the convex region 1b, and the n-type semiconductor junction region 6A is formed. Further, the p-type semiconductor layer 5 and the transparent conductive film 7 remain in the groove 1a, and a p-type semiconductor junction region 5A is formed.

Next, on the back side of the n-type semiconductor substrate 1, a p-type electrode 9 is formed in the p-type semiconductor junction region 5A, and an n-type electrode 10 is formed in the n-type semiconductor junction region 6A (FIG. 3-3 (l)). Step S117). The p-type electrode 9 and the n-type electrode 10 are formed by, for example, printing and drying an electrode material paste by a screen printing method, and then baking it. For forming the n-type electrode 10 and the p-type electrode 9, for example, a low-temperature sintered type printing silver (Ag) paste that is sintered at 200 ° C. to 300 ° C. or less is used. In addition, annealing in a hydrogen-containing atmosphere may be performed after each film is formed in order to improve defects in silicon-based films and increase the conductivity of the transparent conductive film.

By performing the steps as described above, the solar cell shown in FIGS. 1-1 and 1-2 can be manufactured. In the above description, the p-type semiconductor junction region 5A is provided in the trench 1a. However, the n-type semiconductor junction region 6 is provided in the trench 1a. May be. That is, it is only necessary that either a region having the same conductivity type as that of the n-type semiconductor substrate 1 or a region having a conductivity type opposite to that of the n-type semiconductor substrate 1 is provided in the groove 1a.

In the first embodiment described above, in the manufacture of a heterostructure back junction solar cell capable of realizing high photoelectric conversion efficiency by suppressing the shadow loss on the light receiving surface side, the groove portion 1a is formed on the back surface side of the n-type semiconductor substrate 1. Then, an etching paste 102 is applied in the groove 1a and a desired film is removed by etching. Thereby, a desired pattern can be etched with high accuracy, and adjacent patterns do not overlap even when the patterns are reduced. Therefore, it is possible to accurately form a fine pattern junction region in which the p-type semiconductor junction region 5A and the n-type semiconductor junction region 6A are alternately arranged, and to reduce the wiring pitch of the electrodes of the p-type electrode 9 and the n-type electrode 10. Is feasible.

In a heterojunction back junction solar cell, the pitch between the p-type region and the n-type region that are alternately arranged greatly affects the characteristics. This is because when the positive and negative carriers generated in the semiconductor substrate when irradiated with light move to the p-type region and the n-type region, the distance moved in the semiconductor substrate depends on the pitch of each region. It is. Therefore, when the pitch between the p-type region and the n-type region is short and the wiring pitch between the p-type electrode and the n-type electrode is short, carrier recombination can be suppressed and the solar cell characteristics can be improved.

On the other hand, when the etching paste is simply applied onto the film to be etched, the etching paste spreads when heated and etched after the application. For this reason, a desired pattern cannot be etched with high accuracy, and when the pattern is reduced, adjacent patterns may overlap each other, and the wiring pitch of the p-type region, the n-type region, and the electrode may be reduced. Reduction was difficult.

However, in Embodiment 1, since the etching paste 102 is applied in the groove 1a, the above problem does not occur. That is, in the pattern formation for arranging the junction regions of two conductive thin films on the back surface of the n-type semiconductor substrate 1, after forming the n-type thin film, the etching paste application region corresponding to the p-type thin film formation region Is dug in advance to form a groove 1a, and an etching paste is applied in the groove 1a. As a result, the spread (liquid dripping) of the etching paste after application can be suppressed, and the precision of the etching pattern can be improved and a fine array pattern can be formed.

Further, by etching unnecessary portions in a state where the protective resist 103 is applied in the groove 1a, it is possible to suppress the spread (sagging) of the protective resist 103 after application, thereby improving the etching pattern accuracy. And a fine array pattern can be formed.

Further, in the first embodiment, almost all the region on the back surface side of the n-type semiconductor substrate 1 is passivated by the p-type semiconductor layer 5 or the n-type semiconductor layer 6 so that the solar cell characteristics such as the open circuit voltage and the short-circuit current density can be obtained. Can be improved.

Therefore, according to the first embodiment, the recombination of carriers on the back surface side of the n-type semiconductor substrate 1 can be suppressed and the solar cell characteristics can be improved, and the heterostructure back surface junction type having excellent photoelectric conversion efficiency. Solar cells can be created.

Embodiment 2. FIG.
FIG. 4: is principal part sectional drawing which shows typically the cross-section of the solar cell which is a photovoltaic apparatus concerning Embodiment 2 of this invention. The structure pattern of the solar cell according to the second embodiment viewed from the back side is the same as that shown in FIG. 1-1. FIG. 4 is a cross-sectional view of a main part corresponding to FIG. 1-2. The solar cell according to the second embodiment has the same configuration as the solar cell according to the first embodiment except for the p-type semiconductor junction region 5B. In FIG. 4, the same members as those of the solar cell according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

The solar cell according to the second embodiment has an n-type semiconductor substrate 1 which is a first conductive type crystalline semiconductor substrate. On the surface of the n-type semiconductor substrate 1 on the light receiving surface side, a texture 2 made of fine irregularities is formed. On the texture 2, a passivation film 3 and an antireflection film 4 are laminated in this order. Instead of the passivation film 3, a stacked structure of an intrinsic silicon film and a silicon film having the same conductivity type as that of the crystalline semiconductor substrate may be provided.

A p-type semiconductor junction region 5B having a conductivity type (p-type) opposite to that of the n-type semiconductor substrate 1 is the same as that of the n-type semiconductor substrate 1 on the surface (rear surface) opposite to the light-receiving surface of the n-type semiconductor substrate 1. The n-type semiconductor junction region 6A having a conductivity type (n-type) is formed in a comb shape. The p-type semiconductor junction region 5B corresponds to the p-type semiconductor junction region 5A in the first embodiment. The p-type semiconductor junction region 5 </ b> B is provided in a groove portion 1 c formed on the back surface of the n-type semiconductor substrate 1. The groove portion 1c is a groove portion having two steps, and is formed in an inner region in the width direction of the first groove portion 1d on the first groove portion (first recess) 1d and the bottom surface portion of the first groove portion (first recess) 1d. A two-step groove portion (two-step recess portion) formed by extending in the same direction as the first groove portion 1d and having a second groove portion (second recess portion) 1e having a groove depth deeper than the first groove portion 1d. is there.

Then, on the back surface of the n-type semiconductor substrate 1, the p-type semiconductor junction region 5B and the n-type semiconductor junction region 6A are arranged so that the portions corresponding to the comb teeth in the comb shape are alternately meshed one by one. Yes. That is, one of the regions corresponding to the comb teeth in the comb shape of the p-type semiconductor junction region 5B and one of the regions corresponding to the comb teeth in the comb shape of the n-type semiconductor junction region 6A. They are arranged so that they mesh alternately.

In the p-type semiconductor junction region 5B, the p-type semiconductor layer 5 made of a thin film is formed in the groove 1c on the back surface of the n-type semiconductor substrate 1, and forms a pn junction with the back surface of the n-type semiconductor substrate 1. Further, in order to control the impurity profile at the interface between the n-type semiconductor substrate 1 and the p-type semiconductor layer 5 to be steep, an intrinsic silicon film (i layer) may be inserted between them. In this case, the n-type semiconductor substrate 1 and the p-type semiconductor layer 5 form a pn junction through the intrinsic silicon film.

A transparent conductive film 7 is formed on the p-type semiconductor layer 5. On the transparent conductive film 7 in the bottom region of the groove 1c, each region in the p-type semiconductor junction region 5B is electrically coupled, and the p-type electrode for collecting the generated electric power from each region and taking it out to the outside 9 is provided in a comb shape similar to the p-type semiconductor junction region 5B.

Next, an example of a method for manufacturing the solar cell according to the second embodiment will be described with reference to FIGS. 5 and 6-1 to 6-3. FIG. 5 is a flowchart for explaining the solar cell manufacturing method according to the second embodiment. 6A to 6C are cross-sectional views for explaining the method for manufacturing the solar cell according to the second embodiment.

First, as in the first embodiment, an n-type semiconductor substrate 1 is prepared as a semiconductor substrate (FIG. 6-1 (a)). Next, as in the case of the first embodiment, a texture 2 made of fine irregularities is formed on the surface of one surface side of the n-type semiconductor substrate 1 (FIG. 6-1 (b), step S201). Although the shape of the texture 2 is not limited, when the texture 2 is formed on the back surface of the n-type semiconductor substrate 1, the groove 1 c for forming the p-type semiconductor junction region 5 </ b> B is formed by a laser in a later process described later. It is desirable that the texture size be smaller than the laser digging depth. Further, when the texture 2 is formed on one surface of the n-type semiconductor substrate 1, a protective film is formed in advance on the surface where the texture 2 is not formed.

Next, a first groove 1d is formed by digging by laser scribing in a region where the p-type semiconductor junction region 5B on the other surface side of the n-type semiconductor substrate 1 is formed, and the other surface of the n-type semiconductor substrate 1 is formed. A first step is formed on the side (FIG. 6-1 (c), step S202). Next, the inner region in the width direction of the bottom region of the first groove portion 1d is subjected to a digging process by laser scribing, and extends in the same direction as the first groove portion 1d so that the groove depth is shallower than the first groove portion 1d. The second groove 1e is formed, and a second step is formed on the other surface side of the n-type semiconductor substrate 1 (FIG. 6-1 (d), step S203). As a result, a groove 1c is formed, and a two-step step is formed on the other surface side of the n-type semiconductor substrate 1. The surface of the n-type semiconductor substrate 1 where the groove 1c is formed becomes the back surface when the solar cell is finally completed. Hereinafter, the surface of the n-type semiconductor substrate 1 on which the groove 1c is formed may be referred to as the back surface.

The digging region for forming the first groove 1d has a comb shape similar to the p-type semiconductor junction region 5B shown in FIG. 1-1, and the pitch between the portions corresponding to the comb teeth in the comb shape is 500 μm to 2 mm. To be about. That is, in the comb shape of the p-type electrode 9 formed in the digging region (p-type semiconductor junction region 5B), the groove portion 1c is formed so that the pitch between the portions corresponding to the comb teeth is about 500 μm to 2 mm. To do. Further, in the comb shape of the n-type electrode 10 formed on the convex region 1b which is a region between the groove portions 1c, the groove portions 1c are formed so that the pitch between the portions corresponding to the comb teeth is about 500 μm to 2 mm. To do.

In the p-type electrode 9 formed in the p-type semiconductor junction region 5B, when the distance between the electrodes corresponding to the comb teeth is larger than 2 mm, the generated carriers move to the electrode when operating as a solar cell. This is because the carrier distance is increased and carrier recombination is likely to occur before the carrier reaches the electrode, and at the same time, the fill factor may be lowered depending on the resistance of the substrate. The same applies to the n-type electrode 10.

Further, the depth of the first groove 1d (or the thickness of the convex region 1b) is about 5 μm to 50 μm, and preferably 5 μm to 10 μm. Since the second groove 1e is formed about 50 μm to 100 μm inside the first groove 1d in the width direction, it is thinner by about 100 μm to 200 μm than the width of the first groove 1d. The depth of the second groove 1e is about 5 to 50 μm in addition to the depth of the first groove 1d, and preferably about 5 to 10 μm. The depth of the first groove 1d and the depth of the second groove 1e are preferable. Is preferably 20 μm or less.

In the present invention, an etching paste or a resist is printed and applied to the groove 1c in a later step, and the thickness (application thickness) at that time is usually about 5 μm to 20 μm. Under this coating thickness condition, when the depth of the groove 1a is smaller than 5 μm, that is, smaller than the coating thickness of the liquid such as the etching paste or the resist, the spread of the liquid such as the applied etching paste or the resist is suppressed. Can not do it. Also, under this coating thickness condition, when the depth of the groove 1a is larger than 20 μm, that is, when it is larger than the coating thickness of a liquid such as a coated etching paste or resist, screen printing becomes difficult. When the depth of the first groove 1d or the second groove 1e exceeds 10 μm, an ink jet or a dispenser may be used instead of screen printing.

In the present embodiment, a laser is used to form the groove 1c, but other methods may be used as long as the pattern formation accuracy is good. When laser damage remains in the laser irradiation portion, isotropic etching may be performed with an alkali or mixed acid after forming a pattern with a laser. However, by forming the groove 1c using a laser, the groove 1c can be formed without using a complicated process such as patterning of resist or photoengraving, so that the throughput is improved.

Next, the passivation film 3 and the antireflection film 4 are formed on the light receiving surface side of the n-type semiconductor substrate 1 on which the texture 2 is formed (FIG. 6-2 (e), step S204, step S205).

Next, the n-type semiconductor layer 6, the transparent conductive film 8, and the protective film 101 are sequentially formed on the back surface of the n-type semiconductor substrate 1 including the groove 1c (FIG. 6-2 (f), step S206, step S207). Step S208). As the n-type semiconductor layer 6, a silicon-based thin film is used. For example, an amorphous silicon film or microcrystalline silicon formed by a CVD method and doped with phosphorus (P) is used. Further, in order to control the impurity profile at the interface between the n-type semiconductor substrate 1 and the n-type semiconductor layer 6 to be steep, an intrinsic silicon film (i layer) may be inserted between them.

Next, the etching paste 102 is applied in the first groove portion 1d and the second groove portion 1e using a printing method (FIG. 6-2 (g), step S209). Thereafter, by heating the n-type semiconductor substrate 1 in an oven or the like, unnecessary portions of the three films of the protective film 101, the transparent conductive film 8, and the n-type semiconductor layer 6 are etched away with the etching paste 102. Further, the etching paste 102 is removed with pure water or a thin alkaline solution (FIG. 6-2 (h), step S210, step S211). The unnecessary portions of the three films are portions in the first groove portion 1d and the second groove portion 1e. Therefore, by etching away unnecessary portions of the three films with the etching paste 102, the surfaces of the first groove 1d and the second groove 1e are exposed, and the three films remain on the convex region 1b.

Depending on the etching paste material and the type of each film to be etched, the protective film 101, the transparent conductive film 8, and the n-type semiconductor layer 6 can be simultaneously etched with the etching paste 102. On the other hand, when these films cannot be etched at the same time, the protective film 101 is first removed with the etching paste 102, then the transparent conductive film 8 is removed with a liquid such as oxalic acid, and the n-type semiconductor layer 6 is further removed with an alkaline solution. A method such as removal can be used.

Next, the p-type semiconductor layer 5 and the transparent conductive film 7 are sequentially formed on the back surface of the n-type semiconductor substrate 1 including the exposed first groove portion 1d and the second groove portion 1e (FIG. 6-3 (i), Step S212, Step S213). As the p-type semiconductor layer 5, a silicon-based thin film is used. For example, amorphous silicon or microcrystalline silicon formed by a CVD method and doped with boron is used. Further, in order to control the impurity profile at the interface between the n-type semiconductor substrate 1 and the p-type semiconductor layer 5 to be steep, an intrinsic silicon film (i layer) may be inserted between them.

The film thickness of the p-type semiconductor layer 5 is about 10 nm to 30 nm. If the film thickness of the n-type semiconductor layer 6 is within this range, unnecessary portions can be easily removed by an etch paste in a subsequent process. A junction formed by the n-type semiconductor substrate 1 and the p-type semiconductor layer 5 can operate as a pn junction of the photovoltaic device.

For the transparent conductive film 7, an indium oxide film is formed by sputtering, for example, as a material that can be removed by etching. As a material other than indium oxide used for the transparent conductive film 7, indium oxide (ITO) doped with 5% to 10% tin, zinc oxide, tin oxide, or the like can be used. However, it is preferable to use a material that absorbs as little light as possible in the entire wavelength region where light absorption in silicon is present.

Next, the first protective resist 201 is applied by printing in the second groove 1e where the p-type semiconductor layer 5 and the transparent conductive film 7 are formed (step S214). The thickness of the first protective resist 201 is the same as the digging depth of the second groove 1e or slightly smaller than the digging depth of the second groove 1e so as not to protrude from the digging of the second groove 1e. Print to a thickness. Thereafter, using the first protective resist 201 as an etching mask, the transparent conductive film 7 other than the second groove portion 1e is removed by etching using a transparent conductive film removing liquid such as oxalic acid (FIG. 6-3 (j), Step S215). Thereby, the area | region comprised only by the p-type semiconductor layer 5 without a transparent conductive film can be formed in the boundary part of the p-type semiconductor junction area | region 5B and the n-type semiconductor junction area | region 6A.

Next, with the first protective resist 201 left in the second groove 1e, the second protective resist 202 is printed so as to fill the first groove 1d in which the p-type semiconductor layer 5 is formed. Application is performed (FIG. 6-3 (k), step S216). The thickness of the second protective resist 202 is the same as the digging depth of the first groove 1d or slightly smaller than the digging depth of the first groove 1d so as not to protrude from the digging part of the first groove 1d. Print to a thickness. Then, using the second protective resist 202 as an etching mask, the p-type semiconductor layer 5 on the convex region 1b is etched away with an alkaline solution or the like, and then the first protective resist 201 and the second protective resist 201 are removed. The resist 202 is removed with a resist remover (FIG. 6-3 (l), step S217, step S218). In FIG. 6-3 (j) to FIG. 6-3 (l), the back surface of the n-type semiconductor substrate 1 is directed downward. Processing is performed.

As the first protective resist 201 and the second protective resist 202, an alkali resistant resist is used. The first protective resist 201 and the second protective resist 202 may be the same material or different materials, but it is preferable that they can be removed simultaneously with the same resist remover. The removal of the transparent conductive film 7 and the p-type semiconductor layer 5 may be performed by vapor phase etching such as RIE or plasma etching.

In this way, the transparent conductive film 7 is formed between the p-type semiconductor layer 5 and the n-type semiconductor layer 6 by performing two-stage etching using the first protective resist 201 and the second protective resist 202. A p-type region which is not stacked can be formed. Thereby, the current leakage due to the contact between the transparent conductive film 7 and the n-type semiconductor layer 6 on the p-type semiconductor layer 5 or between the transparent conductive film 7 on the p-type semiconductor layer 5 and the transparent conductive film 8 on the n-type semiconductor layer 6. Can be prevented. That is, it is possible to electrically insulate the transparent conductive film 7 from the n-type semiconductor layer 6 and the transparent conductive film 8 and prevent current leakage between them.

Next, the protective film 101 remaining on the convex region 1b is removed (FIG. 6-4 (m), step S219). When a silicon oxide film or a silicon nitride film is used as the protective film 101, the protective film 101 can be removed using hydrofluoric acid. Thereby, the n-type semiconductor layer 6 and the transparent conductive film 8 remain on the convex region 1b, and the n-type semiconductor junction region 6A is formed. In the trench 1c, the p-type semiconductor layer 5 and the transparent conductive film 7 remain in the second trench 1e, and only the p-type semiconductor layer 5 remains in the first trench 1d, and the p-type semiconductor junction region 5B. Is formed.

Next, on the back side of the n-type semiconductor substrate 1, the p-type electrode 9 is formed in the second groove 1e of the p-type semiconductor junction region 5B, and the n-type electrode 10 is formed in the n-type semiconductor junction region 6A (FIG. 6-4 (n), step S220). The p-type electrode 9 and the n-type electrode 10 are formed by, for example, printing and drying an electrode material paste by a screen printing method, and then baking it. For forming the n-type electrode 10 and the p-type electrode 9, for example, a low-temperature sintered type printing silver (Ag) paste that is sintered at 200 ° C. to 300 ° C. or less is used. In addition, annealing in a hydrogen-containing atmosphere may be performed after each film is formed in order to improve defects in silicon-based films and increase the conductivity of the transparent conductive film.

By performing the steps as described above, the solar cell according to the second embodiment shown in FIGS. 1-1 and 4 can be manufactured. In the above description, the p-type semiconductor junction region 5B is provided in the trench 1c. However, the n-type semiconductor junction region 6 is provided in the trench 1c. May be. That is, it is only necessary that either a region having the same conductivity type as that of the n-type semiconductor substrate 1 or a region having a conductivity type opposite to that of the n-type semiconductor substrate 1 is provided in the groove portion 1c.

In the second embodiment described above, in the manufacture of a heterostructure back junction solar cell capable of realizing high photoelectric conversion efficiency by suppressing the shadow loss on the light receiving surface side, the groove portion 1a is formed on the back surface side of the n-type semiconductor substrate 1. Then, an etching paste 102 is applied in the groove 1a and a desired film is removed by etching. As a result, a desired pattern can be etched with high accuracy as in the first embodiment, and adjacent patterns do not overlap even when the patterns are reduced. Therefore, it is possible to accurately form a junction region having a fine pattern in which the p-type semiconductor junction region 5B and the n-type semiconductor junction region 6A are alternately arranged, and to reduce the wiring pitch of the electrodes of the p-type electrode 9 and the n-type electrode 10. Is feasible.

Further, by etching unnecessary portions with the first protective resist 201 and the second protective resist 202 applied in the groove 1c, the first protective resist 201 and the second protective resist after application are etched. The spread (drip) of the resist 202 can be suppressed, and the precision of the etching pattern can be improved to form a fine array pattern.

In the second embodiment, as in the case of the first embodiment, almost the entire region on the back side of the n-type semiconductor substrate 1 is passivated by the p-type semiconductor layer 5 or the n-type semiconductor layer 6, and the open circuit voltage or Solar cell characteristics such as short-circuit current density can be improved.

And in Embodiment 2, the p-type area | region where the transparent conductive film 7 is not laminated | stacked between the p-type semiconductor layer 5 and the n-type semiconductor layer 6 can be formed. Thereby, the current leakage due to the contact between the transparent conductive film 7 and the n-type semiconductor layer 6 on the p-type semiconductor layer 5 or between the transparent conductive film 7 on the p-type semiconductor layer 5 and the transparent conductive film 8 on the n-type semiconductor layer 6. Can be prevented.

Therefore, according to the second embodiment, recombination of carriers on the back side of n-type semiconductor substrate 1 is suppressed, and current leakage between p-type semiconductor junction region 5B and n-type semiconductor junction region 6A is prevented. Battery characteristics can be improved, and a heterostructure back junction solar cell having a high short-circuit current and excellent photoelectric conversion efficiency can be produced.

As described above, the method for producing a photovoltaic device according to the present invention is useful for producing a back junction type photovoltaic device having excellent photoelectric conversion efficiency.

1 n-type semiconductor substrate 1a groove 1b convex region 1c groove 1d first groove 1e second groove 2 texture 3 passivation film 4 antireflection film 5 p-type semiconductor layer 5A p-type semiconductor junction region 5B p-type semiconductor junction region 6 n-type Semiconductor layer 6A n-type semiconductor junction region 7 transparent conductive film 8 transparent conductive film 9 p-type electrode 10 n-type electrode 101 protective film 102 etching paste 103 protective resist 201 protective resist 202 protective resist

Claims

A first step of forming a concave-convex structure by forming a concave portion on one surface side of a crystalline semiconductor substrate of the first conductive type or the second conductive type;
A second step of forming a semiconductor film of a first conductivity type on one surface side of the crystalline semiconductor substrate including the inside of the concave portion of the concave-convex structure;
An etching paste is applied in the recess in which the first conductivity type semiconductor film is formed, and the first conductivity type semiconductor film in the recess is removed by etching to expose the surface of the recess and the uneven structure. Forming a first semiconductor junction region between the first conductive type semiconductor film and the crystalline semiconductor substrate on the convex portion, leaving the first conductive type semiconductor film on the convex portion;
A fourth step of removing the etching paste;
A fifth step of forming a second conductivity type semiconductor film in the exposed recess and forming a second semiconductor junction region between the second conductivity type semiconductor film and the crystalline semiconductor substrate in the recess; ,
A method for manufacturing a photovoltaic device, comprising:
The fifth step includes
Forming a second conductivity type semiconductor film on one side of the crystalline semiconductor substrate including the inside of the recess;
A protective resist is formed in the recess in which the second conductive type semiconductor film is formed, and the second conductive type semiconductor film is left in the concave using the protective resist as an etching mask and the convex portion. Etching away the second conductive type semiconductor film above;
Having
The method for manufacturing a photovoltaic device according to claim 1.
After the fifth step,
Forming an electrode on the first conductive type semiconductor film on the convex portion;
Forming an electrode on the second conductivity type semiconductor film in the recess;
The method for manufacturing a photovoltaic device according to claim 1, wherein:
The depth of the recess is in the range of 5 μm to 100 μm, and the coating thickness of the etching paste is equal to or less than the depth of the recess,
The method for manufacturing a photovoltaic device according to any one of claims 1 to 3, wherein:
In the first step, as the concave portion, a two-step concave portion in which a second concave portion narrower than the first concave portion is formed on the inner side in the width direction of the bottom surface portion of the first concave portion,
In the second step, a first conductive type semiconductor film and a first transparent conductive film are formed in this order on one surface side of the crystalline semiconductor substrate including the inside of the two-step concave portion,
In the third step, an etching paste is applied in the two-step recess, and the first conductivity type semiconductor film and the first transparent conductive film in the two-step recess are removed by etching to remove the two-step recess. And exposing the first conductive type semiconductor film and the crystalline semiconductor substrate on the convex portion, leaving the first conductive type semiconductor film and the first transparent conductive film on the convex portion. Forming a first semiconductor junction region of
In the fifth step,
Forming a second conductive type semiconductor film and a second transparent conductive film on one surface side of the crystalline semiconductor substrate including the inside of the two-step recess;
Forming a first protective resist in the second recess, leaving the second transparent conductive film in the second recess using the first protective resist as an etching mask, and in the first recess and the convex; Etch away the second transparent conductive film and the above,
A second protective resist is formed in the first concave portion with the first protective resist remaining in the second concave portion, and the second protective resist is used as an etching mask to form the second protective resist on the convex portion. The conductive semiconductor film is removed by etching, and the second conductive semiconductor film and the crystalline semiconductor are left in the concave portion while leaving the second conductive semiconductor film in the first concave portion and the second concave portion. Forming a second semiconductor junction region with the substrate;
The method for manufacturing a photovoltaic device according to claim 1.
After the fifth step,
Forming an electrode on the first transparent conductive film on the convex portion;
Forming an electrode on the first transparent conductive film in the recess;
The method for manufacturing a photovoltaic device according to claim 5, wherein:
The depth of the two-step recess is in the range of 5 μm to 100 μm, and the thickness of the etching paste is not more than the depth of the recess,
A method for manufacturing a photovoltaic device according to claim 5 or 6.
The thickness of the first protective resist is not more than the depth of the second recess,
The thickness of the second protective resist is not more than the depth of the first recess,
The method for manufacturing a photovoltaic device according to any one of claims 5 to 7, wherein:
Forming the recesses such that the recesses and the protrusions extend alternately and in parallel in substantially the same direction;
The method for producing a photovoltaic device according to any one of claims 1 to 8, wherein:
Forming the recess by laser irradiation on one side of the crystalline semiconductor substrate;
The method for manufacturing a photovoltaic device according to any one of claims 1 to 9, wherein:
A photovoltaic device in which different types of semiconductor junctions are formed on a surface having a convex portion and a concave portion of a crystalline semiconductor substrate of a first conductivity type or a second conductivity type,
The concave portion is a two-step concave portion in which a second concave portion narrower than the first concave portion is formed on the inner side in the width direction of the bottom surface portion of the first concave portion,
A first conductive type semiconductor film and a first transparent conductive film are laminated in this order on the convex portion to form a first semiconductor junction region between the first conductive type semiconductor film and the crystalline semiconductor substrate. ,
A second conductive type semiconductor film and a second transparent conductive film are stacked in this order in the first concave portion and the second concave portion, and the second conductive type semiconductor film and the crystalline semiconductor substrate are formed in this order. 2 semiconductor junction regions are formed,
The first conductive type semiconductor film and the first transparent conductive film are electrically insulated from the second transparent conductive film;
A photovoltaic device characterized by the above.