JP5645734B2 - Solar cell element - Google Patents

Description

  The present invention relates to a solar cell element. In particular, the present invention relates to a solar cell element having a structure suitable for improving conversion efficiency when converting incident light energy into electric energy.

  In recent years, interest in solar power generation has increased, and the production amount of solar cell elements has been increasing year by year. Various materials have been proposed as constituent materials for solar cell elements, but the mainstream at present is crystalline silicon.

  In general, in a solar cell element using a crystalline silicon-based semiconductor substrate, electrodes are formed on each of a light receiving surface (front surface) and a non-light receiving surface (back surface) located on the opposite side of the semiconductor substrate. The electrode on the light receiving surface is composed of a large number of finger electrodes and several bus bar electrodes orthogonal to them, but the light is shielded under the electrodes on the light receiving surface. For this reason, the characteristic of the solar cell element may deteriorate.

  Therefore, various research and development have been carried out for the purpose of improving the characteristics of solar cell elements. As one of them, a solar cell in which a groove is formed on the back surface region of a semiconductor substrate and a buried electrode is provided in the obtained groove. Battery elements have been proposed (see, for example, Patent Documents 1 and 2 below).

Japanese Patent Laid-Open No. 1-125988 JP 2010-251343 A

  However, in the solar cell element provided with the embedded electrode, although Jsc (short circuit current density) is improved, Voc (open circuit voltage) and FF (fill factor) are lowered, and eventually, improvement in conversion efficiency cannot be expected. is there.

  Then, an object of this invention is to provide the solar cell element which can anticipate the improvement of the electrical property of solar cell elements, such as conversion efficiency, compared with the conventional solar cell element.

In order to achieve the above object, a solar cell element according to an embodiment of the present invention is provided with a linear first electrode on a light receiving surface side of a semiconductor substrate, and a linear second electrode on a back surface side of the semiconductor substrate. A concave portion whose surface layer is a passivation layer along the first electrode in a portion that overlaps with the first electrode when seen through the plane on the back surface side of the semiconductor substrate. is provided, said second electrode, characterized in that provided along said recess portion to avoid a site overlapping with the first electrode in plan perspective.

  According to said solar cell element, the recombination of a carrier can be reduced suitably in the light-shielding area | region under a 1st electrode.

Thereby, in particular, Jsc can be improved, and improvement in Voc and FF by reducing dark current and leakage current can be expected. And the solar cell element excellent in the electrical property which the conversion efficiency improved can be provided.

It is a figure which shows typically an example of the solar cell element which concerns on one form of this invention, and is the top view seen from the light-receiving surface (surface) side of a solar cell element. It is a figure which shows typically an example of the solar cell element which concerns on one form of this invention, and is the top view seen from the non-light-receiving surface (back surface) side of a solar cell element. It is the sectional view on the AA line in FIG. It is sectional drawing which shows an example of the conventional solar cell element typically. It is sectional drawing which shows an example of the conventional solar cell element typically. It is a graph which shows the wavelength dependence of external quantum efficiency (EQE) by the presence or absence of bias light.

  Hereinafter, embodiments of the solar cell element according to the present invention will be described in detail with reference to the drawings.

<Basic configuration of solar cell element>
A basic configuration of the solar cell element will be described with reference to FIGS. In the solar cell element S, a linear first electrode 5 is provided on the light receiving surface (front surface) side 9a of the semiconductor substrate 1, and a linear second electrode is provided on the non-light receiving surface (back surface) side 9b of the semiconductor substrate 1. 6 is provided. In addition, the back surface side 9b of the semiconductor substrate 1 is provided along the first electrode 5 (5b) in a portion that overlaps with the first electrode 5 (in particular, a finger electrode 5b described later in the present embodiment) in a plan view. A concave portion 10 whose surface layer is the passivation layer 8 is provided along the first electrode 5 (5b) at a portion overlapping the first electrode 5 (5b) in a plan view, and the second electrode 6 In the embodiment, the back surface collecting electrode 6b), which will be described later , is provided along the concave portion 10 in a portion that avoids the concave portion 10 , that is, in a portion that does not overlap with the first electrode when seen in a plan view .

  Here, the semiconductor substrate 1 includes, for example, a thick first semiconductor layer 2 and a thin second semiconductor layer 3. In addition, the semiconductor substrate 1 has a second semiconductor layer 3 that is a one-conductivity-type semiconductor layer and a second semiconductor layer 2 that is an opposite-conductivity-type semiconductor layer, and the first electrode 5 is connected to the second semiconductor layer 3. The second electrodes 6 are in contact with the first semiconductor layer 2, respectively.

  Further, the portion of the second semiconductor layer 3 that is in contact with the first electrode 5 (5b) is a region 12 (in FIG. 3) in which the concentration of an impurity exhibiting one conductivity type is higher in the second semiconductor layer 3 than in other regions. A region surrounded by a one-dot chain line: a selective emitter region) may be used.

  Further, in the first semiconductor layer 2, the region 11 (in FIG. 3) in which the concentration of the impurity exhibiting the reverse conductivity type along the concave portion 10 is higher than the other region in the portion that overlaps with the first electrode 5 (5 b) as seen through the plane. May be provided with an area surrounded by a broken line (BSF (Back-Surface-Field) area).

  Further, the portion of the first semiconductor layer 2 that is in contact with the second electrode 6 (6b) may be a region in the first semiconductor layer 2 in which the concentration of impurities exhibiting a reverse conductivity type is higher than other regions. .

  The recess 10 may have a groove shape, but it is preferable that the recess 10 is composed of a large number of holes provided along the first electrode 5 as shown in FIG.

With the configuration described above, the solar cell element S can suitably reduce carrier recombination in the light shielding region by narrowing (as much as possible) the light shielding region under the first electrode 5 (5b). As a result, Jsc can be improved, and improvement in Voc and FF by reducing dark current and leakage current can be expected. And the outstanding solar cell element with improved conversion efficiency can be provided.

<Unique structure of this embodiment>
Next, the reason why the concave portion 10 is provided in the solar cell element S of the present embodiment will be described. A cross-sectional view of a general solar cell element J1 is shown in FIG. Moreover, the solar cell element J2 which provided the 2nd electrode 6 which carried out the groove process on the back surface side of the semiconductor substrate 1, and was embedded there is shown in FIG. Note that the same members as those in FIGS.

  In the solar cell element J1 shown in FIG. 4, attention was paid to the influence of light shielding by the finger electrodes 5b constituting the first electrode 5 on the light receiving surface side. Then, in the solar cell element J1 using polycrystalline silicon as the semiconductor substrate 1, a region (photo area) in a photo state irradiated with bias light rather than a region (dark area) in a dark state immediately below the finger electrode 5b. ) Confirmed that the minority carrier lifetime and diffusion length were greater by measurement. Here, the bias light means light irradiation by simulated sunlight.

  FIG. 6 shows the measurement wavelength dependence of the external quantum efficiency (EQE) of the solar cell element depending on the presence or absence of bias light. As shown in FIG. 6, it can be seen that the EQE is smaller when the bias light is not present in almost the entire measurement wavelength range than when the bias light is present. This is because the electron occupancy rate of the defect level serving as the recombination center differs between the photo state and the dark state. That is, for example, in a p-type semiconductor, the suspected Fermi level Efe in the photo state is located on the higher electron energy side than the Fermi level Ef in the thermal equilibrium state (dark state). Also, the electron occupancy of the recombination center located on the low electron side is increased. In other words, the vacancy ratio of defect levels where electrons are trapped decreases, and this reduces the probability of recombination of electrons that are minority carriers in the p-type semiconductor. A low recombination probability corresponds to a long lifetime and a long diffusion length.

Table 1 shows the analysis results of FIG. As is clear from Table 1, the minority carrier lifetime and diffusion length are shorter in the dark region, and the crystal quality (crystal defects that become recombination centers become inactive by light irradiation compared to the photo region. It can be seen that quality is improved). In Table 1, the effective back surface coupling speed includes the influence of the BSF region 7. Jsc means intrinsic Jsc excluding the influence of light shielding of the finger electrode 5b, and is a value calculated assuming that the light shielding area by the finger electrode 5b is about 7% of the entire light receiving surface of the cell.

  Therefore, for example, as in the solar cell element J2 shown in FIG. 5, a groove is formed in the back surface region facing the finger electrode 5b position of the semiconductor substrate 1 to form a buried portion of the second electrode 6 that is a buried electrode. Thus, it is considered that the dark region formed for light shielding by the finger electrode 5b is reduced, carrier recombination is reduced, Jsc is improved, and the characteristics of the solar cell element are improved.

  However, when a groove is formed in the back surface region of the semiconductor substrate 1 opposite to the position of the finger electrode 5b to form the embedded portion of the second electrode 6, the distance between the finger electrode 5b and the second electrode 6 is reduced (crystal quality is reduced). Since the inferior light-shielding region is shortened), dark current and leakage current increase, and Voc and FF decrease.

  Therefore, for example, as shown in FIGS. 1 to 3, in the back surface region facing the finger electrode 5 b constituting the first electrode of the semiconductor substrate 1, a recess 10 that is a dot-like or groove-like opening is provided, and A passivation layer 8 is provided on the surface layer of the recess 10, and a BSF region 11 is provided in some cases. The back surface collecting electrode 6b constituting the second electrode 6 is selectively brought into electrical contact with the semiconductor substrate 1 at a position other than the recess member 10, thereby forming a light shielding region under the finger electrode 5b. It has been found that the dark current and leakage current that flow can be reduced, and that Voc and FF can be improved and the conversion efficiency can be improved as compared with the solar cell elements J1 and J2 having the conventional structure.

<Specific examples of solar cell elements>
Next, a more specific example of the form of the solar cell element will be described with reference to FIGS. For example, as the semiconductor substrate 1 having the p-type first semiconductor layer 2, a crystalline silicon substrate such as a single crystal silicon substrate or a polycrystalline silicon substrate is preferably used. The specific resistance of such a semiconductor substrate 1 is about 0.2 to 2.0 Ω · cm. The thickness of the semiconductor substrate 1 is about 150 to 250 μm. Moreover, the shape of the semiconductor substrate 1 is not particularly limited, but a rectangular shape is preferable from the viewpoint of the manufacturing method and when a solar cell module is configured by arranging a large number of solar cell elements.

  When a crystalline silicon substrate exhibiting p-type conductivity is used as the semiconductor substrate 1, for example, boron or gallium is preferably added as the dopant element.

  The second semiconductor layer 3 has a conductivity type opposite to that of the first semiconductor layer 2 and is provided on the light receiving surface side 9 a of the first semiconductor layer 2. If the first semiconductor layer 2 has a p-type conductivity, the second semiconductor layer 3 is formed to have an n-type conductivity, and can be formed by diffusing a dopant element such as phosphorus, for example.

  In addition, it is preferable to form a third semiconductor layer having the same conductivity type as that of the second semiconductor layer 3 at the position where the first electrode 5 is formed, thicker than the second semiconductor layer 3, and having a higher dopant concentration. By increasing the thickness of the third semiconductor layer and increasing the dopant concentration, the contact resistance with the electrode and the recombination current (leakage current) at the pn junction can be reduced. As an example of a method for increasing the thickness of the third semiconductor layer and increasing the dopant concentration, after forming the second semiconductor layer 3 by the coating thermal diffusion method or the vapor phase thermal diffusion method, By irradiating the semiconductor substrate 1 with a laser in accordance with the electrode shape of the electrode 5, phosphorus is re-diffused from the phosphorus glass to the second semiconductor layer 3 to form a third semiconductor layer.

The antireflection layer 4 made of an antireflection film plays a role of reducing the reflectance of light in a desired wavelength region and increasing the amount of photogenerated carriers on the light receiving surface side 9a of the solar cell element. For example, a silicon nitride film, a titanium oxide film, or a silicon oxide film is used for the antireflection layer 4. The refractive index and thickness of the antireflection layer 4 are appropriately selected depending on the constituent materials, and are set so as to realize a non-reflection condition with respect to appropriate incident light. The semiconductor substrate 1 made of crystalline silicon preferably has a refractive index of about 1.8 to 2.3 and a thickness of about 500 to 1200 mm. Further, when the antireflection layer 4 is made of, for example, a silicon nitride film formed by a plasma CVD method, it is preferable because it can have a passivation effect.

The BSF region 7 provided on the back surface side 9b of the semiconductor substrate 1 has a role of reducing a decrease in efficiency due to carrier recombination in the vicinity of the back surface side 9b, and forms an internal electric field on the back surface side 9b. is there. The BSF region 7 has the same conductivity type as that of the first semiconductor layer 2, but has a majority carrier concentration higher than the concentration of majority carriers contained in the first semiconductor layer 2. This means that the dopant element is present at a concentration higher than the concentration of the dopant element added to exhibit one conductivity type in the semiconductor substrate 1. If the semiconductor substrate 1 exhibits p-type, the BSF region 7 is doped with a dopant element such as boron or aluminum at a high concentration, for example, on the back surface side 9b, and the concentration of the element is 1 × 10 ^{18 to} 5 × 10 ²¹ atoms. / Cm ³ is preferably formed.

  As shown in FIG. 1, the 1st electrode 5 which is a surface electrode has the bus-bar electrode 5a and the several linear finger electrode 5b. At least a part of the bus bar electrode 5a intersects the finger electrode 5b. The bus bar electrode 5a has a width of about 1.3 to 2.5 mm, for example. On the other hand, the finger electrode 5b is linear, the line width is about 50-200 micrometers, and is thinner than the bus-bar electrode 5a. A plurality of finger electrodes 5b are provided with an interval of about 1.5 to 3 mm.

  The thickness of the first electrode 5 is about 10 to 40 μm. The first electrode 5 can be formed by, for example, applying a paste for forming an electrode made of silver powder, glass frit, an organic vehicle, or the like into a desired shape by screen printing or the like and then baking it.

  In addition, the 1st electrode 5 may further provide the linear auxiliary electrode 5c which cross | intersects the finger electrode 5b in the both ends which cross | intersect with respect to the longitudinal direction of the finger electrode 5b. As a result, the current supplied in the plating method can be made to flow uniformly to the first electrode 5 and a plating electrode layer having a uniform thickness can be formed. However, it is preferable because the increase in resistance can be reduced and a current can flow through the other finger electrode 5b to the bus bar electrode 5a.

  As shown in FIG. 2, the 2nd electrode 6 which is a back surface electrode has the back surface output extraction electrode 6a and the back surface current collection electrode 6b. The back surface output extraction electrode 6a has a thickness of about 10 to 30 μm and a width of about 1.3 to 7 mm. The back surface output extraction electrode 6a is formed, for example, by applying a silver paste in a desired shape and baking it. Further, the back surface collecting electrode 6b has a thickness of about 15 to 50 μm, and in the present embodiment, a finger-like or contact portion with the semiconductor substrate 1 is formed on substantially the entire surface excluding the back surface output extraction electrode 6a and the recess 10. Only the dots and fingers are formed. This back surface collecting electrode 6b can be formed by, for example, applying an aluminum paste in a desired shape and then baking it. The second electrode 6 can also be formed using thin film formation such as vapor deposition or sputtering, or plating.

In addition, a passivation layer 8 that functions as a back surface passivation film is provided on the back surface side 9 b of the semiconductor substrate 1. The passivation layer 8 forms an insulating layer made of an aluminum oxide film, a silicon oxide film, a silicon nitride film, or the like, covers almost the entire surface of the passivation layer 8, and selectively makes electrical contact with the BSF region 7. It is preferable to form the second electrode 6. Here, the BSF region 7 forms an internal electric field on the back surface side 9b, and has a role of reducing a decrease in efficiency due to carrier recombination in the vicinity of the back surface side 9b.

  As the semiconductor substrate 1, for example, a p-type single crystal silicon substrate or a polycrystalline silicon substrate such as a polycrystalline silicon substrate is preferably used.

<Method for producing solar cell element>
Next, a specific method for manufacturing the solar cell element S will be described. First, the semiconductor substrate 1 constituting the first semiconductor layer 2 is prepared. When the semiconductor substrate 1 is a single crystal silicon substrate, it is formed by, for example, the Czochralski (CZ) method, and when the semiconductor substrate 1 is a polycrystalline silicon substrate, it is formed by, for example, a casting method. In the following description, an example using p-type polycrystalline silicon will be described.

  First, a polycrystalline silicon ingot is produced by, for example, a casting method. Next, the ingot is sliced to a thickness of 250 μm or less, for example. Thereafter, the mechanically damaged layer and the contaminated layer on the cut surface of the semiconductor substrate 1 are etched with a solution such as NaOH, KOH or hydrofluoric acid. Note that it is more desirable to form a minute uneven structure (texture) on the surface of the semiconductor substrate 1 by using a wet etching method or a dry etching method after this etching step. Further, the above-described damaged layer removing step can be omitted depending on the texture forming conditions.

Next, the n-type second semiconductor layer 3 is formed in the surface layer on the light receiving surface side 9 a of the semiconductor substrate 1. Such a second semiconductor layer 3 has a coating thermal diffusion method in which P ₂ O ₅ in a paste state is applied to the surface of the semiconductor substrate 1 for thermal diffusion, and phosphorus oxychloride (POCl ₃ ) in a gas state is a diffusion source. The gas phase thermal diffusion method and the ion implantation method for directly diffusing phosphorus ions are used. The second semiconductor layer 3 is formed to have a thickness of about 0.2 to 2 μm and a sheet resistance of about 40 to 150Ω / □. Note that the method for forming the second semiconductor layer 3 is not limited to the above method. For example, a crystalline silicon film including a hydrogenated amorphous silicon film or a microcrystalline silicon film may be formed using a thin film technique. Good. Furthermore, an i-type silicon region may be formed between the semiconductor substrate 1 and the second semiconductor layer 3.

  In addition, it is preferable to form a third semiconductor layer having the same conductivity type as that of the second semiconductor layer at the position where the first electrode 5 is formed, a doping concentration higher than that of the second semiconductor layer 3, and a thickness greater. The third semiconductor layer is formed to a thickness of about 0.2 to 2.5 μm and a sheet resistance of about 20 to 60Ω / □. After the second semiconductor layer 3 is formed, the third semiconductor layer is irradiated from the phosphor glass to the second semiconductor by irradiating the semiconductor substrate 1 with a laser in accordance with the electrode shape of the first electrode 5 with the phosphor glass remaining. Formed by re-diffusion of phosphorus into layer 3.

  When the second semiconductor layer 3 is also formed on the back surface side 9b, only the back surface side 9b is removed by etching to expose the p-type conductivity type region. For example, the second semiconductor layer 3 is removed by immersing only the back surface side 9b of the semiconductor substrate 1 in a hydrofluoric acid solution. Thereafter, when the second semiconductor layer 3 is formed, the phosphorus glass adhering to the surface of the semiconductor substrate 1 is removed by etching. Further, a diffusion mask is formed in advance on the back surface side 9b, and the second semiconductor layer 3 is formed by a vapor phase thermal diffusion method or the like. Thereafter, a similar structure can be formed by a process of subsequently removing the diffusion mask.

  As described above, the semiconductor substrate 1 including the p-type first semiconductor layer 2 and the n-type second semiconductor layer 3 (and the third semiconductor layer) can be prepared.

Next, the antireflection layer 4 is formed. The antireflection layer 4 is formed using, for example, a plasma enhanced chemical vapor deposition (CVD) method, a vapor deposition method, or a sputtering method. For example, when the antireflection layer 4 made of a silicon nitride film is formed by a plasma CVD method, the reaction chamber is set to about 500 ° C. and a mixed gas of silane (SiH ₄ ) and ammonia (NH ₃ ) is nitrogen (N _2). The anti-reflective layer 4 is formed by diluting with (3) and plasmaizing and depositing by glow discharge decomposition.

  Next, the back surface side 9b of the semiconductor substrate 1 is irradiated with a laser in a dot shape or a groove shape to form the recess 10. The shape of the recess 10 may be a dot shape (groove shape) having a diameter (width) of 50 to 500 μm and a depth of 10 to 150 μm, for example, and is provided at a position facing the first electrode 5. The interval in the case of forming dots is about 50 μm to 2 mm. This processing can also be performed, for example, before the formation of the antireflection layer 4 or before the formation of the second semiconductor layer 3.

  After the formation of the recess 10, a back surface passivation film 8 made of, for example, an aluminum oxide film is formed on the back surface side 9b of the semiconductor substrate 1 by using an ALD (Atomic Layer Deposition) method, a vapor deposition method, a sputtering method, or the like. Since the concave portion 10 has a small diameter and a deep shape, the ALD method capable of forming a film with a uniform thickness on the silicon surface is suitable in this embodiment.

  Next, the first electrode 5 (the bus bar electrode 5a and the finger electrode 5b) and the second electrode 6 (the back surface output extraction electrode 6a and the back surface collecting electrode 6b) are formed as follows.

  The first electrode 5 is produced using silver powder, an organic vehicle, and a conductive paste containing glass frit. This conductive paste is applied to the surface side 9 a of the semiconductor substrate 1. Then, by firing at a maximum temperature of 600 to 850 ° C., fire-through occurs, and the semiconductor substrate 1 and the first electrode 5 obtain an electrical contact by breaking through the antireflection layer 4. As a method for applying the conductive paste, a screen printing method or the like can be used. Preferably, after application, the solvent is evaporated and dried at a predetermined temperature.

  Next, the second electrode 6 is formed. The back surface collecting electrode 6b which comprises the 2nd electrode 6 is produced using the aluminum paste containing aluminum powder and an organic vehicle, for example. This paste is applied in the form of dots or fine lines on almost the entire back surface 9b excluding the recesses 10. As a coating method, a screen printing method or the like can be used.

  After applying the paste, it is preferable to evaporate the solvent at a predetermined temperature and dry it from the viewpoint that the paste is less likely to adhere to other parts during operation. Then, by firing the semiconductor substrate 1 in a firing furnace at a maximum temperature of 600 to 850 ° C., fire-through occurs, and the back surface collecting electrode 6b and the BSF region 7 are formed.

  The BSF region 7 may be formed as a floating layer not only directly under the back surface collecting electrode 6b but also in the recess 10.

  The back surface output extraction electrode 6a is manufactured using, for example, a metal powder made of silver powder or the like, and a silver paste containing an organic vehicle and glass frit. This silver paste is applied in a predetermined shape. The silver paste is applied at a position in contact with a part of the aluminum paste, so that the back surface output electrode 6a and the back surface collecting electrode 6b partially overlap.

As a method for applying the paste, a screen printing method or the like can be used. After this application, the solvent is preferably evaporated and dried at a predetermined temperature. And the 2nd electrode 6 is formed in the back surface side 9b of the semiconductor substrate 1 by baking the semiconductor substrate 1 in a baking furnace with the maximum temperature of 600-850 degreeC.

  The first electrode 5 and the second electrode 6 may be fired simultaneously, or a conductive resin paste may be used as the back surface output extraction electrode 6a.

  As described above, a solar cell element with improved conversion efficiency can be produced.

<Other embodiments>
In addition, this invention is not limited to the said embodiment, Many corrections and changes can be added within the scope of the present invention as follows.

  In the above-described embodiment, the example in which the concave portion 10 is provided only directly below the finger 5b constituting the first electrode 5 has been described. However, the portion serving as the light shielding region of the first electrode 5 provided on the light receiving surface side of the semiconductor substrate 1. In other words, the thickness of the semiconductor substrate 1 in the portion serving as the light-shielding region of the first electrode 5 may be reduced. For example, the first electrode 5 side may be concave, and the first electrode 5 may be formed directly below the bus bar electrode 5a. May also be provided with a recess.

  Moreover, the 1st electrode 5 may be comprised from the base electrode layer mentioned above and the plating electrode layer which is a conductive layer formed on it by the plating method. As the plating electrode material, copper, silver, tin or the like is preferably used. In this case, the thicknesses of the base electrode layer and the plating electrode layer are preferably 1 to 10 μm and 5 to 30 μm, respectively. Since the base electrode layer is formed by applying and baking an electrode forming paste, the porosity is higher than 5%. The plating electrode layer is formed so that the porosity is 5% or less. By reducing the thickness of the base electrode layer to 10 μm or less, preferably 8 μm or less, the line resistance can be reduced while maintaining the total thickness of the first electrode 5.

  Below, the more specific Example of the solar cell element of this embodiment is described. The reference drawings are FIGS.

  First, in order to produce the solar cell elements of Examples 1 to 3 (structures shown in FIGS. 1 to 3) shown in Table 2, polycrystalline silicon having a thickness of 220 μm, an outer shape of 156 mm × 156 mm, and a specific resistance of 1.5 Ω · cm. A substrate (semiconductor substrate 1) was prepared, and the damaged layer on the surface of the silicon substrate was etched and washed with NaOH.

Next, a texture was formed on the surface 9a by a dry etching method. Then, the second semiconductor layer 3 was formed by vapor phase thermal diffusion using POCl ₃ as a diffusion source. At this time, the sheet resistance of the second semiconductor layer 3 was 70Ω / □. After removing the second semiconductor layer 3 on the back surface 9b side with a hydrofluoric acid solution and removing the phosphor glass by etching with a hydrofluoric acid solution, a silicon nitride film to be the antireflection layer 4 was formed on the surface 9a by plasma CVD. . The antireflection layer 4 had a thickness of 80 nm and a refractive index of 2.0.

  Next, a laser beam was irradiated in a dot shape to a position facing the formation position of the finger electrode 5b on the back surface 9b side of the semiconductor substrate 1 to form a recess 10. One hole constituting the recess 10 had a diameter of 100 μm, a depth of 50 μm (Example 1), 100 μm (Example 2), and 150 μm (Example 3).

Next, a back surface passivation film 8 made of an aluminum oxide film was formed on the back surface side 9b using trimethylaluminum (TMA) and ozone (O ₃ ) as raw materials and using the ALD method. The back surface passivation film 8 had a thickness of 30 nm and a refractive index of 1.6.
Further, a silver paste was applied to the front surface 9a of the semiconductor substrate 1 and an aluminum paste was applied and baked at a position other than the opening of the back surface 9b to form the first electrode 5, the BSF region 7, and the back current collecting electrode 6b. Further, a silver paste was applied to the back surface 9b and fired to form a back surface output extraction electrode 6a. The back surface collecting electrode 6b was finger-shaped with a width of 150 μm, and the pitch was 1 mm.

  Next, Comparative Example 1 in Table 2 is a solar cell element having the structure shown in FIG. 4, and the BSF region 7 and the second electrode 6 are formed on the back surface of the semiconductor substrate 1 without forming the recess 10 shown in FIG. 3. Was produced in the same manner as in Examples 1 to 3 except that was formed on substantially the entire back surface side 9b of the semiconductor substrate 1.

  Comparative Examples 2 to 5 in Table 2 are solar cell elements having the structure shown in FIG. 5, and the BSF region 7 and the second electrode 6 having the recesses shown in FIG. It was produced in the same manner as in Examples 1 to 3 except that it was formed.

  Here, the light-shielding area by the finger electrodes 5b of Comparative Examples 1 to 5 and Examples 1 to 3 was all about 7% with respect to the entire light receiving surface.

  Table 2 shows the results of measuring Jsc, Voc, FF and conversion efficiency for Examples 1 to 3 and Comparative Examples 1 to 5 produced as described above. Note that Jsc in Table 2 is different from Jsc in Table 1 and is effective Jsc including the influence of light shielding of the finger electrode 5b.

  As is apparent from Table 2, it was confirmed that Examples 1 to 3 were improved with respect to all of Jsc, Voc, FF and conversion efficiency with respect to Comparative Examples 2 to 4. In addition, Examples 1 to 3 showed higher results in Jsc and conversion efficiency than all Comparative Examples 1 to 5, and the effects of this embodiment could be confirmed.

1: Semiconductor substrate 2: First semiconductor layer (reverse conductivity type semiconductor layer)
3: Second semiconductor layer (one conductivity type semiconductor layer)
4: Antireflection layer 5: First electrode (surface electrode)
5a: Bus bar electrode 5b: Finger electrode 5c: Auxiliary electrode 6: Second electrode (back electrode)
6a: Back surface output extraction electrode 6b: Back surface collecting electrode 7: BSF region 8: Back surface passivation layer 9a: Light receiving surface (front surface) side 9b: Non-light receiving surface (back surface) side 10: Recess

Claims (6)

A solar cell element in which a linear first electrode is provided on a light receiving surface side of a semiconductor substrate, and a linear second electrode is provided on a back surface side of the semiconductor substrate,
On the back side of the semiconductor substrate,
A concave portion whose surface layer is a passivation layer is provided along the first electrode in a portion that overlaps with the first electrode when seen in a plan view.
Wherein the second electrode, the solar cell element, characterized in that provided along said recess portion to avoid a site overlapping with the first electrode in plan perspective.   The semiconductor substrate has a one conductivity type semiconductor layer and a reverse conductivity type semiconductor layer, the first electrode is in contact with the one conductivity type semiconductor layer, and the second electrode is in contact with the reverse conductivity type semiconductor layer. The solar cell element according to claim 1.   The region of the one-conductivity-type semiconductor layer that is in contact with the first electrode is a region in which the concentration of impurities exhibiting one conductivity-type in the one-conductivity-type semiconductor layer is higher than other regions. 2. The solar cell element according to 2.   4. The solar cell according to claim 2, wherein in the reverse conductivity type semiconductor layer, a region having a concentration of an impurity exhibiting the reverse conductivity type is higher than other regions along the concave portion. element.   The region of the reverse conductivity type semiconductor layer that is in contact with the second electrode is a region in which the concentration of impurities exhibiting the reverse conductivity type is higher than other regions in the reverse conductivity type semiconductor layer. Item 5. The solar cell element according to any one of Items 2 to 4.   6. The solar cell element according to claim 1, wherein the concave portion includes a plurality of holes provided along the first electrode.