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WO2011046091A1 - Dispositif à aimants - Google Patents

Dispositif à aimants Download PDF

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Publication number
WO2011046091A1
WO2011046091A1 PCT/JP2010/067788 JP2010067788W WO2011046091A1 WO 2011046091 A1 WO2011046091 A1 WO 2011046091A1 JP 2010067788 W JP2010067788 W JP 2010067788W WO 2011046091 A1 WO2011046091 A1 WO 2011046091A1
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WO
WIPO (PCT)
Prior art keywords
magnetic
magnetic shield
shield
substrate
curved region
Prior art date
Application number
PCT/JP2010/067788
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English (en)
Japanese (ja)
Inventor
敬仁 渡邊
眞子　隆志
Original Assignee
日本電気株式会社
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Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP2011536127A priority Critical patent/JPWO2011046091A1/ja
Publication of WO2011046091A1 publication Critical patent/WO2011046091A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the present invention relates to a magnetic device.
  • the present invention relates to a magnetic device provided with a magnetic shield.
  • a magnetic element using a magnetic substance is known.
  • a magnetoresistive element Magnetic Resistance Element
  • a typical magnetoresistive element has a structure in which a non-magnetic layer is sandwiched between two magnetic layers. One magnetic layer is a magnetization fixed layer whose magnetization direction is fixed, and the other is a magnetization free layer whose magnetization direction can be reversed.
  • the resistance value of the magnetoresistive element configured in this way is higher when the magnetization fixed layer and the magnetization free layer are antiparallel than when the magnetization directions are parallel to each other.
  • a magnetic random access memory (MRAM) and various logic circuits can be configured.
  • a magnetic shield In a magnetic device using a magnetic element, it is important to prevent the magnetization state (magnetization direction, etc.) of the magnetic material from fluctuating due to external disturbances for its normal operation.
  • a “magnetic shield” is generally used.
  • Patent Document 1 Japanese Patent Laid-Open No. 2003-124538 discloses an information storage device in which the surface of a resin for sealing an MRAM chip is curved.
  • a resin mixed with high permeability powder is used for the resin sealing of the MRAM chip.
  • the periphery of the MRAM chip is hardened with a sealing resin mixed with a high magnetic permeability powder.
  • Patent Document 2 Japanese Patent Application Laid-Open No. 2003-309196 discloses a magnetic shield package of a magnetic nonvolatile memory element.
  • FIG. 1 shows a cross-sectional structure of the magnetic shield package.
  • the magnetic shield package 110 includes an MRAM element 111, a wire 112, a lead frame 113, and a magnetic shield 114.
  • the MRAM element 111 is connected to the lead frame 113 by a wire 112. Further, the entire periphery of the MRAM element 111 is surrounded by a hollow magnetic shield 114.
  • the magnetic shield 114 is made of an insulating soft magnetic material and has a rectangular cross-sectional shape as shown in FIG.
  • Patent Document 1 has the following problems. That is, in the information storage device described in Patent Document 1, the surface of the resin that seals the MRAM chip is curved, but the periphery of the MRAM chip is solidified with a sealing resin mixed with high magnetic permeability powder. In addition, there is no space with low magnetic permeability between the sealing resin and the MRAM chip. In the case of this structure, a shielding effect against a high-frequency magnetic field variation may be obtained, but a shielding effect against a static magnetic field cannot be obtained. This is because the magnetic flux of the static magnetic field is concentrated in the high permeability region. Since the high magnetic permeability resin surrounding the MRAM chip concentrates the magnetic flux of the static magnetic field around the MRAM chip, the MRAM chip does not have a shielding effect but rather damages the MRAM chip.
  • An object of the present invention is to provide a technique capable of further improving the shielding effect in a magnetic device including a magnetic shield.
  • a magnetic device in one aspect of the present invention, includes a substrate, at least one magnetic element mounted on the first main surface of the substrate, and a magnetic shield of a soft magnetic material disposed on the first main surface side of the substrate.
  • the magnetic shield includes a curved region that curves so as to be convex when viewed from the substrate.
  • the curved region includes at least a region where the magnetic shield and the magnetic element overlap when viewed from the top surface of the substrate.
  • the space between the magnetic shield and the magnetic element is magnetically hollow.
  • the shielding effect is further improved in the magnetic device including the magnetic shield.
  • FIG. 1 is a cross-sectional view showing a typical magnetic shield package according to the related art.
  • FIG. 2 is a cross-sectional view showing the structure of the magnetic device according to the embodiment of the present invention.
  • FIG. 3 is a perspective view showing an example of the shape of the magnetic shield according to the present embodiment.
  • FIG. 4 is a perspective view showing another example of the shape of the magnetic shield according to the present embodiment.
  • FIG. 5 is a cross-sectional view showing the structure of the magnetic device according to the present embodiment.
  • FIG. 6 is a schematic diagram for explaining the effect of the magnetic shield according to the present embodiment.
  • FIG. 7 is a schematic diagram for explaining the simulation conditions.
  • FIG. 8 is a schematic diagram for explaining the simulation conditions.
  • FIG. 9 is a graph showing the curvature dependency of the shielding effect.
  • FIG. 10 is a graph showing the thickness dependence of the shielding effect.
  • FIG. 11 is a cross-sectional view showing a first modification of the magnetic device according to the present embodiment.
  • FIG. 12 is a cross-sectional view showing a second modification of the magnetic device according to the present embodiment.
  • FIG. 13 is a cross-sectional view showing a third modification of the magnetic device according to the present embodiment.
  • FIG. 14 is a cross-sectional view showing a fourth modification of the magnetic device according to the present embodiment.
  • FIG. 15 is a cross-sectional view showing a fifth modification of the magnetic device according to the present embodiment.
  • FIG. 16 is a cross-sectional view showing an example of a package of the magnetic device according to the present embodiment.
  • FIG. 11 is a cross-sectional view showing a first modification of the magnetic device according to the present embodiment.
  • FIG. 12 is a cross-sectional view showing a second modification of the magnetic device according to the present embodiment.
  • FIG. 13 is a cross-section
  • FIG. 17 is a cross-sectional view showing another example of the package of the magnetic device according to the present embodiment.
  • FIG. 18 is a cross-sectional view showing still another example of the package of the magnetic device according to the present embodiment.
  • FIG. 19 is a perspective view showing still another example of the package of the magnetic device according to the present embodiment.
  • FIG. 2 is a cross-sectional view showing the structure of the magnetic device 1 according to the embodiment of the present invention.
  • the magnetic device 1 includes a substrate 10, a magnetic element 20, and a magnetic shield 30.
  • the direction perpendicular to the surface of the substrate 10 is the Z direction
  • the plane directions perpendicular to the Z direction are the X direction and the Y direction.
  • the substrate 10 is a member on which the magnetic element 20 is mounted.
  • Examples of the substrate 10 include a wiring substrate, a lead frame, and a semiconductor substrate.
  • the substrate 10 has a first main surface (front surface) 11 on which the magnetic element 20 is mounted, and a second main surface (back surface) 12 opposite to the first main surface 11. ing.
  • the magnetic element 20 is an element using a magnetic material.
  • Examples of the magnetic element 20 include a magnetoresistive element, an MRAM chip, and a logic circuit using the magnetoresistive element.
  • at least one magnetic element 20 is mounted on the first main surface 11 of the substrate 10.
  • the magnetic shield 30 is made of a soft magnetic material.
  • This soft magnetic material has a sufficiently high relative magnetic permeability (preferably 1000 or more).
  • the soft magnetic material include iron, nickel, silicon steel, permalloy, ferrite, amorphous magnetic alloy, and nanocrystal magnetic alloy. If there is a concern about a short circuit between the magnetic shield 30 and an internal structure such as a bonding wire, an insulating magnetic material (ferrite, etc.) may be used as the material of the magnetic shield 30.
  • the surface of the magnetic shield 30 made of a conductive magnetic material may be coated with an insulator.
  • the magnetic shield 30 is at least disposed on the first main surface 11 side of the substrate 10. Furthermore, at least a part of the magnetic shield 30 is curved so as to be convex when viewed from the substrate 10.
  • the region where the magnetic shield 30 is curved is hereinafter referred to as “curved region RC”.
  • the curved region RC includes at least a region where the magnetic shield 30 and the magnetic element 20 overlap. In other words, the curved portion of the magnetic shield 30 covers the upper side of the magnetic element 20. In the example shown in FIG. 2, the curved region RC extends over the entire area of the magnetic shield 30.
  • FIG. 3 and 4 are perspective views showing examples of the shape of the magnetic shield 30.
  • the magnetic shield 30 has a dome shape.
  • the magnetic shield 30 has a tunnel shape (partial cylindrical shape).
  • the space MC between the magnetic shield 30 and the magnetic element 20 is “magnetically hollow”, and is hereinafter referred to as “magnetic cavity space MC”.
  • Magneticically hollow means that the magnetic permeability is extremely low (relative magnetic permeability ⁇ 1) compared to the magnetic shield 30 having high magnetic permeability (relative magnetic permeability> 1000).
  • the magnetic cavity space MC is physically hollow.
  • the magnetic cavity space MC may be filled with a nonmagnetic insulator 40.
  • the nonmagnetic insulator 40 is, for example, a molding resin.
  • the magnetic shield 30 has the curved region RC that is curved in a convex shape when viewed from the substrate 10. Therefore, the external magnetic field He in the Z direction is not perpendicular to the surface of the magnetic shield 30 at almost all positions in the curved region RC. As a result, as shown in FIG. 6, the magnetic flux of the external magnetic field He is efficiently guided into the high magnetic permeability magnetic shield 30 without penetrating the magnetic shield 30. In other words, the magnetic flux of the external magnetic field He is bent by the magnetic shield 30 in a direction away from the Z direction. In particular, since the curved region RC covers the magnetic element 20, the magnetic flux of the external magnetic field He is bent in a direction away from the magnetic element 20 above the magnetic element 20.
  • the magnetic permeability of the magnetic cavity space MC between the magnetic shield 30 and the magnetic element 20 is extremely lower than the magnetic permeability of the magnetic shield 30. Therefore, the magnetic flux once guided into the magnetic shield 30 having high permeability is effectively prevented from leaking into the magnetic cavity space MC.
  • the magnetic flux of the external magnetic field He reaching the vicinity of the magnetic element 20 is greatly reduced. That is, the shielding effect by the magnetic shield 30 is improved. For this reason, when an MRAM chip using a perpendicular magnetization film is employed as the magnetic element 20, the magnetic shield 30 of the present embodiment is particularly suitable.
  • the inventors of the present application have demonstrated the effect of this embodiment through simulation.
  • 7 and 8 are diagrams for explaining the simulation conditions.
  • the shape of the magnetic shield 30 is the tunnel shape (partial cylindrical shape) shown in FIG.
  • the length of the cylinder in the longitudinal direction is 20 mm.
  • the radius of curvature of the inner diameter of the cylinder is r [mm], and the curvature is 1 / r [/ mm].
  • the thickness of the magnetic shield 30 is d [mm].
  • the relative permeability of the magnetic shield 30 is 2000, and its saturation magnetization is 1 [T].
  • a magnet was disposed at a position 20 mm away from the bottom of the magnetic shield 30 in the Z direction.
  • the magnet has a plane area of 20 mm ⁇ 28 mm and a thickness of 50 mm.
  • the coercive force of the magnet is 3000 [Oe], and the residual magnetization is 4000 [G].
  • the shielding effect against the vertical magnetic field generated by this magnet was investigated.
  • FIG. 9 is a graph showing the curvature dependency of the shielding effect.
  • the vertical axis represents the vertical magnetic field [Oe] near the element, and the horizontal axis represents the curvature 1 / r [/ mm].
  • the thickness d is fixed at 0.15 mm.
  • FIG. 9 shows that the shielding effect is enhanced by curving the magnetic shield. However, if the curvature is too large, the shielding effect tends to weaken. A sufficient shielding effect is obtained when the curvature is 0.06 [/ mm] or less, which is preferable.
  • FIG. 10 is a graph showing the thickness dependence of the shielding effect.
  • the vertical axis represents the vertical magnetic field [Oe] near the element, and the horizontal axis represents the thickness d [mm].
  • the curvature radius r is fixed at 26 mm.
  • FIG. 10 shows that a certain thickness d is necessary to obtain a sufficient shielding effect.
  • the thickness d is 0.1 mm or less, the magnetic shield 30 is considered to be in a saturated state.
  • the demagnetizing field component inside the magnetic shield 30 is considered to be weak.
  • the shielding effect by the magnetic shield is improved.
  • the shielding effect is not limited to the external magnetic field in the Z direction.
  • the curved magnetic shield 30 achieves the same shielding effect for all directions.
  • FIG. 11 is a cross-sectional view showing a first modification example of the magnetic device 1.
  • the curved region RC may be only a part of the magnetic shield 30. Even in that case, the curved region RC includes at least a region where the magnetic element 20 and the magnetic shield 30 overlap.
  • FIG. 12 is a cross-sectional view showing a second modification example of the magnetic device 1.
  • magnetic shields 30 may be provided on both sides of the substrate 10 as shown in FIG. More specifically, the first magnetic shield 30A is arranged on the first main surface 11 side, and the second magnetic shield 30B is arranged on the second main surface 12 side.
  • Each of the magnetic shields 30 ⁇ / b> A and 30 ⁇ / b> B is the same as the magnetic shield 30. That is, each of the magnetic shields 30 ⁇ / b> A and 30 ⁇ / b> B is curved so as to be convex as viewed from the substrate 10.
  • the space MC between each of the magnetic shields 30A and 30B and the substrate 10 is magnetically hollow. According to this modification, the shielding effect is further improved.
  • FIG. 13 is a cross-sectional view showing a third modification of the magnetic device 1.
  • the outer peripheral surface of the magnetic shield 30 (surface opposite to the magnetic cavity space MC side) is covered with an external mold resin 50. Thereby, corrosion of the magnetic shield 30 is prevented, and workability is also improved.
  • magnetic powder may be mixed in the external mold resin 50 outside the magnetic shield 30. That is, the outer peripheral surface of the magnetic shield 30 (surface opposite to the magnetic cavity space MC side) may be covered with the external mold resin 50 mixed with magnetic powder. Thereby, the shielding effect as a whole further increases. Further, the magnetic flux emitted from the end of the magnetic shield 30 can be collected not on the magnetic cavity space MC but on the external mold resin 50 side due to the difference in magnetic permeability. The penetration of the magnetic flux into the magnetic cavity space MC is further suppressed, which is preferable.
  • FIG. 14 is a cross-sectional view showing a fourth modified example of the magnetic device 1.
  • the magnetic shield 30 is a metal magnetic shield formed of a conductive magnetic material.
  • the metal magnetic shield 30 is grounded.
  • the ground pad 61 is provided on the substrate 10, and the metal magnetic shield 30 is electrically connected to the ground pad 61 via the solder 62.
  • the grounded metal magnetic shield 30 also serves as an electromagnetic wave shield, which is preferable.
  • FIG. 15 is a cross-sectional view showing a fifth modification of the magnetic device 1.
  • a plurality of magnetic elements 20 are mounted on the substrate 10, and the magnetic shield 30 is provided in common so as to cover all of the plurality of magnetic elements 20.
  • two MRAM chips 20-1 and 20-2 are mounted on the wiring board 10, and the magnetic shield 30 is provided in common so as to cover both of the MRAM chips 20-1 and 20-2.
  • FIG. 15 shows a mode in which two MRAM chips 20-1 and 20-2 are arranged in the X-axis direction, but a mode in which a plurality of MRAM chips are arranged in the Y-axis direction, 2 in the X-axis direction and the Y-axis direction.
  • a dimensional arrangement is also possible.
  • FIG. 16 shows an example of a BGA (Ball Grid Array) package.
  • a magnetic element 20 is mounted on a wiring board 10 having solder balls 71 as external terminals.
  • the magnetic element 20 is, for example, an MRAM chip using a perpendicular magnetization film.
  • the adhesive layer 72 between the wiring board 10 and the MRAM chip 20 is DAF (Die Attach Film) or DAP (Die Attach Paste).
  • the MRAM chip 20 is electrically connected to the wiring board 10 via bonding wires 73.
  • the magnetic cavity space MC between the magnetic shield 30 and the wiring board 10 may be physically hollow or filled with a nonmagnetic insulator 40.
  • a nonmagnetic insulator 40 When a short circuit between the magnetic shield 30 and the bonding wire 73 is a concern, an insulating magnetic material (ferrite, etc.) may be used as the material of the magnetic shield 30.
  • the surface of the magnetic shield 30 made of a conductive magnetic material may be coated with an insulator.
  • the magnetic shield 30 may be fixed to the wiring board 10 with an adhesive 74.
  • the adhesive 74 may be omitted.
  • the magnetic shield 30 is a metal magnetic shield, the metal magnetic shield 30 is electrically connected to the ground pad of the wiring board 10 via a conductive member (solder, conductive resin, conductive adhesive, etc.). It may be connected.
  • the outer peripheral surface of the magnetic shield 30 may be covered with an external mold resin 50 mixed with magnetic powder.
  • FIG. 17 shows an example of FCBGA (Flip Chip Chip Ball Grid Array) package.
  • a magnetic element 20 is mounted on a wiring board 10 having solder balls 81 as external terminals.
  • the magnetic element 20 is, for example, an MRAM chip using a perpendicular magnetization film.
  • Solder bumps 82 as connection terminals are formed on the MRAM chip 20, and the MRAM chip 20 is electrically connected to the wiring substrate 10 via the solder bumps 82.
  • the magnetic cavity space MC between the magnetic shield 30 and the wiring board 10 may be physically hollow or filled with a nonmagnetic insulator 40.
  • the magnetic shield 30 may be fixed to the wiring board 10 with an adhesive 84.
  • the adhesive 84 may not be required.
  • the magnetic shield 30 is a metal magnetic shield, the metal magnetic shield 30 is electrically connected to the ground pad of the wiring board 10 via a conductive member (solder, conductive resin, conductive adhesive, etc.). It may be connected.
  • the outer peripheral surface of the magnetic shield 30 may be covered with an external mold resin 50 mixed with magnetic powder.
  • FIG. 18 shows an example of QFP (Quad Flat Package).
  • a magnetic element 20 is mounted on a die pad 91 corresponding to the substrate 10.
  • the magnetic element 20 is, for example, an MRAM chip using a perpendicular magnetization film.
  • the adhesive layer 92 between the die pad 91 and the MRAM chip 20 is DAF or DAP.
  • the MRAM chip 20 is electrically connected to a lead frame 95 as an external terminal via a bonding wire 93.
  • the magnetic shield 30 is placed on the lead frame 95. Therefore, it is desirable that the magnetic shield 30 is formed of an insulating magnetic material, or the conductive magnetic shield 30 is coated with an insulating material.
  • the magnetic shield 30 may be fixed to the lead frame 95 with an insulating adhesive 94.
  • the magnetic cavity space MC inside the magnetic shield 30 may be physically hollow or may be filled with a nonmagnetic insulator 40.
  • the outer peripheral surface of the magnetic shield 30 may be covered with an external mold resin 50 mixed with magnetic powder.
  • the first magnetic shield 30A and the second magnetic shield 30B are respectively disposed on both sides of the die pad 91 (substrate 10).
  • the second magnetic shield 30B is removed, the effects of the present invention can be obtained.
  • FIG. 19 shows an example of a multichip module package.
  • a plurality of MRAM chips 20 ⁇ / b> A are mounted on the substrate 10.
  • the MRAM chip 20A and another semiconductor chip 20B may be mixedly mounted in one package.
  • the magnetic shield 30 is provided so as to cover all the chips.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

L'invention concerne un dispositif à aimants comprenant un substrat, au moins un élément d'aimant monté sur une première surface principale du substrat et un écran magnétique faiblement ferromagnétique disposé du côté première surface principale du substrat. L'écran magnétique comprend une région incurvée de courbure convexe vue du substrat. La région incurvée comprend au moins la région où l'écran magnétique et un élément d'aimant se recouvrent, lorsqu'ils sont vus depuis une position située au-dessus de la surface supérieure du substrat. L'espace entre l'écran magnétique et l'élément d'aimant constitue une cavité magnétique.
PCT/JP2010/067788 2009-10-13 2010-10-08 Dispositif à aimants WO2011046091A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011536127A JPWO2011046091A1 (ja) 2009-10-13 2010-10-08 磁性体装置

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Application Number Priority Date Filing Date Title
JP2009236326 2009-10-13
JP2009-236326 2009-10-13

Publications (1)

Publication Number Publication Date
WO2011046091A1 true WO2011046091A1 (fr) 2011-04-21

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PCT/JP2010/067788 WO2011046091A1 (fr) 2009-10-13 2010-10-08 Dispositif à aimants

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Country Link
JP (1) JPWO2011046091A1 (fr)
WO (1) WO2011046091A1 (fr)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013145844A (ja) * 2012-01-16 2013-07-25 Dainippon Printing Co Ltd 半導体装置
JP2014036192A (ja) * 2012-08-10 2014-02-24 Toshiba Corp 不揮発性半導体記憶装置
JP2015053450A (ja) * 2013-09-09 2015-03-19 株式会社東芝 半導体装置及びその製造方法
JP2015065223A (ja) * 2013-09-24 2015-04-09 株式会社東芝 半導体装置及びその製造方法
JP2016148687A (ja) * 2016-05-27 2016-08-18 株式会社東芝 素子パッケージ及び電気回路
JP2016171114A (ja) * 2015-03-11 2016-09-23 新光電気工業株式会社 半導体装置
JP2017167021A (ja) * 2016-03-17 2017-09-21 Tdk株式会社 磁気センサ
US10070230B2 (en) 2012-11-20 2018-09-04 Kabushiki Kaisha Toshiba Microphone package
EP4421867A1 (fr) * 2023-02-27 2024-08-28 GLOBALFOUNDRIES Singapore Pte. Ltd. Blindages magnétiques pour circuits intégrés

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WO1997040654A1 (fr) * 1996-04-24 1997-10-30 Okamura, Susumu Dispositif a semi-conducteurs
JP2003124538A (ja) * 2001-10-16 2003-04-25 Sony Corp 情報記憶装置およびその情報記憶装置を実装した電子機器
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JP2004349476A (ja) * 2003-05-22 2004-12-09 Toshiba Corp 半導体装置
JP2005531928A (ja) * 2002-06-28 2005-10-20 モトローラ・インコーポレイテッド 磁性体を含む電子回路の磁気遮蔽

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WO1997040654A1 (fr) * 1996-04-24 1997-10-30 Okamura, Susumu Dispositif a semi-conducteurs
JP2003124538A (ja) * 2001-10-16 2003-04-25 Sony Corp 情報記憶装置およびその情報記憶装置を実装した電子機器
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JP2005531928A (ja) * 2002-06-28 2005-10-20 モトローラ・インコーポレイテッド 磁性体を含む電子回路の磁気遮蔽
JP2004349476A (ja) * 2003-05-22 2004-12-09 Toshiba Corp 半導体装置

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013145844A (ja) * 2012-01-16 2013-07-25 Dainippon Printing Co Ltd 半導体装置
JP2014036192A (ja) * 2012-08-10 2014-02-24 Toshiba Corp 不揮発性半導体記憶装置
US10070230B2 (en) 2012-11-20 2018-09-04 Kabushiki Kaisha Toshiba Microphone package
JP2015053450A (ja) * 2013-09-09 2015-03-19 株式会社東芝 半導体装置及びその製造方法
JP2015065223A (ja) * 2013-09-24 2015-04-09 株式会社東芝 半導体装置及びその製造方法
JP2016171114A (ja) * 2015-03-11 2016-09-23 新光電気工業株式会社 半導体装置
US9659880B2 (en) 2015-03-11 2017-05-23 Shinko Electric Industries Co., Ltd. Semiconductor device
JP2017167021A (ja) * 2016-03-17 2017-09-21 Tdk株式会社 磁気センサ
WO2017158900A1 (fr) * 2016-03-17 2017-09-21 Tdk株式会社 Capteur magnétique
CN108780128A (zh) * 2016-03-17 2018-11-09 Tdk株式会社 磁传感器
JP2016148687A (ja) * 2016-05-27 2016-08-18 株式会社東芝 素子パッケージ及び電気回路
EP4421867A1 (fr) * 2023-02-27 2024-08-28 GLOBALFOUNDRIES Singapore Pte. Ltd. Blindages magnétiques pour circuits intégrés

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