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WO2008001363A2 - Mémoire flash monolithique ayant des parties de mémoire de code et de mémoire de données intégrées - Google Patents

Mémoire flash monolithique ayant des parties de mémoire de code et de mémoire de données intégrées Download PDF

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Publication number
WO2008001363A2
WO2008001363A2 PCT/IL2007/000778 IL2007000778W WO2008001363A2 WO 2008001363 A2 WO2008001363 A2 WO 2008001363A2 IL 2007000778 W IL2007000778 W IL 2007000778W WO 2008001363 A2 WO2008001363 A2 WO 2008001363A2
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WO
WIPO (PCT)
Prior art keywords
memory
memory portion
chip according
data
coupled
Prior art date
Application number
PCT/IL2007/000778
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English (en)
Other versions
WO2008001363A3 (fr
Inventor
Rony Levy
Lior Kruh
Adir Raz
Shlomo Berkovitch
Original Assignee
Kdr Flashware Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kdr Flashware Ltd. filed Critical Kdr Flashware Ltd.
Publication of WO2008001363A2 publication Critical patent/WO2008001363A2/fr
Publication of WO2008001363A3 publication Critical patent/WO2008001363A3/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells

Definitions

  • This invention relates to memory chips.
  • Flash memories are classified into two types, namely, a NAND- type and a NOR-type, in accordance with the logical configuration of the memory cells within the memory.
  • NOR-type flash memory each of the memory cells is connected to a corresponding word line and bit line and is independent of adjacent memory cells.
  • each string which contains multiple memory cells
  • each memory cell individually is connected to a corresponding bit line through a bit-line contact. Consequently, the NOR-type flash memory requires a greater number of contacts in order to couple the bit lines and memory cells together than the NAND-type flash memory.
  • the NAND-type flash memory is therefore superior to the NOR-type flash memory in integration density.
  • US 2005/052934 discloses a Unified Memory that may store multiple types of content such as data or fast code or slow code in a common array, a tag bit being used to indicate the type of content such as data or fast code or slow code or single level or multilevel content.
  • Sense amplifiers may be configurable based on the type of data being read.
  • US Pat. No. 6,937,513 discloses a semiconductor memory device that includes a NOR array of memory cells and a NAND array of memory cells configured on the same monolithic semiconductor substrate. Each cell of the NOR array involves a single transistor, similar to each cell of the NAND array.
  • the memory device is, therefore, an integrated circuit that includes not only the NOR and NAND arrays, but also the row and column decoders corresponding to each array. Furthermore, the integrated circuit includes the interface circuitry needed to transfer information as pages into and from the NAND array.
  • the corresponding interface or controller is implemented on the same monolithic substrate as both the NAND array and the NOR array. Addresses targeted for the NOR array are sent as fully memory-mapped data into the NOR array, whereas addresses targeted for the NAND array are sent through the controller integrated within the semiconductor memory device.
  • the single transistor cell of both the NAND array and NOR array preferably involves a flash EEPROM-type transistor that implements a floating gate dielectrically spaced between a control gate and the semiconductor substrate.
  • US Pat. No. 5,982,663 also discloses a nonvolatile memory having a memory field and a redundant field within a single semiconductor chip.
  • the redundant field is used to store essential information regarding device formulation or address mapping.
  • the nonvolatile memory includes a programming circuit capable of program- ming and verifying a selected memory cell within the redundant field with single-bit data while a selected memory cell within the memory field is being programmed and verified with multi-bit data.
  • the nonvolatile memory also includes a reading circuit capable of reading single-bit data from a selected memory cell within the redundant field while multi-bit data is read from a selected memory cell within the memory field.
  • US 2001/055223 describes a nonvolatile semiconductor memory that provides good background description relating to NAND and NOR flash memories.
  • SONOS Silicon-Oxide-Nitride-Oxide-Silicon technology
  • EEPROM electrically reprogrammable memory cells
  • the invention provides a memory with integration for storing code and data on one chip.
  • the memory system also includes a plurality of memory array or one memory array only depending on the application.
  • the array always include a NAND array for storing data, the code array on the other hand can be different types of memory such as:
  • NOR, ROM, OTP, NTP, PROM One configuration is only NAND array with DCA feature which allows code to be stored in NAND memory without ECC and with direct access.
  • the DCA is a configurable memory that allows the system to store code on the non- volatile memory at any time.
  • a memory chip comprising: a first memory portion fabricated using charge trapping technology and having a first set of addresses, the first memory portion being configured using NAND memory cell array architecture, a second memory portion fabricated using charge trapping technology and having a second set of addresses that are distinct from the first set of addresses, a buffer memory portion coupled to the first memory portion for temporary storage of blocks of data that are written to or read from the first memory portion, registers coupled to the first memory portion and to the buffer memory portion for storing an instruction for controlling the first memory portion, and a first interface coupled to the first memory portion through the RAM buffer, to the second memory portion, to the buffer memory portion and to the registers and having an address bus for receiving an address within the first set of addresses or the second set of addresses and having a data bus for conveying data to and from the first memory portion or the second memory portion according to said address; all of said first memory portion, said second memory portion, said buffer memory portion, said registers and said first interface being fabricated on a single
  • a memory chip comprising: a first memory portion having a first set of addresses, the first memory portion being configured using NAND technology and including a high reliability sub-portion and wherein there is further included a decoder (XDA) coupled to the high reliability sub-portion and being responsive to an address of a specified byte or word for addressing a single word line of the high reliability sub-portion containing said byte or word so as to read said single word line and extract therefrom the specified byte or word, a buffer memory portion coupled to the first memory portion for temporary storage of blocks of data that are written to or read from the first memory portion, registers coupled to the first memory portion and to the buffer memory portion for storing an instruction for controlling the first memory portion, and a first interface coupled to the first memory portion, to the buffer memory portion and to the registers and having an address bus for receiving an address within the first set of addresses and having a data bus for conveying data to and from the first memory portion according to said address; all of said first memoi
  • XDA decoder
  • a memory chip comprising: a first memory portion having a first set of addresses, the first memory portion being configured using NAND technology, a second memory portion having a second set of addresses that are distinct from the first set of addresses, a buffer memory portion coupled to the first memory portion for temporary storage of blocks of data that are written to or read from the first memory portion, registers coupled to the first memory portion and to the buffer memory portion for storing an instruction for controlling the first memory portion, a first interface coupled to the first memory portion, to the second memory portion, to the buffer memory portion and to the registers and having an address bus for receiving an address within the first set of addresses or the second set of addresses and having a data bus for conveying data to and from the first memory portion or the second memory portion according to said address; and a second interface coupled to the buffer memory portion and to the registers and adapted to provide access to the first memory portion simultaneous with access via the first interface to the second memory portion; all of said first memory portion, said second memory portion, said buffer memory
  • Fig. 1 is a block diagram illustrating a memory system with data storage and code storage according to a first embodiment
  • Fig. 2 is a block diagram illustrating operation of the XDA block
  • Fig. 3 is a block diagram illustrating a memory system according to a variation of the first embodiment shown in Fig. 1 ;
  • Fig. 4 is a block diagram illustrating a NAND flash memory system according to a second embodiment the invention.
  • Fig. 5 is a diagram illustrating the address decoder
  • Fig. 6 is a block diagram illustrating a memory system having a jump prediction mechanism according to a third embodiment of the invention.
  • Fig. 7 is a block diagram illustrating a memory system according to a variation of the third embodiment shown in Fig. 5;
  • Fig. 8 is a flow chart showing the principal operations carried out by the jump prediction mechanism shown in Fig. 5.
  • Fig. 1 is a block diagram showing a monolithic memory chip 10 comprising a data array 11 (constituting a first memory portion) configured using NAND technology and a code array 12 (constituting a second memory portion).
  • the data array 11 is fabricated using any suitable charge trapping technology such as, for example, Silicon-Oxide-Nitride-Oxide-Silicon technology (SONOS) or NROM.
  • the data array 11 includes a Dynamic Code Allocation unit (DCA) 13 which allows code to be stored in NAND memory without the need for Error Correction Code (ECC) as is conventionally required and with direct access.
  • DCA Dynamic Code Allocation unit
  • the DCA 13 is a configurable memory that allows the memory chip 10 to store code in the non- volatile memory at any time.
  • the DCA 13 is a dynamically configurable NAND Flash memory each of whose memory cells can be configured to store 1 or 2 bits, so as to provide the same high reliability as the code array 12 that is typically configured using NOR technology. This is achieved by use of a custom write/erase algorithm for writing data to the DCA 13 and that eliminates errors and other interferences associated with bit failures in flash memory.
  • a RAM page buffer 14 is coupled via a control logic unit 15 to the data array 11 and allows the data array 11 to be accessed in a similar manner as the code array 12, without the need for special interface lines as are required in a conventional NAND flash memory.
  • An input of the RAM page buffer 14 is coupled to an address decoder 16, which is also coupled directly to the code array 12 and via an XDA 17 to the DCA 13.
  • the address decoder 16 is likewise coupled via control registers 18 to the control logic unit 15 and to the XDA 17, which serves to interface the address decoder 16 to the DCA 13.
  • control registers 18 are coupled via the control logic unit 15 to the first memory portion constituted by the data array 11 and to the buffer memory portion constituted by the RAM page buffer 14 for storing an instruction for controlling the first memory portion.
  • the XDA 17 provides random access of a single word in the DCA 13 by direct addressing through an additional external address pin. In other words, the XDA 17 provides a mechanism for extracting a single word with at least 8 bits from the NAND array without the need to read a whole page, as is conventionally required and thus provides much faster access. Improved performance of the XDA 17 is achieved by dividing the NAND array 11 to two parts to reduce the capacitance of the data lines.
  • the capacitance is increased if more transistors are tied to the I/O (input/output) lines. Since capacitance decreases the access speed, reducing the capacitance increases the speed of the I/O lines.
  • the first memory portion is a data array that allows relatively slow read and fast write data access
  • the second memory portion is a code array that allows fast random access while maintaining substantially zero bit failure.
  • the read operation from the code array is a fast read and the write and erase operations are relatively slow as in conventional NOR-based flash memories.
  • the data array is mapped in pages as in conventional NAND flash memories (data flash) all the read and write operations are in page size not in byte/word size like the code array.
  • the erase operation of the data array is in block mode, every block consisting of a number of pages.
  • the page mode operations give the memory chip 10 a fast write and erase operation similar to standard NAND flash.
  • XIP can be done from the memory chip 10 through the code array address.
  • a RAM page buffer is included to buffer the page operations from the data array in the background and free the bus of the memory chip 10 for code read operations.
  • the access to the RAM buffer is similar to the access to the code array in a word/byte random access memory, whereby the same bus can operate the code and data arrays unlike standard NAND flash that has a multiplex interface.
  • the NAND array 11 is configured to store 4 bits per cell allowing fast data access but at the price of requiring Error Correction Code (ECC).
  • ECC Error Correction Code
  • Multiple-bit memory structures and their operation are known per se and are described, for example, in above-referenced US Pat. No. 5,982,663.
  • the DCA 13 may employ a single bit structure that results in slower but completely reliable read and write operations that obviate the need for error correction.
  • the address decoder 16 is coupled to a first interface 19 by means of which specified memory cells in both the data array 11 and in the code array 12 may be addressed.
  • first interface 19 there may be provided an optional second interface 20 that allows parallel addressing of the data array 11 at the same time that the first interface 19 addresses the code array 12.
  • the first interface 19 is coupled to an external bus 21 comprising an address bus 22, a data bus 23 and control pins 24 and that serves to address the code array 12.
  • the external bus 21 also includes an IO bus 25 and control pins 26 that serve to address the data array 11.
  • the address decoder decodes an address conveyed by the address bus and routes it to the data array 11 or the code array 12, as appropriate, according to the memory space shown in Table 1 below.
  • the control pins 24 and 26 are used to convey write enable, output enable, chip enable, write protect and reset signals to the memory chip 10.
  • the data bus 23 is 8 to 32 bits long and is used for the transfer of data to and from the memory chip 10.
  • the first interface 19 When only the first interface 19 is used to address the data array 11 and the code array 12, it supports random access to the code array 12 in every given bus cycle whereby, for example, a byte or word can be written to the RAM page buffer 14 in a first cycle and in a second cycle a read operation can be performed on the code array.
  • the RAM page buffer 14 contains the page data to be read from or written to the data array.
  • the RAM page buffer allows background operation on the data array while freeing the interface first 19 for reading from the code array.
  • the code array is usually fixed at 16, 32, 64, 128, 256, 512 Mb of code area.
  • the NOR-based code area 12 always requires more silicon space than the NAND-based data array 11 owing to random access of the bits compared to the "page" access in the NAND (usually more than 2KB).
  • a second option is code and NAND only, while a third option is NAND and DCA.
  • the code array 12 can be any one of the following types of memory: NOR, ROM, OTP or NOR with less than 1000 erase cycles (NTP).
  • the DCA 13 is a configurable code area, which can be used to store software code of application programs which are not executable directly from the code area and are used infrequently.
  • the DCA 13 is part of the NAND-based data array 11, and can be configured dynamically as an area where each memory cell stores 1 or 2 bits per cell instead of 4 bits per cell in the data array. By allowing storage of 1 or 2 bits instead of 4 bits the DCA 13 is guaranteed to have the reliability of the NOR-based code array 12, and there is thus no need for ECC. Therefore, the memory bits in the DCA can be accessed directly without ECC and as such it will be faster for the system to retrieve the information for execution in the system.
  • DCA memory There are two types of DCA memory, one is a based on page buffering (like regular NAND) while the other uses the XDA 17, which is accessed by an address word (like NOR flash) allowing XIP of code, the difference between them being the intended software application.
  • the use of XIP is important to the OS (Operating System) kernel and real time applications i.e. baseband software code in cell phones.
  • applications such as games are stored in the OS file system as an application, which runs on virtual memory and is usually designed to be loaded to the RAM when used. Therefore the XDA is used for extension of the NOR-based code array 12 and the DCA 13 is used for storing applications that are designed to be loaded to the RAM during execution.
  • the data and code that is used by the CPU are organized in bits and bytes. Each bit holds one binary digit. Each byte is a group of 8 bits and has a unique address in the memory device.
  • the CPU uses the address to refer to a specific code or data byte/word.
  • the CPU processes the code and the data in bytes, or in groups of 2, 4 or 8 bytes. It will be understood that the CPU is part of the computer but and is therefore not shown in the figures which depicts only the memory chip.
  • Fig. 2 is a block diagram illustrating the manner in which the XDA 17 extracts data from the DCA 13.
  • the XDA 17 comprises a DCA controller 27 that is responsive to an address on the address bus 22 for determining a row and column number of a requested word and for feeding the row number to an X decoder 28 and the column number to a Y decoder 29, both coupled to the DCA and having respective outputs connected to the DCA 13.
  • a RAM buffer 30 connected to the DCA 13 allows the access to the data array 11 to be similar as the access to the code array 12 of Fig. 1 without the need for special interface lines as required in a standard NAND flash.
  • the data array 11 and the code array 12 are accessed via a common interface, such a configuration supports random access to the code array in every given bus cycle, for example a byte or word can be written to the RAM page buffer 14 in one cycle and in the second one a read operation can be done from the code array.
  • the RAM page buffer 14 contains the page data to be read or to be program to or from the data array.
  • the RAM page buffer 14 allows background operations on the data array while freeing the interface for reading from the code array.
  • the second interface 20 is a standard NAND interface with 8-16 IOs and control lines such as ALE CLE.
  • the second interface 20 allows the code and the data to be accessed in parallel thus permitting two hosts, each connected to a respective one of the two interfaces, to operate on the same chip.
  • the second interface 20 may be a NOR interface that is coupled to the page RAM 14 or to the XDA 17.
  • Fig. 3 is a block diagram illustrating a variation of the memory system 10 wherein the two hosts that are connected to chip 10 one through the NOR interface 19 and one from the NAND interface 20 can communicate via the RAM page buffer 14.
  • a lock register 31 is coupled between the address decoder 16, on the one hand, and the RAM page buffer 14 and the control registers 18, on the other hand, and serves to ensure that when one of the hosts is using the RAM page buffer or the data array 11, the other host cannot access the RAM page buffer 14 or the data array 11.
  • a receive register 32 and a transmit register 33 can be used to send short messages between the hosts by using these registers as the physical layer of a communications protocol between the two hosts, thereby to assert a hardware signal to alert the receiving host that a message is ready to be read.
  • FIG. 4 is a block diagram illustrating a NAND flash memory system according to a second embodiment the invention having only a single interface 19, shown as a NOR interface.
  • an input address on the address bus 22 is decoded by the address decoder 16, which feeds corresponding address data to the RAM page buffer 14 and the control registers 18 or to the XDA 17 depending on whether the input address points to the data array 11 or to the DCA 13.
  • the XDA 17 operates as described above with reference to Fig. 2 for accessing a specific word in memory.
  • the address decoder 16 is connected to the external bus 21 and decodes the address from the address bus 22 and routes it to the relevant array according to the memory space shown in Table 1.
  • the external bus 21 includes the data bus 23, address bus 22 and control pins that control write enable, output enable, chip enable and reset (used to reset the memory chip).
  • the data bus 23 is 8-32 bits long and used for the data transfer from and to the memory chip 10.
  • the width of the address bus 22 is the number of lines required to address the memory space of the memory chip 10 (see Table 1)
  • the OE# output enable and WE# write enable are used to detect if data is being read from or written to the memory.
  • the control pins 24 include a ready busy signal that is used to signal to the host if the memory chip is ready for a new operation and to detect if the last operation is completed.
  • the CE# chip enable is used to enable operation of the memory chip and the WP# write protect serves to protect the chip from write operations.
  • the interface can be data address multiplexed or un-multiplexed synchronous or asynchronous.
  • the memory address is divided into two groups as follows:
  • the code registers which are part of the control registers 18 include control and status registers to support program, erase, protection operations and to monitor the memory status.
  • the data RAM the RAM buffer used to read from and write page to the data array.
  • the data registers which are also part of the control registers 18 includes control commands.
  • Status registers which are also part of the control registers 18 monitor the status of the memory.
  • the code block is a code flash that allows random access to the entire code array.
  • the code access can be byte or a word at a time or by a burst or page mode for faster sequential read operation.
  • the control of the code array is done by the code registers.
  • the data block corresponding to the data array 11 is accessed by the Page RAM block address and the control registers address.
  • the RAM page buffer 14 is a cache buffer for the data array and can work as a ping-pong buffer for faster sequential operations.
  • the state control copy the page data from the data array to the RAM page buffer while the interface 19 is free for reading from the code array.
  • the page data can be read from the RAM page buffer.
  • two RAM page buffers 14 can be used. For example, when writing pages of data to the NAND data array 11, a first buffer is filled with the page to be written and a program command is asserted. The second RAM buffer is then filled for the next program operation.
  • Using the ping-pong buffer in sequential operation helps eliminate the transfer time from host to the memory array 11.
  • Such a ping-pong buffer comprising a pair of RAM page buffers can be used for read operations in same way. First, a page is copied from the data array 11 to the first RAM page buffer, and then while the host is reading the page from the first RAM page buffer the second RAM page buffer is filled with the next page to be read.
  • the DCA 13 allows code to be stored on the NAND array 11 without the need for Error Correction Code (ECC).
  • ECC Error Correction Code
  • a memory cell in the DCA is identical to a cell in the NAND array except that it stores only 1 or 2 bits per cell, and employs a different write/erase algorithm. The difference in the algorithm is that a slow erase pulse is used with more frequent verify cycles that is applied to ensure that no over-erase will occur in the flash cell, which would prevent the cell from being re- programmed.
  • an erase control circuit is provided using an erase algorithm that checks whether or not threshold voltages on selected cells reach the pre-verify voltage higher than the maximum value of a target threshold voltage range corresponding to the erased state. If one of the selected cells has its threshold voltage higher than the pre-verify voltage, an erase voltage is applied. When all the cells reach the pre-verify threshold a constant erase voltage is applied, which eliminates most of the over erase of cells.
  • the write operation is done with more pulses and with a verify cycle after each pulse in order to make sure all the cells are programmed correctly while the speed is not important.
  • the size of the DCA is dynamic and can be tailored to the user needs in the initial programming of code into the NAND array. This is done by the internal control registers, and should be part of the initialization of the chip. Once programming starts, the user can switch part of the DCA array to the Data array, but the reverse, namely adding more code space to the DCA cannot be done.
  • the XDA 17 is a decoder that decodes the DCA 13 only.
  • the XDA 17 is controlled by the address decoder 16.
  • the XDA 17 stores the whole word line in an internal buffer 30 first. Then it extracts the relevant byte/word and sends it to the data bus 23. The rest of the bits in the internal buffer 30 serve for sequential addressing.
  • Fig. 6 is a block diagram illustrating a memory system 10 according to a third embodiment of the invention.
  • an embedded controller 35 that is coupled to the RAM page buffer 14 to run internal software that allows smart management of the data including ECC/EDC, wear leveling and bad block management.
  • the embedded controller 35 needs a storage source for its microcode to run from, and should run its code in association with the host CPU that is working with the memory systemlO.
  • This storage can be one of the following:
  • a dedicated ROM 36 that stores the controller code may be coupled to the controller 35.
  • the code can be stored in the main NOR code array 12 such that on power up it is copied to a controller RAM 37 that is coupled to the controller 35.
  • the controller RAM 37 thus functions as a shadow RAM that frees the main NOR code array 12 to the host.
  • the code can be executed in place (XIP) or copied to the controller RAM and executed from there.
  • a dedicated NOR flash (not shown) may be coupled to the controller 35. In this case there will be two NOR flashes: one for the embedded controller 35 and one for the host.
  • a hardware encryption engine can be added to encrypt and decrypt the streaming data and code from and to the arrays.
  • the internal software includes wear leveling so as to avoid writing data to the same places in memory, which eventually would cause memory failure after repeated writes, bad block management, logical to physical management, error correction and detection HW+SW of up to 8 levels of storage in each cell (4 on each side), handle overwrite operation, Internal HW+SW encryption engine for data security.
  • the jump prediction mechanism is based on a jump (JP) controller 38 that is coupled to the NOR code array 12, to the address decoder 16, to the XDA 17 and to a JP buffer 39.
  • JP jump
  • the jump controller 38 "sniffs" the next instructions that are read from the code array 12 and scans for a jump instruction in the fetched code. When a jump instruction is detected, the destination address to the jump is decoded, from the rest of the fetched code. The address of the jump instruction is stored in the JP buffer 39. When the read operation is over and the code array is not accessed, the JP cache fetch is started. The instruction data corresponding to the JP address is copied from the code array to the JP cache RAM. The data copied can include number of bytes before and after this address in order to align the cache if necessary.
  • the JP cache PsAM is checked, and if the code is already stored in the cache, the code is executed from the cache and not fetched from the array. This operation has a very small latency, and therefore the execution speed can be very high because the execution is done directly from fast RAM and not from the slower code array.
  • the cache line that was read is deleted, and the process of JP can be started again.
  • the JP operation is CPU-dependent because the "Jump" op-code instruction is different on every CPU.
  • the JP is configured in the chip initialization state to "On" or "Off by the host CPU. The CPU will configure its corresponding CPU type in the JP configuration register.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)

Abstract

Cette invention a pour objet une puce mémoire (10) comprenant une première partie de mémoire (11) fabriquée à l'aide d'une technologie de piégeage de charge et configurée à l'aide d'une architecture de réseau de cellules mémoire NAND, et une seconde partie de mémoire (12) fabriquée à l'aide d'une technologie de piégeage de charge et ayant respectivement des premier et second ensembles d'adresses mutuellement distincts. Une partie de mémoire tampon (14) est couplée à la première partie de mémoire en vue d'un stockage temporaire de blocs de données écrits ou lus à partir de la première partie de mémoire. Des registres (18) stockent une instruction pour commander la première partie de mémoire. Une première interface (19) possède un bus d'adresse pour recevoir une adresse à l'intérieur des premier ou second ensembles d'adresses et un bus de données pour transporter des données vers et depuis la première partie de mémoire ou la seconde partie de mémoire, conformément à l'adresse. Tous les composants sont fabriqués sur une seule puce.
PCT/IL2007/000778 2006-06-27 2007-06-26 Mémoire flash monolithique ayant des parties de mémoire de code et de mémoire de données intégrées WO2008001363A2 (fr)

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US81659606P 2006-06-27 2006-06-27
US60/816,596 2006-06-27
US84340606P 2006-09-11 2006-09-11
US60/843,406 2006-09-11
US86205406P 2006-10-19 2006-10-19
US60/862,054 2006-10-19
US88716207P 2007-01-30 2007-01-30
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TWI776553B (zh) * 2021-02-19 2022-09-01 旺宏電子股份有限公司 具有晶片內執行能力的串列式反及閘快閃記憶體
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