[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

WO2008079077A2 - Structure nanoélectronique et procédé de production associé - Google Patents

Structure nanoélectronique et procédé de production associé Download PDF

Info

Publication number
WO2008079077A2
WO2008079077A2 PCT/SE2007/001171 SE2007001171W WO2008079077A2 WO 2008079077 A2 WO2008079077 A2 WO 2008079077A2 SE 2007001171 W SE2007001171 W SE 2007001171W WO 2008079077 A2 WO2008079077 A2 WO 2008079077A2
Authority
WO
WIPO (PCT)
Prior art keywords
nanoelement
volume element
semiconductor device
layer
doped
Prior art date
Application number
PCT/SE2007/001171
Other languages
English (en)
Other versions
WO2008079077A3 (fr
Inventor
Patrik Svensson
Jonas Ohlsson
Lars Samuelson
Truls LÖWGREN
Yourii Martynov
Original Assignee
Qunano Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/812,226 external-priority patent/US8049203B2/en
Application filed by Qunano Ab filed Critical Qunano Ab
Priority to EP07861100A priority Critical patent/EP2095426A4/fr
Publication of WO2008079077A2 publication Critical patent/WO2008079077A2/fr
Publication of WO2008079077A3 publication Critical patent/WO2008079077A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02603—Nanowires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02606—Nanotubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02653—Vapour-liquid-solid growth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H01L33/18—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

Definitions

  • the present invention relates to the methods and structures for controlling access resistance and conductivity characteristics of nanoelement devices.
  • Nanostructures include so-called one-dimensional nanoelements, essentially in one-dimensional form, that are of nanometer dimensions in their width and diameter, and are commonly known as nanowires, nanowhiskers, nanorods, nanotubes, etc.
  • nanoelement is used.
  • the basic process of nanostructure formation on substrates by particle assisted growth or the so-called VLS (vapor- liquid-solid) mechanism is well known.
  • the present invention is limited to neither the nanowires nor the VLS process, e.g.
  • nanowires and nanostructures selectively grown nanowires and nanostructures, etched structures, other nanoelements, and structures fabricated from nanowires are also included, although the description is focused on VLS- grown nanowires and selectively grown nanowires. Methods for growing nanowires on semiconductor substrates are described in US 2003010244 and US 20040075464.
  • Semiconductor nanoelement devices show great promise, potentially outperforming standard electrical, opto- electrical, and sensor- etc. semiconductor devices. These devices can utilize certain nanoelement specific properties, 2D, ID, or OD quantum confinement, flexibility in axial material variation due to less lattice match restrictions, antenna properties, ballistic transport, wave guiding properties etc. Furthermore, in order to design first rate semiconductor devices from nanoelements, i.e. transistors, light emitting diodes, semiconductor lasers, and sensors, and to fabricate efficient contacts, particularly with low access resistance, to such devices, the ability to dope and fabricate doped regions is crucial. The general importance of doping is easily exemplified by the basic pn-junction, a structure being a critical part of several device families, where the built in voltage is established by doping of the p and n regions.
  • the limitations in the commonly used planar technology are related to difficulties in making field effect transistors, FET, with low access resistance, the difficulty to control the threshold voltage in the post-growth process, the presence of short-channel effects as the planar gate length is reduced, and the lack of suitable substrate and lattice-matched heterostructure material for the narrow band gap technologies.
  • One advantage of a nanoelement FET is the possibility to tailor the band structure along the transport channel using segments of different band gap and or doping levels. This allows for a reduction in both the source-to- gate and gate-to-drain access resistance. These segments may be incorporated directly during the growth, which is not possible in the planar technologies.
  • nitride based semiconductor materials primarily GaN, but also nitrides comprising Al and In, are not easily p-doped.
  • An efficient p-doping of MOCVD grown GaN may be performed using magnesium as dopant.
  • magnesium and hydrogen are known to form H:Mg complex in GaN, which inhibit the acceptor behavior of the magnesium, making it electrically inactive. The hydrogen can be driven out from the material to activate the magnesium by high temperature annealing or radiation.
  • the magnesium incorporation may have to be as high as 10 21 cm 3 due to the inactivation of the magnesium, even after annealing or irradiation treatment.
  • a high incorporation of magnesium severely damages the crystalline quality of the GaN and limits the hole mobility.
  • the thickness of p-doped GaN layers has to be kept low.
  • threading dislocations may bond magnesium atoms and prevent fabrication of p-material.
  • GaN typically has a very high threading dislocation density (10 8 -10 u cm- 2 ) as it normally is grown on substrates such as AI2O3, Si, and SiC, which yields a inherently large lattice mismatch.
  • planar light emitting diode (LED) devices based on GaN structures suffers from the above mentioned challenge in obtaining a p-doped layer with sufficiently high doping level.
  • Such an LED may comprise an often intrinsic active region with InGaN wells between a n-doped GaN layer and a p-doped GaN layer. When carriers are injected from the p- and n-regions they combine in the active region to generate light.
  • One general problem in such a device is to form a low resistance ohmic contact to the p-doped layer.
  • Another problem may be that the InGaN quality in the active layer is deteriorated by the usually high temperature during p-layer GaN overgrowth or a subsequent high temperature annealing.
  • the doping of nanoelements is challenged by several factors. Physical incorporation of dopants into the nanoelement crystal may be inhibited but also the established carrier concentration from a certain dopant concentration may be lowered as compared to the corresponding doped bulk semiconductor. One factor that limits the physical incorporation and solubility of dopants in nanoelements is that the nanoelement growth temperatures very often are moderate. US25006673 teaches a method of providing charge carriers to a nanowhisker or different segments of a nanowhisker from adjacent layers by modulation doping using an enclosing coaxial jacket or an enclosing matrix of a material with a different bandgap than the semiconductor material of the nanowhisker.
  • the solubility and diffusion of dopant in the catalytic particle will influence the dopant incorporation.
  • One related effect, with similar long term consequences, is the out-diffusion of dopants in the nanoelement to surface sites.
  • the efficiency of the doping - the amount of majority charge carriers established by ionization of donors /acceptor atoms at a certain temperature may be lowered compared to the bulk semiconductor, caused by an increase in donor or acceptor effective activation energy, due to the small dimensions of the nanoelement.
  • Surface depletion effects, decreasing the volume of the carrier reservoir will also be increased due to the high surface to volume ratio of the nanoelement.
  • the object of the present invention is to overcome the drawbacks of the prior art. This is achieved by the semiconductor device and the method as defined in the independent claims.
  • a semiconductor device of the present invention comprises a semiconductor nanoelement and a volume element arranged in epitaxial connection to the nanoelement.
  • the semiconductor device is electrically connectable with the volume element and the nanoelement electrically connected in series.
  • the volume element is at least partly doped to provide a high charge carrier concentration into the nanoelement and a low access resistance in an electrical connection to the volume element.
  • the nanoelement protrudes from a semiconductor substrate.
  • the present invention provides a semiconductor device functional as a LED comprising a nanoelement having a n-GaN core, a shell layer and a p-GaN volume element.
  • a thin highly p-doped p-GaN layer encloses the volume element to provide a low access resistance.
  • the shell layer may be a InGaN or InAlGaN layer and the volume element may comprises p-InGaN instead of p-GaN.
  • the present invention provides a semiconductor device comprising a high mobility, highly doped p-GaN layer.
  • a GaN layer having low threading dislocation density may be epitaxially connected to the high mobility, highly doped p-GaN layer.
  • a method according to the present invention comprises the steps of growing a nanoelement, selective growing a volume element and doping the volume element.
  • Fig. Ia is a schematical illustration of a volume element arranged on a nanoelement according to the present invention
  • Fig. Ib is a schematic illustration of a volume element comprising two concentric layers according to the present invention.
  • Fig. Ic is a schematic illustration of a semiconductor device comprising a p-i-n junction according to the present invention
  • Fig! Id is a schematic illustration of a semiconductor device comprising a thin highly p-doped layer according to the invention
  • Fig. Ie is a schematic illustration is a semiconductor device according to Fig. Id comprising a top electrode and a contact,
  • Fig. 2 is a sectional view of different configurations of funnel structures comprising one nanoelement with a volume element on top and three schematic cross sections of the nanoelement,
  • Fig. 3a is a sectional view of a funnel structure with a volume element with a low resistivity contact on the circumferential and top surfaces, arranged in a wrap around configuration on a nanoelement that is upstanding on a semiconductor substrate,
  • Fig. 3b is a sectional view of a semiconductor device comprising an intrinsic GaAs nanoelement, a p-type GaAs substrate underneath the nanoelement, a heavily n- doped InGaP volume element arranged in a wrap around configuration on the nanoelement, a SiU2 layer surrounding the nanoelement and partly the volume element, and Ti/Au contacts deposited on both sides of the device, whereby a pn- junction is formed in the nanoelement,
  • Fig. 4a is a schematical illustration of an array of GaN nanoelements, each having a volume element of a high mobility, highly doped p-GaN arranged thereon according to the invention
  • Fig. 4b is a schematical illustration of semiconductor device comprising a high mobility, highly doped p-GaN layer extending over an array of GaN nanoelements according to the present invention
  • Fig. 4c is a schematic illustration of the device of Fig. 4b further comprising a re- grown GaN layer extending from the high mobility, highly doped p-GaN layer,
  • Fig. 5 is a sectional view of EWIGFET in InAs, where the doping and diameter are designed so that the channel is closed at zero gate bias, and a volume element on top ensures a low access resistance,
  • Fig. 6 is a sectional view of a FET device comprising an intrinsic GaAs nanoelement upstanding on a p + -GaP:Zn substrate with a gate electrode and a highly n-doped volume element arranged in a wrap around configuration on the nanoelement,
  • Fig. 7 is a sectional view of an array of FET devices according to Fig. 6, however with the volume element arranged on top of the nanoelement,
  • Fig. 8 is a sectional view of an array of three identical LEDs comprising a p-GaAs nanoelement, upstanding on a p-GaP substrate, with a concentric layer of InGaP, a dielectric layer, e.g. Si ⁇ 2 enclosing the nanoelement, a n + -InGaP:Si volume element and a ITO contact deposited on the circumferential and top surfaces of the volume element,
  • Figs. 9a-b schematically illustrate a LED structure grown on Si and a buffer layer of GaP, respectively, with corresponding band diagrams according to the present invention
  • Figs. 10a-b are schematic band diagrams and doping levels for the LED structures in Figs. 9-b,
  • Fig. 11 is a sectional view of a semiconductor device intended for storing charge with a dielectric layer and conductive layer arranged on top of a nanoelement- volume element structure,
  • Fig. 12 is a schematic sectional view of a volume element-nanoelement- volume element structure
  • Fig. 13 is a sectional view of a funnel structure with three heterostructure segments in a nanoelement extending with a volume element in contact with a semiconductor substrate enclosing the first heterostructure segment
  • Fig. 14 is a scanning electron microscope micrograph showing a funnel structure according to Fig. 13,
  • Fig. 15 is a cross sectional view of a volume element-nanoelement funnel structure with one nanoelement enclosed in the volume element and another nanoelement arranged on top of the volume element,
  • Fig. 16 is a scanning electron microscope micrograph showing a funnel structure according to Fig. 15,
  • Fig. 17 is a sectional view of a volume element arranged on a relatively short nanoelement enabling lattice mismatch between the volume element and the substrate,
  • Fig. 18 is a cross sectional view of a volume element arranged on a short nanoelement contacting a patterned low resistivity layer on a substrate,
  • Fig. 19 is an illustration of one processing scheme for a LED device utilizing VLS growth of a nanoelement and growth of a volume element on top,
  • Fig. 20 is a SEM-image of a nanostructure LED according to Fig. 9b,
  • Fig. 21 is a SEM image of nanoelement structures of the invention after the first MOVPE step
  • Figs. 22a-c are photoluminescence graphs of nanowires and LED nanostructure according to Figs. 9a-b and Fig. 21,
  • Fig. 23 is an image of an active LED nanostructure
  • Figs. 24 shows a) Power dependence of Electroluminescence of GaAs LEDs grown on GaP and Si, b) EL spectra at 80 mA from GaP and Si based LED nanostructures,
  • Figs. 25a-b shows SEM images of the sample grown with a NH3 flow rate of 3.0 seem
  • Figs 26a-b shows SEM images of the sample grown with a NH3 flow rate of 1.0 seem
  • Figs 27a-b shows SEM images of the sample grown with a NH3 flow rate of 0.5 seem
  • Fig. 28 shows SEM images of the sample grown with a NH3 flow rate of 0.2 seem.
  • a semiconductor device opens new possibilities for the implementation of different electronic and photonic semiconductor devices, particularly in small dimensions.
  • nanoelement is used for any one- dimensional nanostructure of nanometer dimension in at least their width.
  • Such nanostructures are commonly known as nanowires, nanowhiskers, nanorods, nanotubes, etc.
  • the nanoelements according to this application may comprise at least a first epitaxially grown shell layer made of a semiconductor material, which at least partly encloses a core of the nanoelement.
  • the present invention is intended to solve general difficulties associated with doping of nanoelements, and to establish an alternative and feasible route to the doping of nanoelements, not only for when doping is complicated by the dimensions or the fabrication methods of such nanoelements, but also for providing new possibilities by the different prerequisites and for decreasing access resistances to electrical and optical devices made from nanoelements.
  • nanoelement technology in particular nanowire technology
  • nanowire technology allows for greater flexibility and greater possibility to tailor the performance by e.g. tailoring the band structure along the nanostructure using segments of different band gap and/or doping levels.
  • reasoning about nanoelements hereinafter mainly is referred to the mentioned nanowire technology, in particular particle assisted or VLS grown epitaxial nanowires
  • the present invention is, as appreciated by a skilled person, applicable on nanoelement semiconductor devices in general, irrespective of specific kind of nanoelements utilized.
  • nanoelement format in itself is not optimal from this perspective as the elongated nature and low area of the nanoelement cross-section will build device resistance.
  • the main tools of fabricating low resistance contacts a task complicated by the intrinsically low contact-surfaces given by the nanoelement geometry, are high doping and low band gap adjustment on the semiconductor side of the contact, but as mentioned, the doping of nanoelements is challenged by several factors.
  • the access to sufficient and accurate doping and a large contact surface without appreciably increasing device length and access resistance would be beneficial for all types of semiconductor devices.
  • a nanoelement device is not in need of high doping, or, their doping-level is of less priority and can be balanced against other design parameters.
  • doping of critical parts will decrease device performance.
  • contra-productive doping effects are non-emitting impurity levels in an optical region of e.g. a light emitting diode (LED) structure or impurity scattering, decreasing mobility, in a field effect channel.
  • LED light emitting diode
  • donor doped material is n-type and acceptor doped material is p-type.
  • the n indicates that electrons are charge carriers and consequently the p indicates that holes are the charge carriers.
  • the pure and undoped material is called intrinsic, which is indicated by an i, but may naturally be n- or p-type.
  • the conductivity is varied by adding different amount of dopants.
  • a region that is highly doped is in the figures and hereinafter commonly denoted with a "+" sign.
  • a semiconductor device is based on an at least partly doped volume element 105 epitaxially arranged on a nanoelement 100.
  • the doping of the volume element 105 may have different purposes, such as by way of example providing a low access resistance in an electrical connection of a semiconductor device, forming a pn-junction, modulation doping of the nanoelement, or, as explained below, providing high charge carrier injection into the nanoelement or an active region of the semiconductor device.
  • the volume element 105 is enclosing an end portion of the nanoelement 100, however not limited to this.
  • the volume element 105 is essentially a cylinder of a different composition and/or doping level epitaxially connected to the nanoelement 100. Together they form a radial heterostructure.
  • the volume element 105 is doped to provide high charge carrier injection into the nanoelement 100 and a low access resistance in an electrical connection.
  • the nanoelement 100 comprises a shell layer 131 epitaxially connected to a core 133 of the nanoelement 100.
  • the shell layer 131 encloses an end portion of the core 133.
  • the nanoelement 100 is upstanding on a substrate 110.
  • a volume element 105 is epitaxially arranged on the nanoelement 100, by way of example enclosing an end portion thereof.
  • the volume element 105 is of different composition and/or doping level as compared to the shell layer 133 of the nanoelement 100.
  • a pn-junction may be formed by having different doping of the core 133, the shell layer 131 and the volume element 105.
  • the semiconductor device is a light emitting diode (LED).
  • the semiconductor device comprises a nanoelement 100 upstanding on a semiconductor substrate 110 and in epitaxial connection with said semiconductor substrate 110.
  • the nanoelement 100 comprises a shell layer 131 epitaxially connected to a core 133 of the nanoelement 100.
  • the shell layer 131 encloses an end portion of the core 133.
  • a dielectric layer 120 made of e.g. silicon nitride or silicon oxide, covers a top surface of the semiconductor substrate 110 surrounding the nanoelement 100.
  • the shell layer 131 encloses the part of the core 133 protruding above the dielectric layer 120.
  • a volume element 105 encloses the shell layer 131.
  • the core 133 of the nanoelement 100 is n-doped GaN (n-GaN), grown on a substrate or buffer layer of n-GaN 110
  • the shell layer 131 is by way of example an intrinsic semiconductor material, such as e.g. intrinsic GaN (i-GaN) or InGaN/GaN
  • the volume element 105 is p-doped (p-GaN).
  • the active region typically coincides with the intrinsic shell layer 131.
  • the shell layer 131 may, as understood by a person skilled in the field of semiconductor devices, also comprise a plurality of layers of different composition.
  • One example of such a multilayer is an active region comprising a plurality of wells/ barriers such as GaN/InGaN/GaN/InGaN/InGaN/GaN.
  • a plurality of semiconductor devices as described with reference to Fig. Ic i.e. LEDs, are arranged in an array on the substrate 110.
  • one embodiment of the present invention is a semiconductor device functional as a LED and comprising a nanoelement 100 having a n-GaN core 133 enclosed by an i-GaN shell layer 131, and a p-GaN volume element as exemplified above.
  • a low resistance ohmic contact is accomplished since the semiconductor device comprises at least a first concentric layer 106, which has a substantially higher doping level than the p-GaN volume element 105 and made of a p-doped nitride based semiconductor material such as p-GaN and/or p-InGaN and/or p-InAlGaN and/or AlGaN.
  • the first concentric layer 106 is acceptor doped using magnesium and to obtain the high doping level the first concentric layer 106 is thin. Accordingly the moderately doped p-GaN volume element 105 contributes with charge carriers to the light generation in the LED structure and the highly p-doped first concentric layer 106 provides a low resistance ohmic contact. InGaN instead of GaN in the first concentric layer 106 may yield higher doping levels. Furthermore InGaN has a lower bandgap as compared to GaN. A lower bandgap simplifies the formation of a low resistance ohmic contact. Intrinsic InGaN may also be used in the volume element 105. Although this embodiment and the embodiment described with reference to Fig Ic are functional as LEDs the combination of a volume element 105 and a first concentric layer 106 having different doping levels and/or composition may be used in other applications as well.
  • Fig. Ie illustrates a semiconductor device functional as a LED according to the present invention.
  • this is the semiconductor device of Fig. Id, but in addition comprising an electrical contact layer 127 arranged on the first concentric layer 106 and extending to an electrical contact arrangement 128 beside the nanoelement 100.
  • the nanoelement is epitaxially connected to a n-GaN buffer layer 123 on a semiconductor substrate 110, e.g. made of silicon.
  • the thin highly p- doped first concentric layer 106 provides a low resistance in the connection between the nanoelement and the contact layer 127.
  • High wavelength LEDs comprising an nitride based semiconductor alloy, such as e.g. InGaN or InAlGaN alloys, having a large amount of In in the active region are not easily accomplished with an adjacent highly p-doped layer since p-GaN overgrowth usually is performed at a high temperature.
  • the In-containing active layer may deteriorate due to this high temperature.
  • a semiconductor device comprises a nanoelement 100 having a III-N based semiconductor core 133, such as n-GaN, n-InGaN or InAlGaN, at least partly enclosed by a shell layer 131 of a nitride based semiconductor comprising In, such as InGaN or InAlGaN.
  • a nitride based semiconductor comprising In, such as InGaN or InAlGaN.
  • this embodiment comprises a p-doped InGaN or InAlGaN volume element 105. Those materials can be fabricated at a lower temperature and with better doping efficiency using magnesium as dopant.
  • At least the shell layer 131 and volume element 105 are made of the same material, although being intrinsic and p-doped respectively.
  • the crystal lattice mismatch between the layers in close proximity to the active region is decreased. Thereby the efficiency for longer wavelengths of the LED is increased.
  • One simple example of such a semiconductor device comprises a n-GaN/InGaN nanoelement core 133, an i-InGaN nanoelement shell layer 131 and a p-InGaN volume element 105.
  • a multilayer structure may be used instead of the single layer shell layer 131 as explained above.
  • the present invention provides an epitaxial nanostructure, a so called funnel structure, comprising at least one essentially one-dimensional nanoelement 100 and at least one element 105 extending in three dimensions, having a large volume and a large surface, above and hereinafter referred to as a volume element 105, whereby the challenging doping procedures for nanoelements 100 may be avoided, the processing is simplified and more reliable, the access resistance may be decreased, both due to doping and to an increased contact surface, the advantages of using a nanoelement may be utilized, and new applications and possibilities for nanoelement semiconductor devices open up.
  • the funnel structure comprise one nanoelement portion, possibly with all the attractive properties of such an element, and one epitaxially connected wider portion with an inherently large surface, a volume element portion, not necessarily of nanometer dimension adjacent to the nanoelement, where nanoelement properties are of less importance and rather bulk-like properties, enabling the volume element 105 to easily be highly doped, are sought for.
  • the volume element 105 although not necessarily of nanometer dimension, may have some nanoelement properties, such as the ability to grow a crystalline structure with segments of different composition and without detrimental defects, not possible in using planar technology.
  • the funnel structure works as a carrier reservoir enabling high carrier injection into the nanoelement from a region with well defined doping where low resistance contacts easily can be fabricated, preferably in a wrap around configuration in order to increase contact area and minimize distance between the nanoelement and the contact.
  • the three-dimensional part of the funnel has a certain volume and thickness, eliminating the challenges in doping of one-dimensional nanoelements, in order to achieve the necessary doping concentration and profiles, to decrease internal series resistance and contact resistance, increase carrier injection into the nanoelement, to establish desired built- in- voltage, and to provide a large contact surface.
  • the low internal resistance and the increased amount of carriers due to the funnel nature vouch for a high injection of majority carriers into the nanoelement already at low forward voltages.
  • the funnel structure is for establishing a low resistance connection to a terminal that needs to be separated from other connected circuitry to decrease capacitance in the circuitry.
  • Low resistance and stable ohmic contacts, and in some cases Schottky contacts, are critical for most semiconductor devices.
  • the funnel structure may advantageously also be used as a light emitting diode or a pin detector.
  • the funnel structure may be implemented in a nanoelement FET (field effect transistor) device wherein access resistance is decreased by utilizing funnel structures between drain/gate and source/gate.
  • the increased surface area of a nanoelement device, due to a volume element is not only important as means for reducing the access resistance, but also provides a large contact surface for a dielectric covering the volume element, enabling charge storage in e.g.
  • the resistance arisen from the heterojunction discontinuity in valence or conduction band between two semiconductors or, similarly, the resistance from the Schottky barrier between a semiconductor and a metal can be decreased by high doping. The increased doping will decrease the width of the barrier and facilitate carriers to tunnel through the barrier effectively decreasing contact resistance.
  • the funnel structure comprises a nanoelement 100 consisting of an intrinsic semiconductor forming a first elongated cylinder, and a volume element 105 consisting of a heavy doped semiconductor forming a second cylinder, with an essentially larger diameter, epitaxially grown on one end portion of the nanoelement 100.
  • the volume element 105 may be in a wrap around configuration where the volume element 105 partly encloses the nanoelement 100 end portion.
  • the funnel structure is in one embodiment upstanding on the surface of a crystalline semiconductor substrate 110, however not limited to this.
  • the volume element 105 may be arranged in sequence with the nanoelement 100 or the nanoelement 100 may extend through the volume element 105, either continuing beyond the volume element 105 or ending at the end of the volume element 105. Since different materials and processing may be employed to fabricate the nanoelements, different shapes are possible for the nanoelements.
  • the volume elements 105 can be cylindrical, rounded (mushroom shaped), or slanted at the part enclosing the nanoelement 100.
  • the cross-sections of the nanoelement 100 and the volume element 105 are not necessarily circular 16, but rather polygonal 17 due to the crystal structure of the material, or hollow 18, as illustrated in Fig. 2.
  • one embodiment of the present invention is a funnel structure comprising, from the bottom, a nanoelement 100 of a semiconductor that is intrinsically p-type, upstanding on a semiconductor substrate 110 that is p-doped, forming a first elongated cylinder, with a diameter of about 100 nm and a length of about 2 ⁇ m, a heavy n-doped volume element 105 forming a second cylinder with an essentially larger diameter, i.e.
  • the semiconductor substrate 110 in connection with the nanoelement 100 is p- doped GaAs
  • the nanoelement 100 is an intrinsically p-type GaAs nanowire
  • the volume element 105 is heavy n-doped GaP
  • the low resistivity contact 106 is an ITO (InSnO) layer with a thickness of 10 nm. Due to the doped regions, a pn- junction is formed somewhere in the region between the substrate 110 and the volume element 105. The exact location and extension of the depletion zone is dependent on the doping concentrations and profiles, geometry, etc.
  • the dimensions given for the nanoelement 100 and volume element 105 in the embodiments are by way of example only, and the length and diameter of the nanoelement and the diameter and height of the volume element 105 may be varied, within certain limits of course.
  • the length of the nanoelement 100 may be as short as a few epitaxial layers if the purpose of the nanoelement 100 only is to make it feasible to grow a three-dimensional volume element 105 on the substrate.
  • the volume element 105 diameter preferably is at least 50 nm wider than the diameter of the nanoelement 100.
  • the maximum diameter of the volume element 105 is dependent on the device density.
  • Fig. 3b illustrates another embodiment, which is a similar funnel structure with the same prerequisites as the foregoing example comprising an intrinsic GaAs nanoelement 100, a p-GaAs substrate 110, a highly n-doped InGaP volume element 105, a filler layer 120 of Si ⁇ 2, enclosing the whole nanoelement 100 and partly the volume element 105, and thin film Ti/Au contacts (106, 113) on the top and bottom surfaces of the substrate 110 respectively.
  • a p-type volume element 105 and an n-type one-dimensional nanoelement 100 and substrate 110 e.g. a p-type volume element 105 and an n-type one-dimensional nanoelement 100 and substrate 110.
  • Suitable materials for the substrate include, but is not limited to, 110 Si, GaAs, GaP, GaP:Zn, GaAs, InAs, InP, GaN, Al 2 O 3 , SiC, Ge, GaSb, ZnO, InSb, SOI (silicon-on-insulator), CdS, ZnSe, CdTe, etc.
  • Suitable materials for the nanoelements 100 and the volume elements 105 include, bit is not limited to: GaAs (p), InAs, Ge, ZnO, InN, InGaN, GaN InAlGaN, BN, InP, InAsP, GaInP, InGaP:Si, InGaP:Zn, GaInAs, AUnP, GaAUnP, GaAUnAsP, GaInSb, InSb, Si, etc.
  • Possible donor dopants are, but not limited to, for e.g. GaP are Si, Sn, Te, Se, S, etc, and acceptor dopants for the same material are Zn, Fe, Mg, Be, Cd, etc.
  • the doping level is dependent on the type of semiconductor.
  • GaAs is intrinsic at 10 16 cm 3
  • a typical doping level in the nanoelement 100 is 10 16 -10 17 cm- 3 and 10 17 -10 20 in the volume element, depending on the dimensions and the conditions in the manufacturing process.
  • measuring the doping level in nanoelements is challenging and methods for this are not really well developed today.
  • low resistivity contact materials are dependent on the material to be deposited on, but metal, metal alloys as well as non-metal compounds like Al, Al-Si, TiSi 2 , TiN, W, MoSi 2 , PtSi, CoSi 2 , WSi 2 , In, AuGa, AuSb, Ni/Au, Ni, AuGe, PdGe, Ti/Pt/Au, Ti/Al/Ti/Au, Pd/Au, ITO (InSnO), etc and combinations of e.g. metal and ITO can be used, however not limited to these materials.
  • One embodiment of the present invention is a semiconductor device, wherein a volume element 105 is arranged in a wrap around configuration on an end portion of a nanoelement 100, as shown in Fig. 3b, and the nanoelement 100 is doped and has less than half of the donor or acceptor dopant concentration of the volume element 105.
  • One embodiment of the present invention is a funnel structure according to Fig. 3b, wherein the generally one- dimensional nanoelement 100 is modulation doped by the volume element 105.
  • the volume element material has a higher band gap than the nanoelement material and due to the doping charge carriers diffuse from the volume element 105 into the nanoelement 100. This is advantageous when doping in combination with high carrier mobility is needed.
  • One embodiment of the present invention is a semiconductor device comprising a nanoelement- volume element funnel structure, wherein the nanoelement 100 extends partly through the volume element 105, i.e. a wrap around configuration, and wherein the nanoelement 100 change composition, e.g. from GaAs to GaAsP, approximately where the volume element 105 begins.
  • Another embodiment is based on a funnel structure comprising a volume element 105 on a nanoelement 100 with a wrap around configuration, wherein the volume element 105 composition gradually approaches or approximately have the same composition as the volume element 105 approximately where the volume element 105 begins.
  • One embodiment of the present invention is a semiconductor device comprising a nanoelement volume element funnel structure, wherein the nanoelement 100 is doped to the same type as the volume element 105. This may be necessary when the nanoelement 100 cannot be doped to the required doping level. An additional carrier injection from the volume element 105 is needed. In addition the access resistance is decreased.
  • the nanoelements 100 Due to the nanometer dimensions of the nanoelements 100 it is also possible to selectively change the composition along the length thereof,- to grow a nanoelement of one composition onto a substrate 110 of another composition, and to form he teroj unctions, with maintained epitaxy although a significant lattice mismatch. In particular this allows for attaching a volume element 105 according to the present invention, otherwise not possible to grow on the substrate, to the substrate via a nanoelement 100 without introducing significant defects. Heterostructures along the length of the nanoelement 100 or in the volume element 105 may be introduced to enable the semiconductor device to carry out a desired function or to perform according to certain requirements.
  • a heterostructure in a nanoelement comprises at least two lengthwise segments of different composition and/or doping, a first segment of a first material and a second segment of a second material.
  • An epitaxial boundary is present between the first and the second segment, the boundary being limited to a number of lattice planes, wherein the composition or doping changes gradually.
  • a heterostructure in a volume element comprises a plurality of concentric segments of different composition.
  • one embodiment of the present invention is a semiconductor device comprising a nanostructure having a highly p-doped GaN volume element 105 epitaxially arranged on a GaN nanoelement 100.
  • planar technology has drawbacks with regards to provide highly p- doped nitride based III-N semiconductor materials.
  • the most efficient acceptor dopant is Mg, which however has to be incorporated in high amounts to obtain the desired doping level since a large portion of the Mg usually is inactivated.
  • the Mg may be inactivated by complex forming with hydrogen. The hydrogen can be driven out of the material by high temperature annealing and/ or optical radiation, which activate some of the previously inactivated Mg.
  • Threading dislocation densities are usually high in GaN (10 8 -10 u cm 2 ) as it in planar technology usually is grown on e.g. AI2O3, Si or SiC, which inherently have large crystal lattice mismatch to GaN.
  • nanoelements can be grown from a) dislocation rich material or b) from heavily lattice mismatched material and still be inherently free from threading dislocations.
  • a simplified explanation for a) is that the nanoelement have the freedom to expand or shrink fully and relax to its fundamental crystal lattice size.
  • the nanostructure comprising the highly p-doped GaN volume element may be epitaxially grown on a substrate having a substantial lattice mismatch to GaN, such as Si, or on an intermediate buffer layer of high dislocation density GaN.
  • the crystal lattice mismatch may be at least 2% and the threading dislocation density of the substrate (110) or an intermediate buffer layer being an integral part of the substrate may be at least 1*10 16 cm 3 .
  • Threading dislocations may occur in the nanoelements as well, however the threading dislocation density is preferably less than 3 per nanoelement (100) or preferably less than 5% of the nanoelements (100) in a population on a substrate (110) comprises a threading dislocation.
  • Fig. 4b illustrates one embodiment of the present invention which is based on the same principle as the embodiment described with reference to Fig. 4a.
  • Highly p- doped GaN volume elements 105 have been grown on adjacent GaN nanoelements 100, whereby the growth have been controlled in such way that a continuous high mobility p-GaN layer 140 has been formed on the adjacent nanoelements 100.
  • the usually high incorporation of Mg in p-GaN in planar technology damage the GaN material, decreases hole mobility and makes it necessary to use thin p-GaN layers to avoid too high series resistance.
  • This embodiment of the present invention provides a thicker high mobility p-GaN layer 140. Referring to Fig.
  • one embodiment of the present invention is a semiconductor device comprising a high mobility p-GaN layer 140 on an array of GaN nanoelements.
  • a GaN layer 141 extends from the surface of the p-GaN layer 140 and encloses the nanoelements 100.
  • the nanoelements 100 are preferably in optical contact with the GaN layer 141 and the refractive index of the GaN layer 141 is preferably chosen as high as possible.
  • the GaN layer 141 has been selectively grown from the p-GaN layer 140.
  • nitride based semiconductor materials such as GaN, InGaN and InAlGaN have been acceptor doped using Mg
  • Appropriate acceptor materials are for example Zn and C,
  • the doping level can be made high enough without using such high Mg doping levels that the p-GaN material is deteriorated, as explained in the background.
  • the nanoelement 100 can be doped to the same or different conductivity when compared to the three-dimensional volume element 105.
  • High doping and low band gap adjustment on the semiconductor side of the contact as mentioned, a usual tool for reducing the access resistance in common nanoelement devices, can be utilized also for the volume element 105 in the present invention.
  • the doping level of the volume element 105 may gradually change from the interface to the outer surface, i.e. gradient doping of the volume element 105.
  • heterostructures of the nanoelement 100 and/ or the volume element 105 comprising concentric layers of materials of different compositions and /or doping levels.
  • a concentric layer 106 of the nanoelement 100 or volume element 105 can also be a dielectric material, or a low resistivity material, e.g. a metal, enclosing at least partly the nanoelement 100 or volume element 105.
  • modulation doping mentioned above, of the nanoelement 100 can be obtained by use of a concentric layer 106 of a doped semiconductor material with a higher band gap than the core material.
  • Typical semiconductor material utilized in concentric layers of the nanoelement 100 and volume element 105 are Ga/As/AlGaAs, AlSb, Si, GaP, InP, InAs, InGaP InPSb, GaInPSb, AlPSb, GaAsSb, InAsP, Al, AlAs, GaAlInAsP, etc.
  • the choice of semiconductor materials is not limited to these materials. Referring to Fig.
  • one embodiment of the present invention that comprises heterostructures along the nanoelement 100 and a concentric layer on the nanoelement 100 is an enhancement nanowire wrap insulating gate field effect transistor (EWIGFET), comprising a nanoelement, in this case a VLS grown nanowire, upstanding on a InAs substrate 110, with a first highly n-doped (n + ) InAs nanoelement segment 100a, a second intrinsic n-type InAs nanoelement segment 100b and a third highly n-doped (n + ) InAs nanoelement segment 100c, a thin concentric layer 101 of a dielectric material enclosing the part of the nanoelement segments 100a, 100b, 100c that are not enclosed in a n + -InAs volume element 105 arranged on top of the nanoelement segment 100c.
  • EWIGFET enhancement nanowire wrap insulating gate field effect transistor
  • a gate electrode 125 in a wrap around configuration is provided in between two filler layers 120, 121 that fill the volume surrounding the nanoelement segments 100a, 100b, 100c and partly also the volume element 105 and a thin film Ni contact 106 deposited on the top surface.
  • the volume element 105 is here utilized to decrease the access resistance partly by doping of the volume element 105 and partly by increasing the contact surface area.
  • the nanoelement 100 in the EWIGFET is made of InAs, wherein the doping and diameter are designed so that the channel is closed at zero gate bias. However the same design applies to other materials than InAs, like InSb, InP, GaAs, Ge and Si.
  • a DWIGFET is obtained when the doping levels are increased in such a way that the channel remains open at zero gate bias.
  • an intrinsically p-type GaAs nanoelement 100 with a portion of the nanoelement 100 enclosed in a thin concentric layer 101 of a dielectric material, e.g. Si ⁇ 2, is upstanding on a highle p-doped (p + ) GaP:Zn substrate 110 with a highly n-doped volume element 105 arranged on top of the nanoelement 100, enclosing the portion of the nanoelement without the concentric layer 101.
  • a dielectric material e.g. Si ⁇ 2
  • a gate electrode 125 is provided in a wrap around configuration along a small portion of the nanoelement 100 between the volume element 105 and the substrate 110.
  • the heavy doping of the volume element 105 makes it a carrier reservoir for the undoped nanoelement 100 and creates a pn-junction in the nanoelement 100.
  • a voltage to the gate electrode 125 a current flows in the nanoelement 100.
  • FIG. 7 another embodiment of the present invention, similar to the WIGFET structure described above, is a FET structure.
  • this cross sectional view an array of three FET structures is shown, wherein the volume element 105 is arranged on top of the nanoelement 100 instead of in a wrap around configuration as in Fig. 6.
  • the volume element 105 is doped, either p or n type, in order to be one side of a pn-junction. This region has a certain volume and thickness in order to achieve the necessary doping concentration to decrease internal series resistance and contact resistance, increase carrier injection into the nanoelement 100, while increasing built-in-voltage.
  • the low internal resistance and the increased amount of carriers due to the funnel nature vouch for a high injection of majority carriers into the nanoelement 100 already at low forward voltages.
  • High injection of carriers into the nanoelement 100 introduces high concentrations of electron hole pairs into the nanoelement 100 increasing light emitting recombination.
  • the high concentration of electron-hole pairs in combination with the active region being extended into a waveguide, directing the light, can enable stimulated emission, increasing the output of the device further.
  • the nanoelement 100 material composition can be chosen to propagate into the volume element 105 in order to decrease the optical disturbance by the volume element-nanoelement connection. Extending the length of the nanoelement 100 in the direction of the emitted light will increase re-absorption. To decrease re-absorption the composition of the nanoelement 100 is adjusted in the direction of the emitted light in order to raise the band gap as compared to the energy of the emitted light.
  • one embodiment of the present invention is functional as a LED.
  • An array of three identical such LEDs is illustrated in Fig. 8.
  • the concentric layer 101 is utilized to optimize the wave guiding properties.
  • An insulating and transparent masking material 115 e.g. Si ⁇ 2, covers about the lower half of the nanoelement 100.
  • an InGaP volume element 105 with a diameter of about 500 nm and a length of about 1 ⁇ m, heavily doped with Si to obtain an n+-type material.
  • a top electrode 106 is deposited on the top surface and a bottom electrode 1 13c is deposited on the bottom side of the substrate 110.
  • one embodiment of the present invention is a semiconductor device functional as a LED.
  • a nanoelement 100 is upstanding on a p-GaP substrate or buffer layer 1 10.
  • the nanoelement 100 comprises a core 133, which comprises a thin segment of i-GaP 100a adjacent to the substrate 110 and a i-GaAs segment
  • a band diagram for this LED structure is illustrated in
  • one embodiment of the present invention is a semiconductor device functional as a LED.
  • a nanoelement 100 is upstanding on a p-Si substrate 110.
  • the nanoelement 100 comprises a core 133, which comprises a thin segment of i-GaP 100a adjacent to the substrate 1 10 and a i-GaAs segment 100b, and a i- InGaP shell layer 131.
  • a n-InGaP volume element 105 is epitaxially connected to the nanoelement 100, and enclosing an end portion thereof.
  • a first concentric layer 101 encloses of a dielectric material encloses the remaining portion of the nanoelement.
  • a band diagram for this LED structure is illustrated in Fig. 9.
  • Figs. 9c-d illustrates typical band gap diagrams for a LED structure according to Figs. 9a-b on p-GaP and p-Si, respectively.
  • the shell layer 131 which commonly is the active region of the LED structure, the shell layer 131 may comprise a plurality of layers of different composition.
  • the volume element 105 the top surface is covered by a first concentric dielectric layer 106 in order to store a charge, e.g. for memory devices.
  • This embodiment comprises an intrinsic nanoelement 100 upstanding on a p-type semiconductor substrate 110, a n-doped volume element 105 in a wrap around configuration, a concentric dielectric layer 101 enclosing the portion of the nanoelement 100 that is not enclosed by the volume element 105, a dielectric material 106 deposited on the top and circumferential surfaces of the volume element 105, a second concentric layer 107, i.e. a top electrode on the dielectric material, and a wrap around gate electrode 125.
  • the stored charge can be read out by applying a voltage to the gate electrode 125.
  • the nanoelement- volume element sequence may be repeated along the nanoelement 100.
  • a first n-doped volume element 105a and second p-doped volume element 105b share a common nanoelement 100 in-between, forming a volume element (p)-nanoelement-volume element (n) structure.
  • a structure may advantageously be implemented in LEDs and diodes or as emitter-base and base-collector junctions in hetero-bipolar transistors.
  • Another embodiment is when a first volume element 105a and second volume element 105b of common conductivity type (n or p and individually ohmically connected to a circuitry) are connected through a nanoelement 100 where a non- ohmic terminal altogether forming a volume element (n) -nanoelement- volume element (n) or volume element (p) -nanoelement- volume element (p) structureas illustrated in Fig. 12, whereby charge carriers of the proper type are injected into the nanoelement 100.
  • this structure comprises two volume elements 105a, 105b, one n-type volume element 105b at the bottom, in conjunction with the substrate 110, and one p + -type volume element 105a arranged in a wrap around configuration on top of the nanoelement 100 that is upstanding on the substrate 110 and extending through the lower volume element 105b.
  • a pn-junction is formed and the volume of the active region, i.e. the depletion region, appreciably coincides with the one-dimensional region in the funnel structure, close to the junction between the nanoelement 100 and the upper volume element 105a.
  • the one-dimensional region is easily depleted due to low doping ion concentration and low volume, since the total amount of charge moved is low.
  • the high doping concentration together with a larger volume of the volume elements 105a, 105b gives that the depletion region will protrude into less volume and, especially, less distance in the direction of transport in the volume element 105a.
  • One embodiment comprising a heterostructure in the one dimensional nanoelement 100 is a funnel structure as the one shown in the schematic drawing in Fig. 13 and in the scanning electron microscope micrograph in Fig. 14.
  • a one-dimensional nanoelement comprising a first nanoelement segment 100a of GaP, a second nanoelement segment 100b of GaAsP and a third nanoelement segment 100c of GaP, is upstanding on a semiconductor substrate 110.
  • the first segment 100a is fully enclosed in a three-dimensional GaP volume element 105.
  • This structure decreases the injection resistance from the substrate 110 into the nanoelement segment 100a.
  • This is also the case in an alternative embodiment (not shown) comprising the nanoelement segment 100a, the volume element 105 and only the nanoelement segment 100c, all made of GaP.
  • a similar structure is the funnel structure shown in the schematic drawing in Fig. 15 and in the scanning electron microscope micrograph in Fig. 16, providing another embodiment of the present invention, wherein a first one-dimensional nanoelement 100a made of GaAsP is enclosed, both on the cylindrical mantle surface and on the top, by an InGaP volume element 105.
  • the one-dimensional nanoelement 100b visible in Fig. 16 is grown on top of the volume element 105.
  • a patterned low resistivity layer 118 preferably a metal layer, on the substrate 110 comprising a small hole in the low resistivity layer 118.
  • a nanoelement segment 100a fills up the hole and protrudes sufficiently to enable radial growth of the volume element 105 that is enclosing the nanoelement segment 100a, whereby the volume element 105 forms an ohmic contact between the low resistivity layer 118 and the semiconductor device.
  • a second nanoelement segment 100b is upstanding from the volume element 105.
  • this embodiment is useful when a nonconducting substrate is used and a metallic contact, preferably lithographically defined, is requested.
  • Another embodiment of the present invention is a light emitting device, where the nanoelement main function is to provide a good heterojunction between a substrate 110 and a volume element 105 that normally are impossible to combine due to too large crystal lattice mismatch, i.e. the nanoelement 100 is utilized as an very thin template bridging the incompatible materials.
  • the nanoelement 100 is utilized as an very thin template bridging the incompatible materials.
  • an undoped InGaN nanoelement is grown on a n + GaN/ Sapphire substrate 110 through a silicon nitride mask allowing for a p + GaN volume element 105 on top.
  • a method of fabricating funnel structures is to first grow a nanoelement 100, mask the intended nanoelement 100 with a masking layer 115 and re-grow selectively the intended volume element 105, see Fig. 19.
  • the volume element 105 grows both in axial and radial directions, hence, when the nanoelement 100 is masked partly, the nanoelement 100 becomes enclosed in the volume element 105.
  • Appropriate masking materials are e.g. silicon nitride, silicon oxide etc.
  • nanoelement growth is locally enhanced by a substance, as VLS grown nanowires
  • the ability to alter between radial and axial growth by altering growth conditions enables the procedure (nanowire growth, mask formation, and subsequent selective growth) can be repeated to form nanoelement-volume element sequences of higher order.
  • nanoelement growth and selective growth are not distinguished by separate growth conditions it may be better to first grow the nanoelement 100 along the length and by different selective growth steps grow different types of volume element 105 regions.
  • a fabrication method according to the present invention will be exemplified with the fabrication of a light emitting pn-diode/ array with active nanowire region(s), illustrated in Fig. 19.
  • the method comprises the steps of:
  • the volume element is either doped (8) during the growth or afterwards (not shown). Concentric layers (101,106) may optionally be grown both on the volume element (105) and the nanoelement (100).
  • Examples of realizations of the nanostructured LED according to the present invention will be given as GaAs nanowires epitaxially grown on GaP and Si substrates.
  • the LED functionality has been established on both kinds of substrates.
  • the structures are evaluated in terms of temperature-dependent photoluminescence, electroluminescence, and radiation pattern.
  • a LED device comprises arrays of III-V light emitting nanowire diodes, grown and integrated on Si. Each device is built around a GaAs nanoelement core, directly grown on either GaP or Si. A portion of each diode acts as the active region in these individual nanosized p-i-n light emitting structures.
  • the LED device comprises of p-i-n diode structures corresponding to the embodiments described above with reference to Fig. 9a and 9b.
  • the substrate 110 is an integral part of the device, as it functions as a common p-layer.
  • Each nanostructured LED structure comprise a nanoelement 100 having a core 133 and a shell layer 131 enclosing at least a portion of the nanoelement core 133, a volume element 105 and a first concentric layer 106 forming a top contact.
  • the sequence of p-doped, n-doped and intrinsic semiconductor materials will depend on the substrate material.
  • the structure is: p-GaP (substrate) 110, i-GaP/i-GaAs (nanoelement core) 133, i-InGaP (nanoelement shell layer) 131, and n-InGaP (volume element) 105.
  • the structure is: p-Si(substrate) 110, i-GaP/i-GaAs (nanoelement core) 133, i- InGaP (nanoelement shell layer) 131 and n-InGaP (volume element) 110.
  • the i-GaP (first nanoelement core segment) layer 100a in the nanowire base is approximately 60 nm thick in both the devices and serves the dual purposes of a nucleation segment for improved growth quality and electron barrier.
  • the fabrication process is explained in the following. THMa metal organic sources and TMIn together with AsH3, PH3, and Si 2 He as precursor gases were used. Two growth steps were employed. First, 2 ⁇ m long GaAs/ GaP nanowires, i.e.
  • the nanoelement cores 133 were enclosed with 40 nm thick radial InGaP shell layer 131, nominally lattice matched to GaAs. After this step, samples were unloaded for photoluminescence characterization or subsequent fabrication of the nanostructured LEDs. 80 nm thick Si ⁇ 2 was deposited onto the samples lined for LED fabrication.
  • the SiO 2 was back etched back to only cover the substrate surface and up to approximately l ⁇ m of the side wall of the nanoelements 100.
  • the samples were then reloaded into the MOVPE reactor and a radial Si-doped InGaP volume element 105 was selectively grown on the upper part of the GaAs/InGaP nanoelement 100.
  • the LEDs were fully covered with 150-300 nm thick 200x200 ⁇ m 2 quadratic Ni/Ge/Au contacts 106, each covering approximately 40000 individual nanostructured LEDs.
  • the p-contact was fabricated on the backside of the substrate 110 with conductive Ag paste. Other means of contacting, for example using transparent contacts are known in the art and easily adopted to the present method and device.
  • a scanning electron microscopy (SEM) image of the structure is shown in Fig. 20.
  • One important difference between the Si and the GaP device is the heterostructure sequence in the base of the nanowire, on GaP substrate being p-GaP (substrate) /i- GaP (first nanoelement core segment) /i-GaAs (second nanoelement core segment), while on Si substrate being p-Si (substrate) /i-GaP (first nanoelement core segment) /i-GaAs (first nanoelement core segment), and both hole injection conditions and internal resistance and should be expected to be appreciably different between the two structures.
  • Fig. 21 depicts nanoelement structures after the first MOVPE step. Depicted are nanoelements having GaAs nanoelement cores 133 with a thin InGaP shell layer 131, a GaP nucleation segment 100a in the base of the nanoelements 100, and with the Au based seed particle 130 still attached to the top. Such structures were also transferred to neutral substrates for PL characterization. As shown in FIG. 21 the yield is essentially 100 percent on both GaP and Si substrates. The fabrication of the nanostructured LEDs on Si is refined to the degree that the nanoelements 100 are uniformly aligned the (111) direction normal to the substrates and essentially no nanoelements 100 are grown in the three declined (111) directions that also extends out from the substrate 110.
  • III- V nanoelement growth on Si(111) This in contrast to prior art methods of III- V nanoelement growth on Si(111).
  • the well aligned growth of III- V nanoelements 100 in predefined array structures on Si substrates, as seen in Fig. 21, is a prerequisite for successful large scale fabrication of optical devices, as well as most other applications.
  • LED functionality can be indicated by Photoluminescence (PL) measurements.
  • the measurements here presented were carried out at room temperature and at a temperature of 10 K. The result is illustrated in the graphs of Fig. 22 and Fig. 23.
  • a laser emitting at 473 nm was used as an excitation source.
  • the PL was collected by an optical microscope, dispersed through a spectrometer and detected by a liquid N2 cooled CCD camera.
  • the nanoelements 100 were broken off and transferred from the substrate 110 where they were grown, and then deposited on a patterned Au surface. In this way the nanoelements could also be studied individually.
  • the dashed lines are the spectra from (a large number of) nanoelements 100 still standing on the substrate 110.
  • the spectra from individual nanoelements showed larger differences, with the nanoelements 100 grown from a GaP substrate 110 being more structured.
  • the average PL intensity for the nanoelements grown from Si was about a factor of 20 lower than for the corresponding nanoelements 100 grown from GaP. This is in fair agreement with the 10-30 times lower electro- luminence seen for the Si-LED as compared to the GaP-LED. At room temperature the spectra are broad and featureless and there is very little spectral difference between nanowires from the two samples.
  • the light power/ current dependence is shown for the Si based (Si) and GaP based (GaP) LEDs.
  • the LED on GaP lights up at half the current load (20 mA) of the Si (40 mA) and at 60 mA the power output is approximately 30 times higher on the GaP substrate. However, at 100 mA the power ratio has decreased to 10 times the Si based LED.
  • the EL spectral peak is shown for 80 mA load for both devices.
  • the Si LED peak show a slight red shift and tail with a possible extra peak around 1.35 eV as compared to the GaP substrate device. The shift in peaks can be explained by the different In and Ga diffusion on GaP and Si leading to different InGaP composition.
  • LED devices build on GaN nanoelements are of high commercial interest due to their ability to produce light of wavelengths not accessible with other material combinations.
  • a layer of SiN x (30 run in thickness) was deposited by PECVD.
  • arrays of dot-patterned GaN openings (around 100 nm in diameter) were made by epitaxial beam lithography, EBL, and reactive ion etching, RIE.
  • the pitch between the openings was ranged as 1.0-3.2 ⁇ m.
  • the as-processed samples were inserted into a, horizontal MOCVD chamber to grow GaN nanoelements.
  • the growth process comprises an initial phase wherein temperature was ramped up to the growth zone of 1000-1500 ° C within 5 min with a high NH3 flow rate of 75 seem for approximately 60 seconds giving an annealing.
  • the NH3 flow rate was reduced to 3.0-0.2 seem to start the growth with introducing TMG (trimethylgallium) into the chamber.
  • TMG trimethylgallium
  • Low TMG flow rate was used through this work, between 0.12 and 1.2 ⁇ mol/min.
  • the NH3 flow rate is the crucial factor controlling the growth forms from the openings.
  • Fig. 25 shows the SEM images of the sample grown with the NH3 flow rate of 3.0 seem.
  • FIG. 25 (a) From the top-view image [Fig. 25 (a)], it can be seen that the selective growth from the openings, which is the same as what was reported. The point needed to be specified here is that the lateral size after growth is larger than 1.0 ⁇ m which is much larger than the openings size of around 100 nm. Thus, the lateral growth after GaN had grown out of openings is substantial.
  • Fig. 25 (b) shows the SEM image taken by tilting the sample by 35 ° , which clearly presents that what were obtained are pyramids, not wires. The pyramids are delimited by six
  • FIG. 26 shows the SEM characterizations of the sample grown under NH3 flow rate of 1.0 seem.
  • the top-view image [Fig. 26 (a)] is similar as Fig. 25 (a). But, the 35 ° -tilted image [Fig. 26 (b)] is
  • Fig. 27 shows the growth results with reducing NH3 flow rate further to 0.5 seem. Both top-view and 35°-tilted images indicate the size shrinking in lateral direction, although they are still larger than the openings size of around 100 nm. And the tilted image [Fig. 27 (b)] also shows the vertical facets.
  • NH3 flow rate was lowered to 0.2 seem, true GaN nanowires began to be synthesized as shown in Fig. 28.
  • the NH3 flow rate should be adjusted so that a low supersaturation is achived, or alternatively described; to achieve migration enhanced growth. If other shapes are required, for example pyramids, the NH3 flow rate can be 1 seem or higher. Further fabrication steps, i.e. providing shell layers, volume elements and concentric layers may be performed in the above described manners.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Nanotechnology (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Composite Materials (AREA)
  • Led Devices (AREA)

Abstract

La présente invention concerne un dispositif à semi-conducteurs comprenant un élément nanométrique à semi-conducteurs (100) et un élément de volume (105) agencés en connexion épitaxiale l'un à l'autre. Le dispositif à semi-conducteurs est électriquement raccordable à l'élément de volume (105) et l'élément nanométrique (100) est connecté électriquement en série. L'élément de volume (105) est au moins partiellement dopé afin de produire une concentration de porteurs de charge élevée dans l'élément nanométrique (100) et une faible résistance d'accès dans la connexion électrique avec l'élément de volume (105). De préférence l'élément nanométrique (100) s'avance à partir d'un substrat à semi-conducteurs (110). Une couche concentrique (106) peut être agencée sur l'élément de volume (105) pour former un contact électrique. Des structures de DEL comprenant des structures d'élément de volume/éléments nanométriques (100, 105) sont décrites. Un procédé pour produire un dispositif à semi-conducteurs selon l'invention est également présenté.
PCT/SE2007/001171 2006-12-22 2007-12-22 Structure nanoélectronique et procédé de production associé WO2008079077A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP07861100A EP2095426A4 (fr) 2006-12-22 2007-12-22 Structure nanoélectronique et procédé de production associé

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
SE0602840-1 2006-12-22
SE0602840 2006-12-22
SE0700102 2007-01-12
SE0700102-7 2007-01-12
US11/812,226 2007-06-15
US11/812,226 US8049203B2 (en) 2006-12-22 2007-06-15 Nanoelectronic structure and method of producing such
SE0702404 2007-10-26
SE0702404-5 2007-10-26

Publications (2)

Publication Number Publication Date
WO2008079077A2 true WO2008079077A2 (fr) 2008-07-03
WO2008079077A3 WO2008079077A3 (fr) 2008-08-21

Family

ID=40902775

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SE2007/001171 WO2008079077A2 (fr) 2006-12-22 2007-12-22 Structure nanoélectronique et procédé de production associé

Country Status (2)

Country Link
EP (1) EP2095426A4 (fr)
WO (1) WO2008079077A2 (fr)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010027322A1 (fr) * 2008-09-04 2010-03-11 Qunano Ab Photodiode nanostructurée
JP2011211047A (ja) * 2010-03-30 2011-10-20 Sharp Corp 表示装置、表示装置の製造方法および表示装置の駆動方法
EP2412028A1 (fr) * 2009-03-25 2012-02-01 Glo Ab Dispositif schottky
WO2012035243A1 (fr) * 2010-09-14 2012-03-22 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif optoelectronique a base de nanofils pour l'émission de lumière
WO2012066444A1 (fr) * 2010-11-17 2012-05-24 International Business Machines Corporation Dispositifs à nanofil contraint
EP2472585A1 (fr) * 2009-09-30 2012-07-04 National University Corporation Hokkaido University Transistor à effet de champ et effet tunnel et procédé de fabrication associé
WO2013121289A2 (fr) 2012-02-14 2013-08-22 Qunano Ab Electronique à base de nanofil de nitrure de gallium
EP2667416A1 (fr) * 2012-05-25 2013-11-27 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Transistor à base de nanofil, procédé de fabrication du transistor et composant semi-conducteur intégrant le transistor
WO2014066379A1 (fr) 2012-10-26 2014-05-01 Glo Ab Structure optoélectronique dimensionnée pour nanofil, et procédé de modification de parties sélectionnées de ladite structure
EP2297785A4 (fr) * 2008-07-09 2015-04-29 Qunano Ab Dispositif semi-conducteur optoelectronique
EP2747152A4 (fr) * 2011-08-19 2015-05-20 Postech Acad Ind Found Cellule solaire et procédé de fabrication de ladite cellule
EP2870632A4 (fr) * 2012-07-06 2016-03-09 Qunano Ab Dispositifs diodes esaki à nanofil radial et procédés associés
US9329433B2 (en) 2010-03-12 2016-05-03 Sharp Kabushiki Kaisha Light-emitting device manufacturing method, light-emitting device, lighting device, backlight, liquid-crystal panel, display device, display device manufacturing method, display device drive method and liquid-crystal display device
CN106170867A (zh) * 2014-03-28 2016-11-30 英特尔公司 用于垂直型半导体器件的选择性再生长顶部接触部
KR20160137970A (ko) * 2014-03-28 2016-12-02 인텔 코포레이션 수직 반도체 디바이스들을 제조하기 위한 종횡비 트래핑(art)
CN111668204A (zh) * 2013-09-30 2020-09-15 原子能与替代能源委员会 用于制造具有发光二极管的光电子器件的方法
WO2020260658A1 (fr) * 2019-06-28 2020-12-30 Aledia Procede de fabrication de microfils ou nanofils
TWI856122B (zh) 2019-06-28 2024-09-21 法商艾勒迪亞公司 微米線或奈米線製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3243303B2 (ja) * 1991-10-28 2002-01-07 ゼロックス・コーポレーション 量子閉じ込め半導体発光素子及びその製造方法
US6996147B2 (en) * 2001-03-30 2006-02-07 The Regents Of The University Of California Methods of fabricating nanostructures and nanowires and devices fabricated therefrom
EP1420463A4 (fr) * 2001-08-22 2008-11-26 Sony Corp Element semiconducteur au nitrure et procede de production de cet element
US20040003839A1 (en) * 2002-07-05 2004-01-08 Curtin Lawrence F. Nano photovoltaic/solar cells
US7211143B2 (en) * 2002-12-09 2007-05-01 The Regents Of The University Of California Sacrificial template method of fabricating a nanotube
WO2004088755A1 (fr) * 2003-04-04 2004-10-14 Startskottet 22286 Ab Nanowhiskers pourvus de jonctions pn, et leurs procedes de production
KR100553317B1 (ko) * 2004-04-23 2006-02-20 한국과학기술연구원 실리콘 나노선을 이용한 실리콘 광소자 및 이의 제조방법
JP4740795B2 (ja) * 2005-05-24 2011-08-03 エルジー エレクトロニクス インコーポレイティド ロッド型発光素子及びその製造方法
WO2006135336A1 (fr) * 2005-06-16 2006-12-21 Qunano Ab Transistor a nanofil semi-conducteur

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of EP2095426A4 *

Cited By (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2297785A4 (fr) * 2008-07-09 2015-04-29 Qunano Ab Dispositif semi-conducteur optoelectronique
WO2010027322A1 (fr) * 2008-09-04 2010-03-11 Qunano Ab Photodiode nanostructurée
CN102144298A (zh) * 2008-09-04 2011-08-03 昆南诺股份有限公司 纳米结构的光电二极管
US8692301B2 (en) 2008-09-04 2014-04-08 Qunano Ab Nanostructured photodiode
EP2412028A1 (fr) * 2009-03-25 2012-02-01 Glo Ab Dispositif schottky
US8766395B2 (en) 2009-03-25 2014-07-01 Qunano Ab Schottky device
EP2412028A4 (fr) * 2009-03-25 2014-06-18 Qunano Ab Dispositif schottky
EP2472585A1 (fr) * 2009-09-30 2012-07-04 National University Corporation Hokkaido University Transistor à effet de champ et effet tunnel et procédé de fabrication associé
EP2472585A4 (fr) * 2009-09-30 2014-08-06 Univ Hokkaido Nat Univ Corp Transistor à effet de champ et effet tunnel et procédé de fabrication associé
US9329433B2 (en) 2010-03-12 2016-05-03 Sharp Kabushiki Kaisha Light-emitting device manufacturing method, light-emitting device, lighting device, backlight, liquid-crystal panel, display device, display device manufacturing method, display device drive method and liquid-crystal display device
JP2011211047A (ja) * 2010-03-30 2011-10-20 Sharp Corp 表示装置、表示装置の製造方法および表示装置の駆動方法
WO2012035243A1 (fr) * 2010-09-14 2012-03-22 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif optoelectronique a base de nanofils pour l'émission de lumière
US9263633B2 (en) 2010-09-14 2016-02-16 Commissariat A L'energie Atomique Et Aux Energies Alternatives Nanowire-based optoelectronic device for light-emission
US9093607B2 (en) 2010-09-14 2015-07-28 Commissariat A L'energie Atomique Et Aux Energies Alternatives Nanowire-based optoelectronic device for light emission
GB2500831B (en) * 2010-11-17 2014-07-02 Ibm Nanowire devices
WO2012066444A1 (fr) * 2010-11-17 2012-05-24 International Business Machines Corporation Dispositifs à nanofil contraint
US8969179B2 (en) 2010-11-17 2015-03-03 International Business Machines Corporation Nanowire devices
CN103210492A (zh) * 2010-11-17 2013-07-17 国际商业机器公司 应变纳米线器件
US9245750B2 (en) 2010-11-17 2016-01-26 International Business Machines Corporation Nanowire devices
GB2500831A (en) * 2010-11-17 2013-10-02 Ibm Strained nanowire devices
US9384975B2 (en) 2010-11-17 2016-07-05 International Business Machines Corporation Nanowire devices
EP2747152A4 (fr) * 2011-08-19 2015-05-20 Postech Acad Ind Found Cellule solaire et procédé de fabrication de ladite cellule
WO2013121289A2 (fr) 2012-02-14 2013-08-22 Qunano Ab Electronique à base de nanofil de nitrure de gallium
US9653286B2 (en) 2012-02-14 2017-05-16 Hexagem Ab Gallium nitride nanowire based electronics
US10236178B2 (en) 2012-02-14 2019-03-19 Hexagem Ab Gallium nitride nanowire based electronics
EP2815423A4 (fr) * 2012-02-14 2015-09-09 Qunano Ab Electronique à base de nanofil de nitrure de gallium
FR2991100A1 (fr) * 2012-05-25 2013-11-29 Commissariat Energie Atomique Transistor a base de nanofil, procede de fabrication du transistor, composant semi-conducteur integrant le transistor, programme informatique et support d'enregistrement associes au procede de fabrication
EP2667416A1 (fr) * 2012-05-25 2013-11-27 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Transistor à base de nanofil, procédé de fabrication du transistor et composant semi-conducteur intégrant le transistor
US10090292B2 (en) 2012-07-06 2018-10-02 Qunano Ab Radial nanowire Esaki diode devices and methods
EP2870632A4 (fr) * 2012-07-06 2016-03-09 Qunano Ab Dispositifs diodes esaki à nanofil radial et procédés associés
EP2912699B1 (fr) * 2012-10-26 2019-12-18 Glo Ab Procédé de modification de parties sélectionnées d'une structure optoélectronique à l'échelle d'un nanofil
WO2014066379A1 (fr) 2012-10-26 2014-05-01 Glo Ab Structure optoélectronique dimensionnée pour nanofil, et procédé de modification de parties sélectionnées de ladite structure
CN111668204B (zh) * 2013-09-30 2023-09-15 原子能与替代能源委员会 用于制造具有发光二极管的光电子器件的方法
CN111668204A (zh) * 2013-09-30 2020-09-15 原子能与替代能源委员会 用于制造具有发光二极管的光电子器件的方法
KR20160137969A (ko) * 2014-03-28 2016-12-02 인텔 코포레이션 수직 반도체 디바이스들을 위한 선택적으로 재성장된 상부 컨택트
CN106170867A (zh) * 2014-03-28 2016-11-30 英特尔公司 用于垂直型半导体器件的选择性再生长顶部接触部
US10727339B2 (en) 2014-03-28 2020-07-28 Intel Corporation Selectively regrown top contact for vertical semiconductor devices
KR20160137970A (ko) * 2014-03-28 2016-12-02 인텔 코포레이션 수직 반도체 디바이스들을 제조하기 위한 종횡비 트래핑(art)
KR102167517B1 (ko) * 2014-03-28 2020-10-19 인텔 코포레이션 수직 반도체 디바이스들을 제조하기 위한 종횡비 트래핑(art)
KR102168936B1 (ko) * 2014-03-28 2020-10-22 인텔 코포레이션 수직 반도체 디바이스들을 위한 선택적으로 재성장된 상부 컨택트
EP3123520A4 (fr) * 2014-03-28 2017-11-22 Intel Corporation Contact supérieur mis à nouveau à croître de façon sélective pour des dispositifs verticaux à semi-conducteurs
WO2020260658A1 (fr) * 2019-06-28 2020-12-30 Aledia Procede de fabrication de microfils ou nanofils
FR3098011A1 (fr) * 2019-06-28 2021-01-01 Aledia Procede de fabrication de microfils ou nanofils
TWI856122B (zh) 2019-06-28 2024-09-21 法商艾勒迪亞公司 微米線或奈米線製造方法

Also Published As

Publication number Publication date
WO2008079077A3 (fr) 2008-08-21
EP2095426A2 (fr) 2009-09-02
EP2095426A4 (fr) 2012-10-10

Similar Documents

Publication Publication Date Title
US9096429B2 (en) Nanoelectronic structure and method of producing such
EP2095426A2 (fr) Structure nanoélectronique et procédé de production associé
Tomioka et al. Selective-area growth of III-V nanowires and their applications
EP2509119B1 (fr) Élément électroluminescent et son procédé de fabrication
US8557622B2 (en) Epitaxial growth of in-plane nanowires and nanowire devices
TWI621278B (zh) 具有應變改質表面活性區域之第三族氮化物奈米線ｌｅｄ及其製造方法
Tomioka et al. III–V nanowires on Si substrate: selective-area growth and device applications
US8227817B2 (en) Elevated LED
i Morral Gold-free GaAs nanowire synthesis and optical properties
CN110249491A (zh) 基于在石墨烯型基底上生长的纳米线的激光器或led
CN110678990B (zh) 纳米结构
US8183566B2 (en) Hetero-crystalline semiconductor device and method of making same
EP3358604A1 (fr) Transistor à effet de champ et à effet tunnel
Boras et al. III–V ternary nanowires on Si substrates: growth, characterization and device applications
CN114207778A (zh) 纳米线器件
US9196787B2 (en) Nanowire LED structure with decreased leakage and method of making same
US9196792B2 (en) Nanowire LED structure with decreased leakage and method of making same
Sadaf et al. Structural and electrical characterization of monolithic core–double shell n-GaN/Al/p-AlGaN nanowire heterostructures grown by molecular beam epitaxy
Zwiller et al. Optics with single nanowires
Dai et al. Advanced III–V nanowire growth toward large-scale integration
Yan et al. Semiconductor nanowire heterodimensional structures toward advanced optoelectronic devices
Tomioka et al. III–V Semiconductor nanowires on Si by selective-area metal-organic vapor phase epitaxy
WO2024042219A1 (fr) Dispositif à nanofils avec couche de masque
Jeon et al. Epitaxial Heterostructure Nanowires

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07861100

Country of ref document: EP

Kind code of ref document: A2

REEP Request for entry into the european phase

Ref document number: 2007861100

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2007861100

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 4112/DELNP/2009

Country of ref document: IN

NENP Non-entry into the national phase

Ref country code: DE