WO2007108471A1

WO2007108471A1 - Modulation device, demodulation device, and modulating method

Info

Publication number: WO2007108471A1
Application number: PCT/JP2007/055682
Authority: WO
Inventors: Zhanji Wu; Jifeng Li
Original assignee: Matsushita Electric Industrial Co., Ltd.
Priority date: 2006-03-20
Filing date: 2007-03-20
Publication date: 2007-09-27
Also published as: CN101043483A

Abstract

A modulation device, a demodulation device and a modulating method are provided with a feature to reduce a bit error rate. A modulation device (100) is comprised of an LDPC coding unit (110) for carrying out LDPC coding of a source data block to form a coded data block, a bit disposition changing unit (120) for changing a disposition of each coded bit of the coded data block in order of strength for a bit protection capability, a dividing unit (130) for dividing a coded bit sequence changed in disposition into sub-blocks that are equal to the number of bits composed of a unit bit string indicated by one modulating symbol, and a modulating unit (160) for forming a modulation signal in accordance with a modulation symbol on a constellation corresponding to bit sequences obtained when bit groups extracted from one bit per each sub-block in turn are changed in disposition in response to allocation to sub-blocks of composed bits based on an error tendency per composed bit and the bit protection capability. A demodulation device (200) carries out demodulation processes corresponding to those set forth above.

Description

Specification

Modulation device, demodulation device, and modulation method

Technical field

TECHNICAL FIELD [0001] The present invention relates to a modulation device, a demodulation device, and a modulation method, and in particular, a modulation device that performs channel error correction, a low density parity check code (LDPC code), and an LDPC encoded signal. The present invention relates to a demodulation device that performs demodulation and a modulation method that performs LDPC coding.

Background art

[0002] LDPC codes are a very powerful forward error correction coding method that was rediscovered in the last decade or so. LDPC codes are considered to be effective alternatives to turbo codes because they are already approaching the Shannon limit under the long code structure, and may be adopted in next-generation mobile communications and deep space communications. Is expensive.

FIG. 1 is a diagram showing a simple example of a low density parity check code using a bipartite graph. An LDPC code is a linear block code with a kind of sparse check matrix. Since 1981, when Tanne introduced a method for representing low-density linear block codes using bipartite graphs, bipartite graphs have become the primary tool for analyzing LDPC codes. For an LDPC code, if the information bit length is K, the code length is Ν, and the NORMAL bit is Μ = Ν—Κ, the check matrix の of this code is a matrix whose size is M X N. The bipartite graph shows the following: That is, the N nodes below the bipartite graph represent N codewords and become message nodes, the M nodes above represent M check expressions, and check nodes Called. If the lower message node and the upper check node exist in the same check expression, they are connected using an edge. The number of lines connected to each node is called the degree of this node. For decoding of LDPC codes, the entire process of force decoding using the Sum-Product algorithm is as seen in the application of BP algorithm on the Tanner bipartite graph (eg, Non-Patent Document 1).

[0004] On the other hand, higher-order modulation techniques such as 8PSK, 16QAM, 64QAM, and 256QAM have been introduced in order to further improve the frequency spectrum utilization efficiency (for example, Non-Patent Document 2). Higher order In the modulation constellation diagram, each modulation symbol consists of a few bits. For example, 8PSK, 16QAM, 64QAM, and 256QAM modulation symbols are composed of 3, 4, 6, and 8 bits, respectively. In order to reduce the bit error rate, Golay mapping is usually used for mapping the bit string power to the modulation symbol.

[0005] Figure 2 shows the constellation map of 16QAM Golay coding. A constellation point is represented by 4 bits (a a a a). However, X-axis component (I-axis

1 2 3 4

) Is a a, Y-axis component (Q-axis) is a a, and the constellation diagram energy positive

1 2 3 4

The rule element is c = 1Z10.

FIG. 3 is a diagram showing a constellation map of 64QAM Golay coding.

Each constellation point is represented by 6 bits (a a a a a a). However, X-axis

1 2 3 4 5 6

The minute (I axis) is a a a, and the Y axis component (Q axis) is a a a.

1 2 3 4 5 6

The Lugi regular element is c = lZ42.

[0007] In Golay mapping, the protection capability of each bit in a bit string is uneven, and there are bits with strong protection capability and some bits with weak protection capability. According to the prior art, the protection capability of each bit is determined by the sum of the hamming distances of each bit, and the greater the sum of the hamming distances, the weaker the protection capability of the bits. (See Non-Patent Documents 2 and 3 described at the end of the text for typical derivation process). As a matter of course, the strength of the bit protection capability may be determined by other methods known to those skilled in the art. For example, in the 16Q AM Golay coding constellation map shown in Figure 2, a a is a strong bit and a a is

1 3 2 4 Weak bits. In the constellation map of 64QAM Golay coding shown in Fig. 3, a a is a strong bit, a a is a weak bit, and a a is an intermediate.

1 4 3 6 2 5

[0008] Further, in the conventional LDPC high-order modulation method of bit interleaved code modulation (BICM), as shown in Fig. 4, an LDPC channel encoder and a high-order modulator are randomly combined. They are simply connected in series to a Nell interleaver, and they do not cooperate effectively. According to the current trend (see Non-Patent Documents 4 to 8), in non-regular LDPC codes, the higher the bit node frequency, the stronger the bit protection capability and the lower the bit error rate. It is regarded. Therefore, in the recent LDPC code modulation method (Non-Patent Document 4) based on Bit-Reliability Mapping, as shown in FIG. In addition, high frequency bits are mapped to strong bit positions in high-order modulation, and low V bits are mapped to weak bit positions in high-order modulation.

However, the standard theory (Non-patent Document 9) determines that the protection capability of a bit is determined by the degree of protection indicated by its separation distance, not by frequency.

Non-Special Reference 1: Matthew C. Davey, PHD Thesis: Error-correction using Low-Density Parity-Check Code, Gonville and Caius College, Cambridge, 1999

Non-Patent Document 2: Stephen G. Wilson, Digital Modulation and Coding, Prentice-Hall, 19 96

Patent Document 3: Pavan K. Vitthaladevuni, and Mohamed— Slim Alouini, A Recursive Alg orithm for the Exact BER Computation of Generalized Hierarchical QAM Constellati ons, IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 49, NO. 1, JAN UARY 2003 297

Non-Patent Document 4: Yan Li and William E. Ryan, "Bit-Reliability Mapping in LDPC- Coded Modulation Systems", IEEE Communications Letters, VOL. 9, NO. 1, JANUARY 2005

Non-Patent Document 5: Stephan ten Brink, Gerhard Kramer, and Alexei Ashikhmin, "Design of Low— Density Parity-Check Codes for Modulation and Detection, IEEE Trans. Commun" VOL. 52, NO. 4, APRIL 2004

Non-Patent Document 6: Xiumei Yang; Dongfeng Yuan; Piming Ma; Mingyan Jiang, "New resea rch on unequal error protection (UEP) property of irregular LDPC codes", Consumer Communications and Networking Conference, 2004. CCNC 2004. First IEEE 5 —8 J an. 2004 Page (s): 361-363

^^ Patent Literature 7: Poulliat, C; Declercq, D .; Fijalkow, I .; Optimization of LDPC codes for UEP channels ", International Symposium on Information Theory 2004. Proceeding ngs. 27 June- 2 July 2004 Page (s): 450

Patent Document 8: Rahnavard, N .; Fe n, F .; "Unequal error protection using low—densit y parity-check codes", International Symposium on Information Theory 2004. Proce edings. 27 June— 2 July 2004 Page (s) : 449 Non-Patent Document 9: Wang Xinmei, Xiao Guoqian "Error Correction Code Principle and Method", publisher of Xi'an Electronic Technology University, revised in April 2001

Disclosure of the invention

Problems to be solved by the invention

[0010] In some documents, the bit error rate of nodes with high frequency is low because the frequency distribution of bit nodes of the irregular LDPC codes selected in these documents is extremely wide. This is because very high frequency nodes have a relatively high average degree of protection over very low frequency nodes. Even if all the frequency distribution polynomials for bit nodes and check nodes are determined, the parity check matrix of the configured L DPC codes is diverse, so the bit error rate performance is also greatly different. On the other hand, for the L DPC code where the frequency distribution polynomials of the bit nodes and check nodes are all determined, the above method does not actually differ, so this method can be a general and accurate method. Absent. As is well known, the error correction performance of an LDPC code is almost determined by an element diagram (factor graph) representing the details of its configuration, that is, a bipartite graph. In particular, in the high signal-to-noise ratio region, it is determined by the short cycle on the bipartite graph. Obviously, the above method cannot accurately reflect the topology structure of the bipartite graph of LDPC codes. Therefore, the method described above reflects the unequal error protection (UEP) characteristics of the LDPC code to some extent! However, this method is not a reliable method. In other words, this method is uncertain in predicting the UEP performance of LDPC codes and cannot be used to analyze the UEP characteristics of regular LDPC codes. Therefore, this coded modulation method has a certain limit in terms of improving error correction performance.

An object of the present invention is to provide a modulation device, a demodulation device, and a modulation method that reduce the bit error rate.

Means for solving the problem

[0012] The modulation apparatus according to the present invention is based on the order of LDPC encoding means for forming an encoded data block by performing LDPC encoding on the source data block, and the order of strength of bit protection capability. Bit reordering to reorder each sign key of the sign key data block Dividing means for dividing the rearranged encoded bit sequence into a plurality of sub-blocks equal to the number of constituent bits of a unit bit string represented by one modulation symbol, and the constituent bits Corresponds to the bit string obtained when rearranging bit groups extracted one bit at a time from each sub-block according to the allocation of the configuration bits to the sub-block according to the ease of error for each and the bit protection capability of the sub-block And a modulation means for forming a modulation signal in accordance with the modulation symbol on the constellation.

[0013] The demodulator of the present invention is a demodulator that demodulates the modulated signal formed by the modulator, and converts the modulated signal into the bit string based on the constellation. Demodulating means for allocating each bit of the bit string for each sub-block, combining means for forming the rearranged code key sequence by synthesizing the sub-block, and the bit rearranging means The other bit rearrangement unit that performs the reverse operation on the encoded bit sequence formed by the synthesis unit, and the LDPC decoding process on the code data sequence obtained by the other bit rearrangement unit. And an LDPC decoding means for performing a trap.

[0014] The modulation method of the present invention performs the LDPC code process on the source data block to form an encoded data block, and the code data is based on the order of the strength of the bit protection capability. Rearranging the code bits of the block, dividing the code bit sequence after the rearrangement into a plurality of sub-blocks such as the number of constituent bits of a unit bit string represented by one modulation symbol, Obtained when the bit groups sequentially extracted from each subblock are rearranged in accordance with the allocation of the configuration bits to the subblock based on the ease of error for each configuration bit and the bit protection capability of the subblock. The step of forming the modulation signal according to the modulation symbol on the constellation corresponding to the bit string to be And.

The invention's effect

According to the present invention, it is possible to provide a modulation device, a demodulation device, and a modulation method that reduce the bit error rate.

Brief Description of Drawings [Figure 1] A simple example of a low-density parity check code using a bipartite graph

[Figure 2] Diagram showing the constellation map for 16QAM Golay coding

[Figure 3] Diagram showing constellation map of 64QAM Golay coding

[Fig.4] Diagram for explaining LDPC high-order modulation method based on conventional bit interleaved code modulation (BICM)

[FIG. 5] A diagram for explaining an LDPC high-order modulation method based on conventional bit reliability mapping. [FIG. 6] A hierarchical interleaved LDPC high based on non-uniform error characteristic matching according to an embodiment of the present invention. Diagram for explaining the next modulation method

[Fig. 7] A diagram for explaining the relationship between the separation distance of the LDPC code and the circumference of the shortest short cycle on the bipartite graph

[Fig.8] [2000, 1000] Regular Diagram showing bit error rate performance for different separation distances of LDPC codes

[Fig. 9] A diagram for explaining the relationship between the separation distance of LDPC codes and the circumference of the shortest short cycle on the bipartite graph and the relationship between bit strength and separation distance.

FIG. 10 is a diagram illustrating a main configuration of a modulation apparatus that performs a high-order modulation method of a common LDPC code according to an embodiment of the present invention.

FIG. 11 is a diagram showing a main configuration of a demodulator that demodulates a received signal subjected to high-order modulation of a common LDPC code according to an embodiment of the present invention.

FIG. 12 is a diagram showing a main configuration of a modulation apparatus that performs a high-order modulation method of an LDPC code for IZQ axisymmetric modulation according to an embodiment of the present invention.

FIG. 13 is a diagram showing a main configuration of a demodulating apparatus that demodulates a received signal subjected to high-order modulation of an LDPC code of I / Q axisymmetric modulation according to an embodiment of the present invention.

FIG. 14 is a diagram illustrating a main configuration of a modulation apparatus that performs high-order modulation of an LDPC code of 16QAM modulation according to an embodiment of the present invention.

FIG. 15 is a diagram showing a main configuration of a demodulator that demodulates a received signal subjected to high-order modulation of a 16QAM-modulated LDPC code according to an embodiment of the present invention.

[Fig.16] [2000,1000] regular LDPC code 16QAM and 64QAM performance comparison diagram

[Fig.17] [3000, 1000] irregular LDPC code 16QAM and 64QAM performance comparison diagram BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. It should be pointed out that the embodiments described herein are for illustrative purposes only and do not limit the scope of the invention. The various numerical values described here are not intended to limit the present invention, and these numerical values can be appropriately changed as necessary by those skilled in the art. In the present specification, the present invention has been described by taking IZQ axisymmetric modulation and 16QAM modulation as examples. However, it is obvious that it can be applied to communication systems that employ other M-QAM (M = 2m) modulation methods such as 64Q AM. In the embodiments, the same components are denoted by the same reference numerals, and the description thereof will be omitted because it is redundant.

[0018] LDPC codes have non-uniform error protection characteristics, but normal high-order modulation also has a distinction between strong and weak bits. According to the standard theory of linear unequal error protection coding (LUEP) (see Non-Patent Document 9 above), for a general linear block code, each bit i has a separation distance s. Can be used to represent the protection capability of the bit. The separation distance s can be expressed as follows.

[Equation 1] s _t ≡ xmn {w (X) I AX = 0, x, = 1}

Where A is the parity check matrix and X is the codeword. X represents bit i, and w (X) represents the weight of codeword X. s sets bit X to 1 and bit X satisfies the minimum weight of all codewords in the parity check matrix.

[0019] Further, if t is defined as the protection capability or protection level of bit X, ti is expressed as follows.

[Equation 2]

I s _; -1 1

When t is not larger than the number of error bits generated in the transmitted codeword, t indicates that the bit error of bit X can be corrected accurately by the maximum likelihood decoding function. The smaller s or t, the weaker the protection, or the weak bit is called. [0021] Based on the above UEP protection class concept, this embodiment presents a new LDPC higher-order modulation method using hierarchical interleaving based on non-uniform error characteristic matching.

[0022] As shown in FIG. 6, bits with a low protection grade in the LDPC code are mapped to bits with high protection capability in high-order modulation. In particular, the bits belonging to the codeword with the smallest LDPC weight must be mapped to the strongest bits in higher-order modulation. In short, the weak bits of the LDPC code are mapped to the strong bits of the high-order modulation, and the strong bits of the LDPC code are mapped to the weak bits of the high-order modulation symbol. Thus, by effectively matching the non-uniform error protection characteristics of the LDPC code with the non-uniform error protection characteristics of the higher-order modulation, the bit error rate is lowered and the coded modulation gain is obtained.

[0023] Through research, the inventors found that there is a close relationship between the separation distance of the LDPC code and the short cycle on the bipartite graph. In a bipartite graph composed of loops, the separation distance of a bit is equal to half the circumference of the shortest short cycle in which the bit exists. For example, in the short cycle of length 4 shown in Figure 7, both bits b and b are 1.

1 2

Satisfies the constraints of the check expressions c and c. Therefore, the separation distance between bits b and b is 2,

1 2 1 2

The bit is half the circumference of the shortest short circle with the bit. Therefore, compared to the LDPC higher-order modulation method based on bit reliability mapping, the method of this embodiment can accurately reflect the characteristics of the bipartite graph structure of the LDPC code and can be applied to irregular LDPC codes. It can also be applied to regular LDPC codes. Different LDPC codes with all bit node and check node frequency distributions corresponding to bipartite graphs with different check matrices do not have the same protection class. Therefore, the method of this embodiment has a stronger adaptability to the LDPC code, and is more accurate in determining its UEP characteristics.

[0024] FIG. 8 is a diagram of bit error rate performance of [2000, 1000] regular LDPC codes with different separation distances. It uses binary phase shift keying (BPSK) and additive white Gaussian noise (AWGN) channels. The LDPC code is a [2000, 1000] regular code with half the code rate, and all short cycles of length 4 have been deleted. In the figure, the average bit error rate and the bit error rate when the separation distance is 3 and 4 are shown. From this figure, the separation distance has a significant effect on the bit error rate performance. It can be seen that the larger the separation, the lower the bit error rate.

FIG. 9 is a diagram showing separation distances of a plurality of short cycles. In the figure, there are two short cycles, b c b c b and b c b c b c b. b is a short cycle with a circumference of 4.

1 1 2 2 1 2 2 3 3 4 4 2 1

Exists only in b c b c b. So the separation distance of b is 2. b and b are the circumference

1 1 2 2 1 1 3 4 Only exists in 6 short cycles. So the separation distance between b and b is 3. b is

3 4 2 Force separation in both short cycles The separation distance of b is 2 because it takes half the circumference of the shortest of them (short cycle b c b c b). Put together

1 1 2 2 1 2

And the separation distance between b and b is 2, which is a weak bit, and the separation distance between b and b is

1 2 3 4 Both 3 are strong bits.

[0026] [Basic theory of the present invention]

In a binary linear code C [N, K, d], d is the minimum distance of the code, and its weight distribution function F (C) is assumed as follows.

[Equation 3]

F (0 =

[0027] Further, with reference to the all-zero codeword, γ is assumed to be an energy-to-noise ratio in the AWGN channel. That is, γ is expressed as follows.

Picture

E _s

[0028] The C codeword is a binary phase shift keying (BPSK) additive white Gaussian noise (AWGN) channel that uses soft decision. (Max-likelihood decoding based on soft decision), it is easy to use a standard analysis method of union bound (Union bound based on pair-wise error probability) based on the pairwise error rate. Block error rate P, bit error

W

The rate P can be obtained as follows.

b

[Equation 5] Plock error rate:

Four

Bit error rate / ^:))

[0029] When the signal-to-noise ratio is high !, the asymptotic performance of the block error rate and the bit error rate is determined by the head term Q ((dγ)).

[0030] Normally, the bit-level LLR (log likelihood ratio) value obtained by higher-order demodulation is modeled as an output value in the AWGN channel, and can be input to the channel decoder by an appropriate channel compensation method. Since the protection capability of each bit in 次 -QAM (M = 2 ^m ) higher-order modulation using Golay codes 匕 is not uniform, the signal-to-noise ratio of the output is not the same. It can be seen that the signal-to-noise ratio of the strong bit output in the high-order modulation is larger than the signal-to-noise ratio of the weak bit output, so that the demodulated bit error rate is also low.

[0031] If the signal-to-noise ratio of the output of each bit i is T, the average signal-to-noise ratio of the output of the higher-order modulation is as follows.

[Equation 6]

Y-m '

[0032] Further, it is assumed that the signal-to-noise ratio of the output of the bit having the strongest protection capability is γ. Then

max

It can be seen that the following relationship holds.

[Equation 7]

} max

[0033] When the conventional LDPC high-order modulation method based on bit interleaved code modulation (BICM) is adopted, the asymptotic performance of the block error rate and the bit error rate is determined by the following terms.

[Equation 8] [0034] On the other hand, when the new LDP C high-order modulation method based on hierarchical interleaving based on non-uniform error characteristic matching is adopted, all bits of the LDPC minimum weight are mapped to the strongest bits on the high-order modulation. The modulation output signal to noise ratio of the least weight bit is γ

max. Therefore, the asymptotic performance of the block error rate and bit error rate is determined by the following terms.

[Equation 9]

[0035] Therefore, the method of the present embodiment has an asymptotic coding gain ACG (Asymptomatic Coding Ganv force S) than the conventional method.

[Equation 10]

A C G =

V

[Example 1]

Figure 10 shows the main configuration of a modulation device that performs a high-order modulation method using a common LDPC code. As shown in the figure, the modulation device 100 includes an LDPC encoding unit 110, a bit rearrangement unit 120, a division unit 130, a serial Z parallel (SZP) conversion unit 140, an interleaver 150, and a modulation unit 160. And have. The modulation device 100 is used by being mounted on a wireless transmission device.

[0037] LDPC encoding section 110 receives source data block S and performs LDPC encoding. The code key data block U after the L DPC code key is output to the bit rearrangement unit 120.

[0038] The bit rearrangement unit 120 groups each bit after the code that forms the code data block U according to the protection capability of the bit after the code. The bit rearrangement unit 120 obtains the rearranged data block V by arranging the bits in the order of the group power in which the bit protection capability is low. That is, the bit rearrangement unit 120 sets each bit after the code that constitutes the encoded data block U according to the protection capability of the bit after the code. Rearranged.

[0039] Dividing section 130 receives rearranged data block V and divides it into m sub-data blocks. Here, m corresponds to a modulation order in a modulation unit 160 described later.

[0040] Serial Z parallel (SZP) converter 140 converts rearranged data block V from divider 130 into m substreams in parallel. Each substream corresponds to each subdata block. As described above, the dividing unit 130 and the S / P conversion unit 140 form _m substreams corresponding to the bit protection capability from the encoded data block.

[0041] Interleavers 150-l to m interleave the corresponding sub data blocks. This interleaving is performed so that bits belonging to the same check expression are placed at different positions and an ideal time diversity effect is obtained.

[0042] Modulating section 160 forms a modulated signal according to a bit group sequentially extracted bit by bit from each input substream. Here, each constituent bit represented by one modulation symbol is assigned in advance as a used bit for each substream based on the ease of error for each constituent bit and the bit protection capability of the substream. Specifically, a substream with low bit protection capability is assigned to constituent bits that are less prone to error than a substream with high bit protection capability. That is, the modulation unit 160 converts the modulation signal according to the symbols on the constellation corresponding to the bit string obtained by rearranging the bit groups sequentially extracted bit by bit from each input substream according to the above assignment. Form. Note that the bit protection capability is determined based on the bit separation distance in this embodiment as described above. More specifically, the bit protection capability is determined based on half the circumference of the shortest short cycle on the bipartite graph.

Next, the operation of modulation apparatus 100 having the above configuration will be described. First, it is assumed that the high-order modulation is m-th order, that is, one on the constellation diagram by m bits (a---a).

1 m

, And a force and a are arranged in the order of strong and weak.

1 m

And

The source data block S is LDPC encoded by the LDPC encoding unit 110 to become an encoded data block U. The bit rearrangement unit 120 rearranges the bits in order from the smallest to the largest protection capability of each bit of the encoded data block. Is obtained. The protection capability described here corresponds to the protection class of each bit defined in the above-mentioned document (Non-Patent Document 9). However, a certain fixed order table is calculated in advance and rearrangement is performed once. Even if it corresponds to the interleave operation.

[0045] The rearranged data block V has m rearranged sub data blocks V = {V, V

1 2

, ···, V} equally (if V is not divisible by m, the sign bit with no actual content (all 1's or all 0's or other suitable bit sequences) ) So that it is divisible by m). Here, it is assumed that V to V are arranged in descending order of protection capability.

1 m

[0046] Each rearranged sub data block V (l≤i≤m) is serial / parallel converted and then interleaved to obtain an interleaved sub data block W. Interleaving here must ensure that the bits belonging to the same check expression are placed at a distance and that an ideal time diversity effect is obtained.

[0047] Then, in modulation section 160, each interleaved sub-data block W is input in parallel to a bits in high-order modulation, and constellation corresponding to m bits (a---a) in parallel is input.

1 m

One modulation symbol on the diagram is selected, that is, the final modulation symbol block τ is obtained. A modulation signal is formed according to the modulation symbol block τ.

FIG. 11 is a diagram illustrating a main configuration of a demodulation device that demodulates a reception signal subjected to high-order modulation of a common LDPC code. As shown in the figure, the demodulator 200 includes a demodulator 210, a Dinterleaver 220, a parallel Z-serial (PZS) converter 230, a combiner 240, a bit rearranger 250, and an LDPC decoding. Part 260. The demodulating device 200 is used by being mounted on a wireless receiving device. Corresponding to Fig. 10, we first assume that hat (T), a modulation symbol block of channel output, has been received. Hat corresponds to the symbol (') in the figure. The demodulator 210 performs high-order demodulation of the modulation symbol block hat (T), and then outputs the demodulated output sub-blocks of hat (W) to hat (W) respectively from the bit position of a.

Is done. Each demodulated output sub-block hat (W) (where l≤i≤m) is subjected to a corresponding Dinter Reno 220 trowel and corresponding Dinter Leave, resulting in a Dinter Leave sub-block hat (V). . All the Dinterleave sub-blocks are parallel / serial converted by the parallel Z-serial (PZS) converter 230 and synthesized by the synthesizer 240. Hat (V) = {hat (V), hat (V), ..., hat (V)} is obtained. Then, in the bit rearrangement unit 250, the order is canceled for the combined block, that is, the reverse operation performed for the bit rearrangement unit 120 on the transmission side is performed to obtain the order cancellation block hat (U). Finally, the LDPC decoding unit 260 performs LDPC decoding on the order cancellation block hat (U) to obtain the decoding block block (S).

[0049] (Example 2)

In practical applications, IZQ axisymmetric modulation is usually used for higher-order modulation. Like 16QAM shown in Fig. 2 and 64QAM shown in Fig. 3, the Golay mapping used for the I-axis and Q-axis is the same. In order to avoid losing generality, (a a --- a) bits are used for the I axis and (a a --- a) bits are used for the Q axis in the m-th order high-order modulation. And a force

1 2/2/2 + 1/2 +2 m 1 and a are in the order of strong to weak, and (aa 'a) and (aa' a >> are m / 2 1 2 m / 2 m / 2 + 1/2 + 2 m Assuming that it is completely symmetric, the number of high-order modulation bits in the symmetric system is mZ2 levels.

[0050] FIG. 12 is a diagram illustrating a main configuration of a modulation apparatus that performs a high-order modulation method using an LDPC code of IZQ axisymmetric modulation. As shown in the figure, the modulation device 100A includes an LDPC code key unit 110, a bit rearrangement unit 120, a division unit 130A, a serial Z parallel (SZP) conversion unit 140 A, an interleaver 150, a modulation unit. 160 and a serial Z parallel (SZP) converter 170.

[0051] Dividing section 130A receives rearranged data block V and divides it into mZ2 sub-data blocks. Here, m corresponds to a modulation order in a modulation unit 160 described later. In addition, since the constellation for the IQ axis is considered here, unlike the first embodiment, it is divided into mZ 2 sub-data blocks! /.

[0052] Serial Z parallel (SZP) conversion section 140A converts rearranged data block V into parallel mZ2 substreams. Each substream corresponds to each subdata block. In this way, mZ2 substreams corresponding to the bit protection capability are formed from the encoded data block by the dividing unit 130A and the SZP converting unit 140A.

[0053] Serial Z-parallel (SZP) conversion section 170 divides each substream into two substreams. Thus, the number of substreams input to the modulation unit 160 is the same as in the first embodiment. The operation of modulation apparatus 100A having the above configuration will be described. The source data block S is LDPC code input by the LDPC code key unit 110 to become a code data block U. In the bit rearrangement unit 120, the bits are rearranged in the order of the protection capability of each bit of the sign key data block from the smallest to the largest, and the rearranged data block V is obtained. As in the first embodiment, a fixed order table may be calculated in advance, and the rearrangement may correspond to one interleave operation.

[0055] The sorted data block V is equally divided into mZ2 sorted sub-data blocks V = {V, V, ..., V} (if V is not divisible by mZ2, it is actually Code bit (not all 1's, all 0's, or any other appropriate bit sequence) that has no contents, is appropriately divided and divided by mZ 2). However, V force and V are arranged in the order of low protective strength and high strength.

1 m / 2

Suppose that Each rearranged sub-data block (1≤11172) is subjected to serial / parallel conversion and then interleaved to obtain an interleaved sub-data block Wi. In this interleaving, bits belonging to the same check expression must be placed at separate positions. Then, each interleaved sub-data block W is divided into two data streams of the same size by serial / parallel conversion (if the interleaved sub-data block W cannot be converted into a data stream of the same size, the actual contents are Add the appropriate sign bit (all 1's, all 0's, or other suitable bit sequence) so that it can be converted to a data stream of the same size), a bit and a Enter in the bit. Finally, one modulation symbol on the constellation diagram is selected, ie the final modulation symbol block, which is m / 2 + i 1 m corresponding to m bits (a --- a) in parallel T is obtained.

FIG. 13 is a diagram showing a main configuration of a demodulator that demodulates a received signal subjected to high-order modulation of an LDPC code with IZQ axisymmetric modulation. As shown in the figure, the demodulator 200A includes a demodulation unit 210, a Dinterleaver 220, a parallel Z-serial (PZS) conversion unit 230, a synthesis unit 240, a bit rearrangement unit 250, and an LDPC decoding. Section 260 and a parallel Z-serial (P ZS) conversion section 270. Corresponding to Fig. 12, it is assumed that the modulation symbol block hat (T) of channel output is received first. In demodulator 210, modulation symbol block hat (T) After high-order demodulation, the data stream output from the ^ -bit on the I axis and the data stream power output from the a bit on the symmetric Q-axis Normalar Z-serial (PZS) conversion m / 2 + i

In part 270, parallel / serial conversion is performed to obtain a demodulated output sub-block hat (W). Here l≤i≤m / 2. All demodulated output sub-blocks hat (W) are subjected to corresponding deinterleaving, so that Dinter-leaved sub-block hat (V) is obtained. Next, all the Dinterleave sub-blocks are parallel / serial converted by the parallel Z-serial (PZS) converter 230 and synthesized by the synthesizer 240. The synthesized block hat (V) = (hat (V) , hat (V), ..., hat (V)}. Then, in the bit rearrangement unit 250, the composition

2 m / 2

The order of block hat (V) is released! ヽ, and the order release block hat (U) is obtained. Finally, the LDPC decoding unit 260 performs LDPC decoding on the order cancellation block hat (U) to obtain the decoding block block (S).

[Example 3]

In the third embodiment, among the cases where the IZQ axisymmetric modulation method shown in the second embodiment is adopted, the case of 16QAM in particular will be described. FIG. 14 is a diagram illustrating a main configuration of a modulation apparatus that performs a high-order modulation method of a 16QAM modulation LDPC code. As shown in the figure, modulation apparatus 100B includes LDPC encoding section 110, bit rearrangement section 120, division section 130B, serial Z parallel (SZP) conversion section 140B, interleaver 150, and modulation section 160. And a serial Z parallel (SZP) converter 170. 16QAM uses the constellation map of 16QAM Golay coding shown in Fig.2.

[0058] Dividing section 130B receives rearranged data block V and divides it into two sub data blocks. Here, the number of sub data blocks 2 corresponds to the modulation order 1Z2 in the modulation unit 160 described later.

[0059] Serial Z-parallel (SZP) conversion section 140B converts rearranged data block V into two parallel substreams. Each substream corresponds to each subdata block. In this way, the division unit 130B and the S / P conversion unit 140B form two substreams corresponding to the bit protection capability from the code key data block.

The operation of modulation apparatus 100B having the above configuration will be described. The source data block S is LDPC code input by the LDPC code input unit 110 to become a code data block U. . In the bit rearrangement unit 120, the bits are rearranged in the order of the protection capability of each bit of the sign key data block from the smallest to the largest, and the rearranged data block V is obtained. As in the first embodiment, a fixed order table may be calculated in advance, and the rearrangement may correspond to one interleave operation.

[0061] The rearranged data block V is changed to two rearranged sub data blocks V = {V, V}.

1 Divided into two equal parts. V is a data block with low protection capability, and V is a data block with high protection capability.

1 2

One block. Each reordering sub-data block is serial / parallel converted and then interleaved to obtain interleaved sub-data blocks W and W.

1 2 In this interleaving, bits belonging to the same check expression are always arranged at distant positions. Then, the interleaved sub-data block W is divided into two data streams by serial / parallel conversion.

1 Enter in 3. Also, the interleaved sub data block W is serial / parallel converted,

2

Input to a bit and a bit respectively. Finally, it corresponds to 4 parallel bits (a a a a)

2 4 1 2 3 4, one modulation symbol on the constellation diagram is selected, that is, the final modulation symbol block τ is obtained.

FIG. 15 is a diagram illustrating a main configuration of a demodulator that demodulates a received signal subjected to high-order modulation of an LDPC code of 16QAM modulation. As shown in the figure, the demodulator 200B includes a demodulator 210, a Dinterleaver 220, a parallel Z-serial (PZS) converter 230, a combiner 240, a bit rearranger 250, and an LDPC decoder. 260 and a parallel Z-serial (PZS) converter 270. Corresponding to Fig. 14, it is assumed that the modulation symbol block hat (T) of channel output is received first. In the demodulator 210, after the modulation symbol block hat (T) is demodulated in high order, the data stream output from the a bit on the I axis and the a bit on the symmetric Q axis

The data stream that has also been output in 1 to 3 is subjected to parallel / serial conversion by the normal Z serial (PZS) converter 270, and a demodulated output sub-block hat (W) is obtained. Similarly, the data stream output from the a bit on the I axis and the data stream output from the symmetric Q axis a bit.

twenty four

The data stream is parallel / serial converted by a parallel Z-serial (PZS) converter 270 to obtain a demodulated output sub-block hat (W). Demodulated output sub-blocks hat (W) and h

2 1 at (W) is given a corresponding Dinterleave, Dinterleave subblock hat ( V) and hat (V) are obtained. All Dinterleave sub-blocks are parallel Z serial

1 2

The parallel (serial) conversion is performed in the P (PZS) conversion unit 230, and then the synthesis unit 240 synthesizes the resultant block hat (V) = {hat (V), hat (V)}. And composite block h

1 2

The order of at (V) is released, and the order release block hat (U) is obtained. Finally, the LDPC decoding unit 260 performs LDPC decoding on the order cancellation block hat (U) to obtain the decoding block block (S).

FIG. 16 is a performance comparison diagram of 16QAM and 64QAM of [2000, 1000] regular LDPC codes.

BPSK modulation and AWGN channel are used. The LDPC code is a [2000, 1000] regular code with a code rate of 1/2, the information block length is 1000 bits, the encoded block length is 2000 bits, the check node frequency is 6, and the message node frequency is 3. 16QAM and 64QAM use Golay mapping as shown in Fig. 2 and Fig. 3, respectively. Since it is a regular LDPC code and the method based on bit reliability is not effective, the performance of the method of the present invention (the present invention) was compared with that of the conventional bit interleaved code modulation (BICM). From the figure, it can be seen that, for regular LDPC codes, the method of the present invention has the ability to significantly improve the bit error rate in a region where the signal-to-noise ratio is high, compared to the conventional bit interleaved code modulation method. I understand.

[0064] FIG. 17 is a performance comparison diagram of 16QAM and 64QAM of [3000, 1000] irregular LDPC codes. BPSK modulation and AWGN channel are used. The LDPC code is a [3000, 1000] irregular code with a code rate of 1/3, the information block length is 1000 bits, the coding block length is 3000 bits, the frequency of the check nodes is 4, and the frequency distribution polynomial of the message nodes Is f (x) = x 2Z3 + 2x ³ Z3. 16QAM and 64QAM use Gory Mapping as shown in Fig. 2 and Fig. 3, respectively. Since it is a non-regular LDPC code, the method based on bit reliability (BR) can be used, the method based on bit reliability (BR), bit interleaved code modulation (BICM), and the method of the present invention (the present invention). A comparison was made. From the figure, for non-regular LDPC codes, the method of the present invention has a remarkable bit error rate improvement performance in the region where the signal-to-noise ratio is high, compared with the conventional bit interleave code modulation method. I understand. The bit reliability (BR) method is somewhat effective in the low signal-to-noise ratio region, but has a high signal-to-noise ratio! [0065] That is, the method of the present invention can significantly improve the bit error rate performance in a region with a high signal-to-noise ratio for both regular LDPC codes and non-regular LDPC codes.

[0066] According to the above embodiment, a high-order coded modulation scheme using the low-density parity check code LDPC code including the following steps is presented. That is, the method performs LDPC coding on a source data block to generate a coded data block, and based on the order of strength of protection capability, A step of rearranging each code bit, a step of rearranging each symbol bit in the modulation symbol based on the order of the strength of protection, and a block of the rearranged encoded bit sequence based on the number of symbol bits The coded bit sequence after division and rearrangement is divided into sub-blocks equal to the number of symbol bits, the steps of interleaving each code block in parallel, and a code with strong protection capability The interleaved coded sub-block consisting of the 匕 bits is mapped to symbol bits with weak protection capability. Mapping interleaved coding sub-blocks, which are composed of weakly protected code bits, to symbol bits with strong protection capability, and one parallel symbol bit to form one modulation symbol, High-order modulation of each modulation symbol into a final modulation symbol block.

[0067] Preferably, the step of interleaving the code sub-blocks in parallel includes disposing bits belonging to the same check expression at positions separated from each other.

[0068] Preferably, the strength of the protection capability of each sign bit is determined by the separation distance. However, the greater the separation distance, the stronger the protection capability of the bit.

[0069] Preferably, the separation distance of each sign bit is equal to half the circumference of the shortest short site on the bipartite graph.

[0070] Preferably, the strength of protection of each symbol bit is determined by the sum of the symbol and ming distance of each symbol bit. However, the greater the sum of the Hamming distance, the weaker the protection capability of that bit.

[0071] Preferably, if the encoded bit sequence after rearrangement cannot be equally divided into sub-blocks equal to the number of symbol bits, if necessary, the end of the rearranged encoded bit sequence An empty bit is added at the end so that it can be equally divided into sub-blocks, equal to the number of symbol bits.

In addition, according to the above embodiment, a high-order decoding demodulation method for receiving a modulation symbol block generated by the above-described high-order coding modulation method including the following steps is presented. That is, the method receives a modulation symbol block, performs high-order demodulation on the received modulation symbol block to generate a demodulation sub-block, and a position of each symbol bit corresponds to one demodulation sub-block; Depending on the step of deinterleaving all demodulated sub-blocks in parallel and the correspondence between each symbol bit and each code bit, the sub-blocks after deinterleaving are combined to generate a code bit sequence. A step of generating, a step of canceling the order of the encoded bit sequence, and a step of generating a decoded data block by performing LDPC decoding on the encoded bit sequence whose sequence has been canceled. including.

Further, according to the above embodiment, an orthogonal symmetric high-order code modulation method based on a low density parity check code and an L DPC code including the following steps is presented. Note that m-th order modulation is used, where m = 2N and N are natural numbers. That is, the method performs LDPC coding on a source data block to generate a coded data block and each code in the coded data block based on the order of the strength of protection. Reorder each symbol bit in the modulation symbol based on the order of rearrangement of bits and the order of strength of protection, where m is an even number, so the i-th symbol bit and the N + th It has the same protection ability as the i-th symbol bit, i is a natural number greater than or equal to 1 and less than or equal to N, and the code bit sequence after rearrangement according to the number m of symbol bits is divided into blocks, A step of equally dividing the rearranged encoded bit sequence into half of the number of symbol bits, such as N, and sub-blocks, and interleaving each code sub-block in parallel. A step of converting each of the interleaved code signal sub-blocks into two code signal data streams of the same size, and an encoded data stream comprising code signal bits having strong protection capability Map to a weakly protected symbol bit and map a code data stream consisting of weakly protected code bits to a strong protected symbol bit, but with the same interleaved coding sub-block Are the i-th and N + i-th data streams with the same protection capability. A step of mapping to symbol bits, and a step of constructing one modulation symbol from each parallel symbol bit, and high-order modulating each modulation symbol into a final modulation symbol block.

[0074] Preferably, the step of interleaving the code sub-blocks in parallel includes disposing bits belonging to the same check expression at positions separated from each other.

[0075] Preferably, the strength of the protection capability of each code bit is determined by the separation distance. However, the greater the separation distance, the stronger the protection capability of the bit.

[0076] Preferably, the separation distance of each code bit is equal to half the circumference of the shortest short site on the bipartite graph.

[0077] Preferably, the protection capability of each symbol bit is determined by the sum of the symbol and ming distance of each symbol bit. However, the greater the sum of the Hamming distance, the weaker the protection capability of that bit.

[0078] Preferably, if the reordered code bit sequence power is not equally divided into half the number of symbol bits and equal to N, the end of the rearranged code bit sequence as necessary Add an empty bit to, so that it can be equally divided into half the number of symbol bits, equal to N.

[0079] Preferably, if each interleaved code sub-block cannot be converted into two encoded data streams of the same size, an empty space is added at the end of each interleaved code sub-block as necessary. Are converted so that they can be converted into two identically sized data streams.

Further, according to the above embodiment, a high-order decoding demodulation method for receiving a modulation symbol block generated by the orthogonal symmetric high-order code modulation method including the following steps is provided. That is, the method receives a modulation symbol block, performs high-order demodulation of the received modulation symbol block, generates a demodulation sub-block, and each symbol bit position corresponds to one demodulation sub-block; Combining two demodulated sub-blocks corresponding to the positions of the i-th and N + i-th symbol bits with the same demodulated sub-block and all demodulated sub-blocks after the synthesis in parallel Din leave and the correspondence between each symbol bit and each sign bit Synthesizing the subleaved sub-blocks to generate a coded bit sequence; releasing the order of the coded bit sequence; performing L DPC decoding on the unsigned code bit sequence; Generating a decryption key data block.

[0081] The disclosures of the description, drawings and abstracts contained in the Chinese application No. 200610071413.4 filed on March 20, 2006 are hereby incorporated by reference.

Industrial applicability

The modulation device, demodulation device, and modulation method of the present invention are useful for reducing the bit error rate.

Claims

The scope of the claims

[1] LDPC encoding means for forming an encoded data block by performing LDPC encoding on the source data block;

A bit rearranging means for rearranging each encoded bit of the encoded data block based on the order of bit protection capability;

Dividing means for dividing the rearranged encoded bit sequence into a plurality of sub-blocks equal to the number of constituent bits of a unit bit string represented by one modulation symbol;

When a group of bits sequentially extracted from each sub-block is rearranged according to the assignment of the above-mentioned configuration bits to the sub-block based on the ease of error for each constituent bit and the bit protection capability of the sub-block. A modulation device comprising: modulation means for forming a modulation signal according to a modulation symbol on a constellation corresponding to the obtained bit string.

[2] The modulation device according to [1], wherein the bit rearranging unit rearranges the bits based on the order of bit protection capability determined by the separation distance of the sign bits.

[3] The modulation device according to [2], wherein the separation distance of the sign bit is half of the circumference of the shortest short cycle on the bipartite graph.

[4] An interleaver that is provided between the dividing unit and the modulating unit and performs interleaving for each sub-block,

2. The modulation apparatus according to claim 1, wherein the interleaver performs interleaving so that bits belonging to the same check expression of the LDPC code are arranged at positions separated from each other.

[5] When the modulation means rearranges the bit groups according to the assignment of the high protection capability !, the sub-blocks to the protection bits! 2. The modulation device according to claim 1, wherein a modulation signal is formed in accordance with a modulation symbol on a constellation corresponding to the bit string obtained in (1).

[6] A demodulating device that demodulates the modulation signal formed by the modulation device according to claim 1, wherein the modulation signal is converted into the bit string based on the constellation, and each bit of the bit string is converted. Demodulating means for distributing each sub-block; Combining means for forming the rearranged code bit sequence by combining the sub-blocks;

Other bit rearranging means for applying the reverse operation performed by the bit rearranging means to the coded bit sequence formed by the synthesizing means;

LDPC decoding means for performing LDPC decoding on the code data sequence obtained by the other bit rearranging means;

A demodulator comprising:

[7] forming an encoded data block by performing LDPC code on the source data block;

Rearranging each encoded bit of the encoded data block based on the order of the strength of the bit protection capability; and

Dividing the rearranged encoded bit sequence into a plurality of sub-blocks equal to the number of constituent bits of a unit bit string represented by one modulation symbol;

When a group of bits sequentially extracted from each sub-block is rearranged according to the assignment of the above-mentioned configuration bits to the sub-block based on the ease of error for each constituent bit and the bit protection capability of the sub-block. Forming a modulation signal according to modulation symbols on the constellation corresponding to the resulting bit string;

A modulation method comprising: