KR101426557B1 - Method and appratus for transmitting and receiving data in a communication system using low density parity check code - Google Patents

Abstract

A data transmission method of a communication system using a low density parity check (LDPC) code proposed by the present invention is a data transmission method of an LDPC coding method for generating an LDPC codeword by coding information data bits, Interleaving the LDPC codeword and outputting the codeword bits constituting the LDPC codeword in order; outputting the output codeword bits in a predetermined number of codeword bit groups A signal constellation bit mapping process for mapping bits constituting the codeword bit group to bits constituting modulation symbols according to a predetermined modulation scheme and outputting a mapping signal, Modulating a signal by a high-order modulation and outputting a modulated signal, and modulating the modulated signal by an RF (Radio Frequency) And an RF processing process for transmitting through a transmission antenna.

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Low density parity check (LDPC) code, higher order modulation, signal constellation bit mapping, interleaving

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a data transmission / reception apparatus and a data transmission method in a communication system using a low-

The present invention relates to an apparatus and method for transmitting and receiving data in a communication system, and more particularly, to an apparatus and method for transmitting and receiving data in a communication system using an LDPC code.

Generally, a general procedure of data transmission and reception in a communication system is as follows. That is, the data generated from the source of the transmission side is transmitted through a channel through Source Coding, Channel Coding, Interleaving, Modulation, and the like. In addition, the receiving side receives the wirelessly transmitted signal and performs demodulation, deinterleaving, channel decoding, and source decoding.

However, in a communication system, various noise, fading phenomena and inter-symbol interference (ISI) of a channel cause signal distortion. Especially, in a high-speed digital communication system that requires high data throughput and reliability, such as next generation mobile communication, digital broadcasting, and portable Internet, techniques for overcoming signal distortion due to noise, fading and ISI are essential. The channel coding and interleaving correspond to typical techniques.

Interleaving is a technique for minimizing data transmission loss by preventing frequent occurrence of burst errors while passing through a fading channel by distributing the damaged bits of the bits to be transmitted to a plurality of places without being concentrated in one place, It is used to raise the effect.

In addition, channel coding is widely used as a method for improving the reliability of communication by allowing the receiver side to confirm the distortion of the signal due to noise, fading and ISI and to restore the signal efficiently. Code used for channel coding is called an error-correcting code (ECC) in the sense of correcting errors, and various types of error correction codes are actively studied.

Generally known error correction codes include a block code, a convolutional code, a turbo code, and a low density parity check code (LDPC code). Since the present invention described below relates to a communication system using an LDPC code, a brief description of an LDPC code will be given below.

An LDPC code can not guarantee complete transmission of a signal but is known as a code that minimizes the probability of information loss. That is, the LDPC code was first proposed in the 1960s as the first channel coding code capable of transmitting signals at a level close to the maximum data rate (Shannon limit) known in Shannon's channel coding theory. However, LDPC codes were difficult to implement at the level of technology at that time, so they were not actually used. However, with the development of information theory and technology in the future, studies on the characteristics and generation methods of codes that do not significantly increase complexity using iterative decoding since 1996 have been rediscovered. It is. This LDPC code is evaluated as a very good error correction code that can be used in a next generation mobile communication system in addition to the turbo code.

The LDPC codes are typically represented using graphical representations, and many features can be analyzed through graph theory, algebra, and probability-based methods. Generally, a graph model of a channel code is useful not only for describing codes but also to correspond information of encoded bits to a vertex in a graph and to correspond each bit relation to edges in a graph , It is possible to derive a natural decryption algorithm because each vertex can be regarded as a communication network for exchanging messages determined by each line. For example, trellis-derived decoding algorithms, which can be regarded as a kind of graph, include the well-known Viterbi algorithm and BCJR (Bahl, Cocke, Jelinek and Raviv) algorithms.

The LDPC code can be expressed using a bipartite graph, which is generally defined as a parity-check matrix and is collectively referred to as a Tanner graph. Herein, the half graph means that the vertices constituting the graph are divided into two types. In the case of the LDPC code, a binary graph consisting of a variable node and a vertex called a check node Lt; / RTI > Here, the variable node corresponds one-to-one with the encoded bit.

Hereinafter, a graphical representation method of the LDPC code will be described with reference to FIGS. 1 and 2. FIG. 1 is an exemplary diagram of a parity check matrix H1 of an LDPC code. In FIG. 1, it is assumed that a parity check matrix of an LDPC code including four rows and eight columns is assumed. The matrix of FIG. 1 represents an LDPC code generating codeword of length 8 by having eight columns. That is, each column corresponds to the encoded 8 bits.

2 is a Trellis diagram of a parity check matrix H1 of an LDPC code. That is, FIG. 1 shows a Tanner graph corresponding to H1 in FIG. 2, the Tanner graph of the LDPC code includes eight variable nodes x ₁ (202), x ₂ (204), x ₃ (206), x ₄ (208), x ₅ (210) ₆ 212, x ₇ 214 and x ₈ 216 and four check nodes 218, 220, 222 and 224. Here, the i-th column and the j-th row of the parity check matrix H1 of the LDPC code correspond to the variable nodes x _i and j-th check nodes, respectively. The value of 1, that is, a value other than 0 at the intersection of the i-th column and the j-th row of the parity check matrix H1 of the LDPC code means that the variable nodes x _i and j And the edge is present between the first check node and the second check node.

In the Tanner graph of the LDPC code, the degree of the variable node and the check node means the number of line segments connected to the respective nodes. This means that in the parity check matrix of the LDPC code, Is equal to the number of non-zero entries. For example, in FIG. 2, variable nodes x ₁ 202, x ₂ 204, x ₃ 206, x ₄ 208, x ₅ 210, x ₆ 212, x ₇ 214 ), the order of the x ₈ (216) are each in sequence 4, 3, 3, 3, 2, 2, 2, and 2, the degree of the check nodes (218, 220, 222, 224) is 6, as each sequence , 5, 5, 5. In addition, the number of non-zero elements in each column of the parity check matrix H1 of FIG. 1 corresponding to the variable nodes of FIG. 2 corresponds to the order of 4, 3, 3, 2, 2, 2, And the number of non-zero elements in each row of the parity check matrix H1 of FIG. 1 corresponding to the check nodes in FIG. 2 is in the order of the above-mentioned orders 6, 5, 5, Match.

As described above, each bit encoded corresponds to a column of a parity check matrix one-to-one, and also corresponds to a variable node on the Tanner graph on a one-to-one basis. The degree of the variable node corresponding one-to-one with the encoded bit is also referred to as the degree of the encoded bit. It is known that LDPC codes have better decoding performance than codeword bits having a high degree of codeword bits having a low degree. This is because the decoding performance can be improved as the higher-order variable node obtains more information through iterative decoding than the lower-order variable node.

So far, we have studied LDPC codes. Hereinafter, a signal constellation when a QAM (Quadrature Amplitude Modulation) scheme, which is a higher order modulation scheme used in a communication system, will be described. The modulated symbols in QAM are composed of real part and imaginary part, and various modulation symbols can be constructed by varying the size and sign of each real part and imaginary part. In order to examine the characteristics of the QAM, a QPSK modulation scheme will be described.

3A is a schematic diagram of a signal constellation of a general QPSK (Quadrature Phase Shift Keying) modulation scheme. y ₀ determines the sign of the real part, and y ₁ determines the sign of the imaginary part. That is, when y ₀ is 0, the sign of the real part is positive (plus: +), and when y ₀ is 1, the sign of the real part is minus (-). The sign of the imaginary part is positive (+) when y ₁ is 0, and the sign of the imaginary part is negative (-) when y ₁ is 1. y ₀ , and y ₁ are the sign bits indicating the sign of the real part and the imaginary part, the error occurrence probability of y ₀ , y ₁ is the same. Therefore, in the case of the QPSK modulation method, (y ₀ , y ₁ ) The reliability of each bit is the same. Here, denoted by y _{0, q,} y _{1, q} , the second subscript index q indicates the q-th output of the modulated signal constituent bits.

3B is a schematic diagram of a signal constellation of a general 16-QAM modulation scheme. The meaning of (y ₀ , y ₁ , y ₂ , y ₃ ) corresponding to one modulation signal bit is as follows. The bits y ₀ and y ₂ determine the sign and magnitude of the real part, respectively, and the bits y ₁ and y ₃ respectively determine the sign and magnitude of the imaginary part. In other words, y ₀ and y ₁ determine the sign of the real and imaginary parts of the signal, and y ₂ and y ₃ determine the magnitude of the real and imaginary parts of the signal. Since it is easier to determine the sign than to determine the magnitude of the modulated signal, the probability of error for y ₂ and y ₃ is higher than y ₀ and y ₁ . Therefore, the probability that the errors of the bits do not occur, that is, the reliability, is y ₀ = y ₁ > y ₂ = y ₃ . That is, unlike QPSK, the reliability of each bit of modulation signal constituent bits (y ₀ , y ₁ , y ₂ , y ₃ ) of QAM is different.

In the 16-QAM modulation scheme, two of the four bits constituting the signal determine the sign of the real part and the imaginary part of the signal, and two bits represent the size of the real part and the imaginary part of the signal (y ₀ , y ₁ , y ₂ , y ₃ ) and the role of each bit can be changed.

3C is a schematic diagram of a signal constellation of a general 64-QAM modulation scheme. Here, bits y ₀ , y _2, and y ₄ of (y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y ₅ ) corresponding to one modulation signal bit determine the sign and magnitude of the real part, ₁ , y ₃ and y ₅ determine the sign and magnitude of the imaginary part. Where y ₀ and y ₁ determine the sign of the real and imaginary parts, respectively, and y _2, y ₃ , y _{4 and} y ₅ determine the magnitude of the real and imaginary parts, respectively. The reliability of y ₀ and y ₁ is higher than the reliability of y _2, y ₃ , y _{4 and} y ₅ because it is easier to distinguish the code than to determine the size of the modulated symbol. y _{2 and} y ₃ are determined according to whether the size of the modulated symbol is larger or smaller than _{4 and} y _{4 and} y ₅ are determined based on whether the size of the modulated symbol is close to 4 and 0 based on 2, 6 < / RTI > Therefore _, the size of the determination range of y _{2 and} y ₃ is 4, and the determination range of y _{4 and} y ₅ is 2. Therefore _, the reliability of y _2, y ₃ is higher than y _4, y ₅ . To summarize, the probability (that is, the reliability) that the error of each bit does not occur is y ₀ = y ₁ > y ₂ = y ₃ > y ₄ = y ₅ .

In the 64-QAM modulation scheme, two of the 6 bits constituting the signal determine the sign of the real part and the imaginary part of the signal, and the four bits are only required to indicate the size of the real part and the imaginary part of the signal. Therefore, the order of (y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y ₅ ) and the role of each bit may vary. In the case of a signal constellation of 256-QAM or higher, the role and reliability of the modulation signal constituting bits are changed in the same manner as described above. A detailed description thereof will be omitted.

Conventionally, when interleaving / deinterleaving is performed in a communication system using an LDPC code, an arbitrary interleaving / deinterleaving method may be used regardless of the reliability characteristics of the LDPC code or the modulation code bits of the higher order modulation, The interleaving / deinterleaving scheme considering only the order of the nodes or the check nodes is used, so that the distortion of the signals transmitted through the channels can not be minimized.

Therefore, the present invention provides an apparatus and method for reducing signal distortion in a communication system using an LDPC codeword.

The present invention also provides an interleaving apparatus and method for improving the performance of an LDPC codeword in a communication system using an LDPC codeword.

The present invention also provides a signal constellation bit mapping apparatus and method for improving the performance of an LDPC codeword in a communication system using an LDPC codeword.

A method according to an embodiment of the present invention comprises: A method of transmitting data in a communication system using a Low Density Parity Check (LDPC) code, the method comprising: an LDPC encoding step of encoding the information data bits to generate an LDPC codeword when information data bits are input; Interleaving an LDPC codeword and outputting the codeword bits constituting the LDPC codeword in order; outputting the codeword bits into a predetermined number of codeword groups in a descending order; A signal constellation bit mapping process of mapping bits constituting the codeword bit group to bits constituting modulation symbols according to a predetermined modulation scheme and outputting a mapping signal, A modulating step of modulating the modulated signal by a radio frequency (RF) Lt; RTI ID = 0.0 > RF < / RTI >
An apparatus according to an embodiment of the present invention includes: A data transmission apparatus in a communication system using a Low Density Parity Check (LDPC) code, the apparatus comprising: a data transmission apparatus for interleaving an LDPC codeword generated by coding information data bits, An interleaver for outputting the codeword bits constituting the codeword bit sequence in order; a grouping unit for grouping the output codeword bits into a predetermined number of codeword bit groups in descending order; A bit mapper for performing a signal constellation bit mapping on bits constituting modulation symbols according to a predetermined modulation scheme and outputting a mapping signal; a demodulator for demodulating the mapping signal to output a modulated signal, And a modulator for RF (Radio Frequency) processing and outputting the processed signal to a transmission antenna.

The effects according to the present invention are as follows.

According to the present invention, it is possible to maximize the performance of an LDPC codeword in a communication system using an LDPC codeword. And further improves the decoding performance of the LDPC code. In particular, the reliability of bits having low error correction capability among the bits constituting the LDPC code is improved. In addition, the reliability of data transmission and reception can be improved by enhancing the performance of a link especially in a radio channel environment where a link performance is likely to deteriorate due to noise, fading phenomenon, and inter-symbol interference (ISI). In addition, transmission and reception of a reliable LDPC code reduces the error probability of a signal in the entire communication system, thereby enabling high-speed communication.

The operation principle of the preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions of the present invention, and may be changed according to the intentions or customs of the user, the operator, and the like. Therefore, the definition should be based on the contents throughout this specification.

4 is a configuration diagram of a communication system using an LDPC code according to an embodiment of the present invention. Hereinafter, a configuration of a communication system using an LDPC code according to an embodiment of the present invention will be described with reference to FIG.

The transmitter 400 of the present invention includes an encoder 411, an interleaver 413, a constellation bit mapper (constellation bit mapping) 415 Quot; group "), and a modulator 417. The receiver 450 of the present invention may further include a demodulator 457, a signal constellation bit demapping 455 (hereinafter abbreviated as a "bit demapper"), a demodulator An interleaver 453, and a decoder 451. [

The operation of the transmitter and receiver of the present invention will be briefly described with reference to FIG. 4, and the configuration and operation of the interleaver and bit mapper proposed in the present invention will be described in detail with reference to FIG.

First, when i, which is an information data bit stream, is input to the transmitter 400, i is transmitted to an encoder 411. The encoder 411 encodes the information data bits in a predetermined manner, codeword x and outputs it to the interleaver 413. Here, the encoder 411 is an LDPC encoder and the codeword generated by the encoder 411 is an LDPC codeword.

The interleaver 413 interleaves the LDPC codeword output from the encoder 411 in a predetermined manner and outputs the interleaved signal constellation bit mapper 415. The interleaving operation of the interleaver 413 is performed according to the interleaving scheme proposed in the present invention. A detailed description of the interleaving method will be described later.

The bit mapper 415 maps the bits output from the interleaver 413 (that is, the interleaved LDPC codeword) b to a signal constellation bit in a predetermined manner and outputs the signal constellation bit to the modulator 417. The bit mapper 415 is mapped according to the mapping scheme proposed by the present invention. The mapping scheme maps the bits constituting the modulation symbol according to the degree characteristic of b, and a detailed description thereof will be described later. The modulator 417 modulates the signal output from the bit mapper 415 in a predetermined manner and transmits the modulated signal through a transmission antenna (Tx.Ant). The interleaver 413 and the bit mapper 415 of the present invention minimize the bit error rate (or BER) when the modulator 417 modulates the b Interleaving and bit mapping are performed to improve performance.

Hereinafter, the interleaver 413 and the bit mapper 415 design the relationship between the codeword bit, which is the input signal of the interleaver, and the modulation signal configuration bit, which is the output signal of the bit mapper, to satisfy the following rules. It is assumed that the number of bits of the LDPC codeword is N and the 2 ^2m -QAM modulation scheme is used.

Rule 1) N / m number of bits of the LDPC codeword bits are mapped to bits having intermediate reliability among the modulated signal constituent bits in order of higher order.

Rule 2) N / m number of bits of the LDPC codeword bits are mapped to bits of higher reliability among the modulated signal constituent bits in descending order.

For example, for the codeword c = [c ₁ c ₂ c ₃ ... c _N ] ordered in order, the bits c = [c ₁ c ₂ c ₃ ... c _{N / m} ] And maps the bits of the modulated signal constituting bits to those whose reliability is intermediate. In other words. When 64-QAM is used, it is mapped to y _{2 and} y ₃ bits in FIG. 3C. For convenience of explanation, let a group composed of the bits be G ₁ .

_{And, c = [c NN / m} + 1 c NN / m + 2 c NN / m + 3 ... c N] bits are mapped on the modulation signal configuration bits are bits of the highest reliability. That is, when 64-QAM is used, it is mapped to y _{0 and} y ₁ bits in FIG. 3C. For convenience of explanation, let a group composed of the bits be G _m .

By constructing the relationship between the LDPC codeword bits and the modulated signal constituent bits as described above, the decoding performance of the LDPC codeword can be improved. Since the high order bits are superior to the low order bits, even if they are mapped to the modulation signal configuration bits having low reliability, they can be restored sufficiently to the original signal in the decoding process. However, if the ratio of the higher order bits among the codeword bits is large, error propagation may occur due to too many initial low reliability bits. On the other hand, if high order bits are mapped to high reliability modulation signal configuration bits, the modulation signal configuration bits having low reliability are mapped to relatively low order bits, resulting in an error floor. Therefore, it is possible to improve the decoding performance by mapping bits having a high order to modulated signal configuration bits having intermediate reliability without allocating them to the highest or lowest reliability bits.

Therefore, the bits belonging to the group G ₁ are mapped to modulated signal constituent bits having intermediate reliability. If the bits belonging to the group G _m are mapped to the modulation signal constituting bits having high reliability, excellent decoding performance can be obtained. The bits belonging to the group G _m are composed of codeword bits having a plurality of low orders. At this time, low-order codewords are not able to receive a large amount of information from other bits in the decoding process, resulting in poor decoding performance. Therefore, decoding performance can be improved by mapping good information at an early stage.

Meanwhile, the receiver 450 receives the signal transmitted from the transmitter 400, and outputs the signal through a process reverse to that of the transmitter 400. That is, the signal input to the receiver 450 through the reception antenna Rx. Ant is transmitted to the demodulator 457. The demodulator 457 demodulates the received signal in a demodulation scheme corresponding to the modulation scheme of the modulator 417 of the transmitter 400 and outputs the demodulated signal to the bit demapper 455. The bit demapper 455 bit demaps the signal output from the demodulator 457 according to the mapping scheme performed by the bit mapper 415 of the transmitter 400 and outputs the bit demapper 453 to the de-interleaver 453 . The deinterleaver 453 deinterleaves the signal output from the bit demapper 455 to correspond to the interleaving scheme applied by the interleaver 413 of the transmitter 400 and outputs the deinterleaved signal to the decoder 451. The decoder 451 decodes the deinterleaved signal using the decoding scheme corresponding to the scheme applied by the encoder 411 of the transmitter 400 and restores the final information data bit.

4, the signal output from the modulator 417 is subjected to RF processing in an RF transmitter (not shown in FIG. 4) for transmitting a radio frequency (RF) signal, And a signal received from the receiving antenna is subjected to RF processing in an RF receiving section (not shown in FIG. 4) for RF signal receiving processing and input to the demodulator 457.

The transmitter of the present invention is characterized by an interleaver 413 and a bit mapper 415 using a unequal reliability characteristic of a higher order modulation scheme and the receiver of the present invention has an unequal reliability characteristic of a higher order modulation scheme Interleaver 453 and a bit demapper 455 using the same. 5, the operation of the interleaver and signal constellation bit mapper proposed in the present invention will be described in detail.

5 is a configuration diagram of an interleaver and a signal constellation bit mapper according to an embodiment of the present invention. Hereinafter, a configuration of an interleaver and a signal constellation bit mapper according to the present invention will be described with reference to FIG.

As shown in FIG. 5, the bit mapper 415 of FIG. 4 is composed of a demultiplexer (DEMUX). 5 shows a method using a QPSK modulation signal. The second method shown in (2) is a method using a 16-QAM modulation signal. The third example shown in (3) -QAM modulated signal, and (4) shown in the fourth figure shows a method of using a 256-QAM modulated signal, respectively. In the following, we will discuss four methods together.

When the encoded signal x is input to the interleavers 511, 531, 551, and 571, the interleaved signal b is output. When the interleaved signal b is input to the demultiplexing units 521, 541, 561 and 581, it is divided into a plurality of streams. That is, (1) is divided into two streams because it is QPSK, (2) is divided into 4 streams because it is 16-QAM, (3) is divided into 6 streams because , And (4) are 256-QAM cases, so they are separated into 8 streams. Each of the input signals outputs a signal separated into a plurality of streams according to a corresponding method.

Each of the demultiplexers 521, 541, 561 and 581 receives a stream and separates the stream into a plurality of streams to form bits of a modulated signal. In the present invention, It is important that you configure the bits. Operations of the demultiplexers 521, 541, 561 and 581 will be described in detail below. For convenience of description, the case of using the 16QAM modulation signal of (2) will be described in detail. In the case of using another modulated signal, the same method can be applied.

First, LDPC codeword bits x ₀ , x ₁ ... x _N-2 , x _N-1 are input to the interleaver 531. The interleaving scheme is determined by simultaneously considering the bit mapping scheme of each modulated signal, the degree distribution of bits of the LDPC code, and the reliability of each signal constellation bit. This will be described in detail below.

The output bits b ₀ , b _1, ..., b _N-2 , b _N-1 of the interleaver 531 are input to the demultiplexer 541 and output as separated by the number of bits constituting the modulated signal. That is, since the modulation signal is composed of four bits in the case of 16-QAM, the input bits of the demultiplexer 541 are separated into four bits and output. At this time, four consecutive bits b ₀ , b _1, b ₂ , b ₃ and y ₀ , y ₁ , y ₂ , the bit mapping method is determined according to a mapping relation with y ₃ . The bit mapping method will be described in detail below.

5, the output bits y ₀ , y ₁ , y ₂ of the demultiplexer 541, y ₂ , y ₃ of y ₀ , y ₂ constitute the real part and y ₁ and y ₃ constitute the imaginary part.

Hereinafter, the interleaving method and bit mapping method according to the embodiment of the present invention will be described in detail. The interleaver and bit mapper proposed by the present invention are designed according to the above-mentioned rules.

First, the designing process of the interleaver according to the embodiment of the present invention follows the following steps.

First , the number of columns of the interleaver is determined so as to be equal to the number of bits used in the modulation symbol, that is, the number of modulation signal configuration bits.

Step 2 : The value obtained by dividing the length of the codeword by the number of columns determined in the first step is determined as the number of interleaver rows.

Step 3 : The LDPC codeword bits are written in the order of the columns in the determined interleaver.

Step 4: One bit is read out from each column in which a codeword bit is written.

In Table 1 below, the row and column sizes of the interleaver according to the respective modulation schemes are shown by taking the case where the codeword length is 16200 and 64800, for example.

Hereinafter, the design and operation of the interleaver will be described with reference to FIG. In the following description, it is assumed that the LDPC matrix is sequentially arranged from a row having a higher order. The reason for this assumption is as follows. That is, as described above, the higher the degree of the codeword bits corresponding to the variable nodes of the LDPC matrix, the better the decoding performance. Therefore, the corresponding bits of the codeword generated by assuming the LDPC matrix arranged in descending order are also arranged in descending order, and the codeword bits arranged in the descending order indicate the order of decoding performance between the respective bits.

6 is an exemplary diagram illustrating an operation of an interleaver according to an embodiment of the present invention. The interleaver of FIG. 6 uses a 64-QAM modulation scheme and assumes that the length of the LDPC codeword is 64,800. The description will be made in accordance with four steps of the design and operation of the above-described interleaver.

In the first step, six columns are used as the number of bits used in 64-QAM. In the second step, the number of bits in the row is determined as 64800/6 = 10800, which is the codeword length divided by the number of columns. In the third step, LDPC codeword bits are sequentially input to each column. At this time, the number of bits input to each column is the number of rows (10800). In accordance with the fourth step, one bit is sequentially output from each column. In this case, in FIG. 6 (a), the first bit of the column 1 is sequentially output to the first bit of the column 6, and then the second bit of the column 1 is sequentially output to the second bit of the column 6. Repeat the above procedure for the number of rows (10800).

The LDPC codeword is interleaved through the above process. In addition, in order to further enhance interleaving performance, arbitrary interleaving may be performed in each column. If there is a correlation between adjacent codeword bits, interleaving may be performed to be stronger for a burst error.

The interleaving method has been described so far. Hereinafter, the bit mapping method proposed by the present invention will be described. In the bit mapping scheme described below, bits having a higher order based on the output of one row of the interleaving output of the LDPC codeword, that is, the first and second higher order bits are used as modulated signal constituting bits And a bit mapping method for mapping the low order bits to the bits having high reliability among the modulation signal configuration bits to minimize the overall bit error rate.

Among the output values of the interleaver described in FIG. 6, the output bits of column 1 and column 2 are allocated to the bits having intermediate reliability among the modulation signal configuration bits, and the bits output from column 5 and column 6 are allocated to the reliable bits Method. Assuming an interleaver that sequentially outputs bits from column 1 to bits of column 6 as shown in FIG. 6 (a), the manner in which the output bits of the interleaver are allocated to the modulation signal configuration bits according to each modulation scheme is shown in Table 2 .

<QPSK> b0 maps to y0,0
b1 maps to y1,0 <16 QAM> b0 maps to y2,0
b1 maps to y3,0
b2 maps to y0,0
b3 maps to y1,0 <64 QAM> b0 maps to y2,0
b1 maps to y3,0
b2 maps to y4,0
b3 maps to y5,0
b4 maps to y0,0
b5 maps to y1,0 <256 QAM> b0 maps to y2,0
b1 maps to y3,0
b2 maps to y4,0
b3 maps to y5,0
b4 maps to y6,0
b5 maps to y7,0
b6 maps to y0,0
b7 maps to y1,0

In Table 2, there are 8 bits for 256 QAM, 2 reliability bits, 4 reliability bits, 4 reliability bits, and 2 reliability bits. Therefore, in the case of 256 QAM, there can be various interleavers which can be configured according to the design rule of the present invention. That is, various methods may exist as shown in Table 3 below.

<256 QAM - Method 2> b0 maps to y2,0
b1 maps to y3,0
b2 maps to y6,0
b3 maps to y7,0
b4 maps to y4,0
b5 maps to y5,0
b6 maps to y0,0
b7 maps to y1,0 &Lt; 256 QAM-Method 3 > b0 maps to y4,0
b1 maps to y5,0
b2 maps to y2,0
b3 maps to y3,0
b4 maps to y6,0
b5 maps to y7,0
b6 maps to y0,0
b7 maps to y1,0 &Lt; 256 QAM-Method 4 > b0 maps to y4,0
b1 maps to y5,0
b2 maps to y6,0
b3 maps to y7,0
b4 maps to y2,0
b5 maps to y3,0
b6 maps to y0,0
b7 maps to y1,0

If the number of codeword bits is N, the output bits of the interleaver are b = {b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b ₆ ,. . . , b _N }. Also, the first (0th) modulated signal constituent bits among the modulated signal constituent bits are denoted as y ₀ , ₀ . In other words,

In the case of QPSK (y _0,0 , y _1,0 )

In the case of 16-QAM (y _0,0 , y _1,0 , y _2,0 , y _3,0 )

In the case of 64-QPSK (y _0,0 , y _1,0 , y _2,0 , y _3,0 , y _4,0 , y _5,0 )

In the case of 256-QPSK (y _0,0 , y _1,0 , y _2,0 , y _3,0 , y _4,0 , y _5,0 , y _6,0 , y _7,0 ).

If the interleaved codeword bits are mapped to the modulation symbol configuration bits in the same manner as described above, codeword bits of low order are mapped to the bits of high reliability among the modulation symbol configuration bits, It is possible to increase the reliability in the process. In order to facilitate understanding, input / output of signals according to the interleaving and bit mapping method proposed in the present invention will be briefly described with reference to FIG. 7 below.

FIG. 7 is an exemplary diagram illustrating an interleaving and bit mapping method according to an embodiment of the present invention. Referring to FIG. Assuming that the modulation scheme is 64-QAM and the codeword length is 18, the size of the column of the interleaver is 6 and the size of the row is 3 in the embodiment of FIG.

A code word output from the LDPC encoder _{X = [x 0, x 1} , x 2, x 3, x 4, x 5, x 6, x 7, x 8, x 9, x 10, x 11, x 12, _{x 13, x 14, x 15} , x 16, x 17] referred to the order of the respective bits [8, 8, 8, 8, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2 , 2, 2, 2, 2]. When the interleaver 551 writes the codeword bits in the column order, {x ₀ , x ₁ , x ₂ } is stored in column 1 of the interleaver 551 and {x ₃ , x ₄ , x ₅ } There _{{x 6, x 7, x} 8}, column 4 is _{{x 9, x 10, x} 11}, column 5 is _{{x 12, x 13, x} 14}, column 6 , the {x _15, x _16, x ₁₇ } is input. Bits output in the order of lines in each of the input columns are _{b = [b 0, b 1} , b 2, b 3, b 4, b 5] = [x 0, x ₃ , x ₆ , x ₉ , x ₁₂ , x ₁₅ ].

y, _0,0 , _y2,0 , _y3,0 , _y4,0 , _y5 , and _y5 are mapped according to the mapping rule when they are input to the demultiplexing unit 551 _{, 0} } = {b ₄ , b ₅ , b ₀ , b ₁ , b ₂ , b ₃ } = {x ₁₂ , x ₁₅ , x ₀ , x ₃ , x ₆ , x ₉ }. That is, codewords mapped to y _0,0 and y _1,0 , which are highly reliable code determination bits, are x ₁₂ , x ₁₅ belonging to the second group G _m . Also, the size of the bit y _2,0, of the codeword are mapped to y _3,0-order high decoding performance, the high bit x _0, x _3.

The interleaving and bit mapping method described so far is a method in which the output of the interleaver 551 is outputted in the direction of column 1 to column 6 and bit mapped corresponding thereto. Such interleaving scheme and bit mapping scheme will be referred to as 'forward interleaving' and 'forward bit mapping'. In the present invention, the forward direction is defined as 'direction of column 1 to column 6', but in some cases, 'direction of column 1 in column 6' may be defined as a forward direction.

However, there is no necessity for the interleaver 551 to output the codeword bits only in the forward direction as shown in FIG. 6 (a). Accordingly, if the interleaver 551 outputs codeword bits in the reverse order of FIG. 6A in the reverse order of FIG. 6B, the mapping method of the bit mapper 560 is as follows. Table 4]. This is defined as 'reverse interleaving' and 'reverse bit mapping'.

<QPSK> b0 maps to y0,0
b1 maps to y1,0 <16 QAM> b0 maps to y0,0
b1 maps to y1,0
b2 maps to y2,0
b3 maps to y3,0 <64 QAM> b0 maps to y0,0
b1 maps to y1,0
b2 maps to y4,0
b3 maps to y5,0
b4 maps to y2,0
b5 maps to y3,0 <256 QAM> b0 maps to y0,0
b1 maps to y1,0
b2 maps to y6,0
b3 maps to y7,0
b4 maps to y4,0
b5 maps to y5,0
b6 maps to y2,0
b7 maps to y3,0

An example of the mapping by the reverse bit mapping scheme according to the reverse interleaving of FIG. 6 (b) is shown in FIG. 7 (b).

The output of Figure 7 (b)

_{y = {y 0,0, y 1,0} , y 2,0, y 3,0, y 4,0, y 5,0} = {b 0, b 1, b 4, b 5, b 2, b ₃ } = {x ₁₅ , x ₁₂ , x ₃ , x ₀ , x ₉ , x ₆ }

The output of Figure 7 (a)

_{y = {y 0,0, y 1,0} , y 2,0, y 3,0, y 4,0, y 5,0} = {b 4, b 5, b 0, b 1, b 2, b ₃ } = {x ₁₂ , x ₁₅ , x ₀ , x ₃ , x ₆ , x ₉ }.

Comparing the output of both the case of x is (a) corresponding to the case of y _0,0 x _12, (b) in the case of x is (a) corresponding to the _{x 15, y 1,0 x 15,} (b ), The difference is x ₁₂ . Since y _0,0 and y _1,0 are the same as the code bits and the reliability is the same and x ₁₅ and x ₁₂ correspond to the first and second bits from the least significant bit among the six output bits, ) And Fig. 7 (b) will have the same results in terms of the bit error rate. That is, the first two bits of the six bits are mapped to the high-reliability modulation signal configuration bits, and the two low-order bits (x ₁₂ , x ₁₅ ) are composed of two highly reliable modulation signals Bit, so that they have substantially the same performance in terms of bit error rate.

Although the mapping relation between the interleaver input bits and the modulated signal configuration bits has been described using 64-QAM as an example, a mapping relation according to a general modulation scheme will be described. First, the modulation method is referred to as a 2 ^2m -QAM method, the number of bits of the LDPC codeword is N, the modulation signal of the i-th is y = {y _{0, i} , y _{1, i} , ..., y _{2m-2, i} , y _{2m-1, i} }. It is assumed that interleaving is forward interleaving. In addition, y _{2m-1, i} , y _{2m-2, i} mean the two least reliable bits, and y _{1, i} , y _{0, i} mean two bits with the highest reliability. .

(1) QPSK: i = 0, 1,. . . , N / 2-1,

(y _{0, i} , y _{1, i} ) = (x _i , x _{N / 2 + i} )

(2) 16-QAM: i = 0, 1,. . . , N / 4-1,

(y _{0, i} , _{y 1, i, y 2,} i, y 3, i) = (x 2N / 4 + i, x 3N / 4 + i, x i, x N / 4 + i)

(3) 64-QAM: i = 0, 1,. . . , N / 6-1,

(y _{0, i} , _{y 1, i, y 2,} i, y 3, i, y 4, i, y 5, i) = (x 4N / 6 + i, x 5N / 6 + i, x i, x N / 6 + i , _{x2N / 6 + i} , _{x3N / 6 + i} )

(4) 256-QAM: i = 0, 1,. . . , N / 8-1,

(y _{0, i} , y _{1, i} , y _{2, i} , y _{3, i} , y4 _{, i} , y5 _{, i} , y6 _{, i} , y7 _{, i} )

_{= (X 6N / 8 + i} , x 7N / 8 + i, x i, x N / 8 + i, x 2N / 8 + i, x 3N / 8 + i, x 4N / 8 + i, x 5N / _{8 + i} )

The mapping method of the present invention explained so far is generalized as follows. The codeword composed of N bits is divided into groups of m number of modulation signal constituent bits, and the number of each group element is N / m. Since the LDPC codeword bits are arranged in descending order, the bits of the highest order among the LDPC codeword bits belong to the first group, and the bits of the LDPC codeword bits having the lowest order belong to the last group. The bits belonging to the first group are mapped to two bits whose reliability is intermediate among the bits constituting each of the real part and the imaginary part and the bits belonging to the mth group are mapped in the bits constituting the real part and the imaginary part, It is mapped to two bits.

In the present invention, a bit mapper composed of an interleaver and a demultiplexer is used. However, the present invention can be implemented in software as in the case of storing the interleaver according to the above-described mapping method in a memory without configuring the mapping unit and the interleaver in hardware. And may also be implemented in some cases by directly mapping the codeword bits to the modulation signal configuration bits described above.

 Hereinafter, the performance improvement during data transmission by the interleaving and bit mapping method of the present invention will be described.

8 is a diagram for explaining performance enhancement according to a data transmission method according to an embodiment of the present invention. 8 shows a frame error rate (FER) when an LDPC codeword having a length of 64800 is used. In addition, a 64-QAM modulation signal was used and this is the experimental result on the AWGN channel. The dotted line represents the error rate of the codeword of the interleaver designed in a random manner, and the solid line represents the error rate of the codeword when the interleaver and the bit mapping method according to the present invention are used. It can be seen that the BER performance of the present invention is about 0.2 dB at 10 ^ -4.

The interleaving method and the bit mapping method in the transmitter 400 have been described so far. The deinterleaving and bit demapping scheme used in the receiver 450 will be described below. It is apparent to those skilled in the art that the receiver 450 is configured to correspond to the transmitter 400, so that it will be briefly described. That is, the demodulator 457 of the receiver 450 high-order-demodulates the received signal to output a modulation signal configuration bit, and the constellation bit demapper 455 demodulates and demaps the output modulation signal configuration bit And outputs a signal. The demapping method used at this time corresponds to the bit mapping method of the transmitter 400. That is, two highly reliable bits in the modulated signal constituent bits are demapped to a low-order LDPC codeword, and two low-reliability bits are demapped into a high-order LDPC codeword. The bit demapper 455 corresponds to the bit mapper 415 of the transmitter 400, and thus is configured as a multiplexer (not shown).

The bit demapped and output signal is input to the deinterleaver 453. At this time, the size of the deinterleaver is equal to the size of the interleaver of the transmitter. The bit-mapped signals are sequentially input to the deinterleaver in a row, and output in a forward direction (output from row 1) in the order of the columns. The deinterleaved LDPC codeword bits are output. The output LDPC codewords are input to a decoder 451, decoded and output. If the interleaving of the transmitter 400 was reverse interleaving, it is clear that the deinterleaving of the receiver is also performed in the reverse direction.

1 is an exemplary diagram of a parity check matrix H1 of an LDPC code,

2 is a Trellis diagram of a parity check matrix H1 of an LDPC code,

3A is a schematic diagram of a signal constellation of a general QPSK modulation scheme,

3B is a schematic diagram of a signal constellation of a general 16-QAM modulation scheme,

3C is a schematic diagram of a signal constellation of a general 64-QAM modulation scheme,

4 is a configuration diagram of a communication system using an LDPC code according to an embodiment of the present invention.

5 is a configuration diagram of an interleaver and a signal constellation bit mapper according to an embodiment of the present invention,

6 is a diagram illustrating an operation of an interleaver according to an embodiment of the present invention.

FIG. 7 is a diagram illustrating an interleaver and a bit mapping method according to an embodiment of the present invention. FIG.

8 is a diagram for explaining performance enhancement according to a data transmission scheme according to an embodiment of the present invention.

Claims (12)

A data transmission method of a communication system using a Low Density Parity Check (LDPC) code, An LDPC encoding step of encoding the information data bits to generate an LDPC codeword when information data bits are input; Interleaving the LDPC codeword and outputting codeword bits constituting the LDPC codeword in order; Grouping the output codeword bits into a predetermined number of codeword bit groups in descending order and mapping the bits constituting the codeword bit group to the bits constituting the modulation symbols according to a predetermined modulation scheme A signal constellation bit mapping process for outputting a mapping signal, Modulating the mapping signal to output a modulated signal; (RF) processing the modulated signal and transmitting the modulated signal through a transmission antenna. delete A data transmitting apparatus of a communication system using a Low Density Parity Check (LDPC) code, An interleaver for interleaving the LDPC codeword generated by coding the information data bits and outputting the codeword bits constituting the LDPC codeword in order when the information data bits are input; Grouping the output codeword bits into a predetermined number of codeword bit groups in descending order of the codeword bit group, adding bits constituting the codeword bit group to bits constituting modulation symbols according to a predetermined modulation scheme, A bit mapper for outputting a mapping signal by bit constellation mapping, And a modulator for outputting a modulated signal by performing higher-order modulation on the mapping signal, and RF-processing the modulated signal and outputting the modulated signal to a transmission antenna. delete The method according to claim 1, The signal constellation bit mapping process comprises: Grouping the bits constituting the modulation symbols into a group of modulation bits per reliability corresponding to the number; And mapping the codeword bit group to the modulation bit group. 6. The method of claim 5, The signal constellation bit mapping process comprises: Arranging the codeword bit group according to the order of the codeword bits; Aligning the modulation bit groups according to the reliability; Wherein the alignment order of the codeword bits constituting the aligned codeword bit group is different from the alignment order of the bits constituting the aligned modulation bit group. The method according to claim 6, The first codeword bits constituting the first codeword bit group having the highest order among the codeword bit groups are multiplexed into the first modulation bits constituting the first modulation bit group having the lowest reliability among the modulation bit groups And mapping the data. The method according to claim 1, Wherein the total number of codeword groups is defined as a total number (m) of bits constituting the modulation symbol, and the number (N / m) of codeword bits constituting the codeword bit group is defined as Wherein a total number (N) is defined as a value divided by a total number (m) of bits constituting the modulation symbol. 4. The apparatus of claim 3, wherein the bit mapper comprises: Grouping the bits constituting the modulation symbols into a group of modulation bits per reliability corresponding to the number, and mapping the group of codeword bits to the modulation bit group. 10. The apparatus of claim 9, Arranging the codeword bit groups according to the order of the codeword bits, arranging the modulation bit groups according to the reliability, Wherein the alignment order of the codeword bits constituting the aligned codeword bit group is different from the alignment order of the bits constituting the aligned modulation bit group. 11. The method of claim 10, The bit mapper comprises: The first codeword bits constituting the first codeword bit group having the highest order among the codeword bit groups are multiplexed into the first modulation bits constituting the first modulation bit group having the lowest reliability among the modulation bit groups And mapping the data to the data. The method of claim 3, Wherein the total number of codeword groups is defined as a total number (m) of bits constituting the modulation symbol, and the number (N / m) of codeword bits constituting the codeword bit group is defined as (N) divided by the total number (m) of bits constituting the modulation symbol.

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