WO2006039029A3 - Procede pour former une couche dielectrique a haute permittivite complete mince - Google Patents
Procede pour former une couche dielectrique a haute permittivite complete mince Download PDFInfo
- Publication number
- WO2006039029A3 WO2006039029A3 PCT/US2005/030841 US2005030841W WO2006039029A3 WO 2006039029 A3 WO2006039029 A3 WO 2006039029A3 US 2005030841 W US2005030841 W US 2005030841W WO 2006039029 A3 WO2006039029 A3 WO 2006039029A3
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- WIPO (PCT)
- Prior art keywords
- layer
- substrate
- forming
- complete high
- thick
- Prior art date
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- 238000000034 method Methods 0.000 title abstract 6
- 239000000758 substrate Substances 0.000 abstract 5
- 238000000151 deposition Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
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- H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C16/52—Controlling or regulating the coating process
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- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Inorganic Chemistry (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical Vapour Deposition (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007534604A JP2008515223A (ja) | 2004-09-30 | 2005-08-31 | 薄い一面の高誘電率誘電体層の形成方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/711,721 | 2004-09-30 | ||
US10/711,721 US20060068603A1 (en) | 2004-09-30 | 2004-09-30 | A method for forming a thin complete high-permittivity dielectric layer |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2006039029A2 WO2006039029A2 (fr) | 2006-04-13 |
WO2006039029A3 true WO2006039029A3 (fr) | 2006-07-27 |
Family
ID=36099791
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2005/030841 WO2006039029A2 (fr) | 2004-09-30 | 2005-08-31 | Procede pour former une couche dielectrique a haute permittivite complete mince |
Country Status (6)
Country | Link |
---|---|
US (1) | US20060068603A1 (fr) |
JP (1) | JP2008515223A (fr) |
KR (1) | KR20070067079A (fr) |
CN (1) | CN101032004A (fr) |
TW (1) | TWI270140B (fr) |
WO (1) | WO2006039029A2 (fr) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060151846A1 (en) * | 2005-01-13 | 2006-07-13 | International Business Machines Corporation | Method of forming HfSiN metal for n-FET applications |
JP2009512995A (ja) * | 2005-10-20 | 2009-03-26 | アンテルユニヴェルシテール・ミクロ−エレクトロニカ・サントリュム・ヴェー・ゼッド・ドゥブルヴェ | 高誘電率誘電体層を形成するための方法 |
US7390708B2 (en) * | 2006-10-23 | 2008-06-24 | Interuniversitair Microelektronica Centrum (Imec) Vzw | Patterning of doped poly-silicon gates |
US8084087B2 (en) * | 2007-02-14 | 2011-12-27 | The Board Of Trustees Of The Leland Stanford Junior University | Fabrication method of size-controlled, spatially distributed nanostructures by atomic layer deposition |
TW200842950A (en) * | 2007-02-27 | 2008-11-01 | Sixtron Advanced Materials Inc | Method for forming a film on a substrate |
US7790628B2 (en) * | 2007-08-16 | 2010-09-07 | Tokyo Electron Limited | Method of forming high dielectric constant films using a plurality of oxidation sources |
US7964515B2 (en) * | 2007-12-21 | 2011-06-21 | Tokyo Electron Limited | Method of forming high-dielectric constant films for semiconductor devices |
WO2009084194A1 (fr) * | 2007-12-28 | 2009-07-09 | Tokyo Electron Limited | Procédé de gravure pour film métallique et film d'oxyde métallique, et procédé de fabrication de dispositif à semi-conducteur |
WO2009120327A1 (fr) * | 2008-03-24 | 2009-10-01 | The Board Of Trustees Of The Leland Stanford Junior University | Appareil pour dépôt de nanostructures assisté par microscope à force atomique |
JP2010074065A (ja) * | 2008-09-22 | 2010-04-02 | Canon Anelva Corp | 酸化膜除去のための基板洗浄処理方法 |
CN102064103A (zh) * | 2010-12-02 | 2011-05-18 | 上海集成电路研发中心有限公司 | 高k栅介质层的制备方法 |
US8951829B2 (en) | 2011-04-01 | 2015-02-10 | Micron Technology, Inc. | Resistive switching in memory cells |
JP5801676B2 (ja) * | 2011-10-04 | 2015-10-28 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
CN103311120A (zh) * | 2013-06-03 | 2013-09-18 | 中国科学院微电子研究所 | 一种生长高介电常数电介质叠层的方法 |
US9425078B2 (en) * | 2014-02-26 | 2016-08-23 | Lam Research Corporation | Inhibitor plasma mediated atomic layer deposition for seamless feature fill |
US9667303B2 (en) * | 2015-01-28 | 2017-05-30 | Lam Research Corporation | Dual push between a host computer system and an RF generator |
KR20240146494A (ko) * | 2023-03-29 | 2024-10-08 | 성균관대학교산학협력단 | 플라즈마 화학 기상 증착법 기반 강유전성 결정구조 유도를 통한 강유전체 제조방법 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6232174B1 (en) * | 1998-04-22 | 2001-05-15 | Sharp Kabushiki Kaisha | Methods for fabricating a semiconductor memory device including flattening of a capacitor dielectric film |
US20030109106A1 (en) * | 2001-12-06 | 2003-06-12 | Pacheco Rotondaro Antonio Luis | Noval chemistry and method for the selective removal of high-k dielectrics |
US20040105213A1 (en) * | 2002-11-29 | 2004-06-03 | Ulrich Egger | Ferroelectric capacitor and process for its manufacture |
US20040129674A1 (en) * | 2002-08-27 | 2004-07-08 | Tokyo Electron Limited | Method and system to enhance the removal of high-k dielectric materials |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6238737B1 (en) * | 1999-06-22 | 2001-05-29 | International Business Machines Corporation | Method for protecting refractory metal thin film requiring high temperature processing in an oxidizing atmosphere and structure formed thereby |
US7071122B2 (en) * | 2003-12-10 | 2006-07-04 | International Business Machines Corporation | Field effect transistor with etched-back gate dielectric |
-
2004
- 2004-09-30 US US10/711,721 patent/US20060068603A1/en not_active Abandoned
-
2005
- 2005-08-31 JP JP2007534604A patent/JP2008515223A/ja active Pending
- 2005-08-31 WO PCT/US2005/030841 patent/WO2006039029A2/fr active Application Filing
- 2005-08-31 KR KR1020077003412A patent/KR20070067079A/ko not_active Application Discontinuation
- 2005-08-31 CN CNA2005800329588A patent/CN101032004A/zh active Pending
- 2005-09-20 TW TW094132436A patent/TWI270140B/zh not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6232174B1 (en) * | 1998-04-22 | 2001-05-15 | Sharp Kabushiki Kaisha | Methods for fabricating a semiconductor memory device including flattening of a capacitor dielectric film |
US20030109106A1 (en) * | 2001-12-06 | 2003-06-12 | Pacheco Rotondaro Antonio Luis | Noval chemistry and method for the selective removal of high-k dielectrics |
US20040129674A1 (en) * | 2002-08-27 | 2004-07-08 | Tokyo Electron Limited | Method and system to enhance the removal of high-k dielectric materials |
US20040105213A1 (en) * | 2002-11-29 | 2004-06-03 | Ulrich Egger | Ferroelectric capacitor and process for its manufacture |
Also Published As
Publication number | Publication date |
---|---|
TWI270140B (en) | 2007-01-01 |
CN101032004A (zh) | 2007-09-05 |
KR20070067079A (ko) | 2007-06-27 |
TW200623264A (en) | 2006-07-01 |
JP2008515223A (ja) | 2008-05-08 |
WO2006039029A2 (fr) | 2006-04-13 |
US20060068603A1 (en) | 2006-03-30 |
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