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WO2002065642A1 - Circuit integre a semi-conducteurs, systeme de traitement de donnees et appareil de terminal mobile de communication - Google Patents

Circuit integre a semi-conducteurs, systeme de traitement de donnees et appareil de terminal mobile de communication Download PDF

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Publication number
WO2002065642A1
WO2002065642A1 PCT/JP2001/010007 JP0110007W WO02065642A1 WO 2002065642 A1 WO2002065642 A1 WO 2002065642A1 JP 0110007 W JP0110007 W JP 0110007W WO 02065642 A1 WO02065642 A1 WO 02065642A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
state
arithmetic processing
clock
substrate bias
Prior art date
Application number
PCT/JP2001/010007
Other languages
English (en)
Japanese (ja)
Inventor
Kosaku Aida
Koichi Ashiga
Taichi Ohashi
Original Assignee
Hitachi,Ltd
Hitachi Device Engineering Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi,Ltd, Hitachi Device Engineering Co., Ltd. filed Critical Hitachi,Ltd
Priority to JP2002564839A priority Critical patent/JP3848259B2/ja
Publication of WO2002065642A1 publication Critical patent/WO2002065642A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to a low power consumption control, a clock control, and a substrate bias control of a semiconductor integrated circuit and a data processing system, and relates to a technology which is applicable to a mobile communication terminal device such as a mobile phone. .
  • T CXO Temporal Compensated Voltage Controlled Oscillator
  • Japanese Patent Application Laid-Open No. 10-190444 discloses A technique is described in which a substrate bias is individually controlled for each circuit block, and a substrate threshold of a stopped circuit block is controlled, thereby reducing a sub-threshold leakage current of the circuit block.
  • the present inventor has studied about stopping the operation of the circuit block of the mobile phone and controlling the board bias control optimally according to the operation state.
  • the aforementioned Japanese Patent Application Laid-Open No. 10-190444 describes that the substrate bias control is individually performed for each circuit block, but in any case, how and how to apply and stop the substrate bias to the circuit block. No consideration is given as to whether to control in relation to the state.
  • a DSP which performs a communication protocol process performs a channel codec process required at the time of reception and performs a voice codec process of voice compression / expansion during a call.
  • the present inventor has studied a case where a substrate bias generation circuit for performing substrate bias control is employed.
  • a substrate bias generation circuit for performing substrate bias control is employed.
  • the mobile phone is off It is necessary to keep some circuits operating, such as the metering function and the wake-up event detection function.However, at this time, it is necessary to apply the substrate bias while supplying the operating power to the circuits that have stopped operating. Waste was found.
  • high-speed operation return as in the standby state is not required, nor is it necessary.
  • Another object of the present invention is to further reduce power consumption in a power-off state of a mobile phone or the like even when a substrate bias generation circuit is employed.
  • Still another object of the present invention is to provide a configuration for switching the substrate bias application Z stop to contribute to a reduction in noise to the PLL circuit.
  • Another object of the present invention is to provide a data processing system such as a portable telephone capable of easily realizing sequence control of stopping / starting supply of a block to a circuit block and stopping application of a substrate bias. .
  • Another object of the present invention is to guarantee the operation reliability or operation stability of a mobile communication terminal device such as a mobile phone, and to stop the operation of the built-in circuit block Z start and to apply / stop the substrate bias. The point is to make the transition controllable.
  • a paceband unit for a mobile phone a CPU that performs protocol processing, man-machine interface (MMI) processing, a first timing generation circuit that generates TDMA-type evening using a clock source such as TCXO, and the like.
  • MMI man-machine interface
  • a third circuit package including an intermittent reception timing generation circuit that performs frame synchronization using the clock source of the watch crystal oscillator when no reception operation is performed on the same semiconductor chip is mounted on the same semiconductor chip. Configure the circuit.
  • the first circuit block to the third circuit block need to be operated during a call or intermittent reception, etc., all circuit blocks are operated, but the reception operation during intermittent reception is performed. Otherwise, the clock supply to the first and second circuit blocks is stopped, and a back bias is applied to reduce the leakage current and reduce power consumption.
  • the clock supply is stopped only in the second circuit block, and by applying the back bias, unnecessary leakage current can be reduced. To reduce emissions.
  • the first to third circuit blocks operating on a core power supply of about 1.5 V, the I / O area of a semiconductor integrated circuit operating on a power supply of about 3 V, a real-time clock (RTC) unit, and a semiconductor.
  • a wake-up event detection circuit for the integrated circuit is provided, and when the power switch of the mobile phone is off, the power supply of the circuit block operated by the core power supply and the operation of the board bias voltage generation circuit are stopped, and the voltage is about 3 V.
  • a back bias is applied to all of the first to third circuit blocks to enable a leak current measurement.
  • a semiconductor integrated circuit includes a first arithmetic processing circuit (1), a second arithmetic processing circuit (2), and a control circuit (1) for controlling states of the first and second arithmetic processing circuits. 3, 9, 11).
  • the control circuit includes a first state (normal mode) in which a clock is supplied to the first and second arithmetic processing circuits and a substrate bias is stopped, and a second state in which the clock is supplied to the first arithmetic processing circuit and the substrate is stopped.
  • the second state power save 2 mode in which the clock supply to the processing circuit is stopped and the substrate bias is applied, and the third state in which the clock supply is stopped and the substrate bias is applied to the first and second processing circuits.
  • State power save 1 mode
  • the first arithmetic processing circuit is a circuit such as a CPU that performs mobile communication protocol processing and man-machine interface control
  • the second arithmetic processing circuit is a mobile communication communication circuit. It is a circuit such as DSP that performs signal processing on the baseband signal.
  • the mobile phone is set to the third state during a call waiting state, is set to the first state during an intermittent reception operation or a call operation during a call waiting state, and is set to the second state during an operation during a call waiting state.
  • This semiconductor integrated circuit reduces the operating current by stopping the clock and the leakage current by applying the substrate bias to the first and second arithmetic processing circuits, and performs the first and / or second arithmetic processing circuits. It has an operation mode that enables the above operation, and can achieve low power consumption.
  • the threshold voltage of the circuit In the substrate bias state, the threshold voltage of the circuit is different from normal, so if there is an undesired signal input or an undesired operation, there is a possibility that an undesired state change will occur in the operation stopped state circuit such as the static latch circuit. There is.
  • the first arithmetic processing circuit gives the instruction to make a transition from the first state to the second state, after giving the instruction, the first arithmetic processing circuit inputs / outputs a signal to / from the second arithmetic processing circuit. Since it is easy to avoid the malfunction, it is possible to prevent such a malfunction from occurring.
  • the transition from the second state to the third state may be performed based on the instruction of the first arithmetic processing circuit.
  • the third state the operations of both the arithmetic processing circuits are stopped.
  • the control circuit issues an instruction from the first arithmetic processing circuit.
  • the timer information is set, it is preferable to make a transition from the second state to the third state.
  • the evening information is time information that defines the interval of the intermittent reception operation.
  • the control circuit may detect the elapse of the time set by the evening information and make a transition from the third state to the second state. Thereby, the first arithmetic processing circuit can restart the processing for the intermittent reception operation, for example.
  • the control circuit detects the occurrence of a first external event (such as a key input) and responds to a key input while the operation of the first and second arithmetic processing circuits is stopped. What is necessary is just to make a transition to the second state.
  • the control circuit further controls a fourth state in which the first and second arithmetic processing circuits stop supplying clock and stop supplying operation power. For example, it is only necessary to detect the occurrence of the second external interrupt (power switch-off) and make a transition from the second state or the third state to the fourth state.
  • the mode control circuit may detect the occurrence of a third external event (power switch-on) and transition from the fourth state to the first state.
  • the semiconductor integrated circuit includes an arithmetic processing circuit (CPU, DSP, etc.), and a REG (regulator) for generating an internal power by inputting an external power.
  • a substrate bias generation circuit (VBG) for generating a substrate bias voltage of the arithmetic processing circuit; and a control circuit, wherein the control circuit responds to an instruction to stop power supply to the arithmetic processing circuit. Then, regulation is controlled so that the internal power supply is set to 0V, and the board bias generation circuit is controlled so that the board bias voltage is set to 0V.
  • the operation of the arithmetic processing circuit to be reduced by the operation clock stop and the leakage current reduction by the substrate bias control is stopped and the substrate bias control is performed without depending on the state of the arithmetic processing circuit without malfunction. It can be controlled optimally.
  • a semiconductor integrated circuit that considers that the configuration for switching the application / stop of substrate bias to reduce noise to the PLL circuit has a PLL circuit (1P) with a MOS transistor circuit and a MOS transistor circuit. a logic circuit (1 L), and MO S substrate bias generating circuit (7) for generating a substrate bias voltage of the transistor circuit, the substrate gate one bets (the M 0 S transistors evening circuit and a control circuit (9) Supply board bias voltage
  • a first switch (81a, 81b) that operates and a second switch (1Ps, 1Ls) that supplies the source voltage to the substrate gate of the MOS transistor circuit are connected to the PLL circuit and the logic circuit. Provided separately.
  • the control circuit sets the first switch to an off state when operating the PLL circuit and the logic circuit to which operating power is supplied, sets the second switch to an on state, and stops the operation when the first switch is stopped.
  • the switch is turned on, and the second switch is turned off.
  • the data processing system that takes into account the external clock generation / stop and substrate bias application / stop interlocking control uses a clock generation circuit (114).
  • a semiconductor integrated circuit (150) having an input terminal connected to a clock output terminal of the cook generation circuit and an output terminal connected to an operation power control terminal of the clock generation circuit.
  • the semiconductor integrated circuit includes: an arithmetic processing circuit (1); a regulator (6) for receiving an external power supply to generate an internal power supply; and a substrate bias generating circuit for generating a substrate bias voltage of the arithmetic processing circuit. It has a circuit (7) and a control circuit (3, 9).
  • the control circuit outputs, from the output terminal, a control signal (TCXOON) for instructing supply / stop of operation power in the clock generation circuit based on an instruction from the arithmetic processing circuit, and outputs the control signal.
  • a control signal TXOON
  • an instruction is given to stop the substrate bias to the arithmetic processing circuit, and in response to an operation power supply instruction of the control signal, the supply of a substrate bias to the arithmetic processing circuit is instructed.
  • the semiconductor integrated circuit diverts the operation power supply / stop instruction signal of the clock generation circuit to the substrate bias application stop instruction signal.
  • the instruction signal of the clock generation / stop is used for the instruction of the substrate bias application / stop. This can contribute to a reduction in the control logic scale.
  • a third state (power save 1 mode) for stopping and applying a substrate bias is provided. The state is set to the third state during call waiting, and during intermittent reception operation or call operation during call waiting. Is one state and the second state when operating in standby call. It is more preferable that the operation mode selected when the power switch is off has a fourth state in which the clock supply and the operation power supply to the CPU and DSP units are stopped.
  • FIG. 1 is a block diagram showing a first example of a semiconductor integrated circuit according to the present invention.
  • FIG. 2 is a block diagram showing an example of a mobile phone according to the present invention.
  • FIG. 3 is a circuit diagram showing an example of a configuration of a circuit block built in a semiconductor integrated circuit.
  • FIG. 4 is a block diagram showing a configuration example of the Vbb switch.
  • FIG. 5 is an explanatory diagram exemplifying an operation mode of the Vbb switch and an output voltage thereby.
  • FIG. 6 is an explanatory diagram illustrating the input and output of the Vbb generator.
  • FIG. 7 is a block diagram exemplifying a schematic configuration of the regiyure.
  • FIG. 8 is a description exemplifying the operation modes of the V bb switch, the Reggi Yule, the V b To generator and the TCXO for the operation mode of the semiconductor integrated circuit.
  • Figure 9 is a state transition diagram between power save 1, power save 2, and power off modes.
  • FIG. 10 is an explanatory diagram of wake-up detection means having a gate means at an output stage.
  • FIG. 11 is an explanatory diagram showing a specific example of the gate means of FIG.
  • FIG. 12 is an operation timing chart illustrating a state transition during intermittent reception of a mobile phone. .
  • FIG. 13 is a timing chart showing an operation example when an interrupt occurs due to a keypad press during intermittent reception of a mobile phone.
  • FIG. 14 is a timing chart showing the relationship between the clock supplied to the circuit block and the application of the substrate bias voltage.
  • FIG. 15 is a flowchart illustrating the operation procedure of FIGS. 12 and 13.
  • FIG. 16 is a block diagram showing a second example of the semiconductor integrated circuit according to the present invention.
  • FIG. 17 is a schematic circuit diagram showing, as a second example of a semiconductor integrated circuit, an example in which a PLL circuit is mounted on a circuit block and Vbb switches are divided.
  • FIG. 18 is a block diagram showing a third example of the semiconductor integrated circuit according to the present invention.
  • FIG. 19 is a professional and schematic diagram showing a fourth example of the semiconductor integrated circuit according to the present invention.
  • FIG. 20 is a block diagram showing another example of the regiyure night. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 2 shows an example of a mobile phone according to the present invention.
  • Antenna 1 0 0 The received signal in the radio band received by the antenna is transmitted to the high frequency unit (RF unit) 102 as a received signal via the antenna switch 101.
  • the antenna switch 101 may be a distributor for distributing a reception frequency band and a transmission frequency band, and distributing a signal to the antenna 100 or the RF unit 1 • 2.
  • the received signal is converted to a lower frequency signal by the RF unit 102 and input to the modem 103.
  • the received signal is demodulated by the modulation / demodulation unit 103, converted into a digital signal, and input to the channel codec 104.
  • the channel codec deciphers the received digitized signal, corrects and detects the error, and divides it into communication data such as control data and compressed audio data necessary to realize communication.
  • the control data is sent to CPU 105, where communication protocol processing and the like are performed.
  • the CPU 105 also displays the liquid crystal display 107 via the MMI (man-machine interface) section 106 and receives key press information from the keypad 108. It also performs a man-machine-in-face function that processes through the man-machine-in-face unit 106.
  • the audio data extracted by the channel codec section 104 is expanded by the audio codec section 109, and the audio data is converted into digital data by the D / A section 110. The sound is played back from the speaker 1 1 1 as sound.
  • the filter processing, analog-to-digital conversion, and input to the audio codec section 109 are performed.
  • the audio data is compressed and converted into compressed audio data.
  • the channel codec 104 combines the compressed audio data of the audio codec 109 with the control data from the CPU 105 to generate a transmission data string, which is then subjected to error correction, detection code, After adding the secret code, the transmission data is output to the modem 103. Modulation and demodulation
  • the transmission data is converted from a digital signal to a modulation signal in section 103, and then converted to a high-frequency signal in the radio signal band by the F section 102, amplified, and transmitted through antenna switch 101 to antenna 100. It is transmitted as a wireless signal.
  • the channel codec section 104 and the audio codec section 109 may be constituted by a dedicated logic circuit, or may be constituted by a DSP (digital signal processor) or the like.
  • reference numeral 114 denotes a TCXO (Temperature Compensated Voltage Controlled Oscillator), which generates a clock necessary for the RF unit 102 and a timing required for the mobile phone to perform communication. And a reference clock for the modulator / demodulator 103 and the CPU 105 (not shown).
  • the operation of the RF unit 102 is controlled by the RF control unit 116.
  • the RF control section 116 generates control timing of the RF section 102 based on the evening timing signal from the first timing generation circuit 115.
  • the mobile phone establishes frame synchronization for communication with a base station, and determines a reception position and a transmission position. Even when the mobile phone is in standby mode, the mobile phone periodically receives the radio signal sent from the base station. This is called intermittent reception. It is necessary to keep establishing frame synchronization in order to predict the position of the signal sent periodically from the base station.
  • the first timing generation circuit 115 using the T CXO 114 as a clock source may be used to maintain frame synchronization during the period of non-reception, but usually T CXO 1 14 is a relatively high frequency with an oscillating frequency of more than 10 MHz and a current consumption of several mA, and the current consumption is also high.Therefore, a clock oscillator with a clock oscillation frequency of 32.768 kHz and a current consumption / A 1 17 It is common to use It is.
  • the clock of the clock oscillator 117 is supplied to an RTC (real-time clock) unit 118 for clock, and is also supplied to a second timing generation circuit 119 at the same time.
  • RTC real-time clock
  • Reference numeral 120 denotes a memory, which is a flash EEPROM (Electrically Erasable and Programmable Rea Only Memory) for storing an operation program of the CPU 105 or a RAM (Random Access Memory).
  • EEPROM Electrically Erasable and Programmable Rea Only Memory
  • the above-mentioned channel codec 104, audio codec 109, CPU 105, MMI 106, first timing generator 115, RF controller 116, RTC 118, second timing generator 1 19 is configured on the same semiconductor chip 150.
  • FIG. 1 shows a first example of a semiconductor integrated circuit according to the present invention.
  • the semiconductor integrated circuit shown in the figure realizes the function formed on the semiconductor chip 150 of FIG.
  • 150 is also referred to as a semiconductor integrated circuit.
  • reference numeral 1 denotes a first circuit block (first arithmetic processing circuit).
  • the functions of the circuit 115 and the RF controller 116 are realized.
  • Reference numeral 2 denotes a second circuit block (second arithmetic processing circuit) which implements the functions of the channel codec 104 and the voice codec 109 in the configuration example of the mobile phone.
  • Reference numeral 3 denotes a third circuit block, which implements the function of the second timing generation circuit 119.
  • each of the circuits can be realized as a dedicated circuit, but each of the circuits is separately provided by a microcontroller. It may be composed of a computer module or a microprocessor module.
  • the microcomputer module or the microprocessor module separately configuring the first circuit block 1 and the second circuit block 2 may have the same CPU core.
  • a CPU core may have a CPU unit and a DSP unit.
  • the microphone computer module or the microprocessor module may include a memory, an appropriate peripheral module, a peripheral interface, an n-th circuit, and the like, depending on other functions to be realized. .
  • the circuit block 1, the circuit block 2, and the circuit block 3 are configured in an internal core power supply region 4 on the same semiconductor chip.
  • the clock control unit 3a included in the circuit block 3 controls whether to supply or stop the clock to the circuit blocks 1 and 2.
  • 5 is an I / O power supply region
  • 6 is a regulator (REG) that generates a voltage for the internal core power supply from the I / O power supply.
  • VBG substrate bias generation circuit
  • Reference numerals 81, 82, and 83 denote Vbb switches (VBS) for controlling whether or not to apply a back bias voltage to the circuit blocks 1, 2, and 3, respectively.
  • the Vbb switches 81, 82, and 83 are off (no Vbb applied)
  • the internal core voltage from the regulator 6 is applied to the logic cells of the circuit blocks 1, 2, and 3, and the Vbb switch 81,
  • the back bias voltage (substrate bias voltage) from the substrate bias generating circuit 7 is applied to the logic cells of the circuit blocks 1, 2, and 3.
  • the threshold voltage of the MOS transistor increases, and the leakage current of the logic cells that constitute the circuit blocks 1, 2, and 3 is reduced. It is possible to do.
  • the Vbb switches 81, 82, and 83 are switched by the control signals 81 S, 82 S, and 83 S from the Vbb control unit c 10 is a clock oscillator input from the clock oscillator 117, and 11 is an external circuit This is a wake-up detection unit that detects a wake-up signal from the wake-up device.
  • the control signal 6 S controls the voltage generation / stop of the regulator 6, and the control signal 7 S controls the generation / stop of the substrate bias voltage of the Vbb generator 7.
  • the circuit block 3, the wake-up detection unit 11, and the Vbb control unit 9 are positioned as control circuits that control states such as clock supply / stop to the semiconductor integrated circuit 150 and substrate bias application / stop.
  • the output clock signal from TCX0114 is shown as CLK1.
  • the signal TCXO ON is a power control signal of TCXO 114.
  • the TCXO 114 has a regulator for generating an oscillator and its operating power supply.
  • the signal TCXO ON controls the regulation and the power supply Z supply of the TCXO 114 is controlled.
  • FIG. 3 shows a configuration example of the circuit block 1 (2, 3).
  • Vbp, Vbn, Vbcp, and Vbcn are supplied from the Vbb switch (VBS) 81 (82, 83), and Vdd is supplied from the regi- ure night 6.
  • V s s is the ground potential.
  • the switch cell SWC switches between application of Vdd and potential of Vbb to the logic cell LGC in the circuit block 1 by a signal from the Vbb switch 81.
  • FIG. 4 shows a configuration example of the Vbb switch 81 (82, 83).
  • Vcc and V sub are supplied from Vbb Dienere overnight.
  • Vdd is supplied from regulation 6.
  • the Vbb switch 81 (82, 83) uses the control signal 81S (82S, 83S) from the Vbb control unit 9 to supply Vb p, Vb cp, Vb cn, and Vbn supplied to each circuit block in FIG. Switch on / off of switches 80 1 to 810 so that they have the indicated potential Output.
  • Vbp, Vbcp, Vbcn, and Vbn By switching the switch cell SWC according to the signals Vbp, Vbcp, Vbcn, and Vbn, it is possible to control whether or not a back bias voltage is applied to the circuit circuit.
  • FIG. 6 illustrates the input / output of the Vbb generator 7.
  • Vbb generator 7 When Vbb generator 7 is off (substrate bias voltage generation stopped), the output of Vbb generator — V7 outputs Vcc from the Vcc pin, and the Vsub pin goes into a high-impedance state.
  • Vdd-Vcc When Vbb generator 7 is operating, Vdd-Vcc is output as voltage Vsub, and this potential is charged in parasitic capacitance C ,. Therefore, immediately after the Vbb generator 7 is turned off, the potential of the terminal Vsub is the voltage Vsub, but the charge of the parasitic capacitance C 'is discharged by the leak resistance RL connected to the power supply line of the terminal Vsub, Eventually, it becomes the ground potential V ss of the circuit.
  • the Vbb control unit 9 turns on the power supply of the regulator 6 and the Vbb generator 7, and turns off the Vbb switches 81, 82, and 83.
  • the internal core voltage is applied to circuit blocks 1, 2, and 3.
  • the power supply control signal TCXOON of the reference clock TCX0114 is turned on (operation power supply instruction state), and the reference clock signal CLK1 is also supplied to the semiconductor chip 150.
  • This state is hereinafter referred to as a normal operation mode.
  • the circuit blocks 1 and 2 must operate except the circuit block 3 that includes the second timing generation circuit 1 19 There is no.
  • the clock control unit 3a included in the circuit block 3 stops the clock supply to the circuit blocks 1 and 2, and the Vbb control unit 9 turns on the power supply of the Reggi Yule 6 and the Vbb generator 7 State, the Vbb switches 81 and 82 are turned on, and the Vbb switch 83 is turned off.
  • a back bias voltage is applied to the circuit blocks 1 and 2 to suppress the leakage current of the circuit blocks 1 and 2.
  • the power control signal to the TCXO 114 is turned off, and the clock supply to the semiconductor chip is stopped. This state is hereinafter referred to as power save 1 mode. .
  • the circuit blocks 1 and 3 including the CPU 105 and the MMI section 106 operate, but the circuit block 2 does not need to operate.
  • the clock control unit 3a stops supplying the clock to the circuit block 2
  • the Vbb control unit 9 turns on the power supply of the regulator 6 and the Vbb generator 7, and turns on the Vbb switch 82.
  • the Vbb switches 81:83 are turned off.
  • the circuit blocks 1 and 3 continue to operate, and the back bias voltage is applied to the circuit block 2 so that the leakage current of the circuit block 2 can be suppressed.
  • the power control signal TCX00N to the TCXO 114 is turned on, and the clock signal CLK1 is supplied to the semiconductor chip. This state is hereinafter referred to as power save 2 ⁇ ⁇ ⁇ .
  • the Vbb control unit 9 stops the operation of the regulator 6 and the Vbb generator 7, and sets the Vbb switches 81, 82, and 83 to the power off mode shown in FIG.
  • the leggyle night 6 includes a leggyle night part 6a and a switch 6b.
  • Switch 6 b has contacts a, b, and c.
  • the output of the regulator 6 is in a high impedance state, in the case of b, the output is regulated.
  • the switch 6b When the power supply of the regulator 6 is turned off, the switch 6b is connected to the c side and outputs 0V as the internal core voltage. Therefore, in the power off state of the regulator 6, 0 V is applied to the circuit blocks 1, 2, and 3 as the internal core voltage, and the leak current in the internal core power supply region can be reduced to almost 0 / A. . In this state, only the clock oscillation circuit 10, RTC section 118, and wake-up detection section 11 in the I / O power supply area operate, and the operation of the 1 ⁇ pad is stopped. Can be minimized.
  • the power control signal of TCX0114 is pulled down to the ground by the resistor 114r so that the power control signal TCXOON to TCXO 114 is also turned off (operating power supply stop instruction state).
  • This pull-down resistor 114r may be outside the semiconductor chip or on the semiconductor chip. This state is hereinafter referred to as a power-off mode.
  • the Vbb control unit 9 connects the switch 6 b inside the regulator 6 to the terminal a, and sets the output of the regulator 6 to a high impedance state.
  • the internal core power is supplied from the power supply terminal 12 from the LSI tester.
  • the Vbb control unit 9 turns on the Vbb generator 7, turns on the Vbb switches 81, 82:83, and applies the bag bias voltage to the circuit blocks 1, 2, and 3 to make them in the low leak state.
  • the leakage current in the internal core power supply area is measured by measuring the current of the internal core power supply supplied from the outside. It is possible to detect an internal failure. This state is hereinafter referred to as a leak test mode.
  • FIG. 8 summarizes the operation states of the Vbb switches 81, 82, and 83, the regiureya 6, the Vbb generator 7, and the TCXO 114 for the above operation modes.
  • the Vbb control section 9 turns off the Vbb switches 81, 82, 83, turns on the regulator 6 (normally outputs the internal core voltage), and turns on the Vbb generator 7. State.
  • the power control signal T CXO ON to the T CXO 114 from the circuit block 3 is turned on (operating power voltage supply instruction state).
  • the Vbb controller 9 turns on the Vbb switches 81 and 82, turns off the Vbb switch 83, turns on the regulator 6 (normally outputs the internal core voltage), and turns on the Vbb generator 7. And In this state, the power control signal TCXON from the circuit work 3 to the TCX0114 is turned off (operating power supply stop instruction state).
  • the Vbb control unit 9 turns on the Vbb switch 82, turns off the Vbb switch 83, turns on the regulator 6 (normally outputs the internal core voltage), and turns on the Vbb generator 7. In this state, the instruction to TCX0114 from the circuit work 3 is turned on.
  • the Vbb control unit 9 turns off the Vbb switches 81, 82, and 83, turns off the regulator 6 (0V output), and turns off the Vbb generator 7.
  • the control signal TCX00N of TCX0114 is not driven from the semiconductor chip, but is turned off because it is pulled down.
  • the Vbb control unit 9 turns on the Vbb switches 81, 82, and 83, turns off the regulator 6 (output Hi_Z state), and turns on the Vbb generator. In this mode, the test of the semiconductor chip is assumed. The state of the power control signal T CXO ON to TCXOll 4 does not matter.
  • T CXO 114 the operation of T CXO 114 is the same as when Vbb is not applied to the circuit block 1 including the CPU 105 that performs the main control process, that is, when the circuit block 1 operates. Accordingly, the Vbb control unit 9 controls the Vbb switch 81 using the power control signal TCXON of the TCXO 114 in FIG.
  • FIG. 9 shows the state transition between the normal, power save 1, power save 2, and power off modes.
  • the method of transition of the operation mode according to the actual operation of the mobile phone will be described in detail.
  • the leak test mode is a mode in which a leak current is tested in a process of manufacturing a semiconductor chip, and thus is omitted in this description.
  • the Vbb control unit 9 When transitioning from the normal operation mode to the power-off mode (200), the Vbb control unit 9 receives the control signal from the CPU 105 included in the circuit block 1 and the Vbb switches 81, 82, 83, The Vbb generator 7 is controlled so that the power supply is turned off as shown in FIG. In addition, the Vbb control unit 9 inputs a signal to the semiconductor chip such that a high (High) level is input when the battery voltage is higher than a preset value, and a low (L0 w) level is input when the battery voltage is lower than the predetermined value. A one-voltage monitoring terminal 13 is provided, and the one-voltage monitoring terminal 13 is connected to the Vbb controller 9.
  • the Vbb control unit 9 switches the Vbb switches 81, 82, and 83, the reguille 6 and the Vbb generator 7 to the power supply shown in FIG.
  • the state is controlled so that the power supply is turned off.
  • the state transitions to the power off state regardless of the operating state (204, 206).
  • a wake-up signal is input from the wake-up terminal 14, and the wake-up detection signal 11 is output from the wake-up detection unit 11 to the Vbb control unit 9, and the Vbb control unit Numeral 9 controls the Vbb switches 81, 82, 83, the regulator 6 and the Vbb generator 7 so as to be in the state shown in the normal operation in FIG.
  • the wake-up signal is generated by, for example, pressing a power-on button provided on the mobile phone.
  • the CPU 105 included in the circuit block 1 stops the clock supply to the circuit block 2 by the clock control unit 3 a included in the circuit block 3.
  • the control signal 1 Sa for turning on the V bb switch 82 is output to the V bb control unit 9.
  • the Vbb control section 9 controls the Vbb switches 81, 82, 83, the regulator 6 and the Vbb generator 7 to be in the state of the power save 2 shown in Table 1.
  • the CPU 105 included in the circuit block 1 When transitioning from the power save 2 mode to the normal operation mode (203), the CPU 105 included in the circuit block 1 outputs a control signal 1Sa for turning off the Vbb switch 82 to the Vbb control unit 9. I do.
  • the Vbb control section 9 controls the Vbb switches 81, 82, 83, the regulator 6 and the Vbb generator 7 to be in the normal operation state shown in FIG.
  • the CPU 105 included in the circuit block 1 After waiting for the time for the power supply of the circuit block 2 to stabilize from the back bias potential to the internal core power supply voltage, the CPU 105 included in the circuit block 1 sends the circuit to the clock control unit 3a included in the circuit block 3.
  • the control signal I Sb for starting the clock supply to the block 2 is output, and the operation of the circuit block 2 is restarted.
  • the Vbb controller 9 When transitioning from the power save 2 mode to the power off mode (204), the Vbb controller 9 receives the control signal from the CPU 105 included in the circuit block 1 and the Vbb controller 9 controls the Vbb switches 81, 82, 83, and the regulator. 6. Control the Vbb generator 7 to be in the power-off state shown in FIG. When transitioning from power save 2 mode to power save 1 mode (2
  • the CPU 105 included in the circuit program 1 outputs a control signal 1 Sd for transition to the power save 1 mode to the second evening generation circuit 119 included in the circuit program 3. At this time, the CPU 105 sets the wake-up timing for the next reception in the intermittent reception operation in the second timing generation circuit 119.
  • the second timing generation circuit 119 After receiving the control signal 1 Sd for transitioning to the power save 1 mode from the CPU 105, the second timing generation circuit 119 enters the circuit block 1 by the clock control unit 3a when a preset period elapses. Then, the signal T CXO ON for instructing the T CX 114 to stop power supply is output to the TCXO 114 and the Vbb control unit 9 via the external terminal 15.
  • the Vb b control unit 9 Upon receiving a signal T CXO ON from the second timing generation circuit 119 to instruct power supply to the T CXO 114, the Vb b control unit 9 sets the V b b switches 81, 82, 83, The Vbb generator 7 is controlled so as to be in the power save 1 state shown in FIG.
  • the second evening generating circuit 119 included in the circuit block 3 sends the wake-up detection signal to the wake-up detection unit 11 if the time coincides with the time set by the CPU 105 at the transition of 205, or ,
  • the second timing generation circuit 119 outputs a signal T ⁇ 00 instructing the start of operation to the TCXO 114 via the external terminal 15 to the TCXO 114 and the Vbb control unit 9.
  • the signal detected by the wake-up detector 1 1 is the keypad 1 in this case. This is an interrupt signal such as the press signal of 08.
  • the Vbb control unit 9 controls the Vbb switches 81, 82, 83, the regulator 6 and the Vbb generator 7 Control is performed so as to be in the state of power save 2 shown in FIG. 8, and transition to power save 2.
  • the period during which oscillation stabilizes or the period during which the supply power of the circuit block 1 stabilizes from the back bias potential to the internal core power supply voltage, whichever is longer, is set.
  • the second timing generation circuit 119 starts supplying the clock from the clock control unit 3a to the circuit block 1.
  • a gate means 11A is provided between the wake-up detection unit 11 and the circuit block 1 as shown in FIG. I have.
  • the interrupt signal input to the wake-up detection unit 11 is gated so as not to propagate to the circuit block 1, and the clock supply is restarted. Then, the interrupt signal is propagated to the circuit block 1.
  • an interrupt signal is input to the CPU 105 at the same time that the CPU 105 included in the circuit block 1 operates.
  • an interrupt signal is a negative logic signal, and when a control signal for controlling clock supply to the circuit block 1 is at a high level, the gate means 11A calculates the logical sum of the interrupt signal and the two inputs that receive the clock supply control signal to the circuit block 1. It can be configured with an OR gate.
  • a control signal may be directly input to the Vbb control unit 9 from an external terminal, A circuit for generating a leak test command is provided by using the terminals of, and a control signal is output to the Vbb control unit 9, and in response to this, the Vbb control unit 9 outputs the Vbb switches 81, 82, 83,.
  • the Vbb generator 7 is controlled so as to be in the state of the leak test shown in Fig. 8, and transit to the leak test.
  • FIG. 12 illustrates an operation timing chart of the above-mentioned state transition during intermittent reception by the mobile phone.
  • the mobile phone performs a reception operation, and the semiconductor integrated circuit 150 of the present invention enters the normal operation mode. After the reception processing is completed, the mode transits to the power save 2 mode.
  • the CPU 105 sets the timing for performing the next reception in the second evening generating circuit 119, and then transits to the power save 1 mode.
  • the semiconductor integrated circuit 150 according to the present invention transits to the power save mode 2, enters the normal operation mode, and receives the next reception burst. Thereafter, this operation is repeated.
  • FIG. 12 illustrates an operation timing chart of the above-mentioned state transition during intermittent reception by the mobile phone.
  • the semiconductor integrated circuit 150 in the present invention is in the power save 1 state as shown in FIG. In this state, if an interrupt signal is generated by pressing the keypad 108 or the like, the power save 2 mode is set as described in the above transition 207, and the CPU 105 operates to perform key operation processing. It becomes possible.
  • FIG. 14 shows the relationship between the clock supplied to each circuit block and the application of the substrate bias voltage (Vbb).
  • Vbb substrate bias voltage
  • FIG. 15 is a flowchart illustrating the operation procedure of FIGS. 12 and 13.
  • the CPU 105 included in the circuit block 1 instructs the clock control unit 3a to stop supplying the clock to the circuit block 2.
  • the clock control unit 3a stops supplying the clock to the circuit block 2 (302).
  • the CPU 105 sends a signal to the circuit
  • Vbb control unit 9 turns on the Vbb switch 82 and applies Vbb to the circuit program 2 (303). As a result, the semiconductor integrated circuit 150 transits to the power save 2 mode.
  • the CPU 105 calculates the next wake-up timing and sets it in the second timing generation circuit 119 (304).
  • the CPU 105 sets the clock supply stop to the circuit block 1 and the Vbb application instruction to the second timing generation circuit 119 (305) c
  • the second timing generation circuit 119 waits until a preset time elapses (306). During this period, the CPU 105 performs, for example, a process of issuing a sleep instruction so that the clock supply may be stopped. When the CPU 105 is configured by a complete stick circuit, the operation of the process 306 may be omitted. In short, if the latch circuit or the register circuit inside the CPU holds information in a dynamic format, it is necessary to complete the instruction execution and save the necessary information halfway so that the information is not lost. However, information is stored in the If the configuration is equipped with a latch circuit or a register, there is no problem even if the clock is stopped immediately to stop the operation.
  • the second timing generation circuit 119 outputs a control signal .TCX00 # for instructing the Vbb control unit 9 to apply Vbb to the circuit block 1.
  • the Vbb control section 9 turns on the Vbb switch 81 and applies Vbb to the circuit block 1.
  • the control signal T CX instructing the application of Vb b to the circuit block 1 output from the second evening generating circuit 119 is output.
  • TCXO 114 The operation of TCXO 114 also stops (308). As a result, the semiconductor chip transits to the power save 1 mode.
  • the semiconductor chip waits until an external interrupt signal is input or the next wake-up time set in the second timing generation circuit 119 is reached (309).
  • the wake-up detecting unit 11 When an interrupt signal is input in the process 309, the wake-up detecting unit 11 outputs the interrupt signal 11 S to the second evening generating unit 119.
  • the second timing generation circuit 119 outputs a control signal TCXOON for canceling the application of Vbb to the Vbb control unit 9.
  • the power of the TCX01 14 is turned on by the control signal TCXOON, and the TCXO 114 starts oscillating.
  • the Vbb control unit 9 turns off the Vbb switch 81 in response to the control signal TCXOON from the second timing generation circuit 119, and the application of Vbb to the circuit work 1 is released.
  • the wake-up time set in the second evening timing generation circuit 119 was reached. Also in this case, the second timing generation circuit 119 outputs a control signal TCXOON for canceling the application of Vbb to the Vbb control unit 9.
  • the control signal TCX0 ON turns on the power of TCX0114, and the TCXO114 starts oscillating.
  • the Vbb control unit 9 turns off the Vbb switch 81 in response to the control signal TCXOON from the second timing generation circuit 119, and the application of Vbb to the circuit process 1 is released (310).
  • the second timing generation circuit waits until a preset time elapses (311).
  • the time set at this time is longer than the longer of the TCXO 114 oscillation stabilization time and the time until the voltage supplied to the circuit block 1 stabilizes from the back bias voltage to the internal core power supply voltage. .
  • the second timing generation circuit 119 instructs the clock control unit 3a to start supplying a clock to the circuit procedure 1.
  • the clock control unit 3a starts supplying a clock to the circuit block 1 according to the control signal from the second timing generation circuit 119 (312). This causes a transition to the power save 2 mode.
  • the CPU 105 determines whether the cause of the transition from the processing 309 to the processing 310 is due to the interruption or the next wake-up time (313) o
  • the CPU 105 instructs the Vbb control unit 9 to cancel the application of Vbb to the circuit procedure 2.
  • the Vbb control unit 9 turns off the Vbb switch 82 in response to an instruction from the CPU 105 and cancels the application of Vbb to the circuit block 2 (315) o
  • the CPU 105 waits until a preset time elapses (316). During this time, the voltage supplied to circuit block 2 is Set it to be longer than the time required for the internal voltage to stabilize from the negative voltage.
  • the CPU 105 instructs the clock control unit 3a to restart the supply of the clock to the circuit block 2.
  • the clock control unit 3a starts clock supply to the circuit block 2 according to an instruction from the CPU 105 (317).
  • the semiconductor chip starts the reception process (318). If it is determined in the determination process 313 that this is due to an interrupt, the CPU 105 performs an interrupt process (314).
  • the second timing generation circuit 119 When the next wake-up time set in 1 19 has come, the second timing generation circuit 119 outputs an interrupt signal to the CPU 105, and performs the processing from 315 to 318 to perform the reception processing. be able to.
  • the CPU 105 that performs protocol processing and Man-Machine-In-Interface (MMI) processing is used as the baseband section, and the TDMA-type timing is generated using a clock source such as TC XO.
  • Timing generation circuit 115 and first circuit program 1 having peripheral logic associated therewith, DSP for performing part of channel codec processing and voice codec processing, and second circuit having peripheral logic associated therewith
  • Block 2 and a third circuit block 3 including an intermittent reception timing generation circuit that performs frame synchronization using the clock source of the clock crystal oscillator when reception is not performed during intermittent reception are mounted on the same semiconductor chip.
  • the semiconductor integrated circuit 150 is adopted.
  • circuit blocks 1 to 3 need to be operated during a call or during intermittent reception operation, all circuit blocks are operated, but no intermittent reception operation is performed. Clock supply to the first and second circuit blocks 1 and 2 By stopping the operation and applying a back bias, the leakage current can be reduced and the power consumption can be reduced. During periods when intermittent reception is not performed and reception is not being performed, the clock supply is stopped only in the second circuit block 2 and the back bias is applied to reduce unnecessary leakage current when key operation of the mobile phone is performed. Can be achieved.
  • the above-mentioned circuit blocks 1 to 3 are placed in the area that operates with the core power supply of about 1.5 V, and the RTC section 18 and the wake-up event detection section 11 are provided in the IZO area of the semiconductor integrated circuit that operates with the power supply of about 3 V.
  • the power switch of the telephone is off, the power supply to the circuit blocks 1 to 3 that operate on the core power supply and the operation of the Vbb generator 7 are stopped, and the core operates by operating only the area that operates with a power supply of about 3 V.
  • the leakage current of the power supply section can be reduced, and the power consumption can be further reduced.
  • FIG. 16 shows a second example of the semiconductor integrated circuit according to the present invention. Circuit blocks having the same functions as those in FIG. 1 are denoted by the same reference numerals.
  • a PLL circuit 1a for accelerating the operation clock is included in the CPU 105 included in the circuit block 1.
  • the Vbb switch of the circuit block 1 is divided into a Vbb switch 81a for the PLL circuit 1a and a Vbb switch 81b for another logic circuit.
  • noise from other logic circuits can be prevented from being supplied to the power supply supplied to the PLL circuit 1a, and the oscillation of the PLL circuit 1a can be stabilized.
  • Fig. 17 shows an example in which PLL circuits are mounted on the first and second circuit blocks 1 and 2 and Vbb switches are separated.
  • the circuit block 1 is roughly classified into a PLL circuit 1P having a MOS transistor circuit composed of a MOS transistor Qt and a logic circuit 1L having a MOS transistor circuit composed of an M ⁇ S transistor Qt.
  • MOS Transis Vbb switches (first switches) 81a and 81b for supplying the substrate bias voltage to the substrate gate of the circuit, and a Vss switch (for supplying the source voltage to the substrate gate of the MOS transistor circuit)
  • the second switch) 1 Ps and 1 Ls are separately provided in the PLL circuit and the mouthpiece circuit.
  • the circuit block 2 is roughly divided into a PLL circuit 2P having a MOS transistor circuit and a logic circuit 2L having a MOS transistor circuit.
  • Vbb switches (first switches) 82a and 82b for supplying a substrate bias voltage to the substrate gate of the MOS transistor circuit
  • V ss switches for supplying the source voltage to the substrate gate of the MOS transistor circuit.
  • the switches (second switches) 2Ps and 2Ls are separately provided in the PLL circuit and the logic circuit.
  • the V bb control unit 9 as a control circuit turns off the first switches 81 a and 81 b when operating the PLL circuit 1 P circuit and the logic circuit 1 L to which operating power is supplied,
  • the switches IP s, l Ls are turned on, and when their operations are stopped, the first switches 81 a, 81 b are turned on, and the second switches 1 Ps, 1 Ls are turned off.
  • the substrate gate of the MOS transistor for the PLL circuit and the substrate gate of the MOS transistor for the logic circuit are not directly connected, and at least the switches 81a and 81b or the switches IPs and 1LS intervene. This makes it difficult for the noise generated on the logic circuit 1L side to be transmitted to the PLL circuit 1P via the substrate gate, thereby reducing malfunction due to clock disturbance.
  • the respective operating power supply wirings may be separated between the PLL circuit and the logic circuit.
  • FIG. 18 shows a third example of the semiconductor integrated circuit according to the present invention. Circuit blocks having the same functions as those in FIG. 1 are denoted by the same reference numerals.
  • the regulator 6 configured on the semiconductor chip is deleted, an external regulator 6 e is provided, and the regulator 6 from the Vbb control unit 9 is provided.
  • the control signal is output to an external terminal, and this signal is used to operate the external regulator 6 e.
  • the same effect as the semiconductor integrated circuit according to the first example can be obtained by making the configuration of the external regulation 6e the same as the configuration shown in FIG. However, when the external regulator 6e is used, the terminal a of the switch 6b for setting the output of the regulator to high impedance as described in FIG. 7 may not be provided.
  • FIG. 19 shows a fourth example of the semiconductor integrated circuit according to the present invention. Circuit blocks having the same functions as those in FIG. 1 are denoted by the same reference numerals.
  • the V bb generator 7 configured on the semiconductor chip in the first embodiment is deleted, and an external V bb generator 7 e is provided.
  • the V bb generator control signal from 9 is output to an external terminal, and the external V bb generator 7e is operated using this signal.
  • the internal core power supply area was divided into three circuit blocks, but two circuit blocks or four or more circuit blocks were used. Even if it is divided into blocks, a V bb switch is provided in each circuit block, and a circuit block including the CPU 105 and a circuit block including the second timing generating circuit 119 and the clock control unit 3a are provided.
  • the V bb control unit 9 By controlling the V bb control unit 9 by the control signal of, the leakage current is reduced by applying the pack bias voltage to the operation unnecessary circuit block in the same manner, and the power supply to the semiconductor chip is turned off.
  • a similar effect can be obtained by turning off the power supply of the power supply, applying 0 V to the circuit block, and performing an operation of turning off the power supply for Vbb. .
  • the circuit block 3 has been described as being configured in the internal core power supply area 4, but even if the circuit block 3 is configured in the I / O power supply area 5, the same operation is performed, and the same operation is performed. The effect is obtained.
  • the control signal for controlling the Vbb switch 83 and the (1) 13 switch 83 from the (10 control unit 9) can be omitted.
  • the circuit block 3 is configured in the internal core power region 4, the chip occupied area is smaller than when the circuit block 3 is configured in the 10 power region 5. This is possible because the transistor size of the internal core power region 4 is smaller.
  • Regula Yule 6 has the normal V dd output mode and low V, which is lower than the normal V dd potential where circuit block 3 can operate normally at 32, 768 kHz. Equipped with dd voltage output mode. Specifically, it can be realized by switching the reference voltage of the comparator for generating the constant voltage. With this configuration, normal operation, power saving 2 mode, normal operation is normal V dd voltage And outputs a low Vdd voltage in power save 1 mode. The low Vdd voltage is the minimum operating voltage at which the circuit block 3 operates normally without any trouble.
  • the switching of the output voltage of the regulator 6 is also performed by the power control signal T CXOON of the T CXO 114.
  • the Vdd output voltage OUT can be made variable. That is, the third circuit block 3 includes a first voltage setting circuit 61.0 that can be set from the CPU 105 and a second setting circuit 620 that can be set from the CPU 105.
  • the regulator 6 can output the set value of the first voltage setting circuit 610 or the second voltage setting circuit 620 as Vdd.
  • the initial value of the first voltage setting circuit 610 is a value that causes the regulator 6 to output Vdd at which the first to third circuit blocks 1, 2, and 3 can normally operate.
  • the CPU 105 sends a control signal 611 to the second voltage setting circuit 620 so as to set the output voltage in the power save 1 mode.
  • Output to This setting value is lower than Vdd in normal operation and power save 2 mode, and is the minimum operating voltage at which circuit block 3 operates normally in power save 1 mode.
  • Vdd set in the first voltage setting circuit 610 is output, and when the power control signal of TCXO 114 is off, the second The control signal 621 is output to the regulator section 6a so as to output the Vdd set in the voltage setting circuit 620 of FIG.
  • the operation current can be reduced by stopping the clock and the leakage current can be reduced by applying the substrate bias to each of the first arithmetic processing circuit and the second arithmetic processing circuit.
  • the first arithmetic processing circuit gives the instruction. It is easy to prevent the processing circuit from inputting / outputting signals to / from the second arithmetic processing circuit, and such a signal input / output undesirably changes the state of the second arithmetic processing circuit and causes a malfunction later. It is possible to prevent this from happening.
  • the operation of the arithmetic processing circuit is also stopped, and the operations of both arithmetic processing circuits are stopped. It is possible to prevent the state of the first arithmetic processing circuit from undesirably changing due to a desired signal input / output and causing a malfunction after the operation returns. Moreover, by performing the timer setting process when the first arithmetic processing circuit instructs the operation to stop, the processing procedure for returning the first and second arithmetic processing circuits to the operable state is also simplified.
  • a configuration for switching between application / stop of substrate bias can contribute to a reduction in noise to the PLL circuit. It is possible to realize a data processing system such as a mobile phone that can easily control the sequence of clock supply stop / start and circuit bias application / stop for a circuit block.
  • a mobile communication terminal device such as a mobile phone
  • both the CPU unit and the DSP unit operate, but a reception operation during intermittent reception is performed. If not, stop the clock supply to the CPU and DSP sections and apply a back bias to reduce the leakage current and reduce power consumption.Also, reception is performed during intermittent reception.
  • the key operation of the mobile phone is performed during a period when there is no operation, it is possible to reduce unnecessary leakage current by stopping the clock supply only to the DSP unit and applying "quick bias". Controls the operation stop of the built-in circuit block and the state transition of the application / stop of the board bias while guaranteeing the operation reliability or operation stability of the mobile communication terminal device Rukoto can be.
  • the present invention can be used for low power consumption control, microprocessor control, and substrate bias control of semiconductor integrated circuits and data processing systems, and is widely applied to mobile communication terminals such as mobile phones and PHS. You can do it.

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Abstract

L'invention concerne des circuits de commande (3,9, 11) effectuant une réduction de courant de fonctionnement par arrêt d'horloge et réduction de fuite de courant par application respective d'une polarisation d'un substrat d'un premier circuit de traitement arithmétique (1) tel qu'une UC, et d'un second circuit de traitement arithmétique (2) tel qu'un DSP. Du fait que le premier circuit de traitement arithmétique émet une instruction de décalage à partir des états de fonctionnement des premier et second circuits de traitement arithmétique pour arrêter le fonctionnement du second circuit de traitement arithmétique, il est facile au premier circuit de traitement arithmétique d'empêcher, après émission de ladite instruction, la réception d'un signal et sa transmission par le second circuit de traitement arithmétique. Il est, toutefois, possible de prévenir un mauvais fonctionnement dudit second circuit de traitement arithmétique qui pourrait se produire par réception d'un signal et sa transmission. Même en cas d'arrêt des opérations des deux circuits de traitements arithmétiques par arrêt du premier circuit de traitement arithmétique en plus du second, et dans le cas où cet arrêt s'effectue en fonction d'une instruction émise par le premier circuit de traitement arithmétique, il est alors possible d'empêcher un mauvais fonctionnement du premier circuit de traitement arithmétique qui pourrait se produire du fait d'une réception de signal et d'une transmission non désirées. En conséquence, la polarisation du substrat et l'arrêt de fonctionnement peuvent être commandés de manière optimale par rapport aux blocs de circuit intégrés en fonction de l'état des blocs de circuit sans crainte de mauvais fonctionnements.
PCT/JP2001/010007 2001-02-15 2001-11-16 Circuit integre a semi-conducteurs, systeme de traitement de donnees et appareil de terminal mobile de communication WO2002065642A1 (fr)

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JP2006172264A (ja) * 2004-12-17 2006-06-29 Matsushita Electric Ind Co Ltd 半導体集積回路装置および信号処理システム
WO2008001461A1 (fr) * 2006-06-30 2008-01-03 Fujitsu Limited Circuit intégré à semi-conducteurs
JP2009060690A (ja) * 2007-08-30 2009-03-19 Denso Corp 電源制御装置
JP2016506546A (ja) * 2012-08-28 2016-03-03 ネットコム、ワイヤレス、リミテッドＮｅｔｃｏｍｍ Ｗｉｒｅｌｅｓｓｌｉｍｉｔｅｄ モバイル通信コンピューティングのための装置および方法
JP2018137429A (ja) * 2016-12-27 2018-08-30 ジーエヌ ヒアリング エー／エスＧＮ Ｈｅａｒｉｎｇ Ａ／Ｓ １つ以上の論理回路領域の調節可能なバックバイアス特性を有する集積回路

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JPH10190444A (ja) * 1996-12-27 1998-07-21 Hitachi Ltd 半導体集積回路装置
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JPH0983335A (ja) * 1995-05-19 1997-03-28 Hyundai Electron Ind Co Ltd 待機状態の電力消耗を減少させるための半導体装置
JPH10190444A (ja) * 1996-12-27 1998-07-21 Hitachi Ltd 半導体集積回路装置
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Publication number Priority date Publication date Assignee Title
JP2006172264A (ja) * 2004-12-17 2006-06-29 Matsushita Electric Ind Co Ltd 半導体集積回路装置および信号処理システム
WO2008001461A1 (fr) * 2006-06-30 2008-01-03 Fujitsu Limited Circuit intégré à semi-conducteurs
JPWO2008001461A1 (ja) * 2006-06-30 2009-11-26 富士通株式会社 半導体集積回路
JP4551474B2 (ja) * 2006-06-30 2010-09-29 富士通株式会社 半導体集積回路
JP2009060690A (ja) * 2007-08-30 2009-03-19 Denso Corp 電源制御装置
JP2016506546A (ja) * 2012-08-28 2016-03-03 ネットコム、ワイヤレス、リミテッドＮｅｔｃｏｍｍ Ｗｉｒｅｌｅｓｓｌｉｍｉｔｅｄ モバイル通信コンピューティングのための装置および方法
JP2018137429A (ja) * 2016-12-27 2018-08-30 ジーエヌ ヒアリング エー／エスＧＮ Ｈｅａｒｉｎｇ Ａ／Ｓ １つ以上の論理回路領域の調節可能なバックバイアス特性を有する集積回路

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