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WO1998036450A1 - Semiconductor device and method for manufacturing and mounting thereof, and circuit board mounted with the semiconductor device - Google Patents

Semiconductor device and method for manufacturing and mounting thereof, and circuit board mounted with the semiconductor device Download PDF

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Publication number
WO1998036450A1
WO1998036450A1 PCT/JP1998/000338 JP9800338W WO9836450A1 WO 1998036450 A1 WO1998036450 A1 WO 1998036450A1 JP 9800338 W JP9800338 W JP 9800338W WO 9836450 A1 WO9836450 A1 WO 9836450A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulating film
wiring pattern
semiconductor device
holding plate
thermal expansion
Prior art date
Application number
PCT/JP1998/000338
Other languages
French (fr)
Japanese (ja)
Inventor
Nobuaki Hashimoto
Original Assignee
Seiko Epson Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corporation filed Critical Seiko Epson Corporation
Priority to US09/155,985 priority Critical patent/US6249046B1/en
Priority to JP53555498A priority patent/JP3586867B2/en
Priority to AU56782/98A priority patent/AU5678298A/en
Publication of WO1998036450A1 publication Critical patent/WO1998036450A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09909—Special local insulating pattern, e.g. as dam around component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a surface-mount type semiconductor device, a method of manufacturing the same, a method of mounting the same, and a circuit board on which the same is mounted.
  • BGA ba11 grid array
  • BGA packages are classified into several types depending on the base material of the substrate.In particular, there is a need to mount semiconductor elements with narrow pitch pads, and continuity can be achieved by manufacturing in the form of tape in manufacturing.
  • BGA package using a flexible tape that uses a flexible (flexible) substrate as the substrate of the substrate due to the demand for manufacturing efficiency.
  • bumps which are external terminals, are arranged in an array on a flexible substrate so that they can be surface-mounted.
  • the wiring pattern that connects the chip electrodes to the bumps is formed exposed on the flexible substrate, and when mounted on a circuit board, care must be taken not to degrade the quality of the wiring pattern. It needed to be handled.
  • connection state of the bump and the pad of the circuit board not only cannot the connection state of the bump and the pad of the circuit board be confirmed and inspected, but also the connection cannot be repaired even if there is a connection failure, so that high precision mounting is required.
  • the flexible substrate used for the BGA package may be warped due to its flexibility, making it difficult to mount.
  • the conventional BGA package has various problems during mounting.
  • An object of the present invention is to solve this problem, and an object of the present invention is to provide a surface-mount type semiconductor device which enables easy mounting, a method of manufacturing the same, a method of mounting the same, and a circuit board on which the same is mounted. It is in. Disclosure of the invention
  • a semiconductor device includes: a semiconductor element
  • An external terminal provided on the other surface side of the insulating film and electrically connected to the wiring pattern via the through hole;
  • a holding plate made of a member having conductivity and maintaining flatness, provided on the opposite side of the surface of the wiring pattern on which the insulating film is provided, so as to cover at least a part of the wiring pattern.
  • the holding plate is attached to the insulating film via an insulating adhesive, and is connected to a constant potential portion of the wiring pattern.
  • the wiring pattern forming surface side and the bump forming surface side are different from each other with the insulating film as a boundary, there is no obstacle other than the wiring pattern on the wiring pattern forming surface side. Therefore, since the holding plate can be used as it is without special processing (patterning) to cover the wiring pattern, the manufacturing operation becomes extremely easy.
  • the insulating plate is not only capable of protecting the surface of the wiring pattern but also having sufficient strength to maintain flatness and covering the insulating film, the flexible insulating film is not distorted, and the planar stability of the bump is improved. The yield of mounting on a circuit board is improved.
  • the holding plate has conductivity and is connected to a constant potential portion of the wiring pattern.
  • the constant potential portion is a portion having a potential that does not change during operation of the semiconductor device. Minutes.
  • a short circuit between the conductive holding plate and the wiring pattern can be prevented by the insulating adhesive.
  • the holding plate has a constant potential
  • a signal is transmitted to the wiring pattern along the planar constant potential formed by the holding plate, so that an ideal transmission path is formed, and the impedance, particularly the inductance, is reduced. Small transmission is possible. Then, the delay and dullness of the high-frequency signal are reduced, the transmission characteristics are improved, and a highly reliable semiconductor device can be obtained.
  • a protective layer covering the wiring pattern may exist between the holding plate and the wiring pattern.
  • a protective layer such as a resist is provided in advance on the entire surface of the wiring pattern on the side where the insulating film is not provided and on which the holding plate is to be attached, and the holding plate is further attached thereon with an adhesive. May be attached. Also in this case, since a protective layer is provided on the surface opposite to the surface on which the external terminals are formed in the wiring pattern, it is easy to apply a resist or the like. In addition, when the holding plate is provided, since the wiring pattern is protected in advance by the protective layer, there is no occurrence of a defect in the wiring pattern such as disconnection.
  • the constant potential section may be one of a power supply potential and a ground potential.
  • the wiring pattern may have a curved portion at least in part, and the curved portion may be connected to the holding plate.
  • the holding plate may be connected to a fixed potential portion of the wiring pattern by at least one of a solder and a conductive adhesive.
  • a semiconductor device includes a semiconductor element, an insulating film, a wiring pattern formed on the insulating film and connected to the semiconductor element, and an external terminal formed on the wiring pattern.
  • a holding plate made of a member having conductivity and maintaining flatness, and holding a part of the insulating film;
  • the holding plate is connected to a constant potential portion of the wiring pattern.
  • the provision of the holding plate allows the flexible insulating film to be warped. Can be prevented, and reliable mounting becomes possible.
  • the holding plate has conductivity and is connected to a constant potential portion of the wiring pattern.
  • the constant potential portion is a portion having a potential which does not change during operation of the semiconductor device.
  • the holding plate has a constant potential
  • a signal is transmitted to the wiring pattern along the planar constant potential formed by the holding plate, so that it becomes an ideal transmission path, and the impedance is particularly high. Transmission with small inductance becomes possible. Then, the delay and dullness of the high-frequency signal are reduced, the transmission characteristics are improved, and a highly reliable semiconductor device can be obtained.
  • the holding plate a member having a thermal expansion coefficient larger than that of the insulating film may be used.
  • the holding plate may have a slit or a groove, and an end of the insulating film may be inserted into the slit or the groove and held by the holding plate.
  • the insulating film may have a slit, and the holding plate may be attached to an opposite side of the insulating film via the slit so that an end protrudes.
  • a method for manufacturing a semiconductor device includes the steps of: forming a through hole in an insulating film;
  • the bumps protrude from the side opposite to the wiring pattern, and the holding plate covers the wiring pattern.
  • the holding plate has the same potential as a part of the wiring pattern, and the holding plate is planar, so that electrical connection with low impedance is possible.
  • the holding plate may be attached to the insulating film via an insulating adhesive.
  • the insulating film has an opening corresponding to the wiring pattern
  • a part of the wiring pattern may be bent and connected to the holding plate by pushing a pressing jig from the other surface of the insulating film through the opening.
  • a step of forming a wiring pattern on an insulating film a step of connecting a semiconductor element to the wiring pattern and providing the semiconductor element on the insulating film, and holding an end of the insulating film Attaching a holding plate, and electrically connecting a part of the wiring pattern to the holding plate.
  • the semiconductor device manufactured by this method warpage of the flexible insulating film can be prevented, and reliable mounting becomes possible. Further, since a part of the wiring pattern is electrically connected to the holding plate, a semiconductor device having a structure which is hardly affected by external noise can be obtained.
  • a circuit board according to the present invention includes: the semiconductor device described above; and a substrate on which a desired conductive pattern is formed.
  • the external terminal of the semiconductor device is connected to the conductive pattern.
  • the semiconductor device since the holding plate has a constant potential, the semiconductor device is arranged on a plane having a constant potential. As a result, the semiconductor device has a structure that is less susceptible to external noise, such as a coaxial cable.
  • a circuit board includes: a semiconductor element; an insulating film; a wiring pattern formed on the insulating film and connected to the semiconductor element; A semiconductor material comprising: a bump formed on the substrate; and a holding member made of a member having conductivity and maintaining planarity and electrically connected to the wiring pattern.
  • this circuit board at least the end of the insulating film is fixed, so that the warpage is prevented. Further, since the wiring pattern and the holding plate are electrically connected, a structure that is not easily affected by external noise can be obtained.
  • a mounting method of a semiconductor device includes: an insulating film on which solder bumps are formed; and a holding member made of a member having conductivity and maintaining planarity and electrically connected to the wiring pattern.
  • electrical connection by solder can be performed after the insulating film is fixed with an adhesive to eliminate the warpage of the insulating film. Also, since the wiring pattern and the holding plate are electrically connected, a structure that is less susceptible to external noise can be obtained.
  • FIG. 1 is a diagram illustrating a semiconductor device according to a first embodiment
  • FIG. 2 is a diagram illustrating a semiconductor device according to a second embodiment
  • FIGS. 3A and 3B are diagrams illustrating a third embodiment
  • FIG. 4 is a diagram showing a semiconductor device according to a modification of the fourth embodiment.
  • FIG. 4 is a diagram showing another modification of the fourth embodiment.
  • FIGS. 5A to 5C are diagrams showing the fifth embodiment and its modifications.
  • FIG. 6 is a diagram illustrating a semiconductor device according to an example
  • FIG. 6 is a diagram illustrating a semiconductor device according to a sixth embodiment
  • FIG. 7 is a diagram illustrating a semiconductor device according to a seventh embodiment
  • FIG. 9 is a diagram illustrating a semiconductor device according to an eighth embodiment.
  • FIG. 9 is a diagram illustrating a semiconductor device according to a ninth embodiment.
  • FIG. 10 is a diagram illustrating a semiconductor device according to the tenth embodiment.
  • FIG. 11 is a diagram showing a circuit board according to the first embodiment
  • FIG. FIG. 12B is a diagram showing a circuit board according to an embodiment.
  • FIG. 12B is a diagram showing a modification of the first embodiment.
  • FIG. 13 is a diagram showing a semiconductor device manufactured by applying the method according to the present invention.
  • FIG. 14 is a diagram illustrating a circuit board on which the device is mounted, and
  • FIG. 14 is a diagram illustrating an electronic apparatus including the circuit board on which the semiconductor device manufactured by applying the method according to the present invention is mounted.
  • FIG. 1 is a diagram illustrating a semiconductor device according to the first embodiment.
  • This semiconductor device 10 is one to which a BGA package is applied. That is, in the figure, a large number of bumps 14 are formed on the insulating film 12, and a wiring pattern 20 that connects the electrodes 18 of the semiconductor chip 16 and the bumps 14 is formed.
  • the insulating film 12 is obtained by punching a long film carrier, and uses TAB (Tape Automated Bonding) technology.
  • the insulating film 12 has a through hole 12a.
  • the through hole 12 a is formed on the wiring pattern 20 formed on one surface of the insulating film 12.
  • the bumps 14 are formed so as to protrude from the wiring pattern 20 to the other surface of the insulating film 12 via the through holes 12a. That is, the bumps 14 protrude from the surface opposite to the wiring pattern 20. By doing so, the wiring pattern 20 is not exposed on the side where the bumps 14 are formed.
  • the bump 14 is formed of, for example, solder and the upper portion is formed in a ball shape.
  • the bumps 14 may be integrally formed using solder to the inside of the through-hole 12a, or another conductive member may be provided at least in the through-hole 12a and the solder may be mounted thereon. Further, other than solder, for example, copper or the like may be used.
  • device holes 12b are formed in the insulating film 12, and the ends of the wiring patterns 20 project into the device holes 12b.
  • the device hole 12 b is used for connecting the wiring pattern 20 and the electrode 18 of the semiconductor chip 16. That is, the side of the insulating film 12 where the wiring pattern 20 is formed
  • the semiconductor chip 16 is arranged so that the electrode 18 is located on the surface and inside the device hole 12b, and the wiring pattern 20 and the electrode 18 are bonded.
  • connection region between the semiconductor chip 16 and the insulating film 12 is sealed by the epoxy resin 22.
  • a feature of the present embodiment is that a holding plate 24 is provided on the insulating film 12. Specifically, the holding plate 24 is attached onto the wiring pattern 20 via an insulating adhesive 26.
  • the holding plate 24 may be made of stainless steel, but is preferably made of highly conductive copper or a copper-based alloy.
  • the wiring pattern 20 is covered and protected by the insulating adhesive 26 and the holding plate 24.
  • the insulating adhesive 26 becomes a protective layer similar to the solder resist.
  • the insulating adhesive 26 may be formed as a thermosetting or thermoplastic film, and may be attached to the holding plate 24 in advance. Then, the holding plate 24 can be thermocompression-bonded to the surface of the insulating film 12 having the wiring pattern 20.
  • the holding plate 24 By providing the holding plate 24 in this way, the distortion and undulation of the insulating film 12 are eliminated, the height of the bumps 14 becomes constant, the planar stability is improved, and the mounting yield on the circuit board is reduced. improves.
  • the holding plate 24 may be provided with a resist on the wiring pattern 20 and then pasted thereon via an insulating adhesive. By doing so, it is possible to prevent the holding plate 24 from being stuck with the impurities remaining therein.
  • a projection 24a is formed on the holding plate 24, and the projection 24a is connected to a constant potential of the wiring pattern 20, for example, a GND potential or a power supply potential.
  • a GND potential or a power supply potential for example, a GND potential or a power supply potential.
  • the protrusion 24a is shown only at one position in the drawing, it may be provided at all portions of the wiring pattern 20 where the potential is constant.
  • the holding plate 24 has the same potential as the potential of the wiring pattern 20 connected via the projection 24a.
  • the wiring pattern 20 is formed on the holding plate 24 via the insulating adhesive 26. Is disposed above a planar constant potential.
  • the constant potential is the GND potential
  • a high-frequency signal can be transmitted to the wiring pattern 20 along the planar GND potential, so that an ideal transmission path like a coaxial cable is obtained. That is, the impedance pattern of the wiring pattern 20 can be controlled.
  • the impedance and inductance are caused by the adhesive and the resist layer (if provided), they can be controlled by changing the thickness. As a result, the transmission characteristics can be improved by reducing the delay and dullness of the high-frequency signal.
  • a wiring pattern 20 is formed on the surface of the insulating film 12 on the side of the holding plate 24 to reduce the distance between the two. By doing so, the distance between the wiring pattern 20 and the holding plate 24 is reduced.
  • the capacitance is C
  • the area of the wiring pattern 20 and the holding plate 24 facing each other is S
  • the distance between the wiring pattern 20 and the holding plate 24 is d
  • the dielectric constant in a vacuum is £.
  • the relative permittivity £
  • the portion of the wiring pattern 20 that becomes the power supply potential and the holding plate 24 may be connected by the projection 24a. Even in this case, since the power supply potential is constant, the influence on the signal transmitted to the wiring pattern 20 can be reduced.
  • B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element. This point is common to all embodiments described later.
  • the present embodiment is a back TAB type in which the semiconductor chip 16 is mounted on the same side of the insulating film 12 as the wiring pattern 20 forming surface, but the semiconductor chip 16 is provided on the opposite side of the wiring pattern 20 forming surface. Table with 16 mounted.
  • the semiconductor chip 16 since the back surface of the semiconductor chip 16 comes into contact with the circuit board, if the semiconductor chip 16 is connected to the circuit board via a heat conductive adhesive such as silver paste, the heat dissipation of the semiconductor chip 16 can be reduced. Can be raised.
  • a bump may be provided in the wiring pattern 20 without forming the through hole 12a in the insulating film 12, and a solder resist layer may be formed on the wiring pattern 20 side avoiding the bump.
  • FIG. 2 is a diagram illustrating a semiconductor device according to the second embodiment.
  • the semiconductor device 30 shown in FIG. 2 differs from the semiconductor device 10 shown in FIG. 1 in the structure of the electrical connection between the wiring pattern 32 and the holding plate 34. That is, in FIG. 2, the extended portion 32 a at the left end of the wiring pattern 32 is bent and connected to the holding plate 34.
  • As a connection method there is a method shown in a third embodiment described later.
  • the extension part 32 a is provided in a part of the wiring pattern 32 where the potential becomes the GND potential.
  • the extension 32a is shown only at one end in the figure, it may be provided at any part of the wiring pattern 32 that is at the GND potential. It may be provided at any position.
  • the holding plate 34 is made of copper or the like having high conductivity and good heat conductivity.
  • the holding plate 34 has the same potential as the potential of the wiring pattern 32 connected via the extension 32a, that is, the GND potential. Then, the wiring pattern 32 is disposed above the planar GND potential formed by the holding plate 34 via the insulating adhesive 36. Then, a high-frequency signal can be transmitted to the wiring pattern 32 along the planar GND potential, so that an ideal transmission path is obtained as in a coaxial cable. That is, the impedance inductance of the wiring pattern 32 can be controlled. Since the impedance and inductance are caused by the adhesive and the resist layer (if provided), they can be controlled by changing the thickness. As a result of the control, the transmission characteristics can be improved by reducing the delay and dullness of the high-frequency signal.
  • the part that becomes the power supply potential of the wiring pattern 32 may be connected to the extension plate 32a. Also in this case, since the power supply potential is constant, the influence on the signal transmitted to the wiring pattern 32 can be reduced.
  • FIG. 3A and FIG. 3B are views showing a modified example viewed from the joining means of the second embodiment.
  • a part of the wiring pattern 42 is bent to form a projection 42 a, and the projection 42 a is connected to the holding plate 44.
  • the protrusion 42 a is formed in a portion of the wiring pattern 42 where the potential becomes a constant potential such as a GND potential or a power supply potential.
  • the projection 42 a is formed by pressing the pressing jig 48 from the hole 46 a formed in the insulating film 46. That is, a hole 46 a is previously formed in the insulating film 46 corresponding to a portion of the wiring pattern 42 where the convex portion 42 a is to be formed, and the holding plate 44 4 is formed from the hole 46 a.
  • the wiring pattern 42 is pressed by the pressing jig 48 to form a projection 42 a and is joined to the holding plate 44.
  • the insulating adhesive 45 be removed from the region where the convex portion 42 a is to be formed. Further, when forming the projection 42 a, heat or ultrasonic vibration is applied from the pressing jig 48. Further, the wiring pattern 42 is plated with gold (A n). As the wiring pattern 42, a well-known tin plate or solder plate may be used other than the gold plating. On the other hand, if the metal plate is also provided on the holding plate 44, the joining between the projection 42 a and the holding plate 44 becomes easy.
  • a wiring pattern 52 and a holding plate 54 are connected by a conductive adhesive 56.
  • the insulating adhesive 55 is removed and a conductive adhesive 56 is provided corresponding to the portion of the wiring pattern 52 connected to the holding plate 54, and the holding plate 54 is insulated.
  • solder may be used instead of the conductive adhesive 56. In this case, when the holding plate 54 and the insulating film 58 are thermocompression-bonded, they are heated to the melting point of the solder. Need to be
  • B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element.
  • FIG. 4 is a diagram showing another modified example of the third embodiment, and is an example of the so-called “B-TAB type” mentioned above.
  • the wiring pattern 62 of the semiconductor device 60 shown in the figure includes a projection 62 for connecting to the electrode 64a of the semiconductor chip 64 and a projection 62 for connecting to the conductive holding plate 66. has b.
  • the semiconductor chip 64 is molded with a resin 65. By doing so, it is possible to connect the GND potential or the power supply potential in the wiring pattern 62 to the holding plate 66.
  • the projections 62b and the holding plate 66 are simultaneously connected when the holding plate 66 is attached to the insulating film 68 having the wiring pattern 62 by thermocompression bonding.
  • the other configuration is the same as that of the embodiment shown in FIG.
  • FIG. 5A to 5C are views showing a semiconductor device according to the fifth embodiment.
  • the semiconductor device 100 shown in FIG. 5A has an insulating film 104, a wiring pattern 106, a bump 108 and a semiconductor chip 109, and has an insulating film 104 and a wiring pattern 106.
  • the end is held by the holding plate 102.
  • the holding plate 102 is made of a highly conductive material.
  • the end of the insulating film 104 is held by inserting the end of the insulating film 104 into the groove 102 a formed in the holding plate 102.
  • the wiring pattern 106 is held by the holding plate 102 and is electrically connected. Note that the portion of the wiring pattern 106 connected to the holding plate 102 is the same as in the first embodiment, and the effect of the electrical connection is the same, so the description is omitted.
  • the holding plate 102 has the strength necessary to maintain the flatness, while the insulating film 104 has flexibility. Therefore, the end of the insulating film 104 is By holding the flexible insulating film 104, the flexible insulating film 104 can maintain flatness. Then, the warpage of the insulating film 104 can be suppressed, and the mounting can be performed reliably. Also,
  • the tension is applied to the insulating film 104 by the holding plate 102 so that the insulating film 104 is stretched in one step of the riff opening when the semiconductor device 100 is mounted on the circuit board.
  • flatness can be obtained, so that the bump 108 can be securely mounted on the circuit board.
  • B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element.
  • a space exists between the holding plate 102 and the insulating film 104, but the space may not exist.
  • FIG. 5B shows a modification of the fifth embodiment.
  • the semiconductor device 110 shown in the figure has a point that the insulating film 114 and the end of the wiring pattern 116 are inserted into the slit 112a formed on the holding plate 112. Different from the above semiconductor device 100 o
  • FIG. 5C also shows a modification of the fifth embodiment.
  • the semiconductor device 120 shown in the figure has the end of the insulating film 124 inserted into the slit 124 a formed on the insulating film 124 by inserting the end of the holding plate 122. Part is held. Specifically, the end of the holding plate 122 is inserted from one surface of the insulating film 124 through the slit 124a into the other surface by elastically deforming the end of the holding plate 122. The flatness of the insulating film 124 is maintained by the restoring force. Also, by doing so, the holding plate 122 and the wiring pattern 126 are electrically connected.
  • B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element.
  • the semiconductor device 70 shown in FIG. 6 differs from the above-described fourth embodiment in that the holding plate 72 and the insulating film 74 are entirely fixed by an adhesive 73.
  • the insulating film 74 is tensioned by the holding plate 72, and the insulating film 74 is stretched. Therefore, the solder balls 75 can be securely mounted on the circuit board.
  • the structure of the electrical connection between the wiring pattern 71 and the holding plate 72 is the same as the composition shown in FIG.
  • the end 78 a of the holding plate 78 is caulked in the direction shown by the arrow with respect to the ends of the insulating film 80 and the wiring pattern 81.
  • the holding plate 78 and the insulating film 80 are fixed, and the electrical connection between the wiring pattern 81 and the holding plate 78 is achieved.
  • the holding plate 78 can be stably mounted without using an adhesive in the mass production process.
  • the holding plate 84 has a projection 84 a such as a pin, a hole 86 a is formed in the insulating film 86, and a hole 87 a is formed in the wiring pattern 87. It is formed.
  • the holding plate 84 is attached to the insulating film 86 by fitting the projection 84a with the hole 86a and the hole 87a. Further, the diameter of the hole 87a is formed slightly smaller than that of the hole 86a, so that the electrical connection between the wiring pattern 87 and the holding plate 87 can be ensured.
  • the projection 84a may be formed by bending an end of the holding plate 84. Also in this case, the holding plate 84 can be stably mounted without using an adhesive in the mass production process.
  • the semiconductor device 90 shown in FIG. 9 is different from the semiconductor device 10 shown in FIG. Predder) 9 1 is attached. More specifically, an adhesive 92 is applied to the back surface of the semiconductor chip 16 (the surface opposite to the electrode 18) and the holding plate 24, and the heat dissipation plate 91 is adhered.
  • the adhesive 92 contains silver or the like and has high thermal conductivity and conductivity, and the heat sink 91 is also made of a material having high thermal conductivity and conductivity. By doing so, heat dissipation of the semiconductor chip 16 can be promoted by the heat sink 91, and the back surface of the semiconductor chip 16 can be connected to a constant potential. Then, malfunction of the semiconductor chip 16 is prevented, and reliability is improved.
  • the semiconductor device 94 shown in FIG. 10 has a holding plate 93 in which these are integrated instead of the holding plate 24 and the heat radiating plate 91 of the semiconductor device 90 shown in FIG. That is, the holding plate 93 includes a portion to be attached to the insulating film 12 and a semiconductor chip.
  • the part to be attached to the back of 16 has a shape that is bent so that it becomes more physical. Even when such a holding plate 93 is used, the same effect as in the above embodiment can be obtained.
  • FIG. 11 is a diagram illustrating a circuit board according to the eleventh embodiment.
  • a semiconductor device 132 is mounted on a circuit board 130 shown in FIG.
  • the semiconductor device 13 2 has an insulating film 13 4, a wiring pattern 13 6, a bump 13 8, and a semiconductor chip 13 9, and a circuit board 13 0 for bonding the bump 13 8.
  • a pad 130a is formed.
  • a holding plate 133 is attached to the insulating film 134.
  • the semiconductor device 132 is bonded to the circuit board 130 by an adhesive 128 provided at the end and the center of the insulating film 134. This bonding is performed one step before the lift opening. That is, the semiconductor device 132 is temporarily bonded to the circuit board 130 with an adhesive 128 to eliminate the warpage of the insulating film 134, and then the bump 133 and the pad 1 are removed. Join with 30a.
  • adhesive 128 it reacts at a temperature below the solder melting temperature. It is preferable that an adhesive 128 connects the semiconductor device 132 first and then the solder is melted using a corresponding material. In this way, so-called temporary fixing is performed.
  • the adhesive film 128 is used to eliminate the warpage of the insulating film 134, so that good mounting is possible.
  • a so-called B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element.
  • the present embodiment has the holding plate 133, flatness can be maintained even if the holding plate 133 is omitted.
  • FIG. 12A is a diagram showing a circuit board according to the 12th embodiment.
  • a semiconductor device 142 is mounted on a circuit board 140 shown in FIG.
  • the semiconductor substrate 144 is the same as the semiconductor device 10 shown in FIG. 1 except for the holding plate 144, and therefore the description is omitted.
  • the holding plate 144 is made of a highly conductive material such as copper-stainless steel or a copper-based alloy, and has a hole 144a through which the screw 144 passes. This screw 1 4 6 also has conductivity.
  • the circuit board 140 also has a hole 140a through which the conductive screw 144 passes. On one surface, a ring-shaped pad 1 is formed around the hole 140a. 4 8 are formed. The pad 148 is connected to a constant potential such as a GND potential or a power supply potential on the circuit board 140. Then, the holding plate 144 and the circuit board 140 are fixed by screws 144 and nuts 149 that pass through the respective holes 144a and 140a.
  • the planar holding plate 144 becomes a constant potential such as the GND potential or the power supply potential via the screw 144.
  • a signal can be transmitted along a planar constant potential, so that the transmission characteristics of a high-frequency signal are improved.
  • FIG. 12B is a diagram showing a modification of the 12th embodiment.
  • a pad 152 formed on a circuit board 150 and a holding plate 154 are connected by wires 156.
  • the pads 15 2 are connected to a constant potential. Therefore, the holding plate 154 also has a constant potential, and the transmission characteristics of high-frequency signals are improved.
  • the wires 156 are provided by soldering or by a normal wire bonding method, for example, ultrasonic waves. After that, the wire may be protected with a resin. Note that a so-called B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element.
  • FIG. 13 shows a circuit board 1000 on which a semiconductor device 110 to which the present invention is applied is mounted.
  • an organic substrate such as a glass epoxy substrate is used for the circuit board.
  • Wiring patterns made of, for example, copper are formed on the circuit board so as to form a desired circuit, and the electrical continuity is achieved by mechanically connecting the wiring patterns and the bumps of the semiconductor device.
  • the semiconductor device described above is provided with a structure that absorbs the strain caused by the difference in thermal expansion with the outside, the reliability at the time of connection and thereafter can be improved even if the semiconductor device is mounted on a circuit board. Can be improved.
  • the wiring of the semiconductor device is devised, the reliability at the time of connection and after the connection can be improved.
  • the mounting area can be reduced to the area mounted with bare chips. For this reason, if this circuit board is used for an electronic device, the size of the electronic device itself can be reduced. Also, within the same area, more mounting space can be secured, and higher functionality can be achieved.
  • FIG. 1 As an electronic apparatus including the circuit board 100, a notebook personal computer 1200 is shown in FIG.
  • the present invention can be applied to any electronic device for surface mounting that requires a large number of bumps, similarly to a semiconductor device, regardless of whether it is an active component or a passive component.
  • the electronic part P port P includes, for example, a resistor, a capacitor, a coil, an oscillator, a filter, a temperature sensor, a thermistor, a ballis, a volume or a fuse,

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Abstract

A surface-mounted type semiconductor device which can be easily mounted. The semiconductor device has a semiconductor element (16), an insulating film (12), a wiring pattern (20) which is formed on one face of the insulating film (12) and is connected to the semiconductor element (16), bumps (14) formed on a rear face of the wiring pattern (20) projected on the other face of the insulating film (12) via through holes (12a) in the insulating film (12), and a holding plate (24) which is so pasted on one face of the insulating film (12) as to cover the wiring pattern (20) to keep a flatness with a conductivity. The holding plate (24) is connected to a constant potential section of the wiring pattern (20).

Description

明細: 半導体装置、 その製造方法及びその実装方法並びにこれを実装した回路基板 技術分野  Description: Semiconductor device, method of manufacturing the same, method of mounting the same, and circuit board mounting the same
本発明は、 面実装型の半導体装置、 その製造方法及びその実装方法並びにこれ を実装した回路基板に関する。 背景技術  The present invention relates to a surface-mount type semiconductor device, a method of manufacturing the same, a method of mounting the same, and a circuit board on which the same is mounted. Background art
半導体装置の小型化を追求するとべァチップ実装が理想的であるが、 品質の保 証及び取り扱いが難しいため、 パッケージ形態に加工することで対応してきた。 そのパッケージ形態において、 特に多端子化の要求に応じて近年 B G A ( b a 11 grid array) 型パッケージがでてきている。 B G Aパッケージは基板の基材によ り数種類にわけられるが、 特に狭ピッチパッ ドの半導体素子を実装しなければな らないニーズや、 製造においてテープ状にして製造を行うことで連続性をもたせ ることが可能となるといつた製造効率上の要求からフレキシブル （可撓性） 基材 を基板の基材として用いたフレキシブルテープ利用型の B G Aパッケージが存在 する。 この B G Aパヅケージはフレキシブル基板に外部端子であるバンプをエリ ァアレイ状に配置し、 面実装できるようにしたものである。  In order to pursue miniaturization of semiconductor devices, bare chip mounting is ideal. However, since quality assurance and handling are difficult, we have responded by processing them into package forms. In the package form, a BGA (ba11 grid array) type package has recently emerged in response to a demand for multi-terminals. BGA packages are classified into several types depending on the base material of the substrate.In particular, there is a need to mount semiconductor elements with narrow pitch pads, and continuity can be achieved by manufacturing in the form of tape in manufacturing. When it becomes possible, there is a BGA package using a flexible tape that uses a flexible (flexible) substrate as the substrate of the substrate due to the demand for manufacturing efficiency. In this BGA package, bumps, which are external terminals, are arranged in an array on a flexible substrate so that they can be surface-mounted.
この B G Aパッケージによれば、 チヅプの電極からバンプまでを接続する配線 パターンが、 フレキシブル基板に露出して形成されており、 回路基板への実装時 に、 配線パターンの品質を劣化させないように慎重に取り扱うことが必要であつ た。  According to this BGA package, the wiring pattern that connects the chip electrodes to the bumps is formed exposed on the flexible substrate, and when mounted on a circuit board, care must be taken not to degrade the quality of the wiring pattern. It needed to be handled.
しかも、 B G Aパッケージによれば、 バンプと回路基板のパッ ドとの接続状態 の確認及び検査ができないのみならず、 接続不良があっても修復できないため、 実装に高精度が要求されていた。  In addition, according to the BGA package, not only cannot the connection state of the bump and the pad of the circuit board be confirmed and inspected, but also the connection cannot be repaired even if there is a connection failure, so that high precision mounting is required.
あるいは、 B G Aパッケージに使用されるフレキシブル基板は、 その柔軟性か ら、 反りが生じて実装しにくい場合があった。 このように、 従来の B G Aパヅケージは、 実装時に種々の問題を抱えるもので あった。 Alternatively, the flexible substrate used for the BGA package may be warped due to its flexibility, making it difficult to mount. As described above, the conventional BGA package has various problems during mounting.
本発明は、 この問題点を解決するものであり、 その目的は、 容易な実装を可能 にする面実装型の半導体装置、 その製造方法及びその実装方法並びにこれを実装 した回路基板を提供することにある。 発明の開示  An object of the present invention is to solve this problem, and an object of the present invention is to provide a surface-mount type semiconductor device which enables easy mounting, a method of manufacturing the same, a method of mounting the same, and a circuit board on which the same is mounted. It is in. Disclosure of the invention
本発明に係る半導体装置は、 半導体素子と、  A semiconductor device according to the present invention includes: a semiconductor element;
貫通孔を有する絶縁フィルムと、  An insulating film having a through hole,
前記絶縁フィルムの一方の面側において前記貫通孔上を通るように形成される とともに前記半導体素子に接続される配線パターンと、  A wiring pattern formed on one surface side of the insulating film so as to pass over the through hole and connected to the semiconductor element;
前記絶縁フィルムの他方の面側に設けられるとともに前記貫通孔を介して前記 配線パターンと電気的な接続がなされている外部端子と、  An external terminal provided on the other surface side of the insulating film and electrically connected to the wiring pattern via the through hole;
導電性を有するとともに平面性を保つ部材からなり、 前記配線パターンの前記 絶縁フィルムが設けられた面の反対面側に前記配線パターンの少なくとも一部を 覆うように設けられる保持板と、 を有し、  A holding plate made of a member having conductivity and maintaining flatness, provided on the opposite side of the surface of the wiring pattern on which the insulating film is provided, so as to cover at least a part of the wiring pattern. ,
前記保持板は、 絶縁性の接着剤を介して前記絶縁フィルムに貼り付けられると ともに、 前記配線パ夕一ンの一定電位部に接続されてなる。  The holding plate is attached to the insulating film via an insulating adhesive, and is connected to a constant potential portion of the wiring pattern.
この半導体装置は、 絶縁フィルムを境として配線パターン形成面側とバンプ形 成面側が異なるようになっていることから、 配線パターン形成面側には配線パ夕 ーン以外の障害物がない。 従って、 保持板は特殊加工 （パターニング） せずその まま用いられて配線パターンを覆うことができるので、 製造作業が極めて容易に なる。 また、 配線パターンの表面を保護できるだけでなく、 平面性を保てる強度 を有する保持板が絶縁フィルムを覆うので、 可撓性を有する絶縁フィルムは歪む ことがなくなり、 バンプの平面安定性が向上し、 回路基板への実装の歩留まりが 向上する。  In this semiconductor device, since the wiring pattern forming surface side and the bump forming surface side are different from each other with the insulating film as a boundary, there is no obstacle other than the wiring pattern on the wiring pattern forming surface side. Therefore, since the holding plate can be used as it is without special processing (patterning) to cover the wiring pattern, the manufacturing operation becomes extremely easy. In addition, since the insulating plate is not only capable of protecting the surface of the wiring pattern but also having sufficient strength to maintain flatness and covering the insulating film, the flexible insulating film is not distorted, and the planar stability of the bump is improved. The yield of mounting on a circuit board is improved.
また、 前記保持板は、 導電性を有し、 配線パターンの一定電位部と接続されて いる。 ここで、 一定電位部とは、 半導体装置の動作中に変化しない電位となる部 分である。 また、 絶縁性の接着剤によって、 導電性の保持板と配線パターンとの 短絡を防止できる。 Further, the holding plate has conductivity and is connected to a constant potential portion of the wiring pattern. Here, the constant potential portion is a portion having a potential that does not change during operation of the semiconductor device. Minutes. In addition, a short circuit between the conductive holding plate and the wiring pattern can be prevented by the insulating adhesive.
こうして、 保持板が一定の電位になると、 保持板にて形成される面状の一定電 位に沿って、 配線パターンに信号が伝送されるので、 理想的な伝送路となり、 ィ ンピーダンス特にインダクタンスの小さい伝送が可能となる。 そして、 高周波信 号の遅れやなまりを減少させて伝送特性を向上させ、 信頼性の高い半導体装置を 得ることができる。  In this way, when the holding plate has a constant potential, a signal is transmitted to the wiring pattern along the planar constant potential formed by the holding plate, so that an ideal transmission path is formed, and the impedance, particularly the inductance, is reduced. Small transmission is possible. Then, the delay and dullness of the high-frequency signal are reduced, the transmission characteristics are improved, and a highly reliable semiconductor device can be obtained.
前記保持板と前記配線パターンとの間に、 前記配線パ夕一ンを覆う保護層が存 在してもよい。  A protective layer covering the wiring pattern may exist between the holding plate and the wiring pattern.
つまり、 配線パターンの絶縁フィルムが設けられていない側の保持板が貼られ る位置の全面にはあらかじめレジスト等の保護層が設けられていて、 更にその上 に接着剤を介して保持板が貼り付けられても良い。 この場合も、 配線パターンに おける外部端子の形成面とは反対面側に保護層を設けるので、 レジストなどを塗 布することが簡単である。 また、 保持板を設ける際に、 保護層によって予め配線 パターンが保護されているので、 断線など配線パターンについての不良が生じな くなる。  That is, a protective layer such as a resist is provided in advance on the entire surface of the wiring pattern on the side where the insulating film is not provided and on which the holding plate is to be attached, and the holding plate is further attached thereon with an adhesive. May be attached. Also in this case, since a protective layer is provided on the surface opposite to the surface on which the external terminals are formed in the wiring pattern, it is easy to apply a resist or the like. In addition, when the holding plate is provided, since the wiring pattern is protected in advance by the protective layer, there is no occurrence of a defect in the wiring pattern such as disconnection.
一定電位部は、 電源電位及びグランド電位のいずれか一方であってもよい。 前記配線パターンは、 少なくとも一部に湾曲部を有し、 前記湾曲部が前記保持 板に接続されてもよい。  The constant potential section may be one of a power supply potential and a ground potential. The wiring pattern may have a curved portion at least in part, and the curved portion may be connected to the holding plate.
前記保持板は、 ハンダ及び導電性接着剤のうち少なくともいずれか一方によつ て、 前記配線パターンの一定電位部と接続されてもよい。  The holding plate may be connected to a fixed potential portion of the wiring pattern by at least one of a solder and a conductive adhesive.
これらによっても、 伝送特性を向上させられる。  These also improve the transmission characteristics.
本発明に係る半導体装置は、 半導体素子と、 絶縁フィルムと、 前記絶縁フィル ム上に形成されるとともに前記半導体素子に接続される配線パターンと、 前記配 線パターン上に形成される外部端子と、 導電性を有するとともに平面性を保つ部 材からなり前記絶縁フィルムの一部を保持する保持板と、 を有し、  A semiconductor device according to the present invention includes a semiconductor element, an insulating film, a wiring pattern formed on the insulating film and connected to the semiconductor element, and an external terminal formed on the wiring pattern. A holding plate made of a member having conductivity and maintaining flatness, and holding a part of the insulating film;
前記保持板は、 前記配線パターンの一定電位部に接続されてなる。  The holding plate is connected to a constant potential portion of the wiring pattern.
本発明によれば、 保持板を設けることで、 柔軟性を有する絶縁フィルムの反り を防止することができ、 確実な実装が可能になる。 According to the present invention, the provision of the holding plate allows the flexible insulating film to be warped. Can be prevented, and reliable mounting becomes possible.
また、 前記保持板は、 導電性を有し、 配線パターンの一定電位部と接続されて いる。 ここで、 一定電位部とは、 半導体装置の動作中に変化しない電位となる部 分である。  Further, the holding plate has conductivity and is connected to a constant potential portion of the wiring pattern. Here, the constant potential portion is a portion having a potential which does not change during operation of the semiconductor device.
こうして、 保持板が一定の電位になると、 保持板にて形成される面状の一定電 位に沿って、 配線パターンに信号が伝送されるので、 理想的な伝送路となり、 ィ ンピ一ダンス特にインダク夕ンスの小さい伝送が可能となる。 そして、 高周波信 号の遅れやなまりを減少させて伝送特性を向上させ、 信頼性の高い半導体装置を 得ることができる。  In this way, when the holding plate has a constant potential, a signal is transmitted to the wiring pattern along the planar constant potential formed by the holding plate, so that it becomes an ideal transmission path, and the impedance is particularly high. Transmission with small inductance becomes possible. Then, the delay and dullness of the high-frequency signal are reduced, the transmission characteristics are improved, and a highly reliable semiconductor device can be obtained.
前記保持板には、 前記絶縁フィルムの熱膨張係数よりも大きい熱膨張係数を有 する部材を用いてもよい。  As the holding plate, a member having a thermal expansion coefficient larger than that of the insulating film may be used.
上記半導体装置において、 前記保持板は、 スリ ッ ト又は溝を有し、 前記絶縁フ イルムの端部は、 前記スリッ ト又は溝に挿入されて前記保持板に保持されてもよ い。  In the above semiconductor device, the holding plate may have a slit or a groove, and an end of the insulating film may be inserted into the slit or the groove and held by the holding plate.
上記半導体装置において、 前記絶縁フィルムは、 スリ ッ トを有し、 前記保持板 は、 前記スリッ トを介して前記絶縁フィルムの反対側面に、 端部が突出するよう に取り付けられてもよい。  In the semiconductor device, the insulating film may have a slit, and the holding plate may be attached to an opposite side of the insulating film via the slit so that an end protrudes.
本発明に係る半導体装置の製造方法は、 絶縁フィルムに貫通孔を形成する工程 と、  A method for manufacturing a semiconductor device according to the present invention includes the steps of: forming a through hole in an insulating film;
前記絶縁フィルムの一方の面側に前記貫通孔上を通る配線パターンを形成する 工程と、  Forming a wiring pattern passing over the through hole on one surface side of the insulating film;
前記配線パターンにおける前記絶縁フィルム側の面に前記貫通孔を介して前記 絶縁フィルムの他方の面側に突出する外部端子を形成する工程と、  Forming an external terminal projecting on the other surface side of the insulating film through the through hole on a surface of the wiring pattern on the insulating film side;
半導体素子を前記配線パターンに接続して前記絶縁フィルムに設ける工程と、 前記配線パターンの前記絶縁フィルムが設けられた面の反対面側に、 前記配線 パターンの少なくとも一部を覆うように、 導電性を有するとともに平面性を保つ 部材からなる保持板を貼り付ける工程と、  A step of connecting a semiconductor element to the wiring pattern and providing the insulating film on the insulating film; and forming a conductive pattern on the side of the wiring pattern opposite to the surface on which the insulating film is provided, so as to cover at least a part of the wiring pattern. A step of attaching a holding plate made of a member having flatness and having
前記配線パターンの一部を前記保持板に接続する工程と、 を含む。 Connecting a part of the wiring pattern to the holding plate; including.
この方法により製造された半導体装置は、 配線パターンとは反対側からバンプ が突出し、 保持板が配線パターンを覆う。  In the semiconductor device manufactured by this method, the bumps protrude from the side opposite to the wiring pattern, and the holding plate covers the wiring pattern.
この方法により製造された半導体装置によれば、 保持板が、 配線パターンの一 部と同電位となり、 保持板が面状であるため、 インピーダンスの小さい電気的接 続が可能となる。  According to the semiconductor device manufactured by this method, the holding plate has the same potential as a part of the wiring pattern, and the holding plate is planar, so that electrical connection with low impedance is possible.
上記半導体装置の製造方法において、  In the method for manufacturing a semiconductor device,
前記保持板を、 絶縁性の接着剤を介して前記絶縁フィルムに貼り付けてもよい 上記半導体装置の製造方法において、  The holding plate may be attached to the insulating film via an insulating adhesive.
前記絶縁フィルムは、 前記配線パターンに対応する開口部を有し、  The insulating film has an opening corresponding to the wiring pattern,
前記絶縁フィルムの前記他方の面から前記開口部を介して加圧治具を押し入れ て、 前記配線パターンの一部を、 屈曲させて前記保持板に接続してもよい。 本発明に係る半導体装置の製造方法は、 絶縁フィルムに配線パターンを形成す る工程と、 半導体素子を前記配線パターンに接続して前記絶縁フィルムに設ける 工程と、 前記絶縁フィルムの端部を保持する保持板を取り付ける工程と、 前記配 線パターンの一部を前記保持板に電気的に接続する工程と、 を含む。  A part of the wiring pattern may be bent and connected to the holding plate by pushing a pressing jig from the other surface of the insulating film through the opening. In the method for manufacturing a semiconductor device according to the present invention, a step of forming a wiring pattern on an insulating film, a step of connecting a semiconductor element to the wiring pattern and providing the semiconductor element on the insulating film, and holding an end of the insulating film Attaching a holding plate, and electrically connecting a part of the wiring pattern to the holding plate.
この方法により製造された半導体装置によれば、 柔軟性を有する絶縁フィルム の反りを防止することができ、 確実な実装が可能になる。 また、 配線パターンの 一部が保持板に電気的に接続されているので、 外部のノイズの影響を受けにくい 構造の半導体装置を得ることができる。  According to the semiconductor device manufactured by this method, warpage of the flexible insulating film can be prevented, and reliable mounting becomes possible. Further, since a part of the wiring pattern is electrically connected to the holding plate, a semiconductor device having a structure which is hardly affected by external noise can be obtained.
本発明に係る回路基板は、 上記半導体装置と、 所望の導電パターンが形成され た基板と、 を有し、  A circuit board according to the present invention includes: the semiconductor device described above; and a substrate on which a desired conductive pattern is formed.
前記半導体装置の前記外部端子が前記導電パターンに接続されてなる。  The external terminal of the semiconductor device is connected to the conductive pattern.
本発明によれば、 保持板が一定電位となっているので、 半導体装置は一定電位 の平面上に配置されることになる。 このことによって、 半導体装置は、 同軸ケ一 ブルのように、 外部のノイズの影響を受けにくい構造となる。  According to the present invention, since the holding plate has a constant potential, the semiconductor device is arranged on a plane having a constant potential. As a result, the semiconductor device has a structure that is less susceptible to external noise, such as a coaxial cable.
本発明に係る回路基板は、 半導体素子と、 絶縁フィルムと、 前記絶縁フィルム に形成されて前記半導体素子に接続される配線パターンと、 前記配線パターン上 に形成されるバンプと、 導電性を有するとともに平面性を保つ部材からなり前記 配線パターンに電気的に接続される保持材と、 を含む半導体装置と、 A circuit board according to the present invention includes: a semiconductor element; an insulating film; a wiring pattern formed on the insulating film and connected to the semiconductor element; A semiconductor material comprising: a bump formed on the substrate; and a holding member made of a member having conductivity and maintaining planarity and electrically connected to the wiring pattern.
所望の導電パターンが形成され、 前記絶縁フィルムの少なくとも端部と接着剤 にて固定される基板と、  A substrate on which a desired conductive pattern is formed and which is fixed to at least an end portion of the insulating film with an adhesive;
を有する。  Having.
この回路基板によれば、 絶縁フィルムの少なくとも端部が固定されるので、 そ の反りが防止される。 また、 配線パターンと保持板とが電気的に接続されている ので、 外部のノイズの影響を受けにくい構造が得られる。  According to this circuit board, at least the end of the insulating film is fixed, so that the warpage is prevented. Further, since the wiring pattern and the holding plate are electrically connected, a structure that is not easily affected by external noise can be obtained.
本発明に係る半導体装置の実装方法は、 ハンダバンプが形成された絶縁フィル ムと、 導電性を有するとともに平面性を保つ部材からなり前記配線パターンに電 気的に接続される保持材と、 を有する半導体装置の実装方法において、  A mounting method of a semiconductor device according to the present invention includes: an insulating film on which solder bumps are formed; and a holding member made of a member having conductivity and maintaining planarity and electrically connected to the wiring pattern. In the method of mounting a semiconductor device,
前記絶縁フィルムの少なくとも端部に接着剤を塗布して回路基板に接着してか ら、 ハンダバンプを溶融させて前記回路基板のパッ ドに接続する方法である。 本発明によれば、 絶縁フィルムを接着剤で固定して絶縁フィルムの反りをなく してから、 ハンダによる電気的な接続を行うことができる。 また、 配線パターン と保持板とが電気的に接続されているので、 外部のノイズの影響を受けにくい構 造が得られる。 図面の簡単な説明  A method in which an adhesive is applied to at least an end portion of the insulating film and bonded to the circuit board, and then the solder bump is melted and connected to the pad of the circuit board. According to the present invention, electrical connection by solder can be performed after the insulating film is fixed with an adhesive to eliminate the warpage of the insulating film. Also, since the wiring pattern and the holding plate are electrically connected, a structure that is less susceptible to external noise can be obtained. BRIEF DESCRIPTION OF THE FIGURES
図 1は、 第 1実施形態に係る半導体装置を示す図であり、 図 2は、 第 2実施形 態に係る半導体装置を示す図であり、 図 3 A及び図 3 Bは、 第 3実施形態及びそ の変形例に係る半導体装置を示す図であり、 図 4は、 第 4実施形態の他の変形例 を示す図であり、 図 5 A〜図 5 Cは、 第 5実施形態及びその変形例に係る半導体 装置を示す図であり、 図 6は、 第 6実施形態に係る半導体装置を示す図であり、 図 7は、 第 7実施形態に係る半導体装置を示す図であり、 図 8は、 第 8実施形態 に係る半導体装置を示す図であり、 図 9は、 第 9実施形態に係る半導体装置を示 す図であり、 図 1 0は、 第 1 0実施形態に係る半導体装置を示す図であり、 図 1 1は、 第 1 1実施形態に係る回路基板を示す図であり、 図 1 2 Aは、 第 1 2実施 形態に係る回路基板を示す図であり、 図 1 2 Bは、 第 1 2実施形態の変形例を示 す図であり、 図 1 3は、 本発明に係る方法を適用して製造された半導体装置を実 装した回路基板を示す図であり、 図 1 4は、 本発明に係る方法を適用して製造さ れた半導体装置を実装した回路基板を備える電子機器を示す図である。 FIG. 1 is a diagram illustrating a semiconductor device according to a first embodiment, FIG. 2 is a diagram illustrating a semiconductor device according to a second embodiment, and FIGS. 3A and 3B are diagrams illustrating a third embodiment. FIG. 4 is a diagram showing a semiconductor device according to a modification of the fourth embodiment. FIG. 4 is a diagram showing another modification of the fourth embodiment. FIGS. 5A to 5C are diagrams showing the fifth embodiment and its modifications. FIG. 6 is a diagram illustrating a semiconductor device according to an example, FIG. 6 is a diagram illustrating a semiconductor device according to a sixth embodiment, FIG. 7 is a diagram illustrating a semiconductor device according to a seventh embodiment, and FIG. FIG. 9 is a diagram illustrating a semiconductor device according to an eighth embodiment. FIG. 9 is a diagram illustrating a semiconductor device according to a ninth embodiment. FIG. 10 is a diagram illustrating a semiconductor device according to the tenth embodiment. FIG. 11 is a diagram showing a circuit board according to the first embodiment, and FIG. FIG. 12B is a diagram showing a circuit board according to an embodiment. FIG. 12B is a diagram showing a modification of the first embodiment. FIG. 13 is a diagram showing a semiconductor device manufactured by applying the method according to the present invention. FIG. 14 is a diagram illustrating a circuit board on which the device is mounted, and FIG. 14 is a diagram illustrating an electronic apparatus including the circuit board on which the semiconductor device manufactured by applying the method according to the present invention is mounted.
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明の好適な実施の形態について図面を参照して説明する。  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
(第 1実施形態）  (First Embodiment)
図 1は、 第 1実施形態に係る半導体装置を示す図である。 この半導体装置 1 0 は、 B G Aパッケージを適用したものである。 すなわち、 同図において、 絶縁フ イルム 1 2に多数のバンプ 1 4が形成され、 半導体チップ 1 6の電極 1 8とバン プ 1 4とを接続する配線パターン 2 0が形成されている。  FIG. 1 is a diagram illustrating a semiconductor device according to the first embodiment. This semiconductor device 10 is one to which a BGA package is applied. That is, in the figure, a large number of bumps 14 are formed on the insulating film 12, and a wiring pattern 20 that connects the electrodes 18 of the semiconductor chip 16 and the bumps 14 is formed.
絶縁フイルム 1 2は、 長尺のフィルムキヤリァテ一プをパンチングして得られ るもので、 T A B (Tape Automated Bonding) 技術が適用されている。 この絶縁 フィルム 1 2には、 貫通孔 1 2 aが形成されている。 貫通孔 1 2 aは、 絶縁フィ ルム 1 2の一方の面に形成される配線パターン 2 0の上に形成される。 そして、 この貫通孔 1 2 aを介して、 バンプ 1 4は、 配線パターン 2 0から絶縁フィルム 1 2の他方の面に突出するように形成されている。 すなわち、 バンプ 1 4は、 配 線パターン 2 0とは反対側の面に突出する。 こうすることで、 バンプ 1 4が形成 される側には配線パターン 2 0が露出しない構成となる。 なお、 ノ ンプ 1 4は、 例えばハンダから形成されて上部はボール状に形成されている。 貫通孔 1 2 a内 までハンダを用いてバンプ 1 4として一体形成されてもよいし、 他の導電部材が 少なくとも貫通孔 1 2 a内に設けられその上部にハンダが搭載されても良い。 ま た、 ハンダ以外に例えば銅等であってもよい。  The insulating film 12 is obtained by punching a long film carrier, and uses TAB (Tape Automated Bonding) technology. The insulating film 12 has a through hole 12a. The through hole 12 a is formed on the wiring pattern 20 formed on one surface of the insulating film 12. The bumps 14 are formed so as to protrude from the wiring pattern 20 to the other surface of the insulating film 12 via the through holes 12a. That is, the bumps 14 protrude from the surface opposite to the wiring pattern 20. By doing so, the wiring pattern 20 is not exposed on the side where the bumps 14 are formed. The bump 14 is formed of, for example, solder and the upper portion is formed in a ball shape. The bumps 14 may be integrally formed using solder to the inside of the through-hole 12a, or another conductive member may be provided at least in the through-hole 12a and the solder may be mounted thereon. Further, other than solder, for example, copper or the like may be used.
また、 絶縁フィルム 1 2には、 デバイスホール 1 2 bが形成されており、 配線 パターン 2 0の端部がデバイスホール 1 2 bに突出する。 デバイスホール 1 2 b は、 配線パターン 2 0と半導体チップ 1 6の電極 1 8とを接続するために使用さ れる。 すなわち、 絶縁フィルム 1 2における配線パターン 2 0が形成される側の 面であって、 かつ、 デバイスホール 1 2 bの内側に電極 1 8が位置するように、 半導体チヅプ 1 6を配置して、 配線パターン 2 0と電極 1 8とをボンディングす る。 In addition, device holes 12b are formed in the insulating film 12, and the ends of the wiring patterns 20 project into the device holes 12b. The device hole 12 b is used for connecting the wiring pattern 20 and the electrode 18 of the semiconductor chip 16. That is, the side of the insulating film 12 where the wiring pattern 20 is formed The semiconductor chip 16 is arranged so that the electrode 18 is located on the surface and inside the device hole 12b, and the wiring pattern 20 and the electrode 18 are bonded.
そして、 半導体チヅプ 1 6と絶縁フィルム 1 2との接続領域が、 エポキシ樹脂 2 2のポヅティングによって封止される。  Then, the connection region between the semiconductor chip 16 and the insulating film 12 is sealed by the epoxy resin 22.
さらに、 本実施形態の特徴は、 絶縁フィルム 1 2に保持板 2 4が設けられるこ とにある。 詳しくは、 保持板 2 4は、 配線パターン 2 0の上に、 絶縁接着剤 2 6 を介して貼り付けられる。 保持板 2 4は、 ステンレス鋼でもよいが、 導電性の高 い銅や銅系合金等で形成されることが好ましい。  Further, a feature of the present embodiment is that a holding plate 24 is provided on the insulating film 12. Specifically, the holding plate 24 is attached onto the wiring pattern 20 via an insulating adhesive 26. The holding plate 24 may be made of stainless steel, but is preferably made of highly conductive copper or a copper-based alloy.
こうすることで、 配線パ夕一ン 2 0が、 絶縁接着剤 2 6及び保持板 2 4で覆わ れて保護される。 特に、 絶縁接着剤 2 6は、 ソルダレジストと同様な保護層とな る。  By doing so, the wiring pattern 20 is covered and protected by the insulating adhesive 26 and the holding plate 24. In particular, the insulating adhesive 26 becomes a protective layer similar to the solder resist.
絶縁接着剤 2 6は、 熱硬化性又は熱可塑性のフィルムとして形成し、 予め保持 板 2 4に貼り付けておいてもよい。 そして、 保持板 2 4を、 絶縁フィルム 1 2に おける配線パターン 2 0を有する面に熱圧着することができる。  The insulating adhesive 26 may be formed as a thermosetting or thermoplastic film, and may be attached to the holding plate 24 in advance. Then, the holding plate 24 can be thermocompression-bonded to the surface of the insulating film 12 having the wiring pattern 20.
こうして、 保持板 2 4を設けることで、 絶縁フィルム 1 2の歪み、 うねりがな くなり、 バンプ 1 4の高さが一定になって平面安定性が向上し、 回路基板への実 装歩留りが向上する。  By providing the holding plate 24 in this way, the distortion and undulation of the insulating film 12 are eliminated, the height of the bumps 14 becomes constant, the planar stability is improved, and the mounting yield on the circuit board is reduced. improves.
この保持板 2 4は、 レジストを配線パターン 2 0に設けてから、 その上に絶縁 接着剤を介して貼っても良い。 こうすることで、 不純物が入ったままで保持板 2 4を貼り付けるのを防止することができる。  The holding plate 24 may be provided with a resist on the wiring pattern 20 and then pasted thereon via an insulating adhesive. By doing so, it is possible to prevent the holding plate 24 from being stuck with the impurities remaining therein.
また、 保持板 2 4には突起 2 4 aが形成されており、 この突起 2 4 aは配線パ ターン 2 0の一定電位、 例えば G N D電位や電源電位の部分に接続されている。 なお、 突起 2 4 aは、 図において 1箇所にのみ示されているが、 配線パターン 2 0の一定電位となる全ての部分に設けてもよい。  Further, a projection 24a is formed on the holding plate 24, and the projection 24a is connected to a constant potential of the wiring pattern 20, for example, a GND potential or a power supply potential. Although the protrusion 24a is shown only at one position in the drawing, it may be provided at all portions of the wiring pattern 20 where the potential is constant.
この構成によれば、 保持板 2 4は、 突起 2 4 aを介して接続される配線パター ン 2 0の電位と同電位となる。  According to this configuration, the holding plate 24 has the same potential as the potential of the wiring pattern 20 connected via the projection 24a.
そして、 配線パターン 2 0は、 絶縁接着剤 2 6を介して、 保持板 2 4にて形成 される平面状の一定電位の上方に配置される。 特に、 一定電位が G N D電位であ れば、 平面状の G N D電位に沿って、 配線パターン 2 0に高周波信号を伝送する ことができるので、 同軸ケーブルのように、 理想的な伝送路となる。 つまり、 配 線パターン 2 0のィンピーダンスゃィンダク夕ンスをコントロ一ルできる。 Then, the wiring pattern 20 is formed on the holding plate 24 via the insulating adhesive 26. Is disposed above a planar constant potential. In particular, if the constant potential is the GND potential, a high-frequency signal can be transmitted to the wiring pattern 20 along the planar GND potential, so that an ideal transmission path like a coaxial cable is obtained. That is, the impedance pattern of the wiring pattern 20 can be controlled.
なお、 インピーダンスやインダクタンスは、 接着剤やレジスト層 （設ける場合） に起因するため、 これらの厚みを変更することでコントロールできる。 そして、 コントロールできる結果として、 高周波信号の遅れやなまりを減少させて伝送特 性を向上させることができる。  Since the impedance and inductance are caused by the adhesive and the resist layer (if provided), they can be controlled by changing the thickness. As a result, the transmission characteristics can be improved by reducing the delay and dullness of the high-frequency signal.
本実施形態では、 図 1に示すように、 絶縁フィルム 1 2における保持板 2 4側 の面に配線パターン 2 0を形成して、 両者の間隔を小さくしてある。 こうするこ とで、 配線パターン 2 0と保持板 2 4との間隔が小さくなる。 そして、 電気容量 を C、 配線パターン 2 0及び保持板 2 4の対向する面積を S、 配線パターン 2 0 と保持板 2 4との間隔を d、 真空での誘電率を £。 、 比誘電率を £とすると、 In the present embodiment, as shown in FIG. 1, a wiring pattern 20 is formed on the surface of the insulating film 12 on the side of the holding plate 24 to reduce the distance between the two. By doing so, the distance between the wiring pattern 20 and the holding plate 24 is reduced. The capacitance is C, the area of the wiring pattern 20 and the holding plate 24 facing each other is S, the distance between the wiring pattern 20 and the holding plate 24 is d, and the dielectric constant in a vacuum is £. , And the relative permittivity is £,
C = e ε。 S / d C = e ε. S / d
となることから分かるように、 間隔 dが小さくなると電気容量が大きくなつて、 理想的な伝送路が得られる。 As can be seen from the above, as the distance d decreases, the electric capacity increases and an ideal transmission path can be obtained.
G N D電位の代わりに、 配線パターン 2 0の電源電位となる部分と保持板 2 4 とを突起 2 4 aによって接続してもよい。 この場合でも、 電源電位が一定電位で あることから、 配線パターン 2 0に伝送される信号への影響を少なくすることが できる。  Instead of the GND potential, the portion of the wiring pattern 20 that becomes the power supply potential and the holding plate 24 may be connected by the projection 24a. Even in this case, since the power supply potential is constant, the influence on the signal transmitted to the wiring pattern 20 can be reduced.
なお、 半導体素子との接合には、 配線パターン側に突起が一体形成されたいわ ゆる B— T A B型のものを用いても良い。 この点は、 後述する全ての実施形態に おいて共通である。  Note that a so-called B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element. This point is common to all embodiments described later.
また、 本実施形態は、 半導体チップ 1 6が絶縁フィルム 1 2上の配線パターン 2 0形成面と同じ側に実装された裏 T A B型であるが、 配線パターン 2 0形成面 の反対側に半導体チップ 1 6を実装した表 T A B型としてもよい。 この場合には、 半導体チップ 1 6の裏面が、 回路基板と接触することになるので、 銀ペースト等 の熱伝導接着部材を介して回路基板に接続すれば、 半導体チップ 1 6の放熱性を 上げることができる。 または、 絶縁フィルム 1 2に貫通孔 1 2 aを形成せず、 配 線パターン 2 0にバンプを設け、 このバンプを避けて配線パターン 2 0側にソル ダレジスト層を形成してもよい。 これらの形成方法は、 以下の実施形態の全てに 共通である。 また、 半導体チップ 1 6の厚みにより、 絶縁フィルムと回路基板と の間に一定の高さが得られることで、 例えば隣り合うハンダバンプ間のショート 防止にもなる。 Further, the present embodiment is a back TAB type in which the semiconductor chip 16 is mounted on the same side of the insulating film 12 as the wiring pattern 20 forming surface, but the semiconductor chip 16 is provided on the opposite side of the wiring pattern 20 forming surface. Table with 16 mounted. In this case, since the back surface of the semiconductor chip 16 comes into contact with the circuit board, if the semiconductor chip 16 is connected to the circuit board via a heat conductive adhesive such as silver paste, the heat dissipation of the semiconductor chip 16 can be reduced. Can be raised. Alternatively, a bump may be provided in the wiring pattern 20 without forming the through hole 12a in the insulating film 12, and a solder resist layer may be formed on the wiring pattern 20 side avoiding the bump. These forming methods are common to all of the following embodiments. In addition, since a certain height is obtained between the insulating film and the circuit board by the thickness of the semiconductor chip 16, for example, a short circuit between adjacent solder bumps can be prevented.
(第 2実施形態）  (Second embodiment)
図 2は、 第 2実施形態に係る半導体装置を示す図である。 同図に示す半導体装 置 3 0は、 配線パターン 3 2と保持板 3 4との電気的な接続の構造において、 図 1に示す半導体装置 1 0と異なる。 すなわち、 図 2において、 配線パターン 3 2 の左端の延設部 3 2 aが、 屈曲して保持板 3 4に接続されている。 接続の方法と して、 後述する第 3実施形態に示されるものがある。 延設部 3 2 aは、 配線パ夕 ーン 3 2の G N D電位となる部分に設けられている。 なお、 延設部 3 2 aは、 図 において端部の 1箇所にのみ示されているが、 配線パターン 3 2の G N D電位と なる全ての部分に設けてもよく、 端部でなくともそれ以外のどの位置に設けても 良い。 また、 保持板 3 4は、 導電性が高くまた熱伝導性の良い銅などで構成され ている。  FIG. 2 is a diagram illustrating a semiconductor device according to the second embodiment. The semiconductor device 30 shown in FIG. 2 differs from the semiconductor device 10 shown in FIG. 1 in the structure of the electrical connection between the wiring pattern 32 and the holding plate 34. That is, in FIG. 2, the extended portion 32 a at the left end of the wiring pattern 32 is bent and connected to the holding plate 34. As a connection method, there is a method shown in a third embodiment described later. The extension part 32 a is provided in a part of the wiring pattern 32 where the potential becomes the GND potential. Although the extension 32a is shown only at one end in the figure, it may be provided at any part of the wiring pattern 32 that is at the GND potential. It may be provided at any position. The holding plate 34 is made of copper or the like having high conductivity and good heat conductivity.
この構成によれば、 保持板 3 4は、 延設部 3 2 aを介して接続される配線パ夕 ーン 3 2の電位と同電位すなわち G N D電位となる。 そして、 配線パターン 3 2 は、 絶縁接着剤 3 6を介して、 保持板 3 4にて形成される平面状の G N D電位の 上方に配置される。 そうすると、 平面状の G N D電位に沿って、 配線パターン 3 2に高周波信号を伝送することができるので、 同軸ケーブルのように、 理想的な 伝送路となる。 つまり、 配線パターン 3 2のインピーダンスゃィンダク夕ンスを コントロールできる。 なお、 インピーダンスやインダクタンスは、 接着剤やレジ スト層 （設ける場合） に起因するため、 これらの厚みを変更することでコント口 —ルできる。 そして、 コントロールできる結果として、 高周波信号の遅れやなま りを減少させて伝送特性を向上させることができる。  According to this configuration, the holding plate 34 has the same potential as the potential of the wiring pattern 32 connected via the extension 32a, that is, the GND potential. Then, the wiring pattern 32 is disposed above the planar GND potential formed by the holding plate 34 via the insulating adhesive 36. Then, a high-frequency signal can be transmitted to the wiring pattern 32 along the planar GND potential, so that an ideal transmission path is obtained as in a coaxial cable. That is, the impedance inductance of the wiring pattern 32 can be controlled. Since the impedance and inductance are caused by the adhesive and the resist layer (if provided), they can be controlled by changing the thickness. As a result of the control, the transmission characteristics can be improved by reducing the delay and dullness of the high-frequency signal.
あるいは、 G N D電位の代わりに、 配線パターン 3 2の電源電位となる部分と 保持板 3 4とを延設部 3 2 aによって接続してもよい。 この場合でも、 電源電位 が一定電位であることから、 配線パターン 3 2に伝送される信号への影響を少な くすることができる。 Or, instead of the GND potential, the part that becomes the power supply potential of the wiring pattern 32 The holding plate 34 may be connected to the extension plate 32a. Also in this case, since the power supply potential is constant, the influence on the signal transmitted to the wiring pattern 32 can be reduced.
(第 3実施形態）  (Third embodiment)
次に、 図 3 A及び図 3 Bは、 上記第 2実施形態の接合手段からみた変形例を示 す図である。  Next, FIG. 3A and FIG. 3B are views showing a modified example viewed from the joining means of the second embodiment.
図 3 Aに示す半導体装置 4 0は、 配線パターン 4 2の一部が屈曲して凸部 4 2 aを形成し、 この凸部 4 2 aが保持板 4 4に接続されるようになっている。 なお、 凸部 4 2 aは、 配線パターン 4 2のうち、 G N D電位又は電源電位等の一定電位 となる部分に形成される。 こうして、 保持板 4 4を一定電位にして、 上記第 2実 施形態と同様の効果を得ることができる。  In the semiconductor device 40 shown in FIG. 3A, a part of the wiring pattern 42 is bent to form a projection 42 a, and the projection 42 a is connected to the holding plate 44. I have. The protrusion 42 a is formed in a portion of the wiring pattern 42 where the potential becomes a constant potential such as a GND potential or a power supply potential. Thus, the same effect as in the second embodiment can be obtained by setting the holding plate 44 to a constant potential.
凸部 4 2 aは、 絶縁フィルム 4 6に形成された穴 4 6 aから加圧治具 4 8を押 圧して形成される。 すなわち、 配線パターン 4 2のうち凸部 4 2 aを形成する部 分に対応して、 予め、 絶縁フィルム 4 6に穴 4 6 aを形成しておき、 この穴 4 6 aから保持板 4 4に向けて、 配線パターン 4 2を加圧治具 4 8によって押圧して、 凸部 4 2 aを形成して保持板 4 4に接合する。  The projection 42 a is formed by pressing the pressing jig 48 from the hole 46 a formed in the insulating film 46. That is, a hole 46 a is previously formed in the insulating film 46 corresponding to a portion of the wiring pattern 42 where the convex portion 42 a is to be formed, and the holding plate 44 4 is formed from the hole 46 a. The wiring pattern 42 is pressed by the pressing jig 48 to form a projection 42 a and is joined to the holding plate 44.
なお、 凸部 4 2 aを形成する領域には、 絶縁接着剤 4 5を除去しておくことが 好ましい。 また、 凸部 4 2 aを形成するときに、 加圧治具 4 8からは、 熱又は超 音波振動が加えられる。 さらに、 配線パターン 4 2には金 （A n ) メツキが施さ れている。 なお、 配線パターン 4 2としては金メッキ以外にも周知のスズメツキ やハンダメツキを用いても良い。 一方、 保持板 4 4にも金属メツキが施されてい ると、 凸部 4 2 aと保持板 4 4との接合が容易になる。  It is preferable that the insulating adhesive 45 be removed from the region where the convex portion 42 a is to be formed. Further, when forming the projection 42 a, heat or ultrasonic vibration is applied from the pressing jig 48. Further, the wiring pattern 42 is plated with gold (A n). As the wiring pattern 42, a well-known tin plate or solder plate may be used other than the gold plating. On the other hand, if the metal plate is also provided on the holding plate 44, the joining between the projection 42 a and the holding plate 44 becomes easy.
次に、 図 3 Bに示す半導体装置 5 0は、 導電接着剤 5 6によって配線パターン 5 2及び保持板 5 4が接続されたものである。 このように接続するために、 配線 パターン 5 2において保持板 5 4に接続する部分に対応して、 絶縁接着剤 5 5を 除去して導電接着剤 5 6を設けて、 保持板 5 4を絶縁フィルム 5 8に熱圧着する。 あるいは、 導電接着剤 5 6の代わりに、 ハンダを用いても良い。 その場合には、 保持板 5 4と絶縁フィルム 5 8とを熱圧着するときに、 ハンダの融点まで加熱す る必要がある。 Next, in a semiconductor device 50 shown in FIG. 3B, a wiring pattern 52 and a holding plate 54 are connected by a conductive adhesive 56. In order to make such a connection, the insulating adhesive 55 is removed and a conductive adhesive 56 is provided corresponding to the portion of the wiring pattern 52 connected to the holding plate 54, and the holding plate 54 is insulated. Thermocompression bonded to film 58. Alternatively, solder may be used instead of the conductive adhesive 56. In this case, when the holding plate 54 and the insulating film 58 are thermocompression-bonded, they are heated to the melting point of the solder. Need to be
以上の変形例によっても、 上記第 2実施形態と同様の効果を達成することがで ぎる。  According to the above modification, the same effects as those of the second embodiment can be achieved.
なお、 半導体素子との接合には、 配線パターン側に突起が一体形成されたいわ ゆる B— T A B型のものを用いても良い。  Note that a so-called B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element.
(第 4実施形態）  (Fourth embodiment)
次に、 図 4は、 第 3実施形態の他の変形例を示す図であり、 前に挙げたいわゆ る 「B— T A B型」 の例である。 同図に示す半導体装置 6 0の配線パターン 6 2 は、 半導体チップ 6 4の電極 6 4 aとの接続用の突起 6 2 aとともに、 導電性の 保持板 6 6との接続用の突起 6 2 bを有する。 なお、 半導体チップ 6 4は、 樹脂 6 5によってモールドされている。 こうすることで、 配線パターン 6 2における G N D電位又は電源電位と保持板 6 6とを接続することができる。 また、 突起 6 2 bと保持板 6 6とは、 配線パターン 6 2を有する絶縁フィルム 6 8に保持板 6 6を熱圧着して取り付けるときに、 同時に接続される。 なお、 その他の構成は、 図 3 Bに示す実施形態と同様であるため説明を省略する。  Next, FIG. 4 is a diagram showing another modified example of the third embodiment, and is an example of the so-called “B-TAB type” mentioned above. The wiring pattern 62 of the semiconductor device 60 shown in the figure includes a projection 62 for connecting to the electrode 64a of the semiconductor chip 64 and a projection 62 for connecting to the conductive holding plate 66. has b. The semiconductor chip 64 is molded with a resin 65. By doing so, it is possible to connect the GND potential or the power supply potential in the wiring pattern 62 to the holding plate 66. The projections 62b and the holding plate 66 are simultaneously connected when the holding plate 66 is attached to the insulating film 68 having the wiring pattern 62 by thermocompression bonding. The other configuration is the same as that of the embodiment shown in FIG.
(第 5実施形態）  (Fifth embodiment)
図 5 A〜図 5 Cは、 第 5実施形態に係る半導体装置を示す図である。 図 5 Aに 示す半導体装置 1 0 0は、 絶縁フィルム 1 0 4、 配線パターン 1 0 6、 バンプ 1 0 8及び半導体チップ 1 0 9を有し、 絶縁フイルム 1 0 4及び配線パターン 1 0 6の端部が保持板 1 0 2によって保持されている。 保持板 1 0 2は、 導電性の高 い材質からなる。  5A to 5C are views showing a semiconductor device according to the fifth embodiment. The semiconductor device 100 shown in FIG. 5A has an insulating film 104, a wiring pattern 106, a bump 108 and a semiconductor chip 109, and has an insulating film 104 and a wiring pattern 106. The end is held by the holding plate 102. The holding plate 102 is made of a highly conductive material.
詳しくは、 保持板 1 0 2に形成された溝 1 0 2 aに絶縁フィルム 1 0 4の端部 が挿入されることで、 絶縁フィルム 1 0 4の端部が保持されている。 また、 配線 パターン 1 0 6は、 保持板 1 0 2に保持されて電気的に接続されている。 なお、 保持板 1 0 2に接続される配線パターン 1 0 6の部分については、 第 1実施形態 と同様であり、 電気的な接続の効果についても同様であるため説明を省略する。 保持板 1 0 2は、 平面性を保つのに必要な強度を有する一方、 絶縁フィルム 1 0 4は柔軟性を有する。 したがって、 絶縁フィルム 1 0 4の端部が保持板 1 0 2 に保持されることで、 柔軟性のある絶縁フィルム 1 0 4が平面性を保てるように なる。 そして、 絶縁フィルム 1 0 4の反りを抑えて、 確実な実装を行えるように なる。 また、 More specifically, the end of the insulating film 104 is held by inserting the end of the insulating film 104 into the groove 102 a formed in the holding plate 102. The wiring pattern 106 is held by the holding plate 102 and is electrically connected. Note that the portion of the wiring pattern 106 connected to the holding plate 102 is the same as in the first embodiment, and the effect of the electrical connection is the same, so the description is omitted. The holding plate 102 has the strength necessary to maintain the flatness, while the insulating film 104 has flexibility. Therefore, the end of the insulating film 104 is By holding the flexible insulating film 104, the flexible insulating film 104 can maintain flatness. Then, the warpage of the insulating film 104 can be suppressed, and the mounting can be performed reliably. Also,
保持板 1 0 2の熱膨張係数 >絶縁フィルム 1 0 4の熱膨張係数  Thermal expansion coefficient of holding plate 102> Thermal expansion coefficient of insulating film 104
とすることが好ましい。 こうすることで、 回路基板に半導体装置 1 0 0を実装す るときのリフ口一工程で、 保持板 1 0 2によって絶縁フィルム 1 0 4にテンショ ンがかかり、 絶縁フィルム 1 0 4が張るようになり、 その結果平坦性が得られる ので、 バンプ 1 0 8を回路基板に確実に実装することができる。 It is preferable that In this way, the tension is applied to the insulating film 104 by the holding plate 102 so that the insulating film 104 is stretched in one step of the riff opening when the semiconductor device 100 is mounted on the circuit board. As a result, flatness can be obtained, so that the bump 108 can be securely mounted on the circuit board.
なお、 半導体素子との接合には、 配線パターン側に突起が一体形成されたいわ ゆる B— T A B型のものを用いても良い。 また、 本実施形態では、 保持板 1 0 2 と絶縁フィルム 1 0 4との間に空間の存在する例が示されているが、 空間が存在 しないようにしても良い。  Note that a so-called B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element. Further, in the present embodiment, an example is described in which a space exists between the holding plate 102 and the insulating film 104, but the space may not exist.
図 5 Bには、 第 5実施形態の変形例が示されている。 同図に示す半導体装置 1 1 0は、 保持板 1 1 2に形成されたスリッ ト 1 1 2 aに、 絶縁フィルム 1 1 4及 び配線パターン 1 1 6の端部が挿入される点で、 上記半導体装置 1 0 0と相違す る o  FIG. 5B shows a modification of the fifth embodiment. The semiconductor device 110 shown in the figure has a point that the insulating film 114 and the end of the wiring pattern 116 are inserted into the slit 112a formed on the holding plate 112. Different from the above semiconductor device 100 o
また、 図 5 Cにも、 第 5実施形態の変形例が示されている。 同図に示す半導体 装置 1 2 0は、 絶縁フイルム 1 2 4に形成されたスリッ ト 1 2 4 aに、 保持板 1 2 2の端部が挿入されることで、 絶縁フィルム 1 2 4の端部が保持されている。 詳しくは、 絶縁フィルム 1 2 4の一方の面から、 スリッ ト 1 2 4 aを介して他方 の面に、 保持板 1 2 2の端部を弾性変形させて挿入し、 保持板 1 2 2の復元力に よって絶縁フィルム 1 2 4の平面性を保つようになつている。 また、 こうするこ とで、 保持板 1 2 2と配線パターン 1 2 6とが電気的に接続される。  FIG. 5C also shows a modification of the fifth embodiment. The semiconductor device 120 shown in the figure has the end of the insulating film 124 inserted into the slit 124 a formed on the insulating film 124 by inserting the end of the holding plate 122. Part is held. Specifically, the end of the holding plate 122 is inserted from one surface of the insulating film 124 through the slit 124a into the other surface by elastically deforming the end of the holding plate 122. The flatness of the insulating film 124 is maintained by the restoring force. Also, by doing so, the holding plate 122 and the wiring pattern 126 are electrically connected.
これらの半導体装置 1 1 0、 1 2 0であっても、 上記半導体装置 1 0 0と同様 の効果を達成することができる。  Even with these semiconductor devices 110 and 120, the same effects as those of the semiconductor device 100 can be achieved.
なお、 半導体素子との接合には、 配線パターン側に突起が一体形成されたいわ ゆる B— T A B型のものを用いても良い。  Note that a so-called B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element.
(第 6実施形態） 図 6に示す半導体装置 7 0は、 保持板 7 2と絶縁フィルム 7 4とが接着剤 7 3 によって全面固定される点で、 上記第 4実施形態と異なる。 ここで、 (Sixth embodiment) The semiconductor device 70 shown in FIG. 6 differs from the above-described fourth embodiment in that the holding plate 72 and the insulating film 74 are entirely fixed by an adhesive 73. here,
保持板 7 2の熱膨張係数 >絶縁フィルム 7 4の熱膨張係数  Thermal expansion coefficient of holding plate 72> Thermal expansion coefficient of insulating film 74
とすることが好ましい。 こうすることで、 回路基板に半導体装置 7 0を実装する ときのリフロー工程で、 保持板 7 2によって絶縁フイルム 7 4にテンションがか かり、 絶縁フィルム 7 4が張るようになり、 その結果平坦性が得られるので、 ハ ンダボール 7 5を回路基板に確実に実装することができる。 なお、 配線パターン 7 1と保持板 7 2との電気的な接続の構造は、 図 1に示す構図と同様であるので 説明を省略する。 It is preferable that In this way, in the reflow process when the semiconductor device 70 is mounted on the circuit board, the insulating film 74 is tensioned by the holding plate 72, and the insulating film 74 is stretched. Therefore, the solder balls 75 can be securely mounted on the circuit board. The structure of the electrical connection between the wiring pattern 71 and the holding plate 72 is the same as the composition shown in FIG.
(第 7実施形態）  (Seventh embodiment)
図 7に示す半導体装置 7 6では、 保持板 7 8の端部 7 8 aが、 絶縁フィルム 8 0及び配線パターン 8 1の端部に対して、 矢印で示す方向にかしめられている。 これによつて、 保持板 7 8と絶縁フィルム 8 0とが固定され、 かつ、 配線パ夕一 ン 8 1と保持板 7 8との電気的な接続が図られている。 本実施形態によれば、 量 産工程において、 接着剤を用いずに安定して保持板 7 8を取り付けることができ る。  In the semiconductor device 76 shown in FIG. 7, the end 78 a of the holding plate 78 is caulked in the direction shown by the arrow with respect to the ends of the insulating film 80 and the wiring pattern 81. As a result, the holding plate 78 and the insulating film 80 are fixed, and the electrical connection between the wiring pattern 81 and the holding plate 78 is achieved. According to the present embodiment, the holding plate 78 can be stably mounted without using an adhesive in the mass production process.
(第 8実施形態）  (Eighth embodiment)
図 8に示す半導体装置 8 2では、 保持板 8 4がピン等の突起 8 4 aを有し、 絶 縁フィルム 8 6に穴 8 6 aが形成され、 配線パターン 8 7に穴 8 7 aが形成され ている。 突起 8 4 aと、 穴 8 6 a及び穴 8 7 aとをはめ合わせて、 保持板 8 4が 絶縁フィルム 8 6に取り付けられている。 また、 穴 8 6 aよりも穴 8 7 aの直径 がわずかに小さく形成されていおり、 配線パターン 8 7と保持板 8 7との電気的 な接続が確実に図られるようになつている。  In the semiconductor device 82 shown in FIG. 8, the holding plate 84 has a projection 84 a such as a pin, a hole 86 a is formed in the insulating film 86, and a hole 87 a is formed in the wiring pattern 87. It is formed. The holding plate 84 is attached to the insulating film 86 by fitting the projection 84a with the hole 86a and the hole 87a. Further, the diameter of the hole 87a is formed slightly smaller than that of the hole 86a, so that the electrical connection between the wiring pattern 87 and the holding plate 87 can be ensured.
なお、 突起 8 4 aは、 保持板 8 4の端部を曲げて形成されてもよい。 これによ つても、 量産工程において、 接着剤を用いずに安定して保持板 8 4を取り付ける ことができる。  The projection 84a may be formed by bending an end of the holding plate 84. Also in this case, the holding plate 84 can be stably mounted without using an adhesive in the mass production process.
(第 9実施形態）  (Ninth embodiment)
図 9に示す半導体装置 9 0は、 図 1に示す半導体装置 1 0に放熱板 （ヒ一トス プレッダ） 9 1が取り付けられたものである。 詳しくは、 半導体チップ 1 6の裏 面 （電極 1 8とは反対側の面） と保持板 2 4とに、 接着剤 9 2が塗布されて、 放 熱板 9 1が接着されている。 接着剤 9 2は、 銀などを含有して熱伝導性及び導電 性が高く、 放熱板 9 1も熱伝導性及び導電性の高い材料から構成されている。 こ うすることで、 放熱板 9 1によって、 半導体チップ 1 6の熱の発散を促進すると ともに、 半導体チップ 1 6の裏面も一定電位に接続することができる。 そして、 半導体チップ 1 6の誤作動が防止されて信頼性が向上する。 The semiconductor device 90 shown in FIG. 9 is different from the semiconductor device 10 shown in FIG. Predder) 9 1 is attached. More specifically, an adhesive 92 is applied to the back surface of the semiconductor chip 16 (the surface opposite to the electrode 18) and the holding plate 24, and the heat dissipation plate 91 is adhered. The adhesive 92 contains silver or the like and has high thermal conductivity and conductivity, and the heat sink 91 is also made of a material having high thermal conductivity and conductivity. By doing so, heat dissipation of the semiconductor chip 16 can be promoted by the heat sink 91, and the back surface of the semiconductor chip 16 can be connected to a constant potential. Then, malfunction of the semiconductor chip 16 is prevented, and reliability is improved.
(第 1 0実施形態）  (10th embodiment)
図 1 0に示す半導体装置 9 4は、 図 9に示す半導体装置 9 0の保持板 2 4及び 放熱板 9 1の代わりに、 これらが一体化された形状の保持板 9 3を有する。 すな わち、 保持板 9 3は、 絶縁フィルム 1 2に貼り付けられる部分と、 半導体チップ The semiconductor device 94 shown in FIG. 10 has a holding plate 93 in which these are integrated instead of the holding plate 24 and the heat radiating plate 91 of the semiconductor device 90 shown in FIG. That is, the holding plate 93 includes a portion to be attached to the insulating film 12 and a semiconductor chip.
1 6の裏面に貼り付けられる部分と、 がー体的になるように屈曲した形状をなし ている。 このような保持板 9 3を使用しても、 上記実施形態と同様の効果を得る ことができる。 The part to be attached to the back of 16 has a shape that is bent so that it becomes more physical. Even when such a holding plate 93 is used, the same effect as in the above embodiment can be obtained.
(第 1 1実施形態）  (11st Embodiment)
図 1 1は、 第 1 1施形態に係る回路基板を示す図である。 図 1 1に示す回路基 板 1 3 0には、 半導体装置 1 3 2が実装されている。 半導体装置 1 3 2は、 絶縁 フィルム 1 3 4、 配線パターン 1 3 6、 バンプ 1 3 8及び半導体チップ 1 3 9を 有し、 回路基板 1 3 0には、 バンプ 1 3 8をボンディングするためのパッ ド 1 3 0 aが形成されている。 絶縁フィルム 1 3 4には保持板 1 3 3が貼り付けられて いる。  FIG. 11 is a diagram illustrating a circuit board according to the eleventh embodiment. A semiconductor device 132 is mounted on a circuit board 130 shown in FIG. The semiconductor device 13 2 has an insulating film 13 4, a wiring pattern 13 6, a bump 13 8, and a semiconductor chip 13 9, and a circuit board 13 0 for bonding the bump 13 8. A pad 130a is formed. A holding plate 133 is attached to the insulating film 134.
また、 半導体装置 1 3 2は、 絶縁フィルム 1 3 4の端部及び中央部に設けられ た接着剤 1 2 8によって、 回路基板 1 3 0に接着されている。 この接着は、 リフ 口一工程前に行われる。 すなわち、 半導体装置 1 3 2を、 一時的に、 接着剤 1 2 8によって回路基板 1 3 0に接着して、 絶縁フィルム 1 3 4の反りをなくしてか ら、 バンプ 1 3 8とパッ ド 1 3 0 aとを接合する。 絶縁フィルム 1 3 4の反りを なくすには、 少なくとも、 絶縁フィルム 1 3 4の端部を接着剤 1 2 8にて固定す ることが好ましい。 また、 接着剤 1 2 8として、 ハンダ溶融温度以下の温度で反 応するものを用いて、 先に接着剤 1 2 8が半導体装置 1 3 2を接続してその後ハ ンダが溶融することが好ましい。 こうして、 いわゆる仮り止めが行われる。 本実施形態によれば、 接着剤 1 2 8を用いて、 絶縁フィルム 1 3 4の反りをな くしたので、 良好な実装が可能になる。 The semiconductor device 132 is bonded to the circuit board 130 by an adhesive 128 provided at the end and the center of the insulating film 134. This bonding is performed one step before the lift opening. That is, the semiconductor device 132 is temporarily bonded to the circuit board 130 with an adhesive 128 to eliminate the warpage of the insulating film 134, and then the bump 133 and the pad 1 are removed. Join with 30a. In order to eliminate the warpage of the insulating film 134, it is preferable to fix at least the end of the insulating film 134 with an adhesive 128. Also, as adhesive 128, it reacts at a temperature below the solder melting temperature. It is preferable that an adhesive 128 connects the semiconductor device 132 first and then the solder is melted using a corresponding material. In this way, so-called temporary fixing is performed. According to the present embodiment, the adhesive film 128 is used to eliminate the warpage of the insulating film 134, so that good mounting is possible.
なお、 半導体素子との接合には、 配線パターン側に突起が一体形成されたいわ ゆる B— T A B型のものを用いても良い。 また、 本実施形態は、 保持板 1 3 3を 有するが、 保持板 1 3 3を省略したものでも平坦性の維持が可能である。  Note that a so-called B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element. In addition, although the present embodiment has the holding plate 133, flatness can be maintained even if the holding plate 133 is omitted.
(第 1 2実施形態）  (First and second embodiments)
図 1 2 Aは、 第 1 2実施形態に係る回路基板を示す図である。 同図に示す回路 基板 1 4 0には半導体装置 1 4 2が実装されている。 半導体基板 1 4 2は、 保持 板 1 4 4以外の点で、 図 1に示す半導体装置 1 0と同様であるため説明を省略す る  FIG. 12A is a diagram showing a circuit board according to the 12th embodiment. A semiconductor device 142 is mounted on a circuit board 140 shown in FIG. The semiconductor substrate 144 is the same as the semiconductor device 10 shown in FIG. 1 except for the holding plate 144, and therefore the description is omitted.
そして、 保持板 1 4 4は、 銅ゃスレンレス鋼や銅系合金などの導電性の高い材 料で構成され、 ネジ 1 4 6を通す穴 1 4 4 aが形成されている。 このネジ 1 4 6 も導電性を有する。 一方、 回路基板 1 4 0にも、 導電性のネジ 1 4 6を通す穴 1 4 0 aが形成されており、 一方の面において、 この穴 1 4 0 aの周囲にリング状 のパッ ド 1 4 8が形成されている。 パッ ド 1 4 8は、 回路基板 1 4 0における G N D電位又は電源電位等の一定電位に接続されている。 そして、 保持板 1 4 4と 回路基板 1 4 0とが、 それぞれの穴 1 4 4 a、 1 4 0 aに揷通されるネジ 1 4 6 及びナヅ ト 1 4 9にて固定されている。  The holding plate 144 is made of a highly conductive material such as copper-stainless steel or a copper-based alloy, and has a hole 144a through which the screw 144 passes. This screw 1 4 6 also has conductivity. On the other hand, the circuit board 140 also has a hole 140a through which the conductive screw 144 passes. On one surface, a ring-shaped pad 1 is formed around the hole 140a. 4 8 are formed. The pad 148 is connected to a constant potential such as a GND potential or a power supply potential on the circuit board 140. Then, the holding plate 144 and the circuit board 140 are fixed by screws 144 and nuts 149 that pass through the respective holes 144a and 140a.
こうして、 ネジ 1 4 6を介して、 面状の保持板 1 4 4は、 G N D電位又は電源 電位等の一定電位となる。 こうすることで、 半導体装置 1 4 2において、 面状の 一定電位に沿って信号を伝送することができるので、 高周波信号の伝送特性が向 上する。  In this way, the planar holding plate 144 becomes a constant potential such as the GND potential or the power supply potential via the screw 144. By doing so, in the semiconductor device 142, a signal can be transmitted along a planar constant potential, so that the transmission characteristics of a high-frequency signal are improved.
なお、 ネジ 1 4 6によるねじ止めは、 ハンダ付け後に行うことが好ましい。 ま た、 本実施形態では、 ネジ 1 4 6が 1箇所のみに用いられているが、 複数箇所に 設けられても良い。 なお、 対向位置にネジ 1 4 6を設ける場合には、 例えば四隅 に設けることが好ましい。 また、 図 1 2 Bは、 第 1 2実施形態の変形例を示す図である。 同図において、 回路基板 1 5 0に形成されたパッ ド 1 5 2と、 保持板 1 5 4とは、 ワイヤ 1 5 6 にて接続されている。 ここで、 パッ ド 1 5 2は、 一定電位に接続されている。 し たがって、 保持板 1 5 4も一定電位となって、 高周波信号の伝送特性が向上する。 なお、 ワイヤ 1 5 6は、 ハンダ付けを行ったり、 通常のワイヤボンディング手法、 例えば超音波にて設けられる。 また、 その後にワイヤを樹脂で保護してもよい。 なお、 半導体素子との接合には、 配線パターン側に突起が一体形成されたいわ ゆる B— T A B型のものを用いても良い。 It is preferable that screwing with the screw 146 be performed after soldering. Further, in the present embodiment, the screw 146 is used only at one place, but it may be provided at a plurality of places. When the screws 146 are provided at the opposing positions, it is preferable to provide them at, for example, four corners. FIG. 12B is a diagram showing a modification of the 12th embodiment. In the figure, a pad 152 formed on a circuit board 150 and a holding plate 154 are connected by wires 156. Here, the pads 15 2 are connected to a constant potential. Therefore, the holding plate 154 also has a constant potential, and the transmission characteristics of high-frequency signals are improved. The wires 156 are provided by soldering or by a normal wire bonding method, for example, ultrasonic waves. After that, the wire may be protected with a resin. Note that a so-called B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element.
図 1 3には、 本発明を適用した半導体装置 1 1 0 0を実装した回路基板 1 0 0 0が示されている。 回路基板には例えばガラスエポキシ基板等の有機系基板を用 いることが一般的である。 回路基板には例えば銅からなる配線パターンが所望の 回路となるように形成されていて、 それらの配線パターンと半導体装置のバンプ とを機械的に接続することでそれらの電気的導通を図る。 この場合、 上述の半導 体装置に、 外部との熱膨張差により生じる歪みを吸収する構造を設ければ、 本半 導体装置を回路基板に実装しても接続時及びそれ以降の信頼性を向上できる。 ま た更に半導体装置の配線に対しても工夫が成されれば、 接続時及び接続後の信頼 性を向上させることができる。 なお実装面積もベアチップにて実装した面積にま で小さくすることができる。 このため、 この回路基板を電子機器に用いれば電子 機器自体の小型化が図れる。 また、 同一面積内においてはより実装スペースを確 保することができ、 高機能化を図ることも可能である。  FIG. 13 shows a circuit board 1000 on which a semiconductor device 110 to which the present invention is applied is mounted. Generally, an organic substrate such as a glass epoxy substrate is used for the circuit board. Wiring patterns made of, for example, copper are formed on the circuit board so as to form a desired circuit, and the electrical continuity is achieved by mechanically connecting the wiring patterns and the bumps of the semiconductor device. In this case, if the semiconductor device described above is provided with a structure that absorbs the strain caused by the difference in thermal expansion with the outside, the reliability at the time of connection and thereafter can be improved even if the semiconductor device is mounted on a circuit board. Can be improved. Further, if the wiring of the semiconductor device is devised, the reliability at the time of connection and after the connection can be improved. The mounting area can be reduced to the area mounted with bare chips. For this reason, if this circuit board is used for an electronic device, the size of the electronic device itself can be reduced. Also, within the same area, more mounting space can be secured, and higher functionality can be achieved.
そして、 この回路基板 1 0 0 0を備える電子機器として、 図 1 4には、 ノート 型パーソナルコンピュータ 1 2 0 0が示されている。  As an electronic apparatus including the circuit board 100, a notebook personal computer 1200 is shown in FIG.
なお、 半導体装置と同様に多数のバンプを必要とする面実装用の電子部品であ れば、 能動部品か受動部品かを問わず、 本発明を応用することができる。 電子部 P口Pとして、 例えば、 抵抗器、 コンデンサ、 コイル、 発振器、 フィル夕、 温度セン サ、 サーミス夕、 バリス夕、 ボリューム又はヒューズなどがある,  The present invention can be applied to any electronic device for surface mounting that requires a large number of bumps, similarly to a semiconductor device, regardless of whether it is an active component or a passive component. The electronic part P port P includes, for example, a resistor, a capacitor, a coil, an oscillator, a filter, a temperature sensor, a thermistor, a ballis, a volume or a fuse,

Claims

請求の範囲 The scope of the claims
1 . 半導体素子と、 1. a semiconductor element;
貫通孔を有する絶縁フィルムと、  An insulating film having a through hole,
前記絶縁フィルムの一方の面側において前記貫通孔上を通るように形成される とともに前記半導体素子に接続される配線パターンと、  A wiring pattern formed on one surface side of the insulating film so as to pass over the through hole and connected to the semiconductor element;
前記絶縁フィルムの他方の面側に設けられるとともに前記貫通孔を介して前記 配線パターンと電気的な接続がなされている外部端子と、  An external terminal provided on the other surface side of the insulating film and electrically connected to the wiring pattern via the through hole;
導電性を有するとともに平面性を保つ部材からなり、 前記配線パターンの前記 絶縁フィルムが設けられた面の反対面側に前記配線パターンの少なくとも一部を 覆うように設けられる保持板と、 を有し、  A holding plate made of a member having conductivity and maintaining flatness, provided on the opposite side of the surface of the wiring pattern on which the insulating film is provided, so as to cover at least a part of the wiring pattern. ,
前記保持板は、 絶縁性の接着剤を介して前記絶縁フィルムに貼り付けられると ともに、 前記配線パターンの一定電位部に接続されてなる半導体装置。  The semiconductor device, wherein the holding plate is attached to the insulating film via an insulating adhesive and is connected to a constant potential portion of the wiring pattern.
2 . 請求項 1記載の半導体装置において、  2. The semiconductor device according to claim 1,
前記保持板と前記配線パターンとの間に、 前記配線パ夕ーンを覆う保護層が存 在する半導体装置。  A semiconductor device in which a protective layer that covers the wiring pattern exists between the holding plate and the wiring pattern.
3 . 請求項 1記載の半導体装置において、  3. The semiconductor device according to claim 1,
前記一定電位部は、 電源電位及びグランド電位のいずれか一方である半導体装  The constant potential section is a semiconductor device which is either a power supply potential or a ground potential.
4 . 請求項 1記載の半導体装置において、 4. The semiconductor device according to claim 1,
前記配線パターンは、 少なくとも一部に湾曲部を有し、 前記湾曲部が前記保持 板に接続される半導体装置。  The semiconductor device, wherein the wiring pattern has a curved portion at least in part, and the curved portion is connected to the holding plate.
5 . 請求項 1記載の半導体装置において、  5. The semiconductor device according to claim 1,
前記保持板は、 ハンダ及び導電性接着剤のうち少なくともいずれか一方によつ て、 前記配線パターンの前記一定電位部と接続される半導体装置。  The semiconductor device wherein the holding plate is connected to the constant potential portion of the wiring pattern by at least one of a solder and a conductive adhesive.
6 . 半導体素子と、 絶縁フィルムと、 前記絶縁フィルム上に形成されるとともに 前記半導体素子に接続される配線パターンと、 前記配線パターン上に形成される 外部端子と、 導電性を有するとともに平面性を保つ部材からなり前記絶縁フィル ムの一部を保持する保持板と、 を有し、 6. A semiconductor element, an insulating film, a wiring pattern formed on the insulating film and connected to the semiconductor element, an external terminal formed on the wiring pattern, having conductivity and planarity. The insulation fill And a holding plate for holding a part of the system,
前記保持板は、 前記配線パ夕一ンの一定電位部に接続されてなる半導体装置。 The semiconductor device, wherein the holding plate is connected to a constant potential portion of the wiring pattern.
7 . 請求項 6記載の半導体装置において、 7. The semiconductor device according to claim 6,
前記保持板には、 前記絶縁フィルムの熱膨張係数よりも大きい熱膨張係数を有 する部材を用いてなる半導体装置。  A semiconductor device using a member having a thermal expansion coefficient larger than a thermal expansion coefficient of the insulating film as the holding plate.
8 . 請求項 6記載の半導体装置において、  8. The semiconductor device according to claim 6,
前記保持板は、 スリ ッ ト又は溝を有し、  The holding plate has a slit or a groove,
前記絶縁フィルムの端部は、 前記スリッ ト又は溝に挿入されて前記保持板に保 持される半導体装置。  A semiconductor device in which an end of the insulating film is inserted into the slit or the groove and held by the holding plate.
9 . 請求項 6記載の半導体装置において、  9. The semiconductor device according to claim 6,
前記絶縁フィルムは、 スリ ッ トを有し、  The insulating film has a slit,
前記保持板は、 前記スリ ッ トを介して前記絶縁フィルムの反対側面に、 端部が 突出するように取り付けられる半導体装置。  The semiconductor device, wherein the holding plate is attached to an opposite side of the insulating film via the slit so that an end protrudes.
1 0 . 絶縁フィルムに貫通孔を形成する工程と、  10. Forming a through hole in the insulating film;
前記絶縁フィルムの一方の面側に前記貫通孔上を通る配線パターンを形成する 工程と、  Forming a wiring pattern passing over the through hole on one surface side of the insulating film;
前記配線パターンにおける前記絶縁フィルム側の面に前記貫通孔を介して前記 絶縁フィルムの他方の面側に突出する外部端子を形成する工程と、  Forming an external terminal projecting on the other surface side of the insulating film through the through hole on a surface of the wiring pattern on the insulating film side;
半導体素子を前記配線パターンに接続して前記絶縁フィルムに設ける工程と、 前記配線パターンの前記絶縁フィルムが設けられた面の反対面側に、 前記配線 パターンの少なくとも一部を覆うように、 導電性を有するとともに平面性を保つ 部材からなる保持板を貼り付ける工程と、  A step of connecting a semiconductor element to the wiring pattern and providing the insulating film on the insulating film; and forming a conductive pattern on the side of the wiring pattern opposite to the surface on which the insulating film is provided, so as to cover at least a part of the wiring pattern. A step of attaching a holding plate made of a member having flatness and having
前記配線パターンの一部を前記保持板に接続する工程と、  Connecting a part of the wiring pattern to the holding plate;
を含む半導体装置の製造方法。  A method for manufacturing a semiconductor device including:
1 1 . 請求項 1 0記載の半導体装置の製造方法において、  11. The method for manufacturing a semiconductor device according to claim 10, wherein
前記保持板を、 絶縁性の接着剤を介して前記絶縁フィルムに貼り付ける半導体 装置の製造方法。  A method for manufacturing a semiconductor device, wherein the holding plate is attached to the insulating film via an insulating adhesive.
1 2 . 請求項 1 1記載の半導体装置の製造方法において、 前記絶縁フィルムは、 前記配線パターンに対応する開口部を有し、 前記絶縁フィルムの前記他方の面から前記開口部を介して加圧治具を押し入れ て、 前記配線パターンの一部を、 屈曲させて前記保持板に接続する半導体装置の 製造方法。 12. The method for manufacturing a semiconductor device according to claim 11, The insulating film has an opening corresponding to the wiring pattern, and presses a pressing jig through the opening from the other surface of the insulating film to bend a part of the wiring pattern. And a method for manufacturing a semiconductor device connected to the holding plate.
1 3 . 絶縁フィルムに配線パターンを形成する工程と、 半導体素子を前記配線パ ターンに接続して前記絶縁フィルムに設ける工程と、 前記絶縁フィルムの端部を 保持する保持板を取り付ける工程と、 前記配線パターンの一部を前記保持板に電 気的に接続する工程と、 を含む半導体装置の製造方法。  13. A step of forming a wiring pattern on an insulating film, a step of connecting a semiconductor element to the wiring pattern and providing the insulating film on the insulating film, and a step of attaching a holding plate for holding an end of the insulating film. Electrically connecting a part of the wiring pattern to the holding plate.
1 4 . 請求項 1から請求項 5のいずれかに記載の半導体装置と、 所望の導電パ夕 —ンが形成された基板と、 を有し、  14. A semiconductor device according to any one of claims 1 to 5, and a substrate on which a desired conductive pattern is formed,
前記半導体装置の前記外部端子が前記導電パターンに接続された回路基板。 A circuit board in which the external terminals of the semiconductor device are connected to the conductive pattern.
1 5 . 半導体素子と、 絶縁フィルムと、 前記絶縁フィルムに形成されて前記半導 体素子に接続される配線パターンと、 前記配線パターン上に形成されるバンプと、 導電性を有するとともに平面性を保つ部材からなり前記配線パターンに電気的に 接続される保持材と、 を含む半導体装置と、 15. A semiconductor element, an insulating film, a wiring pattern formed on the insulating film and connected to the semiconductor element, a bump formed on the wiring pattern, and having conductivity and planarity. A holding member made of a holding member and electrically connected to the wiring pattern;
所望の導電パターンが形成され、 前記絶縁フィルムの少なくとも端部と接着剤 にて固定される基板と、  A substrate on which a desired conductive pattern is formed and which is fixed to at least an end portion of the insulating film with an adhesive;
を有する回路基板。  A circuit board having
1 6 . ハンダバンプが形成された絶縁フィルムと、 導電性を有するとともに平面 性を保つ部材からなり前記配線パターンに電気的に接続される保持材と、 を有す る半導体装置の実装方法において、  16. A method for mounting a semiconductor device, comprising: an insulating film on which solder bumps are formed; and a holding member made of a member having conductivity and maintaining planarity and electrically connected to the wiring pattern.
前記絶縁フィルムの少なくとも端部に接着剤を塗布して回路基板に接着してか ら、 ハンダバンプを溶融させて前記回路基板のパッ ドに接続する半導体装置の実 装方法。 補正書の請求の範囲 A method of mounting a semiconductor device, wherein an adhesive is applied to at least an end portion of the insulating film and bonded to a circuit board, and then the solder bump is melted and connected to the pad of the circuit board. Claims of amendment
[ 1 9 9 8年 6月 1 7日 （1 7 · 0 6 . 9 8 ) 国際事務局受理：出願当初の請求の範囲 1 , 6， 1 0， 1 3， 1 5及び 1 6は補正された；出願当初の請求の範囲 7は取り下げられた； 他の請求の範囲は変更なし。 （1頁） ]  [June 17, 1998 (17 · 06.998) Accepted by the International Bureau: Claims 1, 6, 10, 10, 13, 15, and 16 at the time of filing of the application were amended. Claim 7 originally filed was withdrawn; other claims remained unchanged. (1 page)]
1， （補正後） 半導体素子と、  1, (after correction)
貫通孔を有する絶縁フィルムと、  An insulating film having a through hole,
前記絶縁フィルムの一方の面側において前記貫通孔上を通るように形成される とともに前記半導体素子に接続される配線パターンと、  A wiring pattern formed on one surface side of the insulating film so as to pass over the through hole and connected to the semiconductor element;
前記絶縁フィルムの他方の面側に設けられるとともに前記貫通孔を介して前記 配線パターンと電気的な接続がなされている外部端子と、  An external terminal provided on the other surface side of the insulating film and electrically connected to the wiring pattern via the through hole;
導電性を有するとともに平面性を保つ部材からなリ、 前記配線パターンの前記 絶縁フィルムが設けられた面の反対面側に前記配線パターンの少なくとも一部を 覆うように設けられる保持板と、 を有し、  A holding plate provided on the surface of the wiring pattern opposite to the surface on which the insulating film is provided so as to cover at least a part of the wiring pattern; And
前記保持板は、 絶縁性の接着剤を介して前記絶縁フィルムに貼り付けられると ともに、 前記配線パターンの一定電位部に接続され、  The holding plate is attached to the insulating film via an insulating adhesive, and is connected to a constant potential portion of the wiring pattern.
前記保持板の熱膨張係数 >前記絶縁フィルムの熱膨張係数  Coefficient of thermal expansion of the holding plate> Coefficient of thermal expansion of the insulating film
の関係を有する半導体装置。 Semiconductor device having the following relationship.
2 . 請求項 1記載の半導体装置において、  2. The semiconductor device according to claim 1,
前記保持板と前記配線パターンとの間に、 前記配線パターンを覆う保護層が存 在する半導体装置。  A semiconductor device in which a protective layer that covers the wiring pattern exists between the holding plate and the wiring pattern.
3 . 請求項 1記載の半導体装置において、  3. The semiconductor device according to claim 1,
前記一定電位部は、 電源電位及びグランド電位のいずれか一方である半導体装 置。  The semiconductor device, wherein the constant potential portion is one of a power supply potential and a ground potential.
4 . 請求項 1記載の半導体装置において、  4. The semiconductor device according to claim 1,
前記配線パターンは、 少なくとも一部に湾曲部を有し、 前記湾曲部が前記保持 板に接続される半導体装置。  The semiconductor device, wherein the wiring pattern has a curved portion at least in part, and the curved portion is connected to the holding plate.
5 . 請求項 1記載の半導体装置において、  5. The semiconductor device according to claim 1,
前記保持板は、 ハンダ及び導電性接着剤のうち少なくともいずれか一方によつ て、 前記配線パタ一ンの前記一定電位部と接続される半導体装置。  The semiconductor device, wherein the holding plate is connected to the fixed potential portion of the wiring pattern by at least one of a solder and a conductive adhesive.
6 . (補正後） 半導体素子と、 絶縁フィルムと、 前記絶縁フィルム上に形成され 楠正された用紙 (条約第 I9条） るとともに前記半導体素子に接続される配線パターンと、 前記配線パターン上に 形成される外部端子と、 導電性を有するとともに平面性を保つ部材からなリ前記 絶縁フィルムの一部を保持する保持板と、 を有し、 6. (After amendment) Semiconductor element, insulating film, and paper formed on said insulating film and polished (Article 9 of the Convention) A wiring pattern connected to the semiconductor element, an external terminal formed on the wiring pattern, and a holding plate holding a part of the insulating film, the member being made of a member having conductivity and maintaining flatness. , And
前記保持板は、 前記配線パターンの一定電位部に接続され、  The holding plate is connected to a constant potential portion of the wiring pattern,
前記保持板の熱膨張係数 >前記絶縁フィルムの熱膨張係数  Coefficient of thermal expansion of the holding plate> Coefficient of thermal expansion of the insulating film
の関係を有する半導体装置。 Semiconductor device having the following relationship.
7 . (削除）  7 (deleted)
8 . 請求項 6記載の半導体装置において、  8. The semiconductor device according to claim 6,
前記保持板は、 スリット又は溝を有し、  The holding plate has a slit or a groove,
前記絶縁フィルムの端部は、 前記スリツ ト又は溝に揷入されて前記保持板に保 持される半導体装置。  A semiconductor device in which an end of the insulating film is inserted into the slit or the groove and held by the holding plate.
9 . 請求項 6記載の半導体装置において、  9. The semiconductor device according to claim 6,
前記絶縁フィルムは、 スリットを有し、  The insulating film has a slit,
前記保持板は、 前記スリットを介して前記絶縁フィルムの反対側面に、 端部が 突出するように取り付けられる半導体装置。  The semiconductor device, wherein the holding plate is attached to an opposite side of the insulating film through the slit so that an end protrudes.
1 0 . (補正後） 絶縁フィルムに貫通孔を形成する工程と、  10. (After correction) a step of forming a through hole in the insulating film;
前記絶縁フィルムの一方の面側に前記貫通孔上を通る配線パターンを形成する 工程と、  Forming a wiring pattern passing over the through hole on one surface side of the insulating film;
前記配線パターンにおける前記絶縁フィルム側の面に前記貫通孔を介して前記 絶縁フィルムの他方の面側に突出する外部端子を形成する工程と、  Forming an external terminal projecting on the other surface side of the insulating film through the through hole on a surface of the wiring pattern on the insulating film side;
半導体素子を前記配線パターンに接続して前記絶縁フィルムに設ける工程と、 前記配線パターンの前記絶縁フィルムが設けられた面の反対面側に、 前記配線 パターンの少なくとも一部を覆うように、 導電性を有するとともに平面性を保つ 部材からなる保持板を貼り付ける工程と、  A step of connecting a semiconductor element to the wiring pattern and providing the insulating film on the insulating film; and forming a conductive pattern on the side of the wiring pattern opposite to the surface on which the insulating film is provided, so as to cover at least a part of the wiring pattern. A step of attaching a holding plate made of a member having flatness and having
前記配線パターンの一部を前記保持板に接続する工程と、  Connecting a part of the wiring pattern to the holding plate;
を含み、  Including
前記保持板の熱膨張係数 >前記絶縁フィルムの熱膨張係数  Coefficient of thermal expansion of the holding plate> Coefficient of thermal expansion of the insulating film
の関係を有する半導体装置の製造方法。 補 ΪΗされた用紙 (条約第 条） Of manufacturing a semiconductor device having the following relationship. Supplemented paper (Article of the Convention)
1 1 . 請求項 1 0記載の半導体装置の製造方法において、 11. The method for manufacturing a semiconductor device according to claim 10, wherein
前記保持板を、 絶縁性の接着剤を介して前記絶縁フィルムに貼り付ける半導体 装置の製造方法。  A method for manufacturing a semiconductor device, wherein the holding plate is attached to the insulating film via an insulating adhesive.
1 2 . 請求項 1 1記載の半導体装置の製造方法において、  12. The method for manufacturing a semiconductor device according to claim 11,
前記絶縁フィルムは、 前記配線パターンに対応する開口部を有し、  The insulating film has an opening corresponding to the wiring pattern,
前記絶縁フィルムの前記他方の面から前記開口部を介して加圧治具を押し入れ て、 前記配線パターンの一部を、 屈曲させて前記保持板に接続する半導体装置の 製造方法。  A method of manufacturing a semiconductor device, wherein a pressing jig is pushed in from the other surface of the insulating film through the opening, and a part of the wiring pattern is bent and connected to the holding plate.
1 3 . (補正後） 絶縁フィルムに配線パターンを形成する工程と、 半導体素子を 前記配線パターンに接続して前記絶縁フィルムに設ける工程と、 前記絶縁フィル ムの端部を保持する保持板を取り付ける工程と、 前記配線パターンの一部を前記 保持板に電気的に接続する工程と、 を含み、  13. After the correction, a step of forming a wiring pattern on the insulating film, a step of connecting a semiconductor element to the wiring pattern and providing the same on the insulating film, and attaching a holding plate for holding an end of the insulating film And electrically connecting a part of the wiring pattern to the holding plate,
前記保持板の熱膨張係数 >前記絶縁フィルムの熱膨張係数  Coefficient of thermal expansion of the holding plate> Coefficient of thermal expansion of the insulating film
の関係を有する半導体装置の製造方法。 Of manufacturing a semiconductor device having the following relationship.
1 4 . 請求項 1から請求項 5のいずれかに記載の半導体装置と、 所望の導電バタ —ンが形成された基板と、 を有し、  14. The semiconductor device according to any one of claims 1 to 5, and a substrate on which a desired conductive pattern is formed,
前記半導体装置の前記外部端子が前記導電パターンに接続された回路基板。 A circuit board in which the external terminals of the semiconductor device are connected to the conductive pattern.
1 5 . (補正後） 半導体素子と、 絶縁フィルムと、 前記絶縁フィルムに形成され て前記半導体素子に接続される配線パターンと、 前記配線パターン上に形成され るバンプと、 導電性を有するとともに平面性を保つ部材からなリ前記配線パタ一 ンに電気的に接続される保持材と、 を含み、 15. After the correction, a semiconductor element, an insulating film, a wiring pattern formed on the insulating film and connected to the semiconductor element, a bump formed on the wiring pattern, and a conductive and planar surface A holding member electrically connected to the wiring pattern, the holding member being a member that maintains the property.
前記保持板の熱膨張係数 >前記絶縁フィルムの熱膨張係数  Coefficient of thermal expansion of the holding plate> Coefficient of thermal expansion of the insulating film
の関係を有する半導体装置と、 A semiconductor device having the relationship:
所望の導電パターンが形成され、 前記絶縁フィルムの少なくとも端部と接着剤 にて固定される基板と、  A substrate on which a desired conductive pattern is formed and which is fixed to at least an end portion of the insulating film with an adhesive;
を有する回路基板。  A circuit board having
1 6 . (補正後） ハンダバンプが形成された絶縁フィルムと、 導電性を有すると ともに平面性を保つ部材からなり前記配線パターンに電気的に接続される保持材 補正されだ用紙 (条約第 19 と、 を有し、 16 (After correction) An insulating film on which solder bumps are formed, and a holding material that is made of a member that has conductivity and maintains flatness and is electrically connected to the wiring pattern. And
前記保持板の熱膨張係数 >前記絶縁フィルムの熱膨張係数  Coefficient of thermal expansion of the holding plate> Coefficient of thermal expansion of the insulating film
の関係を有する半導体装置の実装方法において、 In the mounting method of the semiconductor device having the relationship of
前記絶縁フィルムの少なくとも端部に接着剤を塗布して回路基板に接着してか ら、 ハンダバンプを溶融させて前記回路基板のパッドに接続する半導体装置の実 装方法。  A method of mounting a semiconductor device in which an adhesive is applied to at least an end portion of the insulating film and bonded to a circuit board, and then solder bumps are melted and connected to pads of the circuit board.
補正された用紙 (条約第 19条) 条約 1 9条に基づく説明書 請求の範囲第 1 、 6、 1 0、 1 3、 1 5及び 1 6項のそれぞれは、 Amended paper (Article 19 of the Convention) Statements under Article 19 of the Convention Each of claims 1, 6, 10, 13, 15, and 16
前記保持板の熱膨張係数 >前記絶縁フィルムの熱膨張係数  Coefficient of thermal expansion of the holding plate> Coefficient of thermal expansion of the insulating film
の関係を有することを明確にした。 Clarified that there is a relationship.
これにより本発明は、 リフロー工程で保持板から絶緣フィルムにテンションが かかり、 絶縁フィルムが張るようになり、 その結果平坦性が得られるという効果 を得ることができる。  As a result, the present invention exerts an effect that tension is applied to the insulating film from the holding plate in the reflow step, so that the insulating film is stretched, and as a result, flatness can be obtained.
引用例には、 このような構成及び効果について全く記載されていない。  The cited example does not describe such a configuration and effect at all.
PCT/JP1998/000338 1997-02-13 1998-01-28 Semiconductor device and method for manufacturing and mounting thereof, and circuit board mounted with the semiconductor device WO1998036450A1 (en)

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JP53555498A JP3586867B2 (en) 1997-02-13 1998-01-28 Semiconductor device, method of manufacturing the same, method of mounting the same, and circuit board mounting the same
AU56782/98A AU5678298A (en) 1997-02-13 1998-01-28 Semiconductor device and method for manufacturing and mounting thereof, and circuit board mounted with the semiconductor device

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EP1189273A2 (en) * 2000-09-14 2002-03-20 Shinko Electric Industries Co. Ltd. Semiconductor device and production process

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