WO1994025987A1 - Semiconductor chip encapsulation method, device produced by this method and its application to three dimensional chip interconnection - Google Patents
Semiconductor chip encapsulation method, device produced by this method and its application to three dimensional chip interconnection Download PDFInfo
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- WO1994025987A1 WO1994025987A1 PCT/FR1994/000427 FR9400427W WO9425987A1 WO 1994025987 A1 WO1994025987 A1 WO 1994025987A1 FR 9400427 W FR9400427 W FR 9400427W WO 9425987 A1 WO9425987 A1 WO 9425987A1
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- pellets
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- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
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Definitions
- the subject of the present invention is a method of encapsulating semiconductor wafers as well as the resulting device, each of the wafers containing for example an electronic component, an integrated circuit or a sensor. It also relates to the application of such encapsulation to the three-dimensional interconnection of these pellets.
- the pellets are stacked after having been provided with connection wires oriented towards the lateral faces of the stack, then they are made integral with one another, for example using a resin; the interconnections of the pellets are then made on the faces of the stack.
- the object of the present invention is to modify this process in particular to make it easier to integrate into a semiconductor factory and to reduce its cost.
- cables are conductors, wires for example, directly on a semiconductor washer carrying a large number of pads; the washer being glued on an elastic film, the washer is sawn to individualize the pellets and then the film is stretched so as to spread the pellets; we then join all the pellets and the wires in an insulating material, polymerizable resin for example, then, after polishing, metallic deposits are produced above the wires so as to connect the latter to the sides of the pellets; the assembly is then cut so as to separate the pellets: we then obtain pellets encapsulated in a coating forming a housing, provided with connections.
- FIG. 1 therefore represents an embodiment of the method according to the invention.
- the first step, marked 10 consists in fixing (for example gluing), on an elastic film, a washer of semiconductor material (also known by the English name of "wafer"), in which a large number of pads (usually in the order of several hundred), each containing an integrated circuit or discrete component; the film is for example a self-adhesive polymer type.
- the second step, marked 11, consists in wiring electrical conductors, wires or ribbons, on each of the connection pads of each of the pads contained in the washer.
- FIG. 2 The result of these operations is illustrated in FIG. 2.
- a semiconductor washer 1 has been shown in which a pad 21 has been identified.
- the washer 1 is mounted on the elastic film, marked 2.
- conductors 23, for example wires are connected vertically using the technique called "bail bonding" and consisting of melting the end of the wire 23 to obtain a small ball 24, facilitating its connection to the pad 22.
- Other techniques can be used, as illustrated for example below in FIG. 7.
- the wires 23 are each cut at a predetermined height, which can for example be 150 to 200 ⁇ m, for a wire diameter of about 25 to 30 ⁇ m, a thickness of washer of the order of 500 ⁇ m and of film 2 of the order of 200 ⁇ m, for example.
- the next step (12, Figure 1) consists in sawing the washer 2 preferably over its entire thickness, so as to individualize the pellets such as 21.
- the next step, marked 13, consists in uniformly stretching the elastic film (2); this has the effect of spreading the pellets (21) from each other and, this, regularly. It should be noted that the step 11 of wiring the wires on the washer (1) can, in an alternative embodiment, be carried out only after this step 13 of stretching the elastic film (2).
- the next step, marked 14 consists of joining the pellets and their connection wires and coating the whole in an electrically insulating material, for example an organic resin, epoxy or polyimide, by a casting or molding technique for example, the the material then being, where appropriate, polymerized.
- an electrically insulating material for example an organic resin, epoxy or polyimide
- the next step, marked 15, consists in polishing the upper face (27, FIG. 3) of the coating material 25, so as to obtain a flat surface on which the sections of the wires 23 are flush.
- the thickness of the coating material 25 depends on that of the washer 1 and of the materials concerned, in particular for thermo-mechanical reasons. For example, for a washer 400 to 500 ⁇ m thick, the material 25 can be approximately 150 ⁇ m.
- the next step (16, Figure 1) is to remove the elastic film 2.
- the rear face of the assembly, marked 28 in FIG. 3, is polished, that is to say the face opposite to face 27 to remove the film 2 and / or to thin the pellets 21 in order to reduce the thickness and size, which can be particularly advantageous in the application described below of stacking the pellets encapsulated in three dimensions.
- the elastic film 2 is not removed, which then makes it possible to isolate and / or protect the rear face 28 of the patch.
- the next step, marked 17, consists in making connections connecting each of the conductors 23 to what will become the lateral face of the pads after separation, these connections being made by metallizations on the upper face 27 above the inter-pad interval .
- FIGS 4a and 4b illustrate this step, seen respectively in section and from above.
- FIG. 4a represents the pellets 21 with their wires 23 embedded in the material 25.
- the upper face 27 of the assembly carries metallizations 30 above the wires 23, metallizations which connect each of the wires 23 to the gap 26 between pads.
- These metallizations can take different forms as illustrated in the top view of FIG. 4b: they can connect a wire 23 to the inter-pad area 26, connect two wires 23 of different pads together or further connect a wire 23 to an area 31, used later for testing the pellets for example.
- connections 30 can be made by any known means, for example depositing a metal layer and subsequent etching of this layer.
- the deposit can be a metallic deposit such as gold, nickel and gold, nickel-copper and gold, copper and gold, carried out for example under vacuum by cathodic sputtering, optionally recharged electrochemically.
- the subsequent engraving may for example be a photoengraving.
- a so-called reverse photoengraving that is to say leaving the metal everywhere except around the conductors, the latter making it possible in addition to produce electromagnetic shielding.
- the last step in the production of the encapsulated pellets (step 18, in FIG. 1) consists in the separation of the pellets. This separation is carried out by cutting the material 25 between the pellets, for example using a diamond saw. Semiconductor wafers are then obtained, each coated on five of their faces in an insulating material forming a housing, the latter being provided with connections (metallizations 30), which can be tested and manipulated.
- step 19, Figure 1 When we want to achieve with pellets thus encapsulated a three-dimensional stack (step 19, Figure 1), we have the boxes in a slide allowing to align two of the side faces of the boxes, thus simplifying the problems of relative positioning of the boxes . Between the housings are arranged layers of adhesive material, such as a polymerizable resin for example. Then the assembly is pressed and optionally it is polymerized, so as to secure it.
- adhesive material such as a polymerizable resin for example
- FIG. 5 where there are the pellets 21 and their coating material 25, separated from each other by an adhesive layer 32.
- the film is used elastic 2, an adhesive material - or made adhesive by an appropriate treatment - which is left in place, thus avoiding the interposition of the layers 32.
- On each of the end faces of the stack there is also a closing layer 42 non-adhesive, which is fixed by means of a layer 32.
- the closure layers 42 can be adhesive on one of their faces, thus avoiding the layer 32.
- the metallizations 30 connect each of the conductors 23 to the edge 35 of the stack.
- the next step (20, FIG. 1) consists in interconnecting the various pellets of the stack and in connecting them, if necessary, to pads, called stack pads, allowing their connection to external circuits. These interconnections are made on the faces of the stack, for example as described in the aforementioned French patent application.
- Figure 5 there is shown by way of example the different connections 30 all connected together using a metallization 33 disposed on the face of the stack and extending (34) for example on one or on both of the end faces of the stack. In the latter case, one of the faces can be used for the test while the other is used for mounting the stack on a printed circuit for example.
- the cooling of the pellets in operation can be improved by the insertion of thermal drains between the housings, possibly connected to a radiator.
- a heat sink 38 metallic layer for example, of copper or nitride aluminum, or even diamond, is placed between each pellet 21 by means of a layer of glue 36.
- the left lateral face of the stack is for example glued, by means of a layer of glue 39, preferably thermally conductive, to a radiator 37, which is thus in thermal contact with the drains 38.
- glue 39 preferably thermally conductive
- step 11 of Figure 1 shows, in sectional view, an alternative embodiment of step 11 of Figure 1, namely the wiring of conductors on the washer.
- the washer 1 mounted on its elastic film 2 and carrying pads 22, on which one wishes to wire conductors 23.
- the upper face of the washer 1 is provided with pieces of substrate of the circuit type printed 39, preferably at least one per patch, the printed circuit 39 being fixed on the washer using for example a layer of glue 40.
- the printed circuit 39 carries at least one metallization 41.
- the conductor 23 is no longer cut but it is curved so as to be moreover connected to the metallization 41 carried by the printed circuit 39.
- the conductor 23 can be connected vertically to the pad 22 as shown in the preceding figures or as shown in FIG. 7, connected horizontally as in metallization 41.
- the method described above, as well as the devices obtained, have a certain number of advantages among which the fact that it is possible to process a large number of pellets simultaneously (all those which belong to the same washer) and, this , with techniques known in the semiconductor industry, easily integrated into a production line for semiconductor circuits, which considerably reduces the cost of the encapsulated chip and which makes it possible, by the techniques used, to obtain very small dimensions, in particular by the coating material, which can typically represent an increase in the area (of the pellet) of less than 1%.
- the encapsulation mode is well suited to a "three-dimensional" stack, which can be carried out collectively and simply, with the cost advantages which result therefrom.
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP94913654A EP0647357A1 (en) | 1993-04-27 | 1994-04-15 | Semiconductor chip encapsulation method, device produced by this method and its application to three dimensional chip interconnection |
JP6523941A JPH07509104A (en) | 1993-04-27 | 1994-04-15 | Method for encapsulating semiconductor chips, device obtained by this method, and application to three-dimensional chip interconnection |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9304962A FR2704690B1 (en) | 1993-04-27 | 1993-04-27 | Method for encapsulating semiconductor wafers, device obtained by this process and application to the interconnection of wafers in three dimensions. |
FR93/04962 | 1993-04-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1994025987A1 true WO1994025987A1 (en) | 1994-11-10 |
Family
ID=9446488
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR1994/000427 WO1994025987A1 (en) | 1993-04-27 | 1994-04-15 | Semiconductor chip encapsulation method, device produced by this method and its application to three dimensional chip interconnection |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0647357A1 (en) |
JP (1) | JPH07509104A (en) |
FR (1) | FR2704690B1 (en) |
WO (1) | WO1994025987A1 (en) |
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0257119A1 (en) * | 1986-08-22 | 1988-03-02 | Ibm Deutschland Gmbh | Integrated wiring system for VLSI |
DE3719742A1 (en) * | 1987-06-12 | 1988-12-29 | Siemens Ag | Arrangement and method for separation of the semiconductor chips contained in a wafer whilst maintaining their order |
WO1990011629A1 (en) * | 1989-03-17 | 1990-10-04 | Cray Research, Inc. | Memory metal electrical connector |
FR2645681A1 (en) * | 1989-04-07 | 1990-10-12 | Thomson Csf | Vertical interconnection device for integrated-circuit chips and its method of manufacture |
WO1991000619A1 (en) * | 1989-06-30 | 1991-01-10 | Raychem Corporation | Flying leads for integrated circuits |
WO1992017901A1 (en) * | 1991-03-27 | 1992-10-15 | Integrated System Assemblies Corporation | Multichip integrated circuit module and method of fabrication |
-
1993
- 1993-04-27 FR FR9304962A patent/FR2704690B1/en not_active Expired - Fee Related
-
1994
- 1994-04-15 EP EP94913654A patent/EP0647357A1/en not_active Withdrawn
- 1994-04-15 WO PCT/FR1994/000427 patent/WO1994025987A1/en not_active Application Discontinuation
- 1994-04-15 JP JP6523941A patent/JPH07509104A/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0257119A1 (en) * | 1986-08-22 | 1988-03-02 | Ibm Deutschland Gmbh | Integrated wiring system for VLSI |
DE3719742A1 (en) * | 1987-06-12 | 1988-12-29 | Siemens Ag | Arrangement and method for separation of the semiconductor chips contained in a wafer whilst maintaining their order |
WO1990011629A1 (en) * | 1989-03-17 | 1990-10-04 | Cray Research, Inc. | Memory metal electrical connector |
FR2645681A1 (en) * | 1989-04-07 | 1990-10-12 | Thomson Csf | Vertical interconnection device for integrated-circuit chips and its method of manufacture |
WO1991000619A1 (en) * | 1989-06-30 | 1991-01-10 | Raychem Corporation | Flying leads for integrated circuits |
WO1992017901A1 (en) * | 1991-03-27 | 1992-10-15 | Integrated System Assemblies Corporation | Multichip integrated circuit module and method of fabrication |
Non-Patent Citations (1)
Title |
---|
11th IEEE/CHMT Intl.Electronics Manufacturing Technology Symposium, San Francico, USA, September 16-18, 1991, p. 80-84, C. MEISSER: "Modern Bonding Processes for Large-Scale * |
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US8513794B2 (en) | 2007-08-09 | 2013-08-20 | Tessera, Inc. | Stacked assembly including plurality of stacked microelectronic elements |
US8704379B2 (en) | 2007-09-10 | 2014-04-22 | Invensas Corporation | Semiconductor die mount by conformal die coating |
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US9490230B2 (en) | 2009-10-27 | 2016-11-08 | Invensas Corporation | Selective die electrical insulation by additive process |
US9147583B2 (en) | 2009-10-27 | 2015-09-29 | Invensas Corporation | Selective die electrical insulation by additive process |
US8912661B2 (en) | 2009-11-04 | 2014-12-16 | Invensas Corporation | Stacked die assembly having reduced stress electrical interconnects |
US9490195B1 (en) | 2015-07-17 | 2016-11-08 | Invensas Corporation | Wafer-level flipped die stacks with leadframes or metal foil interconnects |
US9666513B2 (en) | 2015-07-17 | 2017-05-30 | Invensas Corporation | Wafer-level flipped die stacks with leadframes or metal foil interconnects |
US9825002B2 (en) | 2015-07-17 | 2017-11-21 | Invensas Corporation | Flipped die stack |
US9871019B2 (en) | 2015-07-17 | 2018-01-16 | Invensas Corporation | Flipped die stack assemblies with leadframe interconnects |
US9508691B1 (en) | 2015-12-16 | 2016-11-29 | Invensas Corporation | Flipped die stacks with multiple rows of leadframe interconnects |
US9859257B2 (en) | 2015-12-16 | 2018-01-02 | Invensas Corporation | Flipped die stacks with multiple rows of leadframe interconnects |
US10566310B2 (en) | 2016-04-11 | 2020-02-18 | Invensas Corporation | Microelectronic packages having stacked die and wire bond interconnects |
US9595511B1 (en) | 2016-05-12 | 2017-03-14 | Invensas Corporation | Microelectronic packages and assemblies with improved flyby signaling operation |
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Also Published As
Publication number | Publication date |
---|---|
FR2704690A1 (en) | 1994-11-04 |
JPH07509104A (en) | 1995-10-05 |
FR2704690B1 (en) | 1995-06-23 |
EP0647357A1 (en) | 1995-04-12 |
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