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FR2704690B1 - Method for encapsulating semiconductor wafers, device obtained by this process and application to the interconnection of wafers in three dimensions. - Google Patents

Method for encapsulating semiconductor wafers, device obtained by this process and application to the interconnection of wafers in three dimensions.

Info

Publication number
FR2704690B1
FR2704690B1 FR9304962A FR9304962A FR2704690B1 FR 2704690 B1 FR2704690 B1 FR 2704690B1 FR 9304962 A FR9304962 A FR 9304962A FR 9304962 A FR9304962 A FR 9304962A FR 2704690 B1 FR2704690 B1 FR 2704690B1
Authority
FR
France
Prior art keywords
chips
wafers
interconnection
dimensions
application
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9304962A
Other languages
French (fr)
Other versions
FR2704690A1 (en
Inventor
Val Christian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Priority to FR9304962A priority Critical patent/FR2704690B1/en
Priority to EP94913654A priority patent/EP0647357A1/en
Priority to PCT/FR1994/000427 priority patent/WO1994025987A1/en
Priority to JP6523941A priority patent/JPH07509104A/en
Publication of FR2704690A1 publication Critical patent/FR2704690A1/en
Application granted granted Critical
Publication of FR2704690B1 publication Critical patent/FR2704690B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

According to the method of the invention, conductive leads are directly wired onto a semiconductor wafer carrying a large number of chips, the wafer is bonded to a resilient film and cut to separate each chip, after which the film is stretched to space the chips; the totality of the chips and leads are then held in an insulating material such as a polymerizable resin, and, after polishing, metal plating is applied over the leads to connect them to the sides of the chips; the assembly is then cut in order to separate the chips.
FR9304962A 1993-04-27 1993-04-27 Method for encapsulating semiconductor wafers, device obtained by this process and application to the interconnection of wafers in three dimensions. Expired - Fee Related FR2704690B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR9304962A FR2704690B1 (en) 1993-04-27 1993-04-27 Method for encapsulating semiconductor wafers, device obtained by this process and application to the interconnection of wafers in three dimensions.
EP94913654A EP0647357A1 (en) 1993-04-27 1994-04-15 Semiconductor chip encapsulation method, device produced by this method and its application to three dimensional chip interconnection
PCT/FR1994/000427 WO1994025987A1 (en) 1993-04-27 1994-04-15 Semiconductor chip encapsulation method, device produced by this method and its application to three dimensional chip interconnection
JP6523941A JPH07509104A (en) 1993-04-27 1994-04-15 Method for encapsulating semiconductor chips, device obtained by this method, and application to three-dimensional chip interconnection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9304962A FR2704690B1 (en) 1993-04-27 1993-04-27 Method for encapsulating semiconductor wafers, device obtained by this process and application to the interconnection of wafers in three dimensions.

Publications (2)

Publication Number Publication Date
FR2704690A1 FR2704690A1 (en) 1994-11-04
FR2704690B1 true FR2704690B1 (en) 1995-06-23

Family

ID=9446488

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9304962A Expired - Fee Related FR2704690B1 (en) 1993-04-27 1993-04-27 Method for encapsulating semiconductor wafers, device obtained by this process and application to the interconnection of wafers in three dimensions.

Country Status (4)

Country Link
EP (1) EP0647357A1 (en)
JP (1) JPH07509104A (en)
FR (1) FR2704690B1 (en)
WO (1) WO1994025987A1 (en)

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US7829438B2 (en) 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US7943952B2 (en) 2006-07-31 2011-05-17 Cree, Inc. Method of uniform phosphor chip coating and LED package fabricated using method
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
US8167674B2 (en) 2007-12-14 2012-05-01 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US8232564B2 (en) 2007-01-22 2012-07-31 Cree, Inc. Wafer level phosphor coating technique for warm light emitting diodes
US8337071B2 (en) 2005-12-21 2012-12-25 Cree, Inc. Lighting device
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US8637883B2 (en) 2008-03-19 2014-01-28 Cree, Inc. Low index spacer layer in LED devices
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
US8878219B2 (en) 2008-01-11 2014-11-04 Cree, Inc. Flip-chip phosphor coating method and devices fabricated utilizing method
US8969908B2 (en) 2006-04-04 2015-03-03 Cree, Inc. Uniform emission LED package
US9024349B2 (en) 2007-01-22 2015-05-05 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US9041285B2 (en) 2007-12-14 2015-05-26 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US9093616B2 (en) 2003-09-18 2015-07-28 Cree, Inc. Molded chip fabrication method and apparatus
US9159888B2 (en) 2007-01-22 2015-10-13 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US9166126B2 (en) 2011-01-31 2015-10-20 Cree, Inc. Conformally coated light emitting devices and methods for providing the same

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JP2000124354A (en) * 1998-10-21 2000-04-28 Matsushita Electric Ind Co Ltd Chip-size package and its manufacture
JP3235586B2 (en) * 1999-02-25 2001-12-04 日本電気株式会社 Semiconductor device and method of manufacturing semiconductor device
JP3065309B1 (en) 1999-03-11 2000-07-17 沖電気工業株式会社 Method for manufacturing semiconductor device
JP4422380B2 (en) * 1999-10-01 2010-02-24 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
DE10023539B4 (en) * 2000-05-13 2009-04-09 Micronas Gmbh Method for producing a component
JP2004501517A (en) * 2000-06-20 2004-01-15 ナノネクサス　インコーポレイテッド System for testing and packaging integrated circuits
US20020100600A1 (en) * 2001-01-26 2002-08-01 Albert Douglas M. Stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same
DE10137184B4 (en) * 2001-07-31 2007-09-06 Infineon Technologies Ag Method for producing an electronic component with a plastic housing and electronic component
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