US9344273B2

US9344273B2 - Cryptographic device for implementing S-box

Info

Publication number: US9344273B2
Application number: US14/291,665
Authority: US
Inventors: Hong-Mook Choi; Xingguang FENG
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2009-12-01
Filing date: 2014-05-30
Publication date: 2016-05-17
Anticipated expiration: 2030-09-24
Also published as: US20160112194A1; KR101646705B1; US8750497B2; US20110129085A1; KR20110061280A

Abstract

Provided is a cryptographic device implementing an S-Box of an encryption algorithm using a many-to-one binary function. The cryptographic device includes: arrays of first logic gates including I first logic gates which each receive 2 bits of an input signal; 2^Nsecond logic gates which each receive corresponding J bits from among I bits output from the arrays of the first logic gates; and L third logic gates which each receive K bits from among 2^Nbits output from the second logic gates, wherein there is a many-to-one correspondence between the N bits of the input signal and the K bits input to each of the third logic gates, and wherein the N, I, J, K, and L are positive integers. Because a signal output from each array includes only one active bit, current is always consumed constantly to prevent internal data from leaking out to a hacker.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation application of U.S. application Ser. No. 12/889,854, filed Sep. 24, 2010, which claims priority from Korean Patent Application No. 10-2009-0117881, filed on Dec. 1, 2009 in the Korean Intellectual Property Office, the entirety of which is hereby incorporated by reference.

BACKGROUND

1. Field

Apparatuses and methods consistent with exemplary embodiments relate to a cryptographic device.

2. Description of Related Art

In recent years, information transmitted by a user in communications using a smart card or an integrated circuit (IC) card, Internet communications, wireless local area network (LAN) communications, and Internet banking include secret information. Secret information may be leaked by hacking. Therefore, hardware encryption/decryption devices are increasingly being used to prevent the leakage of secret information. Prior to transmission of secret information receiving a signature or passing an authentication procedure, the hardware encryption/decryption device transforms the secret information into a cryptogram.

Because speed of an encryption operation is typically low, most encryption operations are carried out using hardware to be applied to devices such as a smart card. Data encryption standard (DES) is a type of block encryption algorithm and a symmetric key encryption scheme using 56 bits of a key. A substitution box (hereinafter referred to as “S-Box”) for use in DES carries out a substitution operation to convert an m-bit input into an n-bit output.

When DES is embodied with hardware, an S-Box is designed using a lookup table. However, a data value of the S-Box may be exposed to a hacker according to a hardware design technique. Accordingly, there is a need for the hardware design for an S-Box that is capable of preventing exposure of internal data even when the S-Box is attacked by a hacker.

SUMMARY

Exemplary embodiments provide a cryptographic device.

According to an aspect of an exemplary embodiment, there is provided a cryptographic device including: arrays of first logic gates including I first logic gates each receiving 2 bits from among N bits of an input signal, where I and N are positive integers; 2^Nsecond logic gates each receiving corresponding J bits from among I bits output from the arrays of first logic gates, where J is a positive integer; and L third logic gates each receiving K bits from among 2^Nbits of signal output from the second logic gates, where L and K are positive integers, wherein the I bits, the 2^Nbits, and L bits respectively output from the arrays of the first logic gates, the second logic gates, and the third logic gates each have only one active bit, and there is a many-to-one correspondence between the N bits of the input signal and an output signal of the third logic gates.

According to an aspect of an exemplary embodiment, there is provided a cryptographic device including: an array of first logic gates receiving first 2 bits among 6 bits of an input signal and outputting first 4 bits; an array of second logic gates receiving second 2 bits among the 6 bits of the input signal and outputting second 4 bits; an array of third logic gates receiving third 2 bits among the 6 bits of the input signal and outputting third 4 bits; 64 forth logic gates each receiving corresponding 3 bits from among the 4 bits output from the arrays of the first, second, and third logic gates; and 16 fifth logic gates each receiving 4 bits from among the 64 bits output from the fourth logic gates, wherein the 4 bits, the 64 bits, and the 16 bits respectively output from the arrays of the first, second, and third logic gates, the fourth logic gates, and the fifth logic gates each have only one active bit, and there is a many-to-one correspondence between the 6 bits of the input signal and an output signal of the fifth logic gates.

According to an aspect of another exemplary embodiment, there is provided a cryptographic device including: a first decoder which decodes an input signal of N bits into 2^Nbits; and a second decoder which decodes the 2^Nbits output from the first decoder into L bits, wherein the 2^Nbits output from the first decoder and the L bits output from the second decoder each include only one active bit, and wherein N and L are positive integers.

According to an aspect of another exemplary embodiment, there is provided a cryptographic method including: receiving, at each of arrays of first logic gates comprising I first logic gates, 2 bits from among N bits of an input signal; receiving, at each of 2^Nsecond logic gates, corresponding J bits from among I bits output from the arrays of the first logic gates; and receiving, at each of L third logic gates, K bits from among 2^Nbits output from the second logic gates, wherein the I bits, the 2^Nbits, and L bits respectively output from the arrays of the first logic gates, the second logic gates, and the third logic gates each have only one active bit, wherein there is a many-to-one correspondence between the N bits of the input signal and an output signal of the third logic gates, and wherein the N, I, J, K, and L are positive integers, respectively.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments will become more apparent in view of the attached drawings and accompanying detailed description. The exemplary embodiments depicted therein are provided by way of example, not by way of limitation, wherein like reference numerals refer to the same or similar elements. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating aspects of the exemplary embodiments, wherein:

FIG. 1 illustrates a cryptographic device according to an exemplary embodiment;

FIG. 2 illustrates a cryptographic device according to another exemplary embodiment;

FIG. 3 illustrates a detailed circuit configuration of arrays of logic gates shown in FIG. 2 according to an exemplary embodiment;

FIG. 4 illustrates an S-Box lookup table according to an exemplary embodiment;

FIG. 5 illustrates an example of a cryptographic device having a reset function according to an exemplary embodiment; and

FIG. 6 illustrates a circuit configuration of arrays of logic gates shown in FIG. 2 according to another exemplary embodiment.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings.

FIG. 1 illustrates a cryptographic device 100 according to an exemplary embodiment. As illustrated, the cryptographic device 100 includes a first decoder 110, a second decoder 120, and an encoder 130. The first decoder 110 receives an input signal IN which is 6 bits and outputs 64 bits. The 64 bit output from the first decoder 110 includes one active bit from among the 64 bits according to the 6 bits of the input signal IN.

The second decoder 120 decodes the 64 bits from the first decoder 110 into 16 bits. Irrespective of a value of the 6 bits of the input signal IN, power consumed in the first and

second decoders

110 and 120 is constantly maintained. As a result, the cryptographic device 100 may be protected from a hacker's attack, such as a differential power attack (DPA) and an attack through electromagnetic (EM) detection.

The encoder 130 encodes the 16 bits output from the second decoder 120 into a 4 bit output signal OUT and outputs the output signal OUT. The cryptographic device 100 shown in FIG. 1 may convert 6 bits of input signal IN into 4 bits of output signal OUT according to an S-Box many-to-one binary function.

FIG. 2 illustrates a cryptographic device 200 according to another exemplary embodiment. As illustrated, the cryptographic device 200 includes

arrays

211, 212, and 213 of first logic gates, an array 220 of second logic gates, an array 230 of third logic gates, and an encoder 240. The array 211 of the first logic gates receives 2 bits A0 and A1 from among bits of an input signal IN and outputs 4 bits B0, B1, B2, and B3. The array 211 of the first logic gates includes a plurality of logic gates (not shown) each receiving 2 bits A0 and A1. The

other arrays

212 and 213 of the first logic gates are organized with the same or similar circuit structure as the array 211 of the first logic gates and perform the same or similar operations as the array 211 of the first logic gates. Each of the

arrays

211, 212, and 213 receives different 2 bits from among the bits of the input signal IN and outputs 4 bits. That is, the

arrays

211, 212, and 213 output a total of 12 bits B0˜B11.

The array 220 of the second logic gates receives the 12 bits from the

arrays

211, 212, and 213 of the first logic gates and outputs 64 bits C0˜C63. The array 220 of the second logic gates includes a plurality of logic gates (not shown) each receiving 1 bit from each of the

arrays

211, 212, and 213 of the first logic gates (i.e., each receiving a total of 3 bits).

The array 230 of the third logic gates receives the 64 bits C0˜C63 from the array 220 of the second logic gates and outputs 16 bits D0˜D15 corresponding to the 64 bits C0˜C63. The array 230 of the third logic gates includes a plurality of logic gates (not shown) each receiving 4 bits from among the 64 bits C0˜C64 from the array 220 of the second logic gates. There is a many-to-one correspondence according to an S-Box binary function between 6 bits of the input signal IN and a K-bit signal input to the respective logic gates in the array 230 of the third logic gates.

The encoder 240 outputs the 16 bits D0˜D15 output from the array 230 of the third logic gates, as a 4 bit signal OUT. The encoder 240 encodes the 16 bits D0˜D15 into 4 bits of signal OUT. The encoder 240 may be designed to constantly consume current although the 16 bits of signals D0˜D15 have any value. Thus, the cryptographic device 200 shown in FIG. 2 may substitute 6 bits of input signal IN with 4 bits of output signal OUT according to an S-Box binary function.

In the

respective arrays

211, 212, 213, 220, and 230, one of respective logic gates constructed therein (i.e., a total five logic gates) outputs an active bit (or inactive bit) although an input signal IN has any value. Therefore, power is constantly consumed irrespective of the input signal IN.

FIG. 3 illustrates a detailed circuit configuration of arrays of logic gates shown in FIG. 2 according to an exemplary embodiment. Referring to FIG. 3, the array 211 of the first logic gates include two

inverters

301 and 302 and four AND gates 303˜306. The inverter 301 receives an input signal A0, and the inverter 302 receives an input signal A1. The AND gate 303 receives the input signals A0 and A1. The AND gate 304 receives the input signal A0 and an output of the inverter 302. The AND gate 305 receives an output of the inverter 301 and the input signal A1. The AND gate 306 receives outputs of the

inverters

301 and 302. The array 211 of the first logic gates receive 2 bits A0 and A1 and outputs 4 bits through the AND gates 303˜306. The

arrays

212 and 213 of other first logic gates are organized with the same or similar structures as the array 211 of the first logic gates. The array 212 of the first logic gates receives input signals A2 and A3 and the array 213 of the first logic gates receives input signals A4 and A5.

In the array 211 of the first logic gates, only one AND gate among the four AND gates 303˜306 is toggled according to the input signals A0 and A1. That is, only one bit among four bits B0˜B3 output from the four AND gates 303˜306 is an active bit that is a high level. Since the array 211 of the first logic gates always outputs one active bit for all cases of the input signals A0 and A1, current consumed at the array 211 of the first logic gates is always constant. Similar to the array 212 of the first logic gates, each of the

other arrays

212 and 213 of the first logic gates outputs only one active bit.

The array 220 of the second logic gates includes 64 AND gates 311. Each of the AND gates 311 includes three input terminals and an output terminal. Furthermore, each of the AND gates 311 receives 1 bit from each of the

arrays

211, 212, and 213 of the first logic gates (i.e., each of the AND gates 311 receives a total of 3 bits). More specifically, each of the AND gates 311 in the array 220 of the second logic gates receives 1 bit from among the 4 bits B0˜B3, 1 bit from among the 4 bits B4˜B7, and 1 bit from among the 4 bits B9˜B11. The 64 bits C0˜C63 output from the array 220 of the second logic gates are decoding signals according to the number of cases (2⁶) of A0, A1, A2, A3, A4, and A5. Only one of the 64 AND gates 311 in the array 220 of the second logic gates is toggled according to 12 bits B0˜B11 output from the arrays 211˜213 of the first logic gates. That is, among the 64 bits C0˜C63 output from the 64 AND gates 311 in the array 220 of the second logic gates, only one bit is an active bit.

The array 230 of the third logic gates includes 16 OR gates 321. Each of the OR gates 321 includes four input terminals and one output terminal. Each of the OR gates 321 receives 4 bits from among the 64 bits C0˜C63 output from the array 230 of the second logic gates. The 4 bits input to each of the OR gates 321 are determined according to an S-Box lookup table.

FIG. 4 illustrates an S-Box lookup table according to an exemplary embodiment. Although a DES algorithm uses a total of eight S-Boxes, FIG. 4 shows one S-Box. Referring to FIG. 4, the lookup table shows 4 output bits to 6 bits of input signal A0˜A5. Among the 6 bits A0˜A5, 2 bits A0 and A5 designate rows of the lookup table and four bits A1, A2, A3, and A4 designate columns of the lookup table. For example, when the input signal A0˜A5 is “110110”, “0111” of a position designated by a column “1011” of a row “10” designated by the 2 bits A0 and A5 is selected as an output signal. In this case, the output signal “0111” is designated by not only the row “10” and the column “1011” but also a row “00” and a column “1111,” a row “01” and a column “0010,” and a row “11” and a column “0111.” This is because the S-BOX uses a many-to-one binary function.

Returning to FIG. 3, the array 230 of the third logic gates always outputs the same 4 bits to four types of values of 6 bits of input signals A0˜A5 according to the lookup table shown in FIG. 4. Thus, each of the OR gates 321 in the array 230 of the third logic gates receives 4 bits from among the 64 bits C0˜C63 output from the AND gates 311 in the array 220 of the second logic gates. For example, when 6 bits of input signal A0˜A5 are “011110,” “000101,” “110110,” and “101111,” an output signal is “0111.” Therefore, an OR gate corresponding to “0111” in the array 230 of the third logic gates is connected to receive output signals of an AND gate corresponding to “011110,” “000101,” “110110,” and “101111” in the array 220 of the second logic gates. Likewise, input terminals of the OR gates 321 in the array 230 of the third logic gates are connected to output signals of the AND gates 311 in the array 220 of the second logic gates according to the lookup table shown in FIG. 4. The 16 bits D0˜D15 output from the array 230 of the third logic gates are provided to the encoder 240 shown in FIG. 2.

As illustrated in FIG. 3, AND gates in the

arrays

211, 212, and 213 of the first logic gates and the array 220 of the second logic gates are toggled one by one. Further, any one of the OR gates in the array 230 of the third logic gates is toggled. Accordingly, a total of five logic gates are toggled at the

arrays

211, 212, 213, 220, and 230 of the first to third logic gates although the input signals A0-A5 have any value. For this reason, the amount of current consumed at the

arrays

211, 212, 213, 220, and 230 of the first to third logic gates is always constant irrespective of values of the input signals A0˜A6. Accordingly, with a simple circuit configuration, an S-Box for DES algorithm is implemented using hardware, and a cryptographic device with security against a hacker's attack may be implemented.

The cryptographic device 200 shown in FIG. 3 is a cryptographic device implementing one S-Box. Eight cryptographic devices 200 are used to implement eight S-Boxes. In that case, the AND gates 311 in the array 220 of the second logic gates are connected to the OR gates 321 in the array 230 of the third logic gates according to a many-to-one correspondence between input and output signals of the S-Box.

As set forth in the above-described exemplary embodiments, an input signal IN is 6 bits and an output signal OUT is 4 bits. However, bit widths of the input signal IN and the output signal OUT may be variously changed. With the change in bit widths of the input signal IN and the output signal OUT, the number of the

arrays

211, 212, and 213 of the first logic gates, the number of the AND gates 311 in the array 220 of the second logic gates, and the number of the OR gates 230 in the third logic gates are changed. However, a many-to-one correspondence between the input signal IN and the output signal OUT is established.

FIG. 5 illustrates an example of a cryptographic device 500 having a reset function according to an exemplary embodiment. Unlike the cryptographic device 300 illustrated in FIG. 3, the cryptographic device 500 further inputs a clock signal CK to AND gates in arrays 511˜513 of first logic gates. If a previous output signal is logic “1,” the AND gates invert the output signal into logic “0” at a low level of the clock signal CK. In this case, the amount of current consumption is not changed because only 1 bit transitions to an inactive state. Moreover, in the case that input bits A0˜A5 have the same value during a previous cycle and a current cycle of the clock signal CK, it is possible to solve a problem that output bits of the arrays 511˜513 of the first logic gates do not turn to active/inactive bit.

FIG. 6 illustrates another circuit configuration of arrays of logic gates shown in FIG. 2 according to another exemplary embodiment. Referring to FIG. 6, unlike FIG. 3, arrays 611˜613 of first logic gates include OR gates 603˜606, an array 620 of second logic gates includes OR gates 621, and an array 630 of third logic gates includes AND gates 631.

Although input signals A0˜A5 have any value like in FIG. 3, only five logic gates are toggled at

arrays

611, 612, 613, 620, and 630 of first to third logic gates shown in FIG. 6. Signals output from the

arrays

611, 612, 613, 620, and 630 of the first to third logic gates include five inactive bits with the other bits being active bits. Likewise even when the

arrays

211, 212, 213, 220, and 230 of the first to third logic gates illustrated in FIG. 3 are substituted with the

arrays

611, 612, 613, 620, and 630 of the first to third logic gates, the amount of current consumed at the

arrays

611, 612, 613, 620, and 630 of the first to third logic gates is always constant irrespective of values of the input signals A0˜A6.

To sum up, when an S-Box operation is carried out, constant current is always consumed to prevent internal data from leaking to hackers.

While exemplary embodiments have been described with reference to the accompanying drawings, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present inventive concept. Therefore, it should be understood that the above exemplary embodiments are not limiting, but illustrative. Thus, the scope of the inventive concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing description.

Claims

What is claimed is:

1. An integrated circuit (IC) having a cryptographic function, the IC comprising:

a plurality of first circuit logic gates configured to receive an input signal having a plurality of bits;

a plurality of second circuit logic gates, each of the plurality of second circuit logic gates being configured to receive outputs of corresponding first circuit logic gates;

a plurality of third circuit logic gates, each of the plurality of third circuit logic gates being configured to receive outputs of corresponding second circuit logic gates; and

an encoder configured to receive outputs of the plurality of third circuit logic gates and to output an encoded signal having a plurality of bits,

wherein each of a plurality of values of the encoded signal corresponds to at least two values of a plurality of values of the input signal, each value of the encoded signal being represented by the plurality of bits of the encoded signal, each value of the input signal being represented by the plurality of bits of the input signal,

wherein, for any value of the plurality of bits of the input signal, a predetermined number of the first circuit logic gates from among the plurality of first circuit logic gates output logic “1” and the remaining first circuit logic gates output logic “0”,

wherein, for any value of the plurality of bits of the input signal, a predetermined number of the second circuit logic gates from among the plurality of second circuit logic gates output logic “1” and the remaining second circuit logic gates output logic “0”, and

wherein, for any value of the plurality of bits of the input signal, a predetermined number of the third circuit logic gates from among the plurality of third circuit logic gates output logic “1” and the remaining third circuit logic gates output logic “0”.

2. The IC of claim 1, wherein the plurality of first circuit logic gates is arranged into one or more groups, each of the one or more groups including four or more first circuit logic gates from among the plurality of first circuit logic gates, each of the one or more groups being configured to receive two or more bits from among the plurality of bits of the input signal.

3. The IC of claim 2, wherein each of the plurality of second circuit logic gates receives one among outputs of each group of first circuit logic gates.

4. The IC of claim 2, wherein the predetermined number of the second circuit logic gates from among the plurality of second circuit logic gates is one, and

wherein the predetermined number of the third circuit logic gates from among the plurality of third circuit logic gates is one.

5. The IC of claim 4, wherein the predetermined number of the first circuit logic gates from among the plurality of first circuit logic gates equals to the number of the one or more groups, and

wherein one of the first circuit logic gates of each group outputs logic “1” and the remaining first circuit logic gates of each group output logic “0”.

6. The IC of claim 1, wherein the total number of the plurality of bits of the input signal is greater than the total number of the plurality of bits of the encoded signal.

7. The IC of claim 1, wherein the plurality of first circuit logic gates includes a plurality of AND gates,

wherein the plurality of second circuit logic gates includes AND gates, and

wherein the plurality of third circuit logic gates includes a plurality of OR gates.

8. The IC of claim 1, wherein the plurality of first circuit logic gates includes a plurality of OR gates,

wherein the plurality of second circuit logic gates includes OR gates, and

wherein the plurality of third circuit logic gates includes a plurality of AND gates.

9. The IC of claim 1, further comprising a plurality of inverters configured to invert the plurality of bits of the input signal.

10. The IC of claim 1, wherein total power consumed by the plurality of first circuit logic gates, the plurality of second circuit logic gates and the plurality of third circuit logic gates is constantly maintained, for any value of the plurality of bits of the input signal.

11. The IC of claim 1, wherein the IC device is configured to receive a reset signal.

12. The IC of claim 11, wherein each of the plurality of first circuit logic gates is configured to receive the reset signal.

13. The IC of claim 11, wherein the reset signal is a clock signal.

14. The IC of claim 1, wherein the total number of bits of the outputs of the plurality of second circuit logic gates is greater than the number of the plurality of bits of the input signal.

15. The IC of claim 1, wherein the total number of bits of the outputs of the plurality of second circuit logic gates is greater than the total number of bits of the outputs of the plurality of third circuit logic gates.

16. The IC of claim 1, wherein the IC device is a smart card.

17. The IC of claim 1, wherein the IC device is an integrated circuit card.

18. An integrated circuit (IC) having a cryptographic function, the IC comprising:

a decoder comprising a plurality of circuit logic gates configured to receive an input signal consisting of k bits; and

an encoder configured to receive an output signal from the plurality of circuit logic gates of the decoder and to encode the received output signal to generate an output signal having m bits,

wherein the decoder is configured to generate n number of logic ‘1’ in response to any input signal,

wherein each of k, m and n is a positive integer,

wherein k is greater than m, and

wherein the plurality of circuit logic gates comprises:

a plurality of first circuit logic gates configured to receive the input signal consisting of k bits, and

a plurality of second circuit logic gates, each of the plurality of second circuit logic gates being configured to receive outputs of corresponding first circuit logic gates.

19. The IC of claim 18, wherein the decoder comprises a plurality of AND gates and a plurality of OR gates.

20. An integrated circuit (IC) having a cryptographic function, the IC comprising: