KR101673163B1 - Physically unclonable function circuit using the dual rail delay logic - Google Patents

Abstract

The present invention relates to a physical copy protection circuit using dual rail delay logic, and more preferably, a plurality of signals are connected in series to receive a plurality of signals, reflect a delay time set for each of the plurality of input signals, A delay cell for outputting a number of signals; And an arbiter logic connected in series to an end of the delay cell to receive a plurality of signals output from the delay cell and output one signal based on an input time or a power consumption amount of each rail among a plurality of inputted signals; .
According to such a configuration, the physical copy protection circuit using the dual rail delay logic of the present invention uses a delay cell composed of dual rail delay logic in place of a plurality of gates, so that the product can be miniaturized as the use area is reduced, It is possible to speed up the processing of the function of the product.

Description

[0001] The present invention relates to a dual-rail delay logic,

The present invention relates to a physical copy protection circuit using dual rail delay logic, and more particularly, to a physical copy protection circuit which can perform user authentication, object authentication, and the like on a digital device, To a physical copy protection circuit using dual rail delay logic.

Recently, with the rapid development of IT technology, new high-tech devices are rapidly emerging, but on the other hand, economic and industrial losses due to piracy and counterfeiting are increasing day by day. To solve this problem, a new technology called Physical Unclonable Function (PUF) system has emerged.

Such a PUF is a technology that allows individual devices to have unique characteristics, such as biometric information such as human fingerprints or irises. That is, a PUF represents a technology that can never replicate its unique characteristics even if the device is created in exactly the same way.

These PUFs are currently used mainly for secure key storage and identity authentication using physically random and non-replicable characteristics. In other words, PUF does not extract random seeds using software generated functions, but rather physical characteristics that each chip and equipment must be manufactured equally when the chip or equipment is physically manufactured It can be used to authenticate an object by extracting a true random seed value and using the extracted seed value as a unique value. Since it is a genuine random value, it can be applied to a non-clone chip or equipment It can be used to generate code that can be

In particular, embedded PUFs using standard cells and memory are divided into memory based PUF and delay based PUF. The memory based PUF extracts only the part that satisfies the main characteristics of the PUF in the currently developed memory and uses it as the PUF. The delay based PUF uses the delay characteristic that can be generated through the hardware physical property as the PUF, The most typical examples are Arbiter PUF (PUF) and Ring Oscillator PUF (PUF).

The memory-based PUF is a PUF based on an SRAM memory. The memory-based PUF is an unstable initial value of the SRAM memory. This memory-based PUF is a practical PUF that is easier to create and practical than other PUFs in that it creates a PUF by using existing memory primitives as it is without further work to create a PUF. In this memory-based PUF, the randomness of the initial value of the SRAM memory is difficult to manufacture all the memories in the manufacturing process under the same fabrication conditions in the manufacturing process of the memory, so that the SRAM-based PUF satisfying the PUF characteristics sufficiently There is an advantage that it can be made easily.

Of the remaining delay-based PUFs, the arbiter logic PUF is a PUF that transmits the same signal to two paths having the same distance and determines the output depending on which signal first arrives at the arbiter logic. However, in order to construct such a PUF, an additional PUF module is required for each 1-bit output (response) of the PUF, and a conventional delay-based PUF requires a large number of multiplexers and latches, happened.

KR 10-2013-0129334 (Device and method for security authentication between devices based on PUF in object intelligence communication, i-city care) 2013.11.28.

In order to solve the problems of the prior art as described above, the present invention realizes a physical copy protection circuit using a delay cell including a dual rail logic, thereby realizing not only a small area but also a high reliability I want to provide a physical copy protection circuit using dual rail delay logic.

According to an aspect of the present invention, there is provided a physical copy protection circuit using dual rail delay logic in which a plurality of signals are serially connected to each other, And outputting the plurality of signals; And an arbiter logic connected in series to an end of the delay cell to receive a plurality of signals output from the delay cell and output one signal based on an input time or a power consumption amount of each rail among a plurality of inputted signals; .

More preferably at least one dual rail delay logic, and may include delay cells connected in parallel with each other.

In particular, it may include dual rail delay logic receiving a plurality of signals.

More preferably, when a plurality of signals are input, one of the plurality of signals is input as a challenge signal, and the remaining signals are input to the output terminal of the previously arranged data cell and the dual rail delay ≪ / RTI > logic.

More preferably, the delay cell may include a delay cell in which a number corresponding to the number of challenge bits is connected in series in response to the received challenge signal.

And more preferably at least one buffer connected in series between a plurality of delay cells connected in series.

More preferably, the arbiter logic may output a high-level signal for a signal having the fastest input time among the input signals.

More preferably, the analog comparator may include an arbiter logic for outputting a high-level signal to the signal having the largest magnitude among a plurality of input signals.

More preferably, it may include arbiter logic including at least one of a comparator, an adder, a divider, and a multiplier.

The physical copy protection circuit using the dual rail delay logic of the present invention uses a delay cell composed of dual rail delay logic instead of a plurality of gates to reduce the size of the product as the use area decreases, The processing speed can be increased.

In addition, the physical copy prevention circuit using the dual rail delay logic of the present invention is capable of preventing the competition condition of each rail from unexpectedly changing due to external environmental conditions through the delay cell having the dual rail logic, It is possible to reduce the cost required for the post-processing process.

In addition, the physical copy protection circuit using the dual rail delay logic of the present invention improves the reliability of a product by inserting a buffer between a plurality of delay cells including dual rail logic to compensate a signal attenuation phenomenon with respect to an output current There is an effect that can be.

1 is a block diagram of a physical copy protection circuit using dual rail delay logic in accordance with an embodiment of the present invention.
2 illustrates a delay cell portion of a physical copy protection circuit using dual rail delay logic according to another embodiment of the present invention.
3 is a diagram illustrating input signals of dual rail delay logic.
4 is a circuit diagram showing the internal basic structure of the dual rail delay logic.
5 is a circuit diagram showing an XOR / XNOR gate structure of dual rail delay logic.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, the present invention will be described in detail with reference to preferred embodiments and accompanying drawings, which will be easily understood by those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

A commonly used physical copy protection circuit (PUF) is a small, low-power circuit that is attached to a standard silicon chip and uses output (CRP, Challenge-Response Pair) The ID of the chip can be authenticated. That is, if an authentication method for a specific device is briefly described using a physical copy protection circuit, an authentication server stores input values and unique output values (CRPs) corresponding thereto, and a challenge value The corresponding device including the physical copy protection circuit transmits an output value through the physical copy protection circuit and verifies whether or not the output value transmitted and the output value pre-stored in the authentication server coincide with each other, .

Hereinafter, a physical copy protection circuit (PUF) using dual rail delay logic that can be used for secure key storage and object authentication using the above-mentioned physically random characteristic and non-replicable characteristic will be described in more detail.

1 is a block diagram of a physical copy protection circuit using dual rail delay logic in accordance with an embodiment of the present invention.

As shown in FIG. 1, the physical copy protection circuit 100 using the dual rail delay logic of the present invention includes a delay cell 120 and an arbiter logic 140.

A plurality of delay cells 120 are serially connected to each other to receive a plurality of signals and to output a plurality of signals reflecting a delay time reflecting a preset delay time to a plurality of input signals. The delay cell 120 includes at least one dual rail delay logic 122 connected in parallel with each other.

The dual rail delay logic 122 receives a plurality of signals from the outside, and one of the plurality of received signals is input as a challenge signal, and the remaining signals are input to the dual rail delay logic 122, And is received as a complement of the output value of the previously arranged data cell and the output value.

The delay cell 120 is serially connected with a number corresponding to the number of challenge bits in response to a challenge signal corresponding to a challenge bit according to analysis of randomness and reliability characteristics. For example, in order to verify the characteristics of response data of about 2 ^ 8 by requiring 8-bit challenge bits, a total of eight delay cells, which is equal to the number of the challenge bits, are serially connected to constitute a physical copy protection circuit do.

At this time, the delay cell can basically include two dual rail logic (DCVSL), but it can implement the present invention even if it includes only one dual rail logic.

In particular, the capacitances of the internal nodes constituting the dual rail logic in the delay cell are different in size, and the amount of current that can be stored in each capacitance is also different from each other. Therefore, depending on the amount of current charged or discharged from the internal node from VDD to VCC according to the input value inputted to the dual rail logic, the output node corresponding to each rail among the two output nodes (out and out bar) A difference in power consumption occurs between the power consumption and the power consumption. Therefore, a delay cell including dual rail logic having characteristics that use a power consumption delay difference from VDD to VCC, which causes such a difference in power consumption amount, can be constituted.

The arbiter logic 140 is connected in series to the ends of a plurality of delay cells 120 connected in series to receive a plurality of signals output from the delay cell 120 connected to the front end, And outputs one signal (Response) based on the input time or the power consumption amount among the plurality of inputted signals. The arbiter logic 140 outputs a signal of a high level (1) for a signal having the fastest input time among a plurality of input signals, and outputs a low level (0) signal for the remaining input signals except for the signal having the fastest input time .

Alternatively, the arbiter logic 140 may include an analog comparator to compare the amount of power consumed by each rail to output a signal of a high level (1) to a signal input through the rail having the largest size, And outputs a signal of a low level (0) to the signal input through the input terminal.

Accordingly, the arbiter logic 140 determines a race condition for each rail and outputs a signal. For example, the arbiter logic 140 outputs a first delay rail of a plurality of signals input to the arbiter logic When the input time of the signal inputted through the second delay rail is faster than the input time of the signal inputted through the second delay rail, the signal corresponding to the high level (1) is outputted. Otherwise, And outputs a corresponding signal (response). At this time, the arbiter logic 140 may include at least one of a comparator, an adder, a divider, and a multiplier.

In addition, the arbiter logic 140 compares the power consumption used in each rail, not the race condition for each rail, in response to a signal input through a delay rail having the largest power consumption amount among the power consumption of each rail A signal corresponding to the low level (0) is output to the signal inputted through the remaining rails except for the rail having the highest power consumption among all the rails, and a signal (response) corresponding to the high level Can be output. In particular, when the arbiter logic 140 uses the power consumption of each rail as a comparison reference, the comparator 140 may output an analog comparator such as a sense amplifier. At this time, the sense amplifier used is a high gain, wide band amplifier used for amplifying a read signal in a computer memory device to a logic level and converting it into a logic signal. And a read amplifier. It is necessary to have a gain bandwidth capable of amplifying a weak output signal in a memory device and also to have a good noise elimination property, an overload proof property and a rapid performance recovery ability against a noise entering in a write cycle. In addition, a stable threshold detector for judging the input level and a strobe gate for sending the correct waveform at the correct time are provided. Since the noise voltage appearing in the sense amplifier in the write cycle is almost the same phase voltage, a differential amplifier Is used.

Also, a secret key can be generated by applying a hash function to an output value corresponding to an output signal output from the arbiter logic.

In addition, the physical copy protection circuit using the dual rail delay logic of the present invention may further include a buffer in addition to the delay cell and the arbiter logic in the internal structure.

2 illustrates a delay cell portion of a physical copy protection circuit using dual rail delay logic according to another embodiment of the present invention.

2, the physical copy protection circuit using the dual rail delay logic of the present invention includes at least one buffer 130 between a plurality of delay cells 120 in addition to the delay cell and the arbiter logic described above with reference to FIG. And a challenge bit can be formed by connecting in units of 8 bits based on 8 bits, 16 bits, 24 bits, or more, through the buffer connected in this way.

In addition, at least one buffer is serially connected between a plurality of delay cells to compensate for signal degradation to an output current, thereby improving user reliability.

3 is a diagram illustrating input signals of dual rail delay logic.

As shown in FIG. 3 (a), the dual rail delay logic used in the present invention has two input signals. However, according to the user's setting, as shown in FIG. 3 (b) Signal.

As described above, when the dual rail delay logic receives two or more input signals, one of the plurality of input signals may be used as a challenge signal. Hereinafter, for the remaining input signals except for the input signal used as the challenge signal, an output signal representing the output value of the delay cell disposed in the previous time of the delay cell including the current dual rail delay logic and an output corresponding to the complement value of the output value Signals are input as the input signals of the current dual rail delay logic, respectively.

The internal structure of the dual rail delay logic is composed of one dual rail logic in which the delay block is the same as one basic gate as shown in FIG. 4, and in particular, the structure of the XOR / XNOR gate of the dual rail logic is shown in FIG. . Particularly, when designing the respective delay blocks by varying the widths of the PMOS transistor and the NMOS transistor constituting the dual rail delay logic, a plurality of PUF IDs can be designed.

That is, the output of the same input of the physical copy protection circuit using the dual rail delay logic of the present invention is a unique value. By using a characteristic (CRP, Challenge-Response Pair) between the input value and the output value, Based authentication can be easily performed.

The physical copy protection circuit (PUF) implemented as described above can be used in various fields, and can be applied to IDs for preventing copying of financial ICs or automobile keys such as credit cards that should not be replicated. Also, the physical copy protection circuit using the dual rail delay logic can be used as an ultra lightweight module for object authentication. For example, by giving each individual unique ID like the electronic passport to the PUF chip, The authentication module of the present invention can be mounted on the MRTD and can also be used as an activation key for generating a random key and can be safely used with a secret key in the existing encryption algorithm.

The physical copy protection circuit using the dual rail delay logic of the present invention uses a delay cell composed of dual rail delay logic instead of a plurality of gates to reduce the size of the product as the use area decreases, The processing speed can be increased.

In addition, the physical copy protection circuit using the dual rail delay logic of the present invention can prevent the contention condition of each rail from being unavoidably changed due to external environmental conditions such as a change in ambient temperature through a delay cell having dual rail logic, It is possible to reduce the cost required for the post-treatment process.

In addition, the physical copy protection circuit using the dual rail delay logic of the present invention improves the reliability of a product by inserting a buffer between a plurality of delay cells including dual rail logic to compensate a signal attenuation phenomenon with respect to an output current There is an effect that can be.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Do.

120: Delay cell 140: Arbiter logic

Claims (9)

A plurality of delay lines connected in series to each other to receive a plurality of signals, to reflect the delay time set in each of the plurality of input signals, to output the plurality of signals, and at least one dual rail delay logic ; And
An arbiter logic connected in series to the end of the delay cell for receiving a plurality of signals output from the delay cell and outputting a signal based on an input time or power consumption of each rail among a plurality of input signals;
/ RTI >
The dual rail delay logic
Wherein when a plurality of signals are input, one of the plurality of signals is input as a challenge signal, and the remaining signals are input as an output value of a previously arranged data cell and a complement value of the output value, Physical copy protection circuit using logic.
The method according to claim 1,
The delay cell
And a dual rail delay logic that generates a difference in power consumption at an output node corresponding to each of the two output nodes of the dual rail.
delete delete The method according to claim 1,
The delay cell
And a number corresponding to the number of challenge bits is serially connected in response to the received challenge signal.
The method according to claim 1,
At least one buffer serially connected between a plurality of delay cells connected in series;
Further comprising a second delay delay logic coupled to the first and second delay lines.
The method according to claim 1,
The arbiter logic
And outputs a high level signal in response to a signal having the fastest input time among the plurality of input signals.
The method according to claim 1,
The arbiter logic
And outputs a high level signal in response to a signal having a largest power consumption amount of each rail, including an analog comparator.
The method according to claim 1,
The arbiter logic
Wherein the at least one counter includes at least one of a comparator, an adder, a divider, and a multiplier.

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