[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

US20110189843A1 - Plasma doping method and method for fabricating semiconductor device using the same - Google Patents

Plasma doping method and method for fabricating semiconductor device using the same Download PDF

Info

Publication number
US20110189843A1
US20110189843A1 US12/774,311 US77431110A US2011189843A1 US 20110189843 A1 US20110189843 A1 US 20110189843A1 US 77431110 A US77431110 A US 77431110A US 2011189843 A1 US2011189843 A1 US 2011189843A1
Authority
US
United States
Prior art keywords
doping
layer
forming
sidewall
conductive structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/774,311
Other languages
English (en)
Inventor
Jin-Ku LEE
Jae-Geun Oh
Young-Ho Lee
Mi-Ri Lee
Seung-Beom Baek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Assigned to HYNIX SEMICONDUCTOR, INC. reassignment HYNIX SEMICONDUCTOR, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BAEK, SEUNG-BEOM, LEE, JIN-KU, LEE, MI-RI, LEE, YOUNG-HO, OH, JAE-GEUN
Publication of US20110189843A1 publication Critical patent/US20110189843A1/en
Priority to US14/185,551 priority Critical patent/US9054128B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H01L21/2236—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Definitions

  • Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a plasma doping method and a method for fabricating a semiconductor device using the same.
  • an ion beam implantation method is usually used.
  • the ion beam implantation method is also referred to as a “beam line implantation method.”
  • FIG. 1 illustrates a tilt ion implantation doping method for a semiconductor device.
  • a substrate 11 including a plurality of conductive structures 12 is formed.
  • the plurality of conductive structures 12 are formed over the substrate 11 with a predetermined space between them.
  • the doping is performed through a tilt ion implantation method (see reference numeral ‘ 13 ’) because the gap between the conductive structures 12 is narrow and the conductive structures 12 are formed to have a predetermined height.
  • the tilt ion implantation 13 is performed at a certain tilt angle. However, a concern may arise in that a target region is not doped due to a shadow cast by, for example, the area 13 A of a neighboring conductive structure 12 during the tilt ion implantation 13 .
  • the tilt ion implantation 13 is performed, it is difficult to dope a doping target region with a desired level of doping concentration and a desired doping depth because the conductive structures 12 may be relatively tall and the gap between the conductive structures 12 may be relatively narrow.
  • Another way for doping a specific region of a 3D conductive structure is a method using a doped material such as doped polysilicon.
  • a doped material such as doped polysilicon.
  • a target region is doped by thermally diffusing the dopant of the doped material through an annealing process.
  • An embodiment of the present invention is directed to a doping method that forms a doped region at a desired location of a three-dimensional (3D) conductive structure and controls the doping depth and doping dose of the doped region relatively easily, and a method for fabricating a semiconductor device using the same.
  • Another embodiment of the present invention is directed to a doping method that provides a shallow doping depth and prevents a floating body effect, and a method for fabricating a semiconductor device using the same.
  • a method for doping a semiconductor device includes: forming a conductive structure having a sidewall; exposing a portion of the sidewall of the conductive structure; and forming a doped region in the exposed portion of the sidewall by performing a plasma doping process.
  • the method may further include: forming a protective layer on a surface of the doped region; and performing an annealing process to activate the doped region.
  • the method may further include: forming a protective layer on the surface of the doped region by performing an annealing process for activating the doped region.
  • a method for fabricating a semiconductor device includes: forming an active region having a sidewall by etching a substrate; exposing a portion of the sidewall of the active region; forming a junction in the exposed portion of the sidewall by performing a plasma doping process; and forming a protective layer on a surface of the junction.
  • the method may further include: removing the protective layer; forming a side contact coupled to the junction; and forming a buried bit line electrically coupled to the junction through the side contact.
  • the forming of the protective layer may be performed while an annealing process for activating the junction is performed simultaneously.
  • a method for fabricating a semiconductor device includes: forming a conductive structure having a sidewall by etching a substrate with a hard mask pattern used as an etch barrier; forming a liner layer covering the conductive structure; forming a first anti-doping layer filling a portion of a gap between the conductive structure and a second anti-doping layer covering a first sidewall of each of the conductive structure over the liner layer; forming a contact region exposing a portion of a second sidewall of the conductive structure by removing the liner layer and a portion of the first anti-doping layer formed over the second sidewall; forming a junction in the contact region by performing a plasma doping process; removing the second anti-doping layer; forming a protective layer on a surface of the junction; and removing the first anti-doping layer.
  • FIG. 1 illustrates a tilt-ion-implantation doping method for a semiconductor device.
  • FIGS. 2A and 2B are cross-sectional views illustrating a doping method for a semiconductor device in accordance with a first embodiment of the present invention.
  • FIGS. 3A to 3E are cross-sectional views illustrating a doping method for a semiconductor device in accordance with a second embodiment of the present invention.
  • FIGS. 4A to 4C are cross-sectional views illustrating a semiconductor device fabrication method using the doping method according to the second embodiment of the present invention.
  • FIGS. 5A to 5D are cross-sectional views illustrating a doping method for a semiconductor device in accordance with a third embodiment of the present invention.
  • FIGS. 6A to 6C are cross-sectional views illustrating a semiconductor device fabrication method using the doping method according to the third embodiment of the present invention.
  • FIGS. 7A to 7L are cross-sectional views illustrating a method for forming an opening in accordance with the first to third embodiments of the present invention.
  • first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate but also a case where a third layer exists between the first layer and the second layer or the substrate.
  • FIGS. 2A and 2B are cross-sectional views illustrating a doping method for a semiconductor device in accordance with a first embodiment of the present invention.
  • a plurality of conductive structures 203 are formed over a substrate 201 .
  • the substrate 201 includes a silicon substrate.
  • the conductive structures 203 are formed by etching the substrate 201 . Since the substrate 201 includes a silicon substrate, the conductive structures 203 include silicon as well.
  • the conductive structures 203 extend on the surface of the substrate 201 in a direction perpendicular to the illustration page for FIG. 2A .
  • the conductive structures 203 include line-type pillars (that is, pillars each forming a line).
  • the conductive structures 203 include an active region.
  • the active region is an area where a channel region, a source region, and a drain region of a transistor are formed.
  • the source region and the drain region are also referred to as a “junction.”
  • the conductive structures 203 have sidewalls, which include at least a first sidewall and a second sidewall. Since the conductive structures 203 include an active region in the form of a pillar-type active region having a line shape.
  • the line-shaped pillar-type active region is called “line-type active pillar.”
  • a hard mask layer 202 is formed over the upper portions of the conductive structures 203 .
  • the hard mask layer 202 functions as an etch barrier in forming the conductive structures 203 .
  • the hard mask layer 202 may be formed of a dielectric material, such as an oxide and a nitride. According to an example, a nitride layer is used as the hard mask layer 202 .
  • the hard mask layer 202 may also include a silicon nitride layer.
  • the insulation layer includes a first liner layer 204 and a second liner layer 205 .
  • the first liner layer 204 includes an oxide layer such as a silicon oxide layer.
  • the second liner layer 205 includes a nitride layer such as a silicon nitride layer.
  • An opening 208 is formed by removing a portion of the insulation layer.
  • the opening 208 has a one-side-opening (OSO) structure which selectively exposes a portion of the sidewalls of a conductive structure 203 .
  • the opening 208 may be a line-type opening.
  • a first anti-doping layer 206 and a second anti-doping layer 207 are formed on the surface of the insulation layer.
  • the first anti-doping layer 206 fills a portion of the gap between the conductive structures 203 .
  • the second anti-doping layer 207 is formed on the insulation layer over an unopened sidewall of the conductive structure 203 that is opposite from the sidewall where the opening 208 is formed.
  • the first anti-doping layer 206 protects the substrate 201 between the conductive structures 203 from being doped during a subsequent plasma doping process.
  • the second anti-doping layer 207 protects the unopened sidewall of the conductive structure 203 from being doped during a subsequent plasma doping process.
  • the first anti-doping layer 206 and the second anti-doping layer 207 operate as an insulation layer.
  • the first anti-doping layer 206 includes undoped polysilicon.
  • the second anti-doping layer 207 includes a material having a selectivity with respect to the first anti-doping layer 206 , the first liner layer 204 , and the second liner layer 205 .
  • the second anti-doping layer 207 may include a metal nitride layer, such as titanium nitride (TiN) layer.
  • TiN titanium nitride
  • the second anti-doping layer 207 may be formed of a spacer.
  • the insulation layer providing the opening 208 and the hard mask layer 202 may function as an anti-doping layer as well. Plasma doping is performed onto a portion of the sidewalls of the conductive structure 203 exposed through the opening 208 and not to other portions.
  • the first liner layer 204 , the second liner layer 205 , the first anti-doping layer 206 , and the second anti-doping layer 207 function as anti-doping layers.
  • the anti-doping layers provide the opening 208 exposing a portion of the sidewalls of the conductive structure 203 . A method for forming the opening 208 will be described later with reference to FIGS. 7A to 7I .
  • a plasma doping process 209 is performed.
  • a portion of the sidewalls of the conductive structure 203 exposed through the opening 208 is doped.
  • a doped region 210 is formed.
  • the doped region 210 includes a junction, which becomes a source region and a drain region of a transistor.
  • the doped region 210 is formed on a portion of the sidewalls of a conductive structure 203 to constitute a one-side-junction (OSJ). Since the doped region 210 is formed through a plasma doping process 209 , it forms a shallow sidewall junction.
  • OSJ one-side-junction
  • the upper portions of the conductive structures 203 are protected from being doped by the hard mask layer 202 .
  • the other sidewalls of the conductive structures 203 except for the portion of the sidewalls exposed through the opening 208 are protected by the first liner layer 204 , the second liner layer 205 , the first anti-doping layer 206 and the second anti-doping layer 207 from being doped (see reference signs A, B, and C).
  • the first anti-doping layer 206 and the second anti-doping layer 207 they contribute to protecting the other sidewalls from being doped with a dopant except for the portion of the sidewalls exposed through the opening 208 .
  • the plasma doping process 209 is a doping method of exciting a doping source into a plasma status and implanting dopant ions in the excited plasma into a specimen.
  • a bias voltage is applied to the specimen, the dopant ions in the plasma may simultaneously gather over the surface of the specimen.
  • the bias voltage may be referred to as doping energy.
  • the plasma doping process 209 is performed using a source of doping energy, a doping dose, and a doping source.
  • the doping source is a material containing a dopant to be applied to the doped region 210 .
  • the doping source includes a dopant gas.
  • the doping source may be a dopant gas such as arsenic (As) and phosphorus (P).
  • the doping source may include arsine (AsH 3 ) or phosphine (PH 3 ).
  • the arsenic (As) and phosphorus (P) are well-known N-type dopants.
  • a dopant gas containing boron (B) may be used as the doping source. Boron is a well-known P-type dopant.
  • the doping energy signifies a bias voltage applied to the substrate 201 .
  • the doping energy may be a voltage not higher than approximately 20 KV. To achieve a shallow depth of the doped area, the doping energy is adjusted to be as small as possible. For example, the doping energy may be lower than approximately 1 KV, while doping energy lower than approximately 20 KV is considered to be relatively low. Since ion implantation is generally performed based on projection range (Rp), high doping energy over approximately 30 KeV may be used.
  • the doping energy is applied to the conductive structures 203 as well.
  • the plasma doping process 209 may be performed in a sidewall direction (that is, a direction facing a sidewall). By the collision of ions in the excited plasma, the plasma doping process 209 performed in the sidewall direction is facilitated.
  • the doping dose affects the implantation amount of a dopant.
  • the doping dose ranges from approximately 1 ⁇ 10 15 to approximately 1 ⁇ 10 17 atoms/cm 2 .
  • the dopant applied to the doped region 210 forms a doping concentration of at least more than 1 ⁇ 10 20 atoms/cm 3 .
  • a gas for exciting the plasma may be introduced.
  • the gas for exciting the plasma includes argon (Ar), helium (He) and so forth.
  • the doped region 210 may be formed at a desired location.
  • the plasma doping process 209 uses a low doping energy of lower than approximately 20 KV, most of the dopant remains on the surface. Therefore, the doping depth of the doped region 210 formed by the plasma doping process 209 may be controlled to be shallow. Since the doping depth of the doped region 210 is controlled to be shallow, the floating body effect is prevented/reduced.
  • FIGS. 3A to 3E are cross-sectional views illustrating a doping method for a semiconductor device in accordance with a second embodiment of the present invention.
  • a plurality of conductive structures 303 are formed over a substrate 301 .
  • the substrate 301 includes a silicon substrate.
  • the conductive structures 303 are formed by etching the substrate 201 . Since the substrate 301 includes a silicon substrate, the conductive structures 303 include silicon as well.
  • the conductive structures 303 extend on the surface of the substrate 301 in a direction perpendicular to the illustration page for FIG. 3A .
  • the conductive structures 303 include line-type pillars (that is, pillars each forming a line).
  • the conductive structures 303 include an active region.
  • the active region is an area where a channel region, a source region, and a drain region of a transistor are formed.
  • the source region and the drain region are also referred to as a “junction”.
  • the conductive structures 303 have sidewalls, which include at least a first sidewall and a second sidewall. Since the conductive structures 303 include the active region in the form of a pillar-type active region having a line shape.
  • the line-shaped pillar-type active region is called “line-type active pillar.”
  • a hard mask layer 302 is formed over the upper portions of the conductive structures 303 .
  • the hard mask layer 302 functions as an etch barrier in forming the conductive structures 303 .
  • the hard mask layer 302 may be formed of a dielectric material, such as an oxide and a nitride. According to an example, a nitride layer is used as the hard mask layer 302 .
  • the hard mask layer 302 may include a silicon nitride layer.
  • the insulation layer includes a first liner layer 304 and a second liner layer 305 .
  • the first liner layer 304 includes an oxide layer such as a silicon oxide layer.
  • the second liner layer 305 includes a nitride layer such as a silicon nitride layer.
  • An opening 308 is formed by removing a portion of the insulation layer.
  • the opening 208 has a one-side-opening (OSO) structure which selectively exposes a portion of the sidewalls of a conductive structure 303 .
  • the opening 308 may be a line-type opening.
  • a first anti-doping layer 306 and a second anti-doping layer 307 are formed on the surface of the insulation layer.
  • the first anti-doping layer 306 fills a portion of the gap between the conductive structures 303 .
  • the second anti-doping layer 307 is formed on the insulation layer over an unopened sidewall of the conductive structure 303 that is opposite from the sidewall where the opening 308 is formed.
  • the first anti-doping layer 306 protects the substrate 301 between the conductive structures 303 from being doped during a subsequent plasma doping process.
  • the second anti-doping layer 307 protects the unopened sidewall of the conductive structure 303 from being doped during a subsequent plasma doping process.
  • the first anti-doping layer 306 and the second anti-doping layer 307 operate as an insulation layer.
  • the first anti-doping layer 306 includes undoped polysilicon.
  • the second anti-doping layer 307 includes a material having a selectivity with respect to the first anti-doping layer 306 , the first liner layer 304 , and the second liner layer 305 .
  • the second anti-doping layer 307 may include a metal nitride layer, such as titanium nitride (TiN) layer.
  • TiN titanium nitride
  • the second anti-doping layer 307 may be formed of a spacer.
  • the insulation layer providing the opening 308 and the hard mask layer 302 may function as an anti-doping layer as well. Plasma doping is performed onto a portion of the sidewalls of the conductive structure 303 exposed through the opening 308 and not to other portions.
  • the first liner layer 304 , the second liner layer 305 , the first anti-doping layer 306 , and the second anti-doping layer 307 function as anti-doping layers.
  • the anti-doping layers provide the opening 308 exposing a portion of the sidewalls of the conductive structure 303 . A method for forming the opening 308 will be described later with reference to FIGS. 7A to 7I .
  • a plasma doping process 309 is performed.
  • a portion of the sidewalls of the conductive structure 303 exposed through the opening 308 is doped.
  • a doped region 310 is formed.
  • the doped region 310 includes a junction, which becomes a source region and a drain region of a transistor.
  • the doped region 310 is formed on a portion of the sidewalls of a conductive structure 303 to constitute a one-side-junction (OSJ). Since the doped region 310 is formed through a plasma doping process 309 , it forms a shallow sidewall junction.
  • OSJ one-side-junction
  • the upper portions of the conductive structures 303 are protected from being doped by the hard mask layer 302 .
  • the other sidewalls of the conductive structures 303 except for the portion of the sidewalls exposed through the opening 308 are protected by the first liner layer 304 , the second liner layer 305 , the first anti-doping layer 306 and the second anti-doping layer 307 from being doped (see reference signs A, B, and C).
  • the first anti-doping layer 306 and the second anti-doping layer 307 they contribute to protecting the other sidewalls from being doped with a dopant except for the portion of the sidewalls exposed through the opening 208 .
  • the plasma doping process 309 is a doping method of exciting a doping source into a plasma status and implanting dopant ions in the excited plasma into a specimen.
  • a bias voltage is applied to the specimen, the dopant ions in the plasma may simultaneously gather over the surface of the specimen.
  • the bias voltage may be referred to as doping energy.
  • the plasma doping process 309 is performed using a source of doping energy, a doping dose, and a doping source.
  • the doping source is a material containing a dopant to be applied to the doped region 310 .
  • the doping source includes a dopant gas.
  • the doping source may be a dopant gas containing arsenic (As) and phosphorus (P).
  • the doping source includes arsine (AsH 3 ) or phosphine (PH 3 ).
  • the arsenic (As) and phosphorus (P) are well-known N-type dopants.
  • a dopant gas containing boron (B) may be used as the doping source. Boron is well-known P-type dopant.
  • the doping energy signifies a bias voltage applied to the substrate 301 .
  • the doping energy may be a voltage not higher than at least approximately 20 KV. To achieve a shallow depth of the doped area, the doping energy is adjusted to be as small as possible. For example, the doping energy may be lower than approximately 1 KV, while doping energy lower than approximately 20 KV is considered to be relatively low. Since ion implantation is generally performed based on projection range (Rp), high doping energy over approximately 30 KeV may be used.
  • the doping energy is applied to the conductive structures 303 as well.
  • the plasma doping process 309 may be performed in a sidewall direction (that is, a direction facing a sidewall). By the collision of ions in the exited plasma, the plasma doping process 309 performed in the sidewall direction is facilitated.
  • the doping dose affects the implantation amount of a dopant.
  • the doping dose ranges from approximately 1 ⁇ 10 15 to approximately 1 ⁇ 10 17 atoms/cm 2 .
  • the dopant applied to the doped region 310 forms a doping concentration of at least more than 1 ⁇ 10 2 ° atoms/cm 3 .
  • a gas for exciting the plasma may be introduced.
  • the gas for exciting the plasma includes argon (Ar), helium (He) and so forth.
  • the second anti-doping layer 307 is removed. Subsequently, a protective layer 311 is formed on the surface of the doped region 310 .
  • the protective layer 311 protects the dopant of the doped region 310 from being lost during a subsequent process, such as a process of removing the first anti-doping layer 306 .
  • the protective layer 311 is formed through a furnace oxidation or plasma oxidation, where the protective layer 311 is formed with a thickness of 50 ⁇ .
  • an annealing process 312 is performed to activate the dopant doping the doped region 310 .
  • the annealing process 312 may be a rapid thermal annealing (RTA).
  • the first anti-doping layer 306 is removed.
  • the first anti-doping layer 306 is removed through an etch process or a cleaning process.
  • a wet chemical or an etching gas capable of selectively removing polysilicon is used.
  • the loss of the dopant doping the doped region 310 is minimized/reduced.
  • a structure linked to the side of the doped region 310 is formed subsequently for the second embodiment.
  • the structure may, for example, be a bit line, a capacitor or a metal line.
  • the doped region 310 may be formed at a desired location.
  • the plasma doping process 309 uses a low doping energy of lower than approximately 20 KV, most of the dopant remains on the surface. Therefore, the doping depth of the doped region 310 formed by the plasma doping process 309 may be controlled to be shallow. Since the doping depth of the doped region 310 is controlled to be shallow, the floating body effect is prevented/reduced.
  • the doping concentration is maintained to be higher than 10 20 atoms/cm 3 .
  • FIGS. 4A to 4C are cross-sectional views illustrating a semiconductor device fabrication method using the doping method according to the second embodiment of the present invention.
  • the drawings show cross-sectional views after the protective layer 311 and the doped region 310 are formed as shown in FIGS. 3A to 3E and the subsequent removal of the protective layer 311 as described below.
  • the doped region 310 may function as a junction which becomes a source region or a drain region.
  • a method for forming a buried bit line coupled to the doped region 310 will be described.
  • the protective layer 311 is removed. Accordingly, a contact region 313 exposing a side of the doped region 310 is formed.
  • the contact region 313 has the same shape as the opening 308 .
  • a side contact 314 coupled to the conductive structure 303 is formed, where the side contact 314 may be a metal silicide.
  • the metal silicide include titanium silicide (TiSi 2 ), cobalt silicide (CoSi 2 ), and nickel silicide (NiSi).
  • titanium silicide (TiSi 2 ) is formed by sequentially depositing a titanium (Ti) layer and a titanium nitride (TiN) layer and performing a thermal treatment. Subsequently, titanium not reacted with the titanium nitride is removed. The titanium reacted with the titanium nitride may remain, where it forms barrier metal.
  • cobalt silicide which is more stable at a high temperature, may be selected in order to prevent deterioration during a subsequent high-temperature thermal treatment.
  • the side contact 314 may be referred to as “a buried strap filling the contact region 313 .”
  • the side contact 314 has a one-side-contact (OSC) structure formed on one side of the conductive structure 303 .
  • OSC one-side-contact
  • the side contact 314 is formed of a metal silicide, the concentration of the dopant doping the doped region 310 is maintained over 10 20 atoms/cm 3 . Therefore, silicide may be formed relatively easily.
  • a bit line conductive layer is deposited over the structure with the side contact 314 formed therein.
  • the bit line conductive layer is deposited so as to fill the gap between the conductive structures 303 .
  • the bit line conductive layer includes a metal layer, such as titanium nitride (TiN) layer and a tungsten (W) layer.
  • TiN titanium nitride
  • W tungsten
  • the bit line conductive layer may be formed by stacking a titanium nitride layer and a tungsten (TiN/W) layer.
  • bit line conductive layer is removed up to a certain height where a contact with the side contact 314 is maintained. Accordingly, a buried bit line 315 contacting the side contact 314 is formed.
  • the buried bit line 315 is arranged in parallel with the conductive structures 303 , and the doped region 310 is electrically coupled to the buried bit line 315 through the side contact 314 .
  • the side contact 314 forms an ohmic contact between the doped region 310 and the buried bit line 315 .
  • FIGS. 5A to 5D are cross-sectional views illustrating a doping method for a semiconductor device in accordance with a third embodiment of the present invention.
  • a plurality of conductive structures 403 are formed over a substrate 401 .
  • the substrate 401 includes a silicon substrate.
  • the conductive structures 403 are formed by etching the substrate 401 . Since the substrate 401 includes a silicon substrate, the conductive structures 403 include silicon as well.
  • the conductive structures 403 extend the surface of the substrate 401 in a direction perpendicular to the illustration page for FIG. 5A .
  • the conductive structures 403 include line-type pillars (that is, pillars each forming a line).
  • the conductive structures 403 include an active region.
  • the active region is an area where a channel region, a source region, and a drain region of a transistor are formed.
  • the source region and the drain region are also referred to as a “junction”.
  • the conductive structures 403 have sidewalls, which include at least a first sidewall and a second sidewall. Since the conductive structures 403 include an active region in the form of a pillar-type active region having a line shape.
  • the line-shaped pillar-type active region is called “line-type active pillar.”
  • a hard mask layer 402 is formed over the upper portions of the conductive structures 403 .
  • the hard mask layer 402 functions as an etch barrier in forming the conductive structures 403 .
  • the hard mask layer 402 may be formed of a dielectric material, such as an oxide and a nitride. According to an example, a nitride layer is used as the hard mask layer 402 .
  • the hard mask layer 402 may include a silicon nitride layer.
  • the insulation layer includes a first liner layer 404 and a second liner layer 405 .
  • the first liner layer 404 includes an oxide layer such as a silicon oxide layer.
  • the second liner layer 405 includes a nitride layer such as a silicon nitride layer.
  • An opening 408 is formed by removing a portion of the insulation layer.
  • the opening 408 has a one-side-opening (OSO) structure which selectively exposes a portion of the sidewalls of a conductive structure 403 .
  • the opening 408 may include a line-type opening.
  • a first anti-doping layer 406 and a second anti-doping layer 407 are formed on the surface of the insulation layer.
  • the first anti-doping layer 406 fills a portion of the gap between the conductive structures 403 .
  • the second anti-doping layer 407 is formed on the insulation layer an unopened sidewall of the conductive structure 403 that is opposite from the sidewall where the opening 408 is formed.
  • the first anti-doping layer 406 protects the substrate 401 between the conductive structures 403 from being doped during a subsequent plasma doping process.
  • the second anti-doping layer 407 protects the unopened sidewall of the conductive structure 403 from being doped during a subsequent plasma doping process.
  • the first anti-doping layer 406 and the second anti-doping layer 407 operate as an insulation layer.
  • the first anti-doping layer 406 includes undoped polysilicon.
  • the second anti-doping layer 407 includes a material having a selectivity with respect to the first anti-doping layer 406 , the first liner layer 404 , and the second liner layer 405 .
  • the second anti-doping layer 407 may include a metal nitride layer, such as titanium nitride (TiN) layer.
  • TiN titanium nitride
  • the second anti-doping layer 407 may be formed of a spacer.
  • the insulation layer providing the opening 408 and the hard mask layer 402 may function as anti-doping layer as well. Plasma doping is performed onto a portion of the sidewalls of the conductive structure 303 exposed through the opening 408 and not to other portions.
  • the first liner layer 404 , the second liner layer 405 , the first anti-doping layer 406 , and the second anti-doping layer 407 function as anti-doping layers.
  • the anti-doping layers provide the opening 408 exposing a portion of the sidewalls of the conductive structure 403 . A method for forming the opening 408 will be described later with reference to FIGS. 7A to 7I .
  • a plasma doping process 409 is performed.
  • a portion of the sidewalls of the conductive structure 403 exposed through the opening 408 is doped.
  • a doped region 410 is formed.
  • the doped region 410 includes a junction, which becomes a source region and a drain region of a transistor.
  • the doped region 410 is formed on a portion of the sidewalls of a conductive structure 403 to constitute a one-side-junction (OSJ). Since the doped region 410 is formed through a plasma doping process 409 , it forms a shallow sidewall junction.
  • OSJ one-side-junction
  • the upper portions of the conductive structures 403 are protected from being doped by the hard mask layer 402 .
  • the other sidewalls of the conductive structures 403 except for the portion of the sidewalls exposed through the opening 408 are protected by the first liner layer 404 , the second liner layer 405 , the first anti-doping layer 406 and the second anti-doping layer 407 from being doped (see reference signs A, B, and C).
  • the first anti-doping layer 406 and the second anti-doping layer 407 they contribute to protecting the other sidewalls from being doped with a dopant except for the portion of the sidewalls exposed through the opening 408 .
  • the plasma doping process 409 is a doping method of exciting a doping source into a plasma status and implanting dopant ions in the excited plasma into a specimen.
  • a bias voltage is applied to the specimen, the dopant ions in the plasma may simultaneously gather over the surface of the specimen.
  • the bias voltage may be referred to as doping energy.
  • the plasma doping process 409 is performed using a source of doping energy, a doping dose, and a doping source.
  • the doping source is a material containing a dopant to be applied to the doped region 410 .
  • the doping source includes a dopant gas.
  • the doping source may be a dopant gas containing arsenic (As) and phosphorus (P).
  • the doping source may include arsine (AsH 3 ) or phosphine (PH 3 ).
  • the arsenic (As) and phosphorus (P) are well-known N-type dopants.
  • a dopant gas containing boron (B) may be used as the doping source. Boron is well-known P-type dopant.
  • the doping energy signifies a bias voltage applied to the substrate 401 .
  • the doping energy may be a voltage not higher than at least approximately 20 KV. To achieve a shallow depth of the doped area, the doping energy is adjusted to be as small as possible. For example, the doping energy may be lower than approximately 1 KV, while doping energy lower than approximately 20 KV is considered to be relatively low. Since ion implantation is generally performed based on projection range (Rp), high doping energy over approximately 30 KeV may be used.
  • the doping energy is applied to the conductive structures 403 as well.
  • the plasma doping process 409 may be performed in a sidewall direction (that is, a direction facing a sidewall). By the collision of ions in the excited plasma, the plasma doping process 409 performed in the sidewall direction is facilitated.
  • the doping dose affects the implantation amount of a dopant.
  • the doping dose ranges from approximately 1 ⁇ 10 15 to approximately 1 ⁇ 10 17 atoms/cm 2 .
  • the dopant applied to the doped region 410 forms a doping concentration of at least more than 1 ⁇ 10 20 atoms/cm 3 .
  • a gas for exciting the plasma may be introduced.
  • the gas for exciting the plasma includes argon (Ar), helium (He) and so forth.
  • the second anti-doping layer 407 is removed. Subsequently, a protective layer 411 is formed on the surface of the doped region 410 .
  • the protective layer 411 is formed while performing an annealing process 412 for activating the dopant doping the doped region 410 .
  • the protective layer 411 protects the dopant of the doped region 410 from being lost during a subsequent process, such as a process of removing the first anti-doping layer 406 .
  • a rapid thermal treatment is used to perform the annealing process 412 while forming the protective layer 411 .
  • the protective layer 411 is formed by supplying an oxygen-containing gas or a nitrogen-containing gas while the rapid thermal treatment is performed simultaneously.
  • the oxygen-containing gas may be oxygen gas.
  • the nitrogen-containing gas may be nitrogen trifluoride (NF 3 ) gas.
  • NF 3 nitrogen trifluoride
  • the first anti-doping layer 406 is removed.
  • the first anti-doping layer 406 is removed through an etch process or a cleaning process.
  • a wet chemical or an etching gas capable of selectively removing polysilicon is used.
  • the loss of the dopant doping the doped region 410 is minimized/reduced.
  • a structure linked to the side of the doped region 410 is formed subsequently for the second embodiment.
  • the structure may, for example, be a bit line, a capacitor or metal line.
  • the doped region 410 may be formed at a desired location.
  • the plasma doping process 409 uses a low doping energy of lower than approximately 20 KV, most of the dopant remains on the surface. Therefore, the doping depth of the doped region 410 formed by the plasma doping process 409 may be controlled to be shallow. Since the doping depth of the doped region 410 is controlled to be shallow, the floating body effect is prevented/reduced.
  • the doping concentration is maintained to be higher than 10 20 atoms/cm 3 .
  • FIGS. 6A to 6C are cross-sectional views illustrating a semiconductor device fabrication method using the doping method according to the third embodiment of the present invention.
  • the drawings show cross-sectional views after the protective layer 411 and the doped region 410 are formed as shown in FIGS. 5A to 5D .
  • the doped region 410 may function as a junction which becomes a source region or a drain region.
  • the protective layer 411 is removed. Accordingly, a contact region 413 exposing a side of the doped region 410 is formed.
  • the contact region 413 has the same shape as the opening 408 .
  • a side contact 414 coupled to the conductive structure 403 is formed, where the side contact 414 may be a metal silicide.
  • the metal silicide include titanium silicide (TiSi 2 ), cobalt silicide (CoSi 2 ), and nickel silicide (NiSi).
  • titanium silicide (TiSi 2 ) is formed by sequentially depositing a titanium (Ti) layer and a titanium nitride (TiN) layer and performing a thermal treatment. Subsequently, titanium not reacted with the titanium nitride is removed. The titanium reacted with the titanium nitride may remain, where it forms barrier metal.
  • cobalt silicide which is more stable at a high temperature, may be selected in order to prevent deterioration during a subsequent high-temperature thermal treatment.
  • the side contact 414 fills the contact region 413 .
  • the side contact 414 may be referred to as “a buried strap filling the contact region 413 .”
  • the side contact 414 has a one-side-contact (OSC) structure formed on one side of the conductive structure 403 .
  • OSC one-side-contact
  • the side contact 414 is formed of a metal silicide, the concentration of the dopant doping the doped region 410 is maintained over 10 20 atoms/cm 3 . Therefore, silicide may be formed relatively easily.
  • a bit line conductive layer is deposited over the structure with the side contact 414 formed therein.
  • the bit line conductive layer is deposited so as to fill the gap between the conductive structures 403 .
  • the bit line conductive layer includes a metal layer, such as titanium nitride (TiN) layer and a tungsten (W) layer.
  • TiN titanium nitride
  • W tungsten
  • the bit line conductive layer may be formed by stacking a titanium nitride layer and a tungsten (TiN/W) layer.
  • bit line conductive layer is removed up to a certain height where a contact with the side contact 414 is maintained. Accordingly, a buried bit line 415 contacting the side contact 414 is formed.
  • the buried bit line 415 is arranged in parallel with the conductive structures 403 , and the doped region 410 is electrically coupled to the buried bit line 415 through the side contact 414 .
  • the side contact 414 forms an ohmic contact between the doped region 410 and the buried bit line 415 .
  • FIGS. 7A to 7I are cross-sectional views illustrating a method for forming an opening on a sidewall of a conductive structure in accordance with the first to third embodiments of the present invention.
  • a hard mask layer 22 is formed over a substrate 21 .
  • the hard mask layer 22 includes a nitride layer.
  • the hard mask layer 22 may have a multi-layer structure including an oxide layer and a nitride layer.
  • the hard mask layer 22 may include a hard mask nitride layer and a hard mask oxide layer sequentially stacked therein.
  • the hard mask layer 22 may be a hard mask nitride layer, a hard mask oxide layer, a hard mask silicon oxynitride (SiON) and a hard mask carbon layer sequentially stacked therein.
  • a pad oxide layer may be further formed between the substrate 21 and the hard mask layer 22 .
  • the hard mask layer 22 is formed using a photoresist pattern, which is not shown in the drawing.
  • a trench etch process is performed using the hard mask layer 22 as an etch barrier.
  • conductive structures 23 are formed by etching the substrate 21 to a predetermined depth by using the hard mask layer 22 as an etch barrier.
  • the conductive structures 23 are isolated from each other by trenches 23 A formed therebetween.
  • Each conductive structure 23 includes an active region where a transistor is formed.
  • the conductive structure 23 includes two sidewalls.
  • the trench etch process includes an anisotropic etch process.
  • the anisotropic etch process may include a plasma dry etch process using chlorine (Cl2) gas, hydrogen bromide (HBr) gas, or a mixed gas thereof.
  • a plurality of conductive structures 23 are formed over a substrate 21 A by the trenches 23 A.
  • the conductive structures 23 may be line-type pillars, e.g., line-type active pillars.
  • the active pillars may also be referred to as “pillar-type active regions.”
  • a first liner layer 24 is formed as an insulation layer.
  • the first liner layer 24 includes an oxide layer, e.g., silicon oxide layer.
  • a first gap-fill layer 25 for gap-filling the trenches 23 A between the conductive structures 23 is formed over the first liner layer 24 .
  • the first gap-fill layer 25 may be undoped polysilicon or amorphous silicon.
  • the first gap-fill layer 25 is planarized until the surface of the hard mask layer 22 is shown.
  • the planarization of the first gap-fill layer 25 may use a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • an etch-back process is performed.
  • a first anti-doping layer 25 A providing a first recess R 1 is formed.
  • the first liner layer 24 over the hard mask layer 22 may be polished. Accordingly, a first liner pattern 24 A covering both sidewalls of the hard mask layer 22 and both sidewalls of the trenches 23 A is formed.
  • the first liner pattern 24 A covers the bottoms of the trenches 23 A as well.
  • a second liner layer 26 is formed as an insulation layer over the resultant structure with the first anti-doping layer 25 A formed therein.
  • the second liner layer 26 includes a nitride layer, e.g., silicon nitride layer.
  • the second liner layer 26 is etched to thereby form a second liner pattern 26 A.
  • the first anti-doping layer 25 A is recessed to a predetermined depth by using the second liner pattern 26 A as an etch barrier.
  • a second recess R 2 is formed.
  • the first anti-doping layer with the second recess R 2 is denoted by a reference numeral “ 25 B” and referred to as “a first anti-doping pattern 25 B.”
  • a metal nitride layer is conformally formed over the resultant structure with the second recess R 2 formed therein. Subsequently, a spacer etch process is performed to thereby form a second anti-doping layer 27 .
  • the second anti-doping layer 27 is formed over both sidewalls of the conductive structure 23 .
  • the second anti-doping layer 27 may be a titanium nitride (TiN) layer.
  • a second gap-fill layer 28 gap-filling the second recess R 2 with the second anti-doping layer 27 is formed.
  • the second gap-fill layer 28 includes an oxide layer.
  • the second gap-fill layer 28 may be a spin on dielectric (SOD) layer.
  • the second gap-fill layer 28 is planarized and then undergoes an etch-back process. Accordingly, a recessed second gap-fill pattern 28 A is formed.
  • etch barrier 29 is formed over the resultant structure with the second gap-fill pattern 28 A formed therein.
  • the etch barrier 29 may be formed of undoped polysilicon.
  • a tilt ion implantation process 40 is performed.
  • the tilt ion implantation process 40 is performed to implant the ions of the dopant at a predetermined tilt angle.
  • the dopant is implanted into a portion of the etch barrier 29 .
  • the tilt ion implantation process 40 is performed at a predetermined angle.
  • the angle ranges from approximately 5 to approximately 30°.
  • the hard mask layer 22 blocks a part of ion beam. Therefore, a portion of the etch barrier 29 is doped, and the others remain undoped.
  • the dopant that is ion-implanted is a P-type dopant, e.g., boron (B), boron difluoride (BF2) is used to ion-implant the boron.
  • boron difluoride (BF2) is used to ion-implant the boron.
  • boron difluoride (BF2) is used to ion-implant the boron.
  • a portion of the etch barrier 29 remain undoped, which is a portion formed over the left side of the hard mask layer 22 .
  • a portion of the etch barrier 29 formed on the upper surface of the hard mask layer 22 by the tilt ion implantation process 40 of the dopant and a portion formed over the right side of the hard mask layer 22 become a doped etch barrier 29 A doped with the dopant.
  • the etch barrier into which the dopant is not implanted become an undoped etch barrier 29 B.
  • the undoped etch barrier 29 B is shown to have been removed.
  • polysilicon used as the etch barrier has a different etch rate according to whether it is doped with the dopant or not.
  • the undoped polysilicon into which the dopant is not implanted has a fast wet etch rate. Therefore, the undoped polysilicon is selectively removed using a chemical having a high selectivity, which may wet-etch, for example, only undoped polysilicon.
  • the undoped etch barrier 29 B is removed through a wet etch process or a wet cleaning process.
  • the exposed second anti-doping layers 27 are removed. Accordingly, a first gap 30 is formed.
  • the second anti-doping layer 27 is removed through a wet etch process, and as a result, one portion of the second anti-doping layers remains.
  • the remaining portion of the second anti-doping layers is marked with a reference numeral “ 27 A” and referred to as a “remaining portion 27 A of the second anti-doping layers.”
  • the doped etch barrier 29 A is removed.
  • both of the doped etch barrier 29 A and the first anti-doping pattern 25 B are formed of polysilicon, a portion of the first anti-doping pattern 25 B below the second liner pattern 26 A is removed. Accordingly, a second gap 31 is formed. After the second gap 31 is formed, the first anti-doping layer remains as marked with a reference numeral “ 25 C” and referred to as “a first anti-doping portion 25 C.”
  • the first liner pattern 24 A is exposed through the second gap 31 .
  • the second gap-fill pattern 28 A is removed. Since both of the second gap-fill pattern 28 A and the first liner pattern 24 A are oxide layers, a portion of the sidewalls of the conductive structure 23 is exposed. The region exposing the portion of the sidewalls of the conductive structure 23 is referred to as an “opening 32 .”
  • a cleaning process is performed.
  • the cleaning process may be a wet cleaning process.
  • the wet cleaning process is performed using hydrogen fluoride (HF) or a buffered oxide etchant (BOE).
  • HF hydrogen fluoride
  • BOE buffered oxide etchant
  • the second gap-fill pattern 28 A may be selectively removed without damaging the first anti-doping portion 25 C, the remaining portion 27 A of the second anti-doping layers, and the second liner pattern 26 A.
  • an unaffected portion of the first liner pattern 24 A remains.
  • the remaining portion of the first liner pattern 24 A is marked with a reference numeral “ 24 B” and referred to as a “remaining portion 24 B of the first liner pattern.”
  • the hard mask layer 22 , the remaining portion 24 B of the first liner pattern, the second liner pattern 26 A, the first anti-doping portion 25 C, and the remaining portion 27 A of the second anti-doping layers are collectively called “an anti-doping layer.”
  • the anti-doping layer provides the opening 32 which exposes a portion of the sidewalls of the conductive structure 23 .
  • the opening 32 corresponds to the opening 208 in FIG. 2A of the first embodiment, the opening 308 in FIG. 3A of the second embodiment, and the opening 408 in FIG. 5A of the third embodiment.
  • a doped region doped with a dopant may be easily formed at a desired location of a conductive structure having a 3D structure by using a plasma doping method. Also, the doping depth and doping dose of the doped region may be controlled easily.
  • a junction is formed through the plasma doping method, shallow doping depth may be achieved and thus a shallow junction may be formed without a floating body effect.
  • a shallow one-side-junction (OSJ)
  • OSC one-side-contacts
  • BBL buried bit lines
  • F denotes a minimum feature size

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
US12/774,311 2010-01-29 2010-05-05 Plasma doping method and method for fabricating semiconductor device using the same Abandoned US20110189843A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/185,551 US9054128B2 (en) 2010-01-29 2014-02-20 Plasma doping method and method for fabricating semiconductor device using the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2010-0008826 2010-01-29
KR1020100008826A KR101116356B1 (ko) 2010-01-29 2010-01-29 플라즈마 도핑 방법 및 그를 이용한 반도체장치 제조 방법

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/185,551 Division US9054128B2 (en) 2010-01-29 2014-02-20 Plasma doping method and method for fabricating semiconductor device using the same

Publications (1)

Publication Number Publication Date
US20110189843A1 true US20110189843A1 (en) 2011-08-04

Family

ID=44342058

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/774,311 Abandoned US20110189843A1 (en) 2010-01-29 2010-05-05 Plasma doping method and method for fabricating semiconductor device using the same
US14/185,551 Active US9054128B2 (en) 2010-01-29 2014-02-20 Plasma doping method and method for fabricating semiconductor device using the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US14/185,551 Active US9054128B2 (en) 2010-01-29 2014-02-20 Plasma doping method and method for fabricating semiconductor device using the same

Country Status (4)

Country Link
US (2) US20110189843A1 (ko)
KR (1) KR101116356B1 (ko)
CN (1) CN102142364B (ko)
TW (1) TWI520180B (ko)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100301407A1 (en) * 2009-05-28 2010-12-02 Hynix Semiconductor Inc. Semiconductor device having vertical channel transistor and manufacturing method of the same
US20120220120A1 (en) * 2011-02-25 2012-08-30 Hee-Sung Kang Method for fabricating buried bit line in semiconductor device
US20140001527A1 (en) * 2012-06-29 2014-01-02 SK Hynix Inc. Semiconductor device having buried bit lines and method for fabricating the same
US9105655B2 (en) 2011-12-16 2015-08-11 SK Hynix Inc. Semiconductor device and method for manufacturing the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102619874B1 (ko) 2016-06-23 2024-01-03 삼성전자주식회사 불순물 영역을 갖는 반도체 소자
KR102318309B1 (ko) * 2018-05-31 2021-10-28 삼성전자주식회사 3차원 구조의 도핑 농도 결정 방법, 이를 이용한 반도체 장치의 제조 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040235281A1 (en) * 2003-04-25 2004-11-25 Downey Daniel F. Apparatus and methods for junction formation using optical illumination
US20080290371A1 (en) * 2005-12-13 2008-11-27 Cree, Inc. Semiconductor devices including implanted regions and protective layers
US8063438B2 (en) * 2008-02-29 2011-11-22 Samsung Electronics Co., Ltd. Vertical-type semiconductor devices

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4861729A (en) * 1987-08-24 1989-08-29 Matsushita Electric Industrial Co., Ltd. Method of doping impurities into sidewall of trench by use of plasma source
US6818952B2 (en) * 2002-10-01 2004-11-16 International Business Machines Corporation Damascene gate multi-mesa MOSFET
US6703274B1 (en) * 2003-01-03 2004-03-09 International Business Machines Corporation Buried strap with limited outdiffusion and vertical transistor DRAM
US6936518B2 (en) * 2004-01-21 2005-08-30 Intel Corporation Creating shallow junction transistors
US7223669B2 (en) * 2004-06-16 2007-05-29 International Business Machines Corporation Structure and method for collar self-aligned to buried plate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040235281A1 (en) * 2003-04-25 2004-11-25 Downey Daniel F. Apparatus and methods for junction formation using optical illumination
US20080290371A1 (en) * 2005-12-13 2008-11-27 Cree, Inc. Semiconductor devices including implanted regions and protective layers
US8063438B2 (en) * 2008-02-29 2011-11-22 Samsung Electronics Co., Ltd. Vertical-type semiconductor devices

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100301407A1 (en) * 2009-05-28 2010-12-02 Hynix Semiconductor Inc. Semiconductor device having vertical channel transistor and manufacturing method of the same
US8357969B2 (en) * 2009-05-28 2013-01-22 Hynix Semiconductor Inc Semiconductor device having vertical channel transistor and manufacturing method of the same
US20120220120A1 (en) * 2011-02-25 2012-08-30 Hee-Sung Kang Method for fabricating buried bit line in semiconductor device
US9105655B2 (en) 2011-12-16 2015-08-11 SK Hynix Inc. Semiconductor device and method for manufacturing the same
US20140001527A1 (en) * 2012-06-29 2014-01-02 SK Hynix Inc. Semiconductor device having buried bit lines and method for fabricating the same
US8907393B2 (en) * 2012-06-29 2014-12-09 SK Hynix Inc. Semiconductor device having buried bit lines and method for fabricating the same

Also Published As

Publication number Publication date
KR20110089033A (ko) 2011-08-04
TWI520180B (zh) 2016-02-01
US20140170828A1 (en) 2014-06-19
TW201126576A (en) 2011-08-01
US9054128B2 (en) 2015-06-09
KR101116356B1 (ko) 2012-03-09
CN102142364B (zh) 2016-01-13
CN102142364A (zh) 2011-08-03

Similar Documents

Publication Publication Date Title
US9728638B2 (en) Semiconductor device with one-side-contact and method for fabricating the same
US8354342B2 (en) Semiconductor device with side-junction and method for fabricating the same
US9153654B2 (en) Semiconductor device with buried bit line and method for fabricating the same
US8557662B2 (en) Method for fabricating side contact in semiconductor device using double trench process
US8211769B2 (en) Method for forming junctions of vertical cells in semiconductor device
US8399342B2 (en) Method for fabricating semiconductor device with buried bit lines
US9054128B2 (en) Plasma doping method and method for fabricating semiconductor device using the same
US20130011987A1 (en) Method for fabricating semiconductor device with vertical gate
US8546218B2 (en) Method for fabricating semiconductor device with buried word line
US20120009787A1 (en) Method for forming masking layer by using ion implantation and semiconductor device fabricated by using the same
TWI514514B (zh) 具有側接面之半導體裝置的製造方法
US20120302047A1 (en) Method for fabricating semiconductor device with partially open sidewall
US20130210225A1 (en) Method for fabricating semiconductor device
US20120135605A1 (en) Method for forming side-contact region in semiconductor device
US20120153380A1 (en) Method for fabricating semiconductor device
US20120149202A1 (en) Method for fabricating semiconductor device
US8372751B2 (en) Method for fabricating side contact in semiconductor device
KR20120045407A (ko) 측벽접합을 구비한 반도체장치 제조 방법

Legal Events

Date Code Title Description
AS Assignment

Owner name: HYNIX SEMICONDUCTOR, INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, JIN-KU;OH, JAE-GEUN;LEE, YOUNG-HO;AND OTHERS;REEL/FRAME:024339/0397

Effective date: 20100423

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION