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US20050254309A1 - Program method of non-volatile memory device - Google Patents

Program method of non-volatile memory device Download PDF

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Publication number
US20050254309A1
US20050254309A1 US10/976,628 US97662804A US2005254309A1 US 20050254309 A1 US20050254309 A1 US 20050254309A1 US 97662804 A US97662804 A US 97662804A US 2005254309 A1 US2005254309 A1 US 2005254309A1
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US
United States
Prior art keywords
voltage
program
string select
unselected word
program method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/976,628
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English (en)
Inventor
Oh-Suk Kwon
June Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KWON, OH-SUK, LEE, JUNE
Publication of US20050254309A1 publication Critical patent/US20050254309A1/en
Priority to US11/679,072 priority Critical patent/US7596026B2/en
Abandoned legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Definitions

  • the present invention is a semiconductor memory device, and, in particular, a method of programming a non-volatile memory device.
  • a non-volatile memory device offers the large-scale storage capacity and high integration, without refresh of stored data, and one example of the device is a NAND-type flash memory device. Since the NAND-type flash memory device retains the data even in a case of power-off, it is widely used in applications where the possibility of power supply interruption is present such as portable terminal equipment, a portable computer, and so on.
  • Flash EEPROM devices generally include a semiconductor substrate (or bulk) of a first conductivity type, e.g. P-type; spaced source and drain regions of a second conductivity type, e.g. N-type, in the substrate; a channel region at a face of the substrate, between the spaced source and drain regions; a floating gate for storing charge carriers when the device is programmed; and a control gate which overlies the floating gate, opposite the channel region.
  • a semiconductor substrate or bulk of a first conductivity type, e.g. P-type
  • spaced source and drain regions of a second conductivity type e.g. N-type
  • FIG. 1 An array in the well-known NAND-type flash memory device is shown in FIG. 1 .
  • the memory cell array 10 includes a plurality of cell strings 11 corresponding to bit lines.
  • bit lines BL 0 and BL 1 and two cell strings 11 corresponding thereto are exemplified in FIG. 1 , for the sake of convenience.
  • Each of the cell strings 11 is composed of a string select transistor SST as a first select transistor, a ground select transistor GST as a second select transistor, and a plurality of EEPROM cells MC 0 through MCm being serially connected between the select transistors SST and GST.
  • the string select transistor SST has a drain connected to a corresponding bit line and a gate connected to string select line SSL.
  • the ground select transistor GST has a source connected to a common source line CSL and a gate connected to a ground select line GSL. Between the source of the string select transistor SST and the drain of the ground select transistor GST, the flash EEPROM cells MCm-MC 0 are serially connected, which are respectively connected to word lines WLm-WL 0 corresponding thereto.
  • FIG. 2 is a timing diagram for describing a program method of the non-volatile memory device in FIG. 1 .
  • the memory cells in the memory cell array 10 are erased at a certain threshold voltage, e.g. ⁇ 1V.
  • a high voltage e.g. 20V
  • the selected memory cell is charged to a higher threshold voltage while the threshold voltages of unselected memory cells remain unchanged.
  • a ground path is blocked by applying 0V to the gate of the ground select transistor GST.
  • a zero voltage (0V) potential is applied to a selected bit line, e.g., BL 0
  • a power supply voltage Vcc as the program inhibit voltage is applied to an unselected bit line, e.g., BL 1 .
  • a given voltage e.g., the power supply voltage
  • the string select line i.e., the gate of the string select transistor SST connected to the bit line BL 1 , which causes the source of the string select transistor SST (or the channel of a program inhibited cell transistor) to be charged up to Vcc-Vth (Vth is a threshold voltage of the string select transistor).
  • Vth is a threshold voltage of the string select transistor.
  • the string select transistor SST is substantially blocked or shut off.
  • a time period for the aforementioned operation is referred to “a bit line setup period”.
  • the channel voltage Vchannel of the program inhibited cell transistor is boosted by applying a high voltage, e.g. a program voltage Vpgm, to the selected word line, and applying a lower, e.g. a pass voltage Vpass, to the unselected word lines.
  • a high voltage e.g. a program voltage Vpgm
  • a lower e.g. a pass voltage Vpass
  • F-N Fowler-Nordheim
  • a time period for such an operation is referred to “a program period”.
  • a program voltage When a program voltage is applied to the word line, the voltage is applied not only to the selected memory cell but also to the unselected memory cells along the same word line for programming.
  • the unselected memory cell in particular the memory cell adjacent to the selected memory cell, is programmed.
  • the unintentional programming of an unselected memory cell connected to a selected word line is referred to herein as “program disturb.”
  • One of the ways for preventing program disturb is a program inhibit method employing a self-boosting scheme.
  • the program inhibit method employing the self-boosting scheme is disclosed in U.S. Pat. No. 5,677,873 entitled “Method of Programming Flash EEPROM Integrated Circuit Memory Devices to Prevent Inadvertent Programming of Nondesignated NAND memory cells therein”, and U.S. Pat. No. 5,991,202 entitled “Method for Reducing Program Disturb during Self-Boosting in a NAND flash Memory”, which are incorporated herein by reference.
  • the aforementioned program method has the following problem. As memory devices are scaled down, the space between adjacent signal lines is reduced. Thus, there arises capacitive coupling between adjacent signal lines through parasitic capacitance that sexits between the adjacent signal lines. For example, when a program voltage Vpgm or a pass voltage Vpass is applied to a word line WLm adjacent to a string select line SSL (or located just below the string select line), as illustrated in FIG. 2 , a voltage (e.g., Vcc) of the string select line SSL becomes higher than the power supply voltage Vcc due to capacitive coupling with the word line WLm.
  • a program method of a non-volatile memory device comprises setting a string select line to a predetermined voltage, and setting a selected word line to a program voltage and unselected word lines to a pass voltage respectively.
  • the program voltage is varied according to an arrangement of the selected word line.
  • a voltage lower than the pass voltage is supplied to the adjacent unselected word line to the string select line.
  • the predetermined voltage is lower than the voltage supplied to the adjacent unselected word line to the string select line.
  • the string select line is set to the predetermined voltage before the selected and unselected word lines are set to corresponding voltages, respectively.
  • the method further comprises setting each bit line to either a power supply voltage or a ground voltage according to data to be programmed after the selected and unselected word lines are set to corresponding voltages, respectively.
  • the string select line is set to the predetermined voltage after the selected and unselected word lines are set to corresponding voltages, respectively.
  • FIG. 1 is a diagram of an array structure of a conventional NAND-type flash memory device
  • FIG. 2 is a timing diagram for describing a program method of a non-volatile memory device in FIG. 1 ;
  • FIGS. 3 to 5 are timing diagrams for describing program methods of a non-volatile memory device according to exemplary embodiments of the present invention.
  • a pass voltage and a program voltage described in FIG. 2 are respectively referred to as a first pass voltage and a first program voltage and marked by Vpass 1 and Vpgm 1 .
  • a word line connected to a memory cell to be programmed is referred to as a selected word line and remaining word lines as unselected word lines.
  • a second program voltage Vpgm 2 lower than the first program voltage Vpgm 1 is applied to the selected word line adjacent to the string select line SSL.
  • a second pass voltage Vpass 2 lower than the first pass voltage Vpass 1 is applied to the unselected word line adjacent to the string select line SSL.
  • the second pass voltage Vpass 2 and the second program voltage Vpgm 2 are higher than a voltage applied to the string select line SSL.
  • a voltage (e.g., a power supply voltage) of the string select line SSL is prevented from being boosted higher than the power supply voltage Vcc due to capacitive coupling with an adjacent word line.
  • charges that are charged at a channel of a program inhibited cell transistor are prevented from being leaked out to a bit line through a string select transistor SST.
  • FIG. 3 is a timing diagram for a program method of a non-volatile memory device according to a first embodiment of the present invention.
  • a word line WLm adjacent to a string select line SSL is an unselected word line.
  • a program method of a non-volatile memory device according to a first embodiment of the present invention will be more fully described below.
  • memory cells are programmed, they are erased to have, for example, a threshold voltage of ⁇ 1V.
  • Data to be stored in a memory cell array is loaded onto a sense amplifier and latch circuit (not shown) known as a page buffer circuit by a bit organization structure (e.g., ⁇ 8, ⁇ 16, etc.).
  • a bit organization structure e.g., ⁇ 8, ⁇ 16, etc.
  • bit lines BL 0 and BL 1 are pre-charged toat a power supply voltage through the sense amplifier and latch circuit. While the bit lines BL 0 and BL 1 are pre-charged to the power supply voltage, a string select line SSL, the word line WL 0 -WLm and a ground select line GSL are maintained at thea low level of a ground voltage. Since the string select line SSL has the ground voltage, each cell string is electrically separated from a corresponding bit line.
  • the power supply voltage Vcc is supplied to the string select line SSL, so that a channel region of each string is charged up to VCC-Vth (Vth is a threshold voltage of the string select transistor).
  • Vth is a threshold voltage of the string select transistor.
  • string select transistors SST of cell strings 11 are shut off. This forces channel regions of the cell strings 11 to be ingfloated.
  • the first program voltage Vpgm 1 is supplied to a selected word line (e.g., WL 0 ) and the first pass voltage Vpass 1 is supplied to unselected word lines (e.g., WL 1 -WLm- 1 ).
  • unselected word lines e.g., WL 1 -WLm- 1
  • the second pass voltage Vpass 2 lower than the first pass voltage Vpass 1 is supplied to the unselected word line WLm adjacent to the string select line SSL.
  • a voltage of the selected word line WL 0 is increased from the first pass voltage Vpass 1 to the first program voltage Vpgm 1 . Since the channel regions of the cell strings 11 are floated, they are boosted. Accordingly, memory cells of the selected word line WL 0 are not programmed. This is because F-N tunneling is prevented between a floating gate and the channel region.
  • the ground voltage as a program voltage or the power supply voltage as a program inhibit voltage is supplied to each bit line according to the loaded data.
  • the ground voltage is applied to a bit line when data to be programmed is ‘0’
  • the power supply voltage is applied to a bit line when data to be programmed is ‘1’.
  • a string select transistor connected to a bit line having the ground voltage is changed from a shut-off state to a turn-on state, so that a boosted voltage of a string having a turned-on string select transistor is discharged through the sense amplifier and latch circuit. That is, a channel region of a cell string is supplied with the ground voltage.
  • a memory cell(s) in the selected word line WL 0 is programmed through the above F-N tunneling.
  • FIG. 4 is a timing diagram for a program method of a non-volatile memory device according to a second embodiment of the present invention.
  • the second pass voltage Vpass 2 lower than the first pass voltage Vpass 1 is applied to the selected word line WLm. Then, a voltage of the selected word line WLm is increased up to the second program voltage Vpgm 2 .
  • the second program voltage Vpgm 2 is lower than the first program voltage Vpgm 1 and higher than the first and second pass voltages Vpass 1 and Vpass 2 .
  • Each of the remaining unselected word lines WL 0 -WLm- 1 is supplied with the first pass voltage Vpass 1 .
  • the program method of the present non-volatile memory device according to the second embodiment is identical to that in FIG. 3 , and description thereof is thus omitted.
  • FIG. 5 is a timing diagram for a program method of a non-volatile memory device according to a third embodiment of the present invention.
  • the first pass voltage Vpass 1 is simultaneously supplied to all word lines WL 0 -WLm. Then, a voltage of the selected word line WLm is increased from the first pass voltage Vpass 1 to the second program voltage Vpgm 2 .
  • the program method of the prevent non-volatile memory device according to the third embodiment is identical to that in FIG. 3 , and description thereof is thus omitted.
  • a program voltage supplied to a selected word line can be varied according to its arrangement.
  • program/program inhibit conditions of memory cells may be changed differently from expected conditions due to capacitive coupling.
  • the expected conditions comprise a coupling ratio of a memory cell, loading difference by the length of a signal line, etc. Accordingly, program voltages of different levels can be assigned to corresponding word lines to satisfy the optimum program conditions
  • the first/second program voltage Vpgm 1 /Vpgm 2 can be applied directly to a selected word line without applying the first/second pass voltages Vpass 1 /Vpass 2 thereto.
  • the first pass voltage Vpass 1 is supplied to each of the unselected word lines while the second program voltage Vpgm 2 is applied to the selected word line.
  • a power supply voltage is supplied to a string select line after supplying of the first/second program voltage to the selected word line.
  • a ground voltage as a program voltage can be applied to a bit line before a power supply voltage is applied to a string select line.
  • Combinations of the above program methods can be incorporated in the present invention.As can be realized from the described embodiments above, there are a number of combinations of events and voltage levels involved. The combinations depend on, for example, if the selected word line is adjacent to the string select line, and if a step in the embodiment sets the string select line to the predetermined voltage before the word lines are set to corresponding voltages.
  • the term ‘corresponding’ refers to the applied voltage respective of the what is called out in the specific embodiment.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
US10/976,628 2004-05-17 2004-10-29 Program method of non-volatile memory device Abandoned US20050254309A1 (en)

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KR2004-34863 2004-05-17

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US20070140013A1 (en) 2007-06-21

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