[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

US20050127382A1 - Carrier layer for a semiconductor layer sequence and method for producing semiconductor chips - Google Patents

Carrier layer for a semiconductor layer sequence and method for producing semiconductor chips Download PDF

Info

Publication number
US20050127382A1
US20050127382A1 US10/999,854 US99985404A US2005127382A1 US 20050127382 A1 US20050127382 A1 US 20050127382A1 US 99985404 A US99985404 A US 99985404A US 2005127382 A1 US2005127382 A1 US 2005127382A1
Authority
US
United States
Prior art keywords
layer
semiconductor
carrier layer
carrier
sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US10/999,854
Other versions
US7723730B2 (en
Inventor
Stefan Groetsch
Stefan Illek
Andreas Ploessl
Berthold Hahn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Osram Oled GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Assigned to OSRAM OPTO SEMICONDUCTORS GMBH reassignment OSRAM OPTO SEMICONDUCTORS GMBH ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HAHN, BERTHOLD, GROETSCH, STEFAN, ILLEK, STEFAN, PLOESSL, ANDREAS
Publication of US20050127382A1 publication Critical patent/US20050127382A1/en
Application granted granted Critical
Publication of US7723730B2 publication Critical patent/US7723730B2/en
Assigned to OSRAM OLED GMBH reassignment OSRAM OLED GMBH ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OSRAM OPTO SEMICONDUCTORS GMBH
Anticipated expiration legal-status Critical
Active legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/641—Heat extraction or cooling elements characterized by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83048—Thermal treatments, e.g. annealing, controlled pre-heating or pre-cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12036—PN diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/647—Heat extraction or cooling elements the elements conducting electric current to or from the semiconductor body

Definitions

  • the present invention relates to a carrier layer for a semiconductor layer sequence, and particularly to a carrier layer comprising an electrical insulation layer.
  • a carrier layer is regarded as a layer on which the semiconductor layer sequence is arranged in the course of its processing. In particular, this is done prior to a singulation into semiconductor chips which comprise semiconductor chip regions and the latter in turn comprise a part of the semiconductor layer sequence.
  • the semiconductor layer sequence is intended for forming a plurality of semiconductor chip regions. Said semiconductor chips may subsequently be processed further for semiconductor components.
  • the carrier layer is at any rate to be differentiated from a growth substrate of the abovementioned semiconductor layer sequence.
  • a carrier layer of this type should be well matched to the semiconductor layer sequence with regard to its coefficient of expansion, in order to avoid strains that are damaging to the semiconductor layer sequence in the event of heating, and have a high thermal conductivity, in order to ensure a good dissipation of heat from the semiconductor layer sequence, in particular the later semiconductor chip (i.e., the chip formed after singulation).
  • the electrical conductivity thereof is to be chosen to be appropriately high.
  • Carrier layers made of semiconductor materials, such as Ge or GaAs, and made of metals, such as Mo or CuW, are known, by way of example.
  • semiconductor materials in comparison with metals, often have lower thermal or electrical conductivities and often have a lower mechanical stability, in particular with regard to brittlements, thereby increasing the risk of damage to the semiconductor layer sequence and thus the later semiconductor chips.
  • semiconductor materials are usually better matched to the semiconductor layer sequence than metals.
  • chip carriers made of an electrically insulating AlN ceramic is known, on which semiconductor chips can be arranged after singulation.
  • These chip carriers may have a conductor structure that enables the semiconductor chip to be electrically contact-connected from that side of the chip carrier which is opposite to the chip.
  • Said conductor structure may comprise plated-through holes through the chip carrier, so-called vias, which are filled with tungsten.
  • Chip carriers of this type are distinguished by a good thermal conductivity. With regard to their coefficients of expansion, chip carriers of this type can be matched to the semiconductor layer sequence by means of suitable process implementation during production. Since each individual chip is assigned a chip carrier of this type, the production of such chips is cost- and time-intensive.
  • One object of the present invention is to provide a carrier layer for a semiconductor layer sequence of the type mentioned in the introduction, having an improved matching with regard to its thermal properties, in particular the coefficient of expansion, to the semiconductor layer sequence.
  • Another object is to provide a production method for semiconductor chips using a carrier layer of this type.
  • a carrier layer for a semiconductor layer sequence comprising an electrical insulation layer, wherein the insulation layer contains AlN.
  • the AlN is preferably formed as ceramic and/or in radiation-opaque fashion.
  • a ceramic containing aluminum nitride is particularly suitable as the carrier layer.
  • the semiconductor layer sequence is arranged for example on a first main area of the carrier layer.
  • a carrier layer for a semiconductor layer sequence comprises an electrical insulation layer containing a ceramic.
  • a ceramic containing carrier layer is particularly suitable as a carrier layer.
  • the ceramic preferably contains an aluminum nitride or an aluminum oxide.
  • semiconductor layer sequence is to be understood as a general succession of semiconductor layers arranged one above the other, such as, for example, the semiconductor layers of a semiconductor wafer that have been grown for example epitaxially on a growth substrate.
  • a carrier layer of this type has the advantage of a high thermal conductivity, which may in the case of an AlN containing carrier layer for example be as much as 230 W/mK. Furthermore, the risk of a short circuit being caused in the later semiconductor chips during singulation is at least greatly reduced by virtue of the electrically insulating ceramic or of the electrically insulating AlN, respectively.
  • the thermal expansion properties of the carrier layer and of the semiconductor layer sequence are advantageously matched to one another, in particular for protection against strains. This may be achieved for example by means of a suitable process implementation during the production of the carrier layer.
  • a carrier layer of this type may be distinguished by an advantageously high stability compared with carrier layers made of semiconductor materials such as Ge or GaAs.
  • the carrier layer is preferably formed in self-supporting fashion, so that it mechanically stabilizes its inherent weight and, particularly preferably, the semiconductor layer sequence as well.
  • the thickness of the insulation layer is preferably greater than 50 ⁇ m, particularly preferably greater than 100 ⁇ m.
  • the semiconductor layer sequence may be connected to the carrier layer by means of a connecting layer formed for example by a solder, eutectic bonding with suitable metal layers or adhesive bonding. This connection is preferably formed in electrically conductive fashion.
  • the semiconductor layer sequence comprises a radiation-generating active zone, for example a pn junction, a single or multiple quantum well structure.
  • the semiconductor layer sequence may be formed for LED chips, radiation-emitting semiconductor components with a resonator, such as edge-emitting lasers or vertically emitting components such as VCSEL, VECSEL or RCLEDs.
  • the wavelength of the radiation generated lies in the ultraviolet to infrared spectral range.
  • the high thermal conductivity of the carrier layer is advantageous precisely in the case of the lasers mentioned since the heat arising in said components is usually considerable and is advantageously dissipated from the component in order not to impair the function thereof.
  • An additional heat sink may particularly advantageously be dispensed with in the case of lasers and also in the case of the further components presented above.
  • the semiconductor layer sequence can contain at least one III-V semiconductor material, comprising In x Ga y Al 1-x-y P, In x Ga y Al 1-x-y N or In x Ga y Al 1-x-y As, in each case where O ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1 and x+y ⁇ 1.
  • the active zone particularly preferably contains at least one of said materials.
  • a mirror layer is arranged downstream of the active zone, for example between the active zone and the first main area of the carrier layer.
  • Said mirror layer may comprise for example a distributed Bragg mirror, preferably formed in the semiconductor layer sequence, and/or a metal layer, for example containing Au, Al, Ag, Pt or alloys having at least one of said materials.
  • the mirror layer is preferably formed in electrically conductive fashion and/or electrically conductively connected to the semiconductor layer sequence and may be part of an optical resonator, for example for a vertically emitting component.
  • a mirror layer of this type advantageously increases the efficiency of a later semiconductor chip.
  • the latter has a conductor structure, which electrically conductively connects the first main area to a second main area opposite thereto and thereby enables the semiconductor layer sequence to be electrically contact-connected from the second main area of the carrier layer.
  • Said conductor structure can comprise cutouts in the carrier layer that reach from the first to the second main area.
  • an electrically conductive material for example a metal such as, for instance, W, Cu, Ag or Au or an alloy having at least one of said materials, which is electrically conductively connected to the semiconductor layer sequence.
  • the material in the cutout is well matched to the ceramic or to the AlN, respectively, in particular with regard to the mechanical and thermal properties.
  • W for example, fulfils these conditions at least with regard to the coefficient of thermal expansion and with regard to AlN.
  • a carrier layer of this type made of AlN with a conductor structure containing W may be well matched to the semiconductor layer sequence, in particular with regard to the coefficients of expansion.
  • the risk of damage to the semiconductor layer sequence due to strains that are caused thermally is reduced and, more widely, the electrical contact connection of the semiconductor layer sequence by means of the second main area of the carrier layer is made possible.
  • the thermal conductivity with 195 W/mK may also advantageously be increased compared with carrier layers made of semiconductor materials.
  • an additional thermally conductive substance for example in the form of diamond particles, is introduced into said conductor structure, said substance being arranged in the cutout and having a higher thermal conductivity than the electrically conductive material in the cutout.
  • This thermally conductive substance advantageously increases the thermal conductivity of the conductor structure, in particular in the region of the cutout and consequently that of the carrier layer comprising the cutouts.
  • the thermally conductive substance may improve the matching of the mechanical properties of the electrically conductive material in the cutout to that of the insulation layer since the proportion of electrically conductive material in the cutout is reduced at the expense of the thermally conductive substance, which advantageously has suitable mechanical and thermal properties, for this purpose.
  • Another aspect of invention is directed to a method for producing semiconductor chips with a semiconductor chip region that has a radiation-generating active zone and is arranged on a chip carrier containing AlN in a first variation or a ceramic in a second variation.
  • a semiconductor layer sequence is produced on a substrate, such as by epitaxial growth on a growth substrate.
  • the semiconductor layer sequence is subsequently arranged on an AlN-containing or a ceramic containing carrier layer, respectively, whereupon the substrate is removed.
  • the carrier layer or the semiconductor layer sequence are preferably formed as in the corresponding embodiments above, so that the carrier layer comprises for example a conductor structure or the carrier layer and the semiconductor layer sequence may have other features from the features mentioned there. Further embodiments from the above embodiments may also be applied correspondingly to the method.
  • a metallic mirror layer may be applied, preferably by sputtering or vapour deposition, onto the semiconductor layer sequence, on the side remote from the substrate, prior to arrangement on the carrier layer.
  • the semiconductor layer sequence is thereupon patterned into semiconductor chip regions that are preferably spatially separate from one another, and the structure comprising semiconductor chip regions and carrier layer is singulated, for example by sawing or a laser separating method, into semiconductor chips in such a way that the semiconductor chips in each case comprise at least one semiconductor chip region.
  • the singulation can be effected in the interspaces between the semiconductor chip regions.
  • the semiconductor chip is arranged on a chip carrier containing a ceramic or AlN, respectively, after singulation, and which chip carrier emerges from the carrier layer during singulation.
  • Semiconductor chips produced by removal of the growth substrate and arrangement of the semiconductor layer sequence on a carrier layer are referred to as thin-film chips.
  • the patterning of the semiconductor layer sequence may also be wholly or partly effected while the semiconductor layer sequence is still arranged on the substrate, that is to say prior to arrangement on the carrier, and is not restricted to the formation of the semiconductor chip regions. Rather, it is also possible to provide structures that improve the coupling-out of light from the semiconductor chip, protect the chip from damaging effects, or to carry out other processes during the patterning.
  • each semiconductor chip region can be electrically conductively connected to the conductor structure.
  • Such a production method for semiconductor chips has the advantage that, in a continuous process, it is possible to produce semiconductor chips which are arranged on an AlN-containing or respectively a ceramic containing chip carrier that is well matched to the semiconductor layer sequence with regard to the coefficient of expansion and has an advantageously high thermal conductivity.
  • the chips do not have to be arranged individually on the chip carrier since the latter emerges from the carrier layer during singulation, as a result of which the production duration and production costs of semiconductor chips of this type are reduced.
  • FIG. 1A shows a diagrammatic sectional view of a part of an exemplary embodiment of a carrier layer according to the invention
  • FIG. 1B shows a plan view of a part of an exemplary embodiment of a carrier layer according to the invention.
  • FIG. 2 shows a diagrammatic illustration of an exemplary embodiment of a method according to the invention for producing a semiconductor chip, on the basis of intermediate steps, in FIGS. 2A to 2 F.
  • FIG. 1A shows a diagrammatic sectional view of a part of a first exemplary embodiment of a carrier layer according to the invention.
  • the carrier layer 1 comprises an insulation layer 2 containing AlN, in particular an AlN ceramic, having a thickness of 200 ⁇ m, for example. Cutouts 3 are provided in the insulation layer 2 , an electrical conductor material 4 , for example W, being arranged in said cutouts in such a way that a first main area 5 of the carrier layer 1 is electrically conductively connected to a second main area 6 .
  • a semiconductor layer sequence 7 Arranged over the carrier layer 1 is a semiconductor layer sequence 7 , which is connected to the carrier layer 1 by means of a connecting layer 8 and a mirror layer 9 .
  • the connecting layer 8 is formed in electrically conductive fashion, for example as solder, so that the radiation-generating active zone 10 of the semiconductor layer sequence 7 is conductively connected to the conductor material 4 by means of the electrically conductive mirror layer 9 .
  • the carrier layer 1 is formed in self-supporting fashion, mechanically stabilizes the semiconductor layer sequence 7 and ensures that the semiconductor layer sequence 7 can be electrically contact-connected by means of the cutouts 4 from the second main area 6 . Furthermore, the carrier layer 1 , with W in the cutouts, has a high thermal conductivity, for example of 195 W/mK, which is additionally increased by introducing a thermally conductive substance 11 , for example diamond particles, into the electrical conductor material in the cutout 3 . Moreover, in particular by means of the process implementation during the production of the insulation layer 2 , the carrier layer 1 may be matched to the coefficients of thermal expansion of the semiconductor layer sequence in such a way that the latter is improved compared with metallic carrier layers. Furthermore, a carrier layer of this type has an increased electrical and thermal conductivity compared with most semiconductor materials at least in the region of the cutouts 4 .
  • the semiconductor layer sequence 7 may be formed for LED chips, radiation-emitting semiconductor components with a resonator, such as edge-emitting lasers or vertically emitting components such as VCSEL, VECSEL or RCLEDs, and the mirror layer 9 may comprise for example a metal layer or a distributed Bragg mirror that may be formed in the semiconductor layer sequence 7 .
  • FIG. 1B illustrates a plan view of a part of an exemplary embodiment of a carrier layer according to the invention.
  • FIG. 1A shows a part of a plan view of the second main area 6 of a carrier layer 1 , such as, for instance, that from FIG. 1A .
  • the cutouts 3 in the insulation layer 2 with the conductor material 4 and the thermally conductive substance 11 are arranged in a regular grid, which proves to be advantageous for the further processing, in particular during the production of semiconductor chips using a carrier layer 1 of this type (cf. FIG. 2 and the associated description), and have a circular cross section, for example, in plan view.
  • FIG. 1B illustrates as an example of a regular grid a square lattice, at the lattice points of which a cutout 3 is respectively arranged.
  • the cutouts 3 are stamped into the still soft AlN material (“green sheet”; a green sheet is a ceramic compound which is still soft, but may nevertheless be formed or patterned, such that the patterned structure, e.g., vias, keeps its shape; afterward the green sheet is sintered to stabilize the patterned structure resulting in a mechanically stable and solid ceramic carrier layer), for example, in order to produce a carrier layer of this type.
  • the tools used determine the form of the cross section of the cutouts.
  • a W paste as conductor material 4 and the thermally conductive substance 11 may be introduced into the cutout 3 .
  • the carrier layer 1 is then completed by sintering and the semiconductor layer sequence 7 may be arranged on the carrier layer 1 in the manner illustrated in FIG. 1A .
  • the AlN material is sintered after the production of the cutouts 3 and the semiconductor layer sequence 7 is then arranged on the AlN material.
  • the conductor material 4 may thereupon be introduced into the cutouts 3 by means of a galvanic procedure. This process may advantageously be carried out at temperatures that are not harmful to the semiconductor layer sequence 7 .
  • a conductor material 4 containing Ag or Cu is preferably used for this purpose.
  • FIG. 2 shows a diagrammatic illustration of an exemplary embodiment of a method according to the invention for producing a semiconductor chip, on the basis of intermediate steps illustrated in FIGS. 2A to 2 F.
  • an LED thin-film chip with a mirror layer is described in this exemplary embodiment.
  • the method illustrated may be correspondingly applied to chips that are formed for LEDs, RCLEDs and also for lasers such as VCSEL, VECSEL or edge-emitting lasers or for other types of semiconductor chips.
  • a semiconductor layer sequence 7 for example containing In x Ga y Al 1-x-y P or In x Ga y Al 1-x-y N, grown epitaxially on a growth substrate 16 , with a radiation-generating active zone 10 , is provided with a mirror layer 9 in a first intermediate step in FIG. 2A .
  • the growth substrate 16 is preferably of GaAs and the mirror layer is made of Au;
  • In x Ga y Al 1-x-y N for example sapphire or SiC are suitable as growth substrates and Ag or Al are suitable as material for the mirror layer.
  • The, particularly metal-containing, mirror layer 9 is preferably applied by sputtering or vapor deposition onto that side of the semiconductor layer sequence 7 which is remote from the growth substrate 16 .
  • the mirror layer 9 is fixed on a first main area 5 of the carrier layer 1 by means of an electrically conductive connecting layer 8 , for example a solder.
  • the carrier layer 1 has an electrical insulation layer 2 made of AlN, in particular an AlN ceramic, in which cutouts 3 are provided, a conductor material 4 , for example W, being arranged in said cutouts, and a thermally conductive substance 11 , for example in the form of diamond particles, in turn being arranged in said conductor material.
  • the conductor structure comprising the cutouts 3 with the conductor material 4 permits the semiconductor layer sequence 7 to be electrically contact-connected from a second main area 6 of the carrier layer 1 opposite to the first main area 5 .
  • the electrical contact is effected by means of the conductor material 4 , which is electrically conductively connected to the semiconductor layer sequence 7 by means of the conductive connecting layer 8 and the mirror layer 9 .
  • the growth substrate 16 is thereupon removed preferably by etching, mechanical loading or a laser ablation method, which results in the structure shown in FIG. 2B with the carrier layer 1 and the semiconductor layer sequence 7 arranged thereon.
  • a carrier layer of this type is particularly suitable for use in the case of semiconductor layer sequences containing In x Ga y Al 1-x-y P or In x Ga y Al 1-x-y N, since AlN with approximately 4.4 ppm/° C. has a coefficient of thermal expansion that is well matched to those of the growth substrates GaAs and sapphire, having values of approximately 6 and 4.5 ppm/° C., respectively. Furthermore, the thermal conductivity of a carrier layer according to the invention with approximately 195 W/mK is also advantageously increased compared with carrier layers made of semiconductor materials such as GaAs, for example, which has a thermal conductivity of approximately 55 W/mK.
  • the semiconductor layer sequence 7 is patterned, for example by masking and etching techniques, into semiconductor chip regions 12 in such a way that the latter are spatially separated from one another by interspaces 13 .
  • the semiconductor chip regions 12 may be provided with radiation-coupling out, passivation or protection structures that advantageously increase the coupling-out of radiation from the later semiconductor chip or protect the chip from damaging effects.
  • the patterning may also be wholly or partly effected while the semiconductor layer sequence 7 is still arranged on the growth substrate 16 .
  • FIGS. 2C and 2D show the semiconductor chip regions 12 arranged on the carrier layer 1 after the above patterning process.
  • FIG. 2C no conductor material 4 is arranged in the region of the interspaces 13 , in contrast to FIG. 2D .
  • the arrangement illustrated in FIG. 2C therefore requires a high alignment outlay, either during the patterning of the semiconductor layer sequence 7 on the carrier layer 1 or during the arrangement of the already partly or completely patterned semiconductor layer sequence 7 on the carrier layer 1 .
  • the cutouts 3 in the carrier layer 1 during the production thereof, must also be arranged in accordance with the size of a later semiconductor chip.
  • the advantage of such an arrangement of the conductor material 4 is that the singulation of the structure illustrated, for example by sawing, along the separating lines 14 into semiconductor chips 15 , as illustrated in FIG. 2E , is effected only in the electrically insulating AlN.
  • each semiconductor chip region 12 is thus assigned at least one cutout 3 with the conductor material 4 , which is completely covered by the semiconductor chip region 12 .
  • conductor material 4 is arranged in the region of some interspaces 13 .
  • This has the advantage of a lower necessary alignment outlay compared with the arrangement in FIG. 2C .
  • it is merely necessary to ensure that essentially each semiconductor chip region 2 is connected to the conductor material. This may be achieved for example by means of a correspondingly high density of cutouts 3 with conductor material 4 in the insulation layer 2 .
  • singulation into semiconductor chips 15 is subsequently effected along the separating lines 14 , as illustrated in FIG. 2F , then this is done at least partly in the conductor material 4 , whereby the risk of a short circuit of the active zone 10 may be increased.
  • the conductor material 4 is W, for example, which has a high hardness, it is possible to reduce the formation of W slivers during singulation, for example by sawing, which in turns reduces the risk of a short circuit.
  • the “saw blade” may become blunt, which can be compensated for by sawing in the AlN ceramic again since ceramics are often used to sharpen the “saw blades”.
  • the semiconductor chips 15 illustrated in FIGS. 2E and 2F in each case comprise one semiconductor chip region 12 arranged on a chip carrier 101 that emerges from the carrier layer 1 during singulation.
  • the semiconductor chip regions 12 can be electrically contact-connected by means of the conductor material from the second main area 6 and the chip carrier 101 ensures a good dissipation of heat from the semiconductor chip region 12 .
  • the mirror layer 9 reflects the radiation generated in the active zone 10 and thus increases the efficiency of the semiconductor chip 15 .
  • Such a production method for semiconductor chips has the advantage that the AlN-containing carrier layer can be processed conjointly with the semiconductor layer sequence. Consequently, it is not necessary for each individual semiconductor chip 15 to be equipped with a chip carrier 101 of this type, thereby reducing the production costs and the required production time for semiconductor chips on a chip carrier of this type.
  • an additional heat sink can advantageously be dispensed with owing to the high thermal conductivity of the carrier layer.
  • the volume thereof may be increased for example by larger interspaces 13 or a thicker carrier layer 1 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Ceramic Products (AREA)
  • Dicing (AREA)

Abstract

A carrier layer (1) for a semiconductor layer sequence comprising an electrical insulation layer (2) containing AlN or a ceramic. Furthermore a method for producing semiconductor chips is described.

Description

    RELATED APPLICATIONS
  • This patent application claims the priority of German. Patent Application No. 103 55 600.1 filed Nov. 28, 2003, the disclosure content of which is hereby incorporated by reference.
    • FIELD OF THE INVENTION
  • The present invention relates to a carrier layer for a semiconductor layer sequence, and particularly to a carrier layer comprising an electrical insulation layer.
    • BACKGROUND OF THE INVENTION
  • In the context of the invention, a carrier layer is regarded as a layer on which the semiconductor layer sequence is arranged in the course of its processing. In particular, this is done prior to a singulation into semiconductor chips which comprise semiconductor chip regions and the latter in turn comprise a part of the semiconductor layer sequence. In particular, the semiconductor layer sequence is intended for forming a plurality of semiconductor chip regions. Said semiconductor chips may subsequently be processed further for semiconductor components. The carrier layer is at any rate to be differentiated from a growth substrate of the abovementioned semiconductor layer sequence.
  • A carrier layer of this type should be well matched to the semiconductor layer sequence with regard to its coefficient of expansion, in order to avoid strains that are damaging to the semiconductor layer sequence in the event of heating, and have a high thermal conductivity, in order to ensure a good dissipation of heat from the semiconductor layer sequence, in particular the later semiconductor chip (i.e., the chip formed after singulation). For the case where the electrical contact connection of the semiconductor layer sequence is effected through the carrier layer, the electrical conductivity thereof is to be chosen to be appropriately high.
  • Carrier layers made of semiconductor materials, such as Ge or GaAs, and made of metals, such as Mo or CuW, are known, by way of example.
  • If metallic carrier layers are used, which usually have a high thermal conductivity, then during singulation, which is often effected by sawing, the risk may be increased of metal slivers or warpage arising on the metal, which render the semiconductor chip unusable, for example due to a short circuit. Frequently, the coefficient of thermal expansion is also inadequately matched to the semiconductor layer sequence and strains may arise between the carrier layer and the semiconductor layer sequence in the event of heating, which have a damaging effect on the semiconductor layer sequence.
  • By contrast, semiconductor materials, in comparison with metals, often have lower thermal or electrical conductivities and often have a lower mechanical stability, in particular with regard to brittlements, thereby increasing the risk of damage to the semiconductor layer sequence and thus the later semiconductor chips. With regard to the coefficients of thermal expansion, however, semiconductor materials are usually better matched to the semiconductor layer sequence than metals.
  • Furthermore, a chip carrier made of an electrically insulating AlN ceramic is known, on which semiconductor chips can be arranged after singulation. These chip carriers may have a conductor structure that enables the semiconductor chip to be electrically contact-connected from that side of the chip carrier which is opposite to the chip. Said conductor structure may comprise plated-through holes through the chip carrier, so-called vias, which are filled with tungsten. Chip carriers of this type are distinguished by a good thermal conductivity. With regard to their coefficients of expansion, chip carriers of this type can be matched to the semiconductor layer sequence by means of suitable process implementation during production. Since each individual chip is assigned a chip carrier of this type, the production of such chips is cost- and time-intensive.
    • SUMMARY OF THE INVENTION
  • One object of the present invention is to provide a carrier layer for a semiconductor layer sequence of the type mentioned in the introduction, having an improved matching with regard to its thermal properties, in particular the coefficient of expansion, to the semiconductor layer sequence.
  • Another object is to provide a production method for semiconductor chips using a carrier layer of this type.
  • This and other objects are attained in accordance with one aspect of the present invention directed to a carrier layer for a semiconductor layer sequence, the carrier layer comprising an electrical insulation layer, wherein the insulation layer contains AlN.
  • The AlN is preferably formed as ceramic and/or in radiation-opaque fashion. A ceramic containing aluminum nitride is particularly suitable as the carrier layer. The semiconductor layer sequence is arranged for example on a first main area of the carrier layer.
  • A carrier layer for a semiconductor layer sequence according to another aspect of the invention comprises an electrical insulation layer containing a ceramic. A ceramic containing carrier layer is particularly suitable as a carrier layer. The ceramic preferably contains an aluminum nitride or an aluminum oxide.
  • It should be noted that, in the context of the present invention, the term semiconductor layer sequence is to be understood as a general succession of semiconductor layers arranged one above the other, such as, for example, the semiconductor layers of a semiconductor wafer that have been grown for example epitaxially on a growth substrate.
  • A carrier layer of this type has the advantage of a high thermal conductivity, which may in the case of an AlN containing carrier layer for example be as much as 230 W/mK. Furthermore, the risk of a short circuit being caused in the later semiconductor chips during singulation is at least greatly reduced by virtue of the electrically insulating ceramic or of the electrically insulating AlN, respectively. The thermal expansion properties of the carrier layer and of the semiconductor layer sequence are advantageously matched to one another, in particular for protection against strains. This may be achieved for example by means of a suitable process implementation during the production of the carrier layer.
  • Furthermore, a carrier layer of this type may be distinguished by an advantageously high stability compared with carrier layers made of semiconductor materials such as Ge or GaAs. For this purpose, the carrier layer is preferably formed in self-supporting fashion, so that it mechanically stabilizes its inherent weight and, particularly preferably, the semiconductor layer sequence as well. The thickness of the insulation layer is preferably greater than 50 μm, particularly preferably greater than 100 μm.
  • The semiconductor layer sequence may be connected to the carrier layer by means of a connecting layer formed for example by a solder, eutectic bonding with suitable metal layers or adhesive bonding. This connection is preferably formed in electrically conductive fashion.
  • In one embodiment of the invention, the semiconductor layer sequence comprises a radiation-generating active zone, for example a pn junction, a single or multiple quantum well structure. The semiconductor layer sequence may be formed for LED chips, radiation-emitting semiconductor components with a resonator, such as edge-emitting lasers or vertically emitting components such as VCSEL, VECSEL or RCLEDs. Preferably, the wavelength of the radiation generated lies in the ultraviolet to infrared spectral range.
  • The high thermal conductivity of the carrier layer is advantageous precisely in the case of the lasers mentioned since the heat arising in said components is usually considerable and is advantageously dissipated from the component in order not to impair the function thereof. An additional heat sink may particularly advantageously be dispensed with in the case of lasers and also in the case of the further components presented above.
  • The semiconductor layer sequence can contain at least one III-V semiconductor material, comprising InxGayAl1-x-yP, InxGayAl1-x-yN or InxGayAl1-x-yAs, in each case where O≦x≦1, 0≦y≦1 and x+y≦1. The active zone particularly preferably contains at least one of said materials.
  • In another embodiment of the invention, a mirror layer is arranged downstream of the active zone, for example between the active zone and the first main area of the carrier layer. Said mirror layer may comprise for example a distributed Bragg mirror, preferably formed in the semiconductor layer sequence, and/or a metal layer, for example containing Au, Al, Ag, Pt or alloys having at least one of said materials. The mirror layer is preferably formed in electrically conductive fashion and/or electrically conductively connected to the semiconductor layer sequence and may be part of an optical resonator, for example for a vertically emitting component. A mirror layer of this type advantageously increases the efficiency of a later semiconductor chip.
  • In another embodiment of the carrier layer, the latter has a conductor structure, which electrically conductively connects the first main area to a second main area opposite thereto and thereby enables the semiconductor layer sequence to be electrically contact-connected from the second main area of the carrier layer.
  • Said conductor structure can comprise cutouts in the carrier layer that reach from the first to the second main area. Arranged in said cutouts is an electrically conductive material, for example a metal such as, for instance, W, Cu, Ag or Au or an alloy having at least one of said materials, which is electrically conductively connected to the semiconductor layer sequence.
  • The material in the cutout is well matched to the ceramic or to the AlN, respectively, in particular with regard to the mechanical and thermal properties. In an advantageous manner, the strains that may occur between the insulation layer and the material in the cutout are thereby reduced and the stability of the carrier layer with the conductor structure is consequently increased. W, for example, fulfils these conditions at least with regard to the coefficient of thermal expansion and with regard to AlN. A carrier layer of this type made of AlN with a conductor structure containing W may be well matched to the semiconductor layer sequence, in particular with regard to the coefficients of expansion. Thus, the risk of damage to the semiconductor layer sequence due to strains that are caused thermally is reduced and, more widely, the electrical contact connection of the semiconductor layer sequence by means of the second main area of the carrier layer is made possible. Furthermore, the thermal conductivity with 195 W/mK, for example, may also advantageously be increased compared with carrier layers made of semiconductor materials.
  • In another embodiment of the conductor structure, an additional thermally conductive substance, for example in the form of diamond particles, is introduced into said conductor structure, said substance being arranged in the cutout and having a higher thermal conductivity than the electrically conductive material in the cutout. This thermally conductive substance advantageously increases the thermal conductivity of the conductor structure, in particular in the region of the cutout and consequently that of the carrier layer comprising the cutouts. Furthermore, the thermally conductive substance may improve the matching of the mechanical properties of the electrically conductive material in the cutout to that of the insulation layer since the proportion of electrically conductive material in the cutout is reduced at the expense of the thermally conductive substance, which advantageously has suitable mechanical and thermal properties, for this purpose.
  • Another aspect of invention is directed to a method for producing semiconductor chips with a semiconductor chip region that has a radiation-generating active zone and is arranged on a chip carrier containing AlN in a first variation or a ceramic in a second variation. Firstly, a semiconductor layer sequence is produced on a substrate, such as by epitaxial growth on a growth substrate. The semiconductor layer sequence is subsequently arranged on an AlN-containing or a ceramic containing carrier layer, respectively, whereupon the substrate is removed.
  • The carrier layer or the semiconductor layer sequence are preferably formed as in the corresponding embodiments above, so that the carrier layer comprises for example a conductor structure or the carrier layer and the semiconductor layer sequence may have other features from the features mentioned there. Further embodiments from the above embodiments may also be applied correspondingly to the method. Thus, by way of example, a metallic mirror layer may be applied, preferably by sputtering or vapour deposition, onto the semiconductor layer sequence, on the side remote from the substrate, prior to arrangement on the carrier layer.
  • From the side opposite to the carrier layer, the semiconductor layer sequence is thereupon patterned into semiconductor chip regions that are preferably spatially separate from one another, and the structure comprising semiconductor chip regions and carrier layer is singulated, for example by sawing or a laser separating method, into semiconductor chips in such a way that the semiconductor chips in each case comprise at least one semiconductor chip region. In this case, the singulation can be effected in the interspaces between the semiconductor chip regions. The semiconductor chip is arranged on a chip carrier containing a ceramic or AlN, respectively, after singulation, and which chip carrier emerges from the carrier layer during singulation. Semiconductor chips produced by removal of the growth substrate and arrangement of the semiconductor layer sequence on a carrier layer are referred to as thin-film chips.
  • The patterning of the semiconductor layer sequence may also be wholly or partly effected while the semiconductor layer sequence is still arranged on the substrate, that is to say prior to arrangement on the carrier, and is not restricted to the formation of the semiconductor chip regions. Rather, it is also possible to provide structures that improve the coupling-out of light from the semiconductor chip, protect the chip from damaging effects, or to carry out other processes during the patterning.
  • After singulation, essentially each semiconductor chip region can be electrically conductively connected to the conductor structure.
  • Such a production method for semiconductor chips has the advantage that, in a continuous process, it is possible to produce semiconductor chips which are arranged on an AlN-containing or respectively a ceramic containing chip carrier that is well matched to the semiconductor layer sequence with regard to the coefficient of expansion and has an advantageously high thermal conductivity. In particular, the chips do not have to be arranged individually on the chip carrier since the latter emerges from the carrier layer during singulation, as a result of which the production duration and production costs of semiconductor chips of this type are reduced.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Further features, advantages and expedients of the invention will become apparent from the descriptions of the following exemplary embodiments in conjunction with the figures.
  • FIG. 1A shows a diagrammatic sectional view of a part of an exemplary embodiment of a carrier layer according to the invention, and FIG. 1B shows a plan view of a part of an exemplary embodiment of a carrier layer according to the invention.
  • FIG. 2 shows a diagrammatic illustration of an exemplary embodiment of a method according to the invention for producing a semiconductor chip, on the basis of intermediate steps, in FIGS. 2A to 2F.
    • DETAILED DESCRIPTION OF THE DRAWINGS
  • Elements that are of the same type and act identically have identical reference symbols in the figures.
  • FIG. 1A shows a diagrammatic sectional view of a part of a first exemplary embodiment of a carrier layer according to the invention.
  • The carrier layer 1 comprises an insulation layer 2 containing AlN, in particular an AlN ceramic, having a thickness of 200 μm, for example. Cutouts 3 are provided in the insulation layer 2, an electrical conductor material 4, for example W, being arranged in said cutouts in such a way that a first main area 5 of the carrier layer 1 is electrically conductively connected to a second main area 6. Arranged over the carrier layer 1 is a semiconductor layer sequence 7, which is connected to the carrier layer 1 by means of a connecting layer 8 and a mirror layer 9. The connecting layer 8 is formed in electrically conductive fashion, for example as solder, so that the radiation-generating active zone 10 of the semiconductor layer sequence 7 is conductively connected to the conductor material 4 by means of the electrically conductive mirror layer 9.
  • The carrier layer 1 is formed in self-supporting fashion, mechanically stabilizes the semiconductor layer sequence 7 and ensures that the semiconductor layer sequence 7 can be electrically contact-connected by means of the cutouts 4 from the second main area 6. Furthermore, the carrier layer 1, with W in the cutouts, has a high thermal conductivity, for example of 195 W/mK, which is additionally increased by introducing a thermally conductive substance 11, for example diamond particles, into the electrical conductor material in the cutout 3. Moreover, in particular by means of the process implementation during the production of the insulation layer 2, the carrier layer 1 may be matched to the coefficients of thermal expansion of the semiconductor layer sequence in such a way that the latter is improved compared with metallic carrier layers. Furthermore, a carrier layer of this type has an increased electrical and thermal conductivity compared with most semiconductor materials at least in the region of the cutouts 4.
  • In this case, the semiconductor layer sequence 7 may be formed for LED chips, radiation-emitting semiconductor components with a resonator, such as edge-emitting lasers or vertically emitting components such as VCSEL, VECSEL or RCLEDs, and the mirror layer 9 may comprise for example a metal layer or a distributed Bragg mirror that may be formed in the semiconductor layer sequence 7.
  • FIG. 1B illustrates a plan view of a part of an exemplary embodiment of a carrier layer according to the invention.
  • The illustration shows a part of a plan view of the second main area 6 of a carrier layer 1, such as, for instance, that from FIG. 1A. In this exemplary embodiment, the cutouts 3 in the insulation layer 2 with the conductor material 4 and the thermally conductive substance 11 are arranged in a regular grid, which proves to be advantageous for the further processing, in particular during the production of semiconductor chips using a carrier layer 1 of this type (cf. FIG. 2 and the associated description), and have a circular cross section, for example, in plan view. FIG. 1B illustrates as an example of a regular grid a square lattice, at the lattice points of which a cutout 3 is respectively arranged.
  • The cutouts 3 are stamped into the still soft AlN material (“green sheet”; a green sheet is a ceramic compound which is still soft, but may nevertheless be formed or patterned, such that the patterned structure, e.g., vias, keeps its shape; afterward the green sheet is sintered to stabilize the patterned structure resulting in a mechanically stable and solid ceramic carrier layer), for example, in order to produce a carrier layer of this type. In this case, the tools used determine the form of the cross section of the cutouts.
  • Afterward, in a first embodiment, a W paste as conductor material 4 and the thermally conductive substance 11 may be introduced into the cutout 3. The carrier layer 1 is then completed by sintering and the semiconductor layer sequence 7 may be arranged on the carrier layer 1 in the manner illustrated in FIG. 1A.
  • In a second embodiment, the AlN material is sintered after the production of the cutouts 3 and the semiconductor layer sequence 7 is then arranged on the AlN material. The conductor material 4 may thereupon be introduced into the cutouts 3 by means of a galvanic procedure. This process may advantageously be carried out at temperatures that are not harmful to the semiconductor layer sequence 7. A conductor material 4 containing Ag or Cu is preferably used for this purpose.
  • FIG. 2 shows a diagrammatic illustration of an exemplary embodiment of a method according to the invention for producing a semiconductor chip, on the basis of intermediate steps illustrated in FIGS. 2A to 2F.
  • The production of an LED thin-film chip with a mirror layer is described in this exemplary embodiment. However, the method illustrated may be correspondingly applied to chips that are formed for LEDs, RCLEDs and also for lasers such as VCSEL, VECSEL or edge-emitting lasers or for other types of semiconductor chips.
  • A semiconductor layer sequence 7, for example containing InxGayAl1-x-yP or InxGayAl1-x-yN, grown epitaxially on a growth substrate 16, with a radiation-generating active zone 10, is provided with a mirror layer 9 in a first intermediate step in FIG. 2A. For InxGayAl1-x-yP, the growth substrate 16 is preferably of GaAs and the mirror layer is made of Au; for InxGayAl1-x-yN, for example sapphire or SiC are suitable as growth substrates and Ag or Al are suitable as material for the mirror layer. The, particularly metal-containing, mirror layer 9 is preferably applied by sputtering or vapor deposition onto that side of the semiconductor layer sequence 7 which is remote from the growth substrate 16.
  • Afterward, the mirror layer 9 is fixed on a first main area 5 of the carrier layer 1 by means of an electrically conductive connecting layer 8, for example a solder. The carrier layer 1 has an electrical insulation layer 2 made of AlN, in particular an AlN ceramic, in which cutouts 3 are provided, a conductor material 4, for example W, being arranged in said cutouts, and a thermally conductive substance 11, for example in the form of diamond particles, in turn being arranged in said conductor material. The conductor structure comprising the cutouts 3 with the conductor material 4 permits the semiconductor layer sequence 7 to be electrically contact-connected from a second main area 6 of the carrier layer 1 opposite to the first main area 5. The electrical contact is effected by means of the conductor material 4, which is electrically conductively connected to the semiconductor layer sequence 7 by means of the conductive connecting layer 8 and the mirror layer 9.
  • The growth substrate 16 is thereupon removed preferably by etching, mechanical loading or a laser ablation method, which results in the structure shown in FIG. 2B with the carrier layer 1 and the semiconductor layer sequence 7 arranged thereon.
  • A carrier layer of this type is particularly suitable for use in the case of semiconductor layer sequences containing InxGayAl1-x-yP or InxGayAl1-x-yN, since AlN with approximately 4.4 ppm/° C. has a coefficient of thermal expansion that is well matched to those of the growth substrates GaAs and sapphire, having values of approximately 6 and 4.5 ppm/° C., respectively. Furthermore, the thermal conductivity of a carrier layer according to the invention with approximately 195 W/mK is also advantageously increased compared with carrier layers made of semiconductor materials such as GaAs, for example, which has a thermal conductivity of approximately 55 W/mK.
  • In a further-reaching method step, the semiconductor layer sequence 7 is patterned, for example by masking and etching techniques, into semiconductor chip regions 12 in such a way that the latter are spatially separated from one another by interspaces 13. Furthermore, the semiconductor chip regions 12 may be provided with radiation-coupling out, passivation or protection structures that advantageously increase the coupling-out of radiation from the later semiconductor chip or protect the chip from damaging effects. The patterning may also be wholly or partly effected while the semiconductor layer sequence 7 is still arranged on the growth substrate 16.
  • FIGS. 2C and 2D show the semiconductor chip regions 12 arranged on the carrier layer 1 after the above patterning process.
  • In FIG. 2C, no conductor material 4 is arranged in the region of the interspaces 13, in contrast to FIG. 2D.
  • The arrangement illustrated in FIG. 2C therefore requires a high alignment outlay, either during the patterning of the semiconductor layer sequence 7 on the carrier layer 1 or during the arrangement of the already partly or completely patterned semiconductor layer sequence 7 on the carrier layer 1. In particular, the cutouts 3 in the carrier layer 1, during the production thereof, must also be arranged in accordance with the size of a later semiconductor chip. The advantage of such an arrangement of the conductor material 4 is that the singulation of the structure illustrated, for example by sawing, along the separating lines 14 into semiconductor chips 15, as illustrated in FIG. 2E, is effected only in the electrically insulating AlN. This at least greatly reduces the risk of a damaging short circuit of the active zone 10 of the semiconductor chip due to slivers of the semiconductor material 4 arising during singulation. Preferably, each semiconductor chip region 12 is thus assigned at least one cutout 3 with the conductor material 4, which is completely covered by the semiconductor chip region 12.
  • In the arrangement shown in FIG. 2D, conductor material 4 is arranged in the region of some interspaces 13. This has the advantage of a lower necessary alignment outlay compared with the arrangement in FIG. 2C. During the patterning of the semiconductor layer sequence 7 or the arrangement on the carrier layer 1, it is merely necessary to ensure that essentially each semiconductor chip region 2 is connected to the conductor material. This may be achieved for example by means of a correspondingly high density of cutouts 3 with conductor material 4 in the insulation layer 2.
  • If singulation into semiconductor chips 15 is subsequently effected along the separating lines 14, as illustrated in FIG. 2F, then this is done at least partly in the conductor material 4, whereby the risk of a short circuit of the active zone 10 may be increased. However, if the conductor material 4 is W, for example, which has a high hardness, it is possible to reduce the formation of W slivers during singulation, for example by sawing, which in turns reduces the risk of a short circuit. When sawing in tungsten, however, the “saw blade” may become blunt, which can be compensated for by sawing in the AlN ceramic again since ceramics are often used to sharpen the “saw blades”.
  • The semiconductor chips 15 illustrated in FIGS. 2E and 2F in each case comprise one semiconductor chip region 12 arranged on a chip carrier 101 that emerges from the carrier layer 1 during singulation. The semiconductor chip regions 12 can be electrically contact-connected by means of the conductor material from the second main area 6 and the chip carrier 101 ensures a good dissipation of heat from the semiconductor chip region 12. The mirror layer 9 reflects the radiation generated in the active zone 10 and thus increases the efficiency of the semiconductor chip 15.
  • Such a production method for semiconductor chips has the advantage that the AlN-containing carrier layer can be processed conjointly with the semiconductor layer sequence. Consequently, it is not necessary for each individual semiconductor chip 15 to be equipped with a chip carrier 101 of this type, thereby reducing the production costs and the required production time for semiconductor chips on a chip carrier of this type.
  • Furthermore, an additional heat sink can advantageously be dispensed with owing to the high thermal conductivity of the carrier layer. In order to increase the thermal capacity of the chip carrier 101, the volume thereof may be increased for example by larger interspaces 13 or a thicker carrier layer 1.
  • The scope of protection of the invention is not limited to the examples given herein above. The invention is embodied in each novel characteristic and each combination of characteristics, which particularly includes every combination of any features which are stated in the claims, even if this feature or this combination of features is not explicitly stated in the claims or in the examples.

Claims (24)

1. A carrier layer (1) for a semiconductor layer sequence (7), the carrier layer (1) comprising an electrical insulation layer (2),
wherein
the insulation layer (2) contains AlN.
2. The carrier layer (1) as claimed in claim 1,
wherein
the insulation layer contains an AlN ceramic.
3. A carrier layer (1) for a semiconductor layer sequence (7), the carrier layer (1) comprising an electrical insulation layer (2),
wherein
the insulation layer (2) contains a ceramic.
4. The carrier layer (1) as claimed in claim 1 or 3,
wherein
the insulation layer (2) is formed in self-supporting fashion.
5. The carrier layer (1) as claimed in claim 1 or 3,
wherein
the carrier layer (1) has a conductor structure.
6. The carrier layer (1) as claimed in claim 5,
wherein
the carrier layer (1) has a first and a second main area and the conductor structure extends from the first (5) to the second main area (6).
7. The carrier layer (1) as claimed in claim 5,
wherein
the conductor structure is at least partly formed in cutouts (3) of the insulation layer (2) that reach from the first to the second main area of the carrier layer (1).
8. The carrier layer (1) as claimed in claim 5,
wherein
the semiconductor layer sequence (7) is electrically conductively connected to the conductor structure.
9. The carrier layer (1) as claimed in claim 5,
wherein
the conductor structure contains a metal.
10. The carrier layer (1) as claimed in claim 9,
wherein
the conductor structure contains W, Ag, Au, Cu or an alloy having at least one of said materials.
11. The carrier layer (1) as claimed in claim 5,
wherein
a thermally conductive substance (11) for increasing the thermal conductivity is at least partly introduced into the conductor structure.
12. The carrier layer (1) as claimed in claim 5,
wherein
the semiconductor layer sequence (7) has a radiation-generating active zone (10).
13. The carrier layer (1) as claimed in claim 12,
wherein
a mirror layer (9) is arranged downstream of the active zone (10).
14. The carrier layer (1) as claimed in claim 13,
wherein
the mirror layer (9) is electrically conductively connected to the semiconductor layer sequence (7).
15. The carrier layer (1) as claimed in claim 13,
wherein
the mirror layer (9) is arranged between the first main area of the carrier layer (1) and the active zone (10).
16. The carrier layer (1) as claimed in claim 1 or 3,
wherein
the semiconductor layer sequence is formed for LED chips or radiation-emitting components with a resonator, in particular edge-emitting lasers or vertically emitting components, including VCSEL, VECSEL and RCLEDs.
17. The carrier layer (1) as claimed in claim 1 or 3,
wherein
the semiconductor layer sequence (7) contains at least one III-V semiconductor material, comprising InxGayAl1-x-yP, InxGayAl1-x-yN or InxGayAl1-x-yAs, in each case where O≦x≦1, 0≦y≦1 and x+y≦1.
18. A method for producing semiconductor chips (15) with a semiconductor chip region (12) that has a radiation-generating active zone (10) and is arranged on a chip carrier (101) containing AlN, featuring the following steps:
provision of a semiconductor layer sequence (7) with the radiation-emitting active zone on a substrate (16),
connection of the semiconductor layer sequence (7) to a carrier layer (1) containing AlN,
removal of the substrate (16),
patterning of the semiconductor layer sequence (7) into semiconductor chip regions (12),
singulation of the structure with semiconductor chip regions (12) and carrier layer (1) into semiconductor chips (15) that each comprise at least one semiconductor chip region (12) and are arranged on a chip carrier (101) that emerges from the carrier layer (1) as a result of the singulation.
19. A method for producing semiconductor chips (15) with a semiconductor chip region (12) that has a radiation-generating active zone (10) and is arranged on a chip carrier (101) containing a ceramic, featuring the following steps:
provision of a semiconductor layer sequence (7) with the radiation-emitting active zone on a substrate (16),
connection of the semiconductor layer sequence (7) to a carrier layer (1) containing a ceramic,
removal of the substrate (16),
patterning of the semiconductor layer sequence (7) into semiconductor chip regions (12),
singulation of the structure with semiconductor chip regions (12) and carrier layer (1) into semiconductor chips (15) that each comprise at least one semiconductor chip region (12) and are arranged on a chip carrier (101) that emerges from the carrier layer (1) as a result of the singulation.
20. The method as claimed in claim 18 or 19,
wherein
the carrier layer (1) has a conductor structure.
21. The method as claimed in claim 18 or 19,
wherein
the carrier layer (1) has a first (5) and a second main area (7) and the conductor structure extends from the first to the second main area.
22. The method as claimed in claim 18 or 19,
wherein
the conductor structure is electrically conductively connected to the semiconductor sequence (7).
23. The method as claimed in claim 18 or 19,
wherein
a mirror layer (9) is arranged between the carrier layer (1) and the semiconductor layer sequence (7).
24. The method as claimed in claim 18 or 19,
wherein
the conductor structure is configured such that essentially each semiconductor chip (15) is electrically conductively connected to the conductor structure after singulation.
US10/999,854 2003-11-28 2004-11-29 Carrier layer for a semiconductor layer sequence and method for producing semiconductor chips Active US7723730B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10355600 2003-11-28
DE10355600.1A DE10355600B4 (en) 2003-11-28 2003-11-28 Semiconductor chip and method for manufacturing semiconductor chips
DE10355600.1 2003-11-28

Publications (2)

Publication Number Publication Date
US20050127382A1 true US20050127382A1 (en) 2005-06-16
US7723730B2 US7723730B2 (en) 2010-05-25

Family

ID=34442323

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/999,854 Active US7723730B2 (en) 2003-11-28 2004-11-29 Carrier layer for a semiconductor layer sequence and method for producing semiconductor chips

Country Status (5)

Country Link
US (1) US7723730B2 (en)
EP (1) EP1536466A3 (en)
JP (1) JP2005167239A (en)
DE (1) DE10355600B4 (en)
TW (1) TWI297200B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090283783A1 (en) * 2005-09-30 2009-11-19 Osram Opto Semiconductors Gmbh Optoelectronic Semiconductor Chip and Method for Producing It
WO2012009424A3 (en) * 2010-07-13 2012-05-18 Nexxus Lighting, Inc Improved heat sinking methods for performance and scalability
US20140363928A1 (en) * 2012-09-24 2014-12-11 LuxVue Technology Corporation Micro device stabilization post
WO2019079239A1 (en) * 2017-10-16 2019-04-25 Crystal Is, Inc. Electrochemical removal of aluminum nitride substrates for electronic and optoelectronic devices
US10985306B2 (en) * 2015-08-12 2021-04-20 Osram Oled Gmbh Optoelectronic semiconductor chip

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7547925B2 (en) 2005-11-14 2009-06-16 Palo Alto Research Center Incorporated Superlattice strain relief layer for semiconductor devices
EP2094460B1 (en) * 2006-12-19 2011-07-13 Philips Intellectual Property & Standards GmbH System for and method of heating objects in a production line
JP5167831B2 (en) * 2008-01-24 2013-03-21 豊田合成株式会社 Group III nitride semiconductor device and manufacturing method thereof
KR100982986B1 (en) * 2008-04-17 2010-09-17 삼성엘이디 주식회사 Submount, LED Package and Manufacturing Method Thereof
DE102010045390A1 (en) 2010-09-15 2012-03-15 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor component and method for producing an optoelectronic semiconductor component
US8726505B2 (en) 2011-07-13 2014-05-20 Revolution Lighting Technologies, Inc. Heat sinking methods for performance and scalability
US10269592B1 (en) 2017-11-30 2019-04-23 International Business Machines Corporation Conductive heat spreader and heat sink assembly for optical devices
KR20230017249A (en) * 2020-05-29 2023-02-03 더 거번먼트 오브 더 유나이티드 스테이츠 오브 아메리카, 에즈 레프리젠티드 바이 더 세크러테리 오브 더 네이비 Transfer of large area III-nitride semiconductor materials and devices to arbitrary substrates

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5770821A (en) * 1995-07-18 1998-06-23 Tokuyama Corporation Submount
US6106891A (en) * 1993-11-17 2000-08-22 International Business Machines Corporation Via fill compositions for direct attach of devices and method for applying same
US6352014B1 (en) * 1999-12-15 2002-03-05 International Business Machines Corporation Method for making punches using multi-layer ceramic technology
US6395572B1 (en) * 1999-04-15 2002-05-28 Rohm Co, Ltd. Method of producing semiconductor light-emitting element
US20020175621A1 (en) * 2001-05-24 2002-11-28 Samsung Electro-Mechanics Co., Ltd. Light emitting diode, light emitting device using the same, and fabrication processes therefor
US20030209714A1 (en) * 2000-10-12 2003-11-13 General Electric Company Solid state lighting device with reduced form factor including led with directional emission and package with microoptics
US20030213964A1 (en) * 2000-03-13 2003-11-20 Flynn Jeffrey S. III-V Nitride homoepitaxial material of improved MOVPE epitaxial quality (surface texture and defect density) formed on free-standing (Al,In,Ga)N substrates, and opto-electronic and electronic devices comprising same
US20040033638A1 (en) * 2000-10-17 2004-02-19 Stefan Bader Method for fabricating a semiconductor component based on GaN
US6996281B2 (en) * 1994-09-21 2006-02-07 Ricoh Co., Ltd. Compression and decompression system with reversible wavelets and lossy reconstruction
US7345350B2 (en) * 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2961964B2 (en) * 1991-07-10 1999-10-12 日本電気株式会社 Semiconductor laser device
US5455738A (en) * 1993-07-28 1995-10-03 E-Systems, Inc. High thermal conductivity, matched CTE. low density mounting plate for a semiconductor circuit
JPH07231049A (en) * 1994-02-17 1995-08-29 Fujitsu Ltd Ceramic multilayer substrate and manufacture thereof
JPH08222786A (en) * 1995-02-15 1996-08-30 Matsushita Electric Ind Co Ltd Electron beam pumping laser, manufacture of electron beam pumping laser, and drive method of electron beam pumping laser
US5867516A (en) * 1996-03-12 1999-02-02 Hewlett-Packard Company Vertical cavity surface emitting laser with reduced turn-on jitter and increased single-mode output
JPH10208270A (en) * 1997-01-29 1998-08-07 Sharp Corp Semiconductor laser device for optical pickup and its manufacture
JP4126749B2 (en) * 1998-04-22 2008-07-30 ソニー株式会社 Manufacturing method of semiconductor device
DE10017336C2 (en) * 2000-04-07 2002-05-16 Vishay Semiconductor Gmbh Process for the production of radiation-emitting semiconductor wafers
JP4908669B2 (en) * 2000-04-27 2012-04-04 ローム株式会社 Chip light emitting device
FR2835096B1 (en) * 2002-01-22 2005-02-18 PROCESS FOR MANUFACTURING SELF-CARRIER SUBSTRATE OF SINGLE-CRYSTALLINE SEMICONDUCTOR MATERIAL
JP4100013B2 (en) * 2002-03-14 2008-06-11 日亜化学工業株式会社 Nitride semiconductor laser device and manufacturing method thereof
JP3509809B2 (en) * 2002-04-30 2004-03-22 住友電気工業株式会社 Submount and semiconductor device
US20060183625A1 (en) * 2002-07-09 2006-08-17 Kenichiro Miyahara Substrate for forming thin film, thin film substrate, optical wave guide, luminescent element and substrate for carrying luminescent element

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6106891A (en) * 1993-11-17 2000-08-22 International Business Machines Corporation Via fill compositions for direct attach of devices and method for applying same
US6996281B2 (en) * 1994-09-21 2006-02-07 Ricoh Co., Ltd. Compression and decompression system with reversible wavelets and lossy reconstruction
US5770821A (en) * 1995-07-18 1998-06-23 Tokuyama Corporation Submount
US6395572B1 (en) * 1999-04-15 2002-05-28 Rohm Co, Ltd. Method of producing semiconductor light-emitting element
US6352014B1 (en) * 1999-12-15 2002-03-05 International Business Machines Corporation Method for making punches using multi-layer ceramic technology
US20030213964A1 (en) * 2000-03-13 2003-11-20 Flynn Jeffrey S. III-V Nitride homoepitaxial material of improved MOVPE epitaxial quality (surface texture and defect density) formed on free-standing (Al,In,Ga)N substrates, and opto-electronic and electronic devices comprising same
US20030209714A1 (en) * 2000-10-12 2003-11-13 General Electric Company Solid state lighting device with reduced form factor including led with directional emission and package with microoptics
US6998281B2 (en) * 2000-10-12 2006-02-14 General Electric Company Solid state lighting device with reduced form factor including LED with directional emission and package with microoptics
US20040033638A1 (en) * 2000-10-17 2004-02-19 Stefan Bader Method for fabricating a semiconductor component based on GaN
US20020175621A1 (en) * 2001-05-24 2002-11-28 Samsung Electro-Mechanics Co., Ltd. Light emitting diode, light emitting device using the same, and fabrication processes therefor
US7345350B2 (en) * 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090283783A1 (en) * 2005-09-30 2009-11-19 Osram Opto Semiconductors Gmbh Optoelectronic Semiconductor Chip and Method for Producing It
US9099574B2 (en) 2005-09-30 2015-08-04 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor chip and method for producing it
WO2012009424A3 (en) * 2010-07-13 2012-05-18 Nexxus Lighting, Inc Improved heat sinking methods for performance and scalability
US20140363928A1 (en) * 2012-09-24 2014-12-11 LuxVue Technology Corporation Micro device stabilization post
US9741592B2 (en) * 2012-09-24 2017-08-22 Apple Inc. Micro device stabilization post
US10424493B2 (en) 2012-09-24 2019-09-24 Apple Inc. Micro device stabilization post
US11011390B2 (en) 2012-09-24 2021-05-18 Apple Inc. Micro device stabilization post
US10985306B2 (en) * 2015-08-12 2021-04-20 Osram Oled Gmbh Optoelectronic semiconductor chip
WO2019079239A1 (en) * 2017-10-16 2019-04-25 Crystal Is, Inc. Electrochemical removal of aluminum nitride substrates for electronic and optoelectronic devices
US10777706B2 (en) 2017-10-16 2020-09-15 Crystal Is, Inc. Electrochemical removal of aluminum nitride substrates for electronic and optoelectronic devices

Also Published As

Publication number Publication date
DE10355600A1 (en) 2005-06-30
JP2005167239A (en) 2005-06-23
US7723730B2 (en) 2010-05-25
TWI297200B (en) 2008-05-21
DE10355600B4 (en) 2021-06-24
EP1536466A2 (en) 2005-06-01
EP1536466A3 (en) 2009-12-30
TW200525709A (en) 2005-08-01

Similar Documents

Publication Publication Date Title
JP6712579B2 (en) Method of mounting light emitting device on supporting substrate
US8524573B2 (en) Method for separating a semiconductor layer from a substrate by irradiating with laser pulses
JP5676396B2 (en) Substrate removal method for high light extraction LED
JP5007027B2 (en) Resonant cavity group III-nitride light emitting device manufactured by removal of growth substrate
US7592630B2 (en) Nitride-based light-emitting device and method of manufacturing the same
US20050214965A1 (en) Vertical GaN light emitting diode and method for manufacturing the same
US20040248377A1 (en) Method for manufacturing vertical gan light emitting diodes
US7723730B2 (en) Carrier layer for a semiconductor layer sequence and method for producing semiconductor chips
JP6148756B2 (en) Optoelectronic semiconductor chip
US20060102933A1 (en) III-V Group compound semiconductor light emitting device and manufacturing method thereof
JP2013102240A (en) Group iii nitride light emitting device having light emitting region with double hetero-structure
US20140080287A1 (en) Method for singulating a component composite assembly
KR101256755B1 (en) Vertical Light Emitting Diode (VLED) Die Having N-Type Confinement Structure With Etch Stop Layer And Method Of Fabrication
US9099574B2 (en) Optoelectronic semiconductor chip and method for producing it
EP2492975B1 (en) Manufacturing method of nitride semiconductor light emitting elements
KR100916366B1 (en) Supporting substrates for semiconductor light emitting device and method of manufacturing vertical structured semiconductor light emitting device using the supporting substrates
JP4817673B2 (en) Nitride semiconductor device fabrication method
US9397280B2 (en) Method of producing an optoelectronic semiconductor chip
JP6100794B2 (en) Semiconductor light emitting device having a thick metal layer
US7592194B2 (en) Radiation-emitting and/or -receiving semiconductor component and method for the patterned application of a contact to a semiconductor body
US20060172506A1 (en) Process for producing a semiconductor chip
US20110175238A1 (en) Method for Producing Semiconductor Chips and Corresponding Semiconductor Chip
JP2006518102A (en) Thin film semiconductor device and manufacturing method thereof
KR100585914B1 (en) Fabrication of GaN-base LED
US20240258764A1 (en) Method for manufacturing optoelectronic components, and optoelectronic components

Legal Events

Date Code Title Description
AS Assignment

Owner name: OSRAM OPTO SEMICONDUCTORS GMBH, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GROETSCH, STEFAN;ILLEK, STEFAN;PLOESSL, ANDREAS;AND OTHERS;REEL/FRAME:016276/0890;SIGNING DATES FROM 20050111 TO 20050120

Owner name: OSRAM OPTO SEMICONDUCTORS GMBH,GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GROETSCH, STEFAN;ILLEK, STEFAN;PLOESSL, ANDREAS;AND OTHERS;SIGNING DATES FROM 20050111 TO 20050120;REEL/FRAME:016276/0890

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552)

Year of fee payment: 8

AS Assignment

Owner name: OSRAM OLED GMBH, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:OSRAM OPTO SEMICONDUCTORS GMBH;REEL/FRAME:051467/0906

Effective date: 20191218

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12