TWI832251B - Power supply device with high conversion efficiency - Google Patents

Abstract

A power supply device with high conversion efficiency includes an input rectifying circuit, a first transformer, a second transformer, a first capacitor, a second capacitor, an output rectifying circuit, an input control circuit, and a microcontroller. The input rectifying circuit generates a first rectifying current and a second rectifying current. The first transformer includes a first main coil and a first secondary coil. A first leakage inductor and a first magnetizing inductor are built in the first transformer. The first main coil receives the first rectifying current through the first leakage inductor. The first capacitor is coupled to the first magnetizing inductor. The second transformer includes a second main coil and a second secondary coil. A second leakage inductor and a second magnetizing inductor are built in the second transformer. The second main coil receives the second rectifying current through the second leakage inductor. The second capacitor is coupled to the second magnetizing inductor.

Description

High conversion efficiency power supply

The present invention relates to a power supply, and in particular to a power supply with high conversion efficiency.

In traditional power supplies, due to limitations in voltage gain and operating bandwidth, they are usually unable to provide high-voltage output specifications. On the other hand, the aforementioned limitations often result in excessive losses and low conversion efficiency of traditional power supplies, which reduce the overall performance of traditional power supplies. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by previous technologies.

In a preferred embodiment, the present invention proposes a power supply with high conversion efficiency, including: an input rectifier circuit that generates a first rectified current and a second clock potential according to a first clock potential and a second clock potential. two rectified currents; an input control circuit coupled to the input rectifying circuit and generating a first control potential and a second control potential according to an input potential; a first transformer including a first main coil and a first A secondary coil, wherein the first transformer has a built-in first leakage inductor and a first exciting inductor, and the first main coil receives the first rectified current through the first leakage inductor; a first capacitor , coupled to the first exciting inductor; a second transformer including a second main coil and a second secondary coil, wherein the second transformer has a built-in second leakage inductor and a second exciting inductor, The second main coil receives the second rectified current through the second leakage inductor; a second capacitor is coupled to the second exciting inductor; an output rectifier circuit is coupled to the first secondary coil and The second secondary coil generates an output potential according to the first control potential and the second control potential; and a microcontroller monitors the input control circuit and generates the first clock potential and the third clock potential accordingly. Second clock potential.

In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are listed below and described in detail with reference to the accompanying drawings.

Certain words are used in the specification and patent claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and the patent application do not use differences in names as a way to distinguish components, but differences in functions of components as a criterion for distinction. The words "include" and "include" mentioned throughout the specification and the scope of the patent application are open-ended terms, and therefore should be interpreted as "include but not limited to." The term "approximately" means that within an acceptable error range, those skilled in the art can solve the technical problem and achieve the basic technical effect within a certain error range. In addition, the word "coupling" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device via other devices or connections. Two devices.

Figure 1 is a schematic diagram of a power supply 100 according to an embodiment of the present invention. For example, the power supply 100 can be applied to a desktop computer, a notebook computer, or an all-in-one computer. As shown in Figure 1, the power supply 100 includes: an input rectifier circuit 110, a first transformer 120, a second transformer 130, a first capacitor C1, a second capacitor C2, an output rectifier circuit 140, a Input control circuit 150, and a microcontroller 180. It should be noted that, although not shown in FIG. 1 , the power supply 100 may further include other components, such as a voltage regulator or/and a negative feedback circuit.

The input rectifier circuit 110 can generate a first rectified current IR1 and a second rectified current IR2 according to a first clock potential VA1 and a second clock potential VA2. The input control circuit 150 is coupled to the input rectifier circuit 110 and can generate a first control potential VC1 and a second control potential VC2 according to an input potential VIN. The input potential VIN can come from an external input power supply, where the input potential VIN can be a DC potential with any level. For example, the potential level of the DC potential can be between 300V and 500V, but is not limited thereto. The first transformer 120 includes a first main coil 121 and a first auxiliary coil 122. The first transformer 120 may further have a first leakage inductor LR1 and a first magnetizing inductor LM1 built-in. The first main coil 121 , the first leakage inductor LR1 , and the first exciting inductor LM1 may be located on the same side of the first transformer 120 , while the first secondary coil 122 may be located on the opposite side of the first transformer 120 . The first primary coil 121 may receive the first rectified current IR1 via the first leakage inductor LR1, and the first secondary coil 122 may operate in response to the first rectified current IR1. The first capacitor C1 is coupled to the first magnetizing inductor LM1, where the first leakage inductor LR1, the first magnetizing inductor LM1, and the first capacitor C1 can jointly form a first resonant tank (Resonant Tank). The second transformer 130 includes a second main winding 131 and a second secondary winding 132, wherein the second transformer 130 may further have a built-in second leakage inductor LR2 and a second magnetizing inductor LM2. The second main coil 131 , the second leakage inductor LR2 , and the second exciting inductor LM2 may be located on the same side of the second transformer 130 , while the second secondary coil 132 may be located on the opposite side of the second transformer 130 . The second primary coil 131 may receive the second rectified current IR2 via the second leakage inductor LR2, and the second secondary coil 132 may operate in response to the second rectified current IR2. The second capacitor C2 is coupled to the second exciting inductor LM2, where the second leakage inductor LR2, the second exciting inductor LM2, and the second capacitor C2 can jointly form a second resonant tank. The output rectifier circuit 140 is coupled to the first secondary coil 122 and the second secondary coil 132, and can generate an output potential VOUT according to the first control potential VC1 and the second control potential VC2. For example, the output potential VOUT can be another DC potential, and its potential level can be between 40V and 60V, but it is not limited thereto. The microcontroller 180 can monitor the operating status of the input control circuit 150 and generate the first clock potential VA1 and the second clock potential VA2 accordingly. Under this design, since the power supply 100 uses both the input rectifier circuit 110 and the output rectifier circuit 140 and is equipped with a plurality of sets of resonant tanks, it can withstand a larger operating voltage. According to actual measurement results, the power supply 100 proposed by the present invention can effectively reduce the total loss and improve the overall conversion efficiency. In other embodiments, the power supply 100 may further include more sets of resonant slots according to different requirements.

The following embodiments will introduce the detailed structure and operation of the power supply 100 . It must be understood that these drawings and descriptions are only examples and are not intended to limit the scope of the invention.

Figure 2 is a circuit diagram of a power supply 200 according to an embodiment of the present invention. In the embodiment of FIG. 2, the power supply 200 has an input node NIN and an output node NOUT, and includes: an input rectifier circuit 210, a first transformer 220, a second transformer 230, and a first capacitor C1 , a second capacitor C2, an output rectifier circuit 240, an input control circuit 250, and a microcontroller 280. The input node NIN of the power supply 200 can receive an input potential VIN from an external input power source, and the output node NOUT of the power supply 200 can be used to output an output potential VOUT to an electronic device (not shown).

The input rectifier circuit 210 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. For example, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can each be an N-type Metal-Oxide-Semiconductor Field-Effect transistor. Transistor, NMOSFET). The first transistor M1 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the control terminal of the first transistor M1 The terminal is used to receive a first clock potential VA1. The first terminal of the first transistor M1 is coupled to a first node N1, and the second terminal of the first transistor M1 is coupled to a second node. N2. The second transistor M2 has a control terminal (for example, a gate), a first terminal (for example, a source), and a second terminal (for example, a drain), wherein the control terminal of the second transistor M2 The terminal is used to receive a second clock potential VA2, the first terminal of the second transistor M2 is coupled to a ground potential VSS (for example: 0V), and the second terminal of the second transistor M2 is coupled to The first node N1. For example, the first clock potential VA1 and the second clock potential VA2 may have substantially complementary logic levels. The third transistor M3 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the control terminal of the third transistor M3 The terminal is used to receive the second clock potential VA2, the first terminal of the third transistor M3 is coupled to a third node N3, and the second terminal of the third transistor M3 is coupled to a fourth node N4. . The fourth transistor M4 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the control terminal of the fourth transistor M4 The terminal is used to receive the first clock potential VA1, the first terminal of the fourth transistor M4 is coupled to the ground potential VSS, and the second terminal of the fourth transistor M4 is coupled to the third node N3. It must be noted that the first node N1 can be used to output a total rectified current IRT, where the total rectified current IRT can be further divided into a first rectified current IR1 and a second rectified current IR2 (that is, ).

The first transformer 220 includes a first main coil 221 and a first auxiliary coil 222, wherein the first transformer 220 further builds a first leakage inductor LR1 and a first magnetizing inductor LM1. Both the first leakage inductor LR1 and the first magnetizing inductor LM1 may be inherent components produced when the first transformer 220 is manufactured, and are not external independent components. The first leakage inductor LR1, the first main coil 221, and the first exciting inductor LM1 can all be located on the same side of the first transformer 220 (for example, the primary side), and the first secondary coil 222 can be located on the first transformer 220 opposite the other side (for example: the secondary side, which can be isolated from the primary side). The first leakage inductor LR1 has a first terminal and a second terminal, wherein the first terminal of the first leakage inductor LR1 is coupled to the first node N1 to receive the first rectified current IR1, and the first leakage inductor LR1 The second terminal of LR1 is coupled to a fifth node N5. The first main coil 221 has a first end and a second end, wherein the first end of the first main coil 221 is coupled to the fifth node N5, and the second end of the first main coil 221 is coupled to a The sixth node N6. The first exciting inductor LM1 has a first terminal and a second terminal, wherein the first terminal of the first exciting inductor LM1 is coupled to the fifth node N5, and the second terminal of the first exciting inductor LM1 is coupled to Connected to the sixth node N6. The first capacitor C1 has a first terminal and a second terminal, wherein the first terminal of the first capacitor C1 is coupled to the third node N3, and the second terminal of the first capacitor C1 is coupled to the sixth node N6. . In some embodiments, the first leakage inductor LR1 , the first magnetizing inductor LM1 , and the first capacitor C1 may together form a first resonant tank of the power supply 200 . The first secondary coil 222 has a first end and a second end, wherein the first end of the first secondary coil 222 is coupled to a seventh node N7, and the second end of the first secondary coil 222 is coupled to An eighth node N8.

The second transformer 230 includes a second main winding 231 and a second secondary winding 232, wherein the second transformer 230 further builds a second leakage inductor LR2 and a second magnetizing inductor LM2. Both the second leakage inductor LR2 and the second magnetizing inductor LM2 may be inherent components produced when the second transformer 230 is manufactured, and are not external independent components. The second leakage inductor LR2, the second main coil 231, and the second exciting inductor LM2 can all be located on the same side of the second transformer 230 (for example, the primary side), and the second secondary coil 232 can be located on the second transformer 230 opposite to the other side (for example: secondary side). The second leakage inductor LR2 has a first terminal and a second terminal, wherein the first terminal of the second leakage inductor LR2 is coupled to the first node N1 to receive the second rectified current IR2, and the second leakage inductor LR2 The second terminal of LR2 is coupled to a ninth node N9. The second main coil 231 has a first end and a second end, wherein the first end of the second main coil 231 is coupled to the ninth node N9, and the second end of the second main coil 231 is coupled to a The tenth node N10. The second exciting inductor LM2 has a first terminal and a second terminal, wherein the first terminal of the second exciting inductor LM2 is coupled to the ninth node N9, and the second terminal of the second exciting inductor LM2 is coupled to Connected to the tenth node N10. The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal of the second capacitor C2 is coupled to the third node N3, and the second terminal of the second capacitor C2 is coupled to the tenth node N10. . In some embodiments, the second leakage inductor LR2, the second magnetizing inductor LM2, and the second capacitor C2 may jointly form a second resonant tank of the power supply 200. The second secondary coil 232 has a first end and a second end, wherein the first end of the second secondary coil 232 is coupled to an eleventh node N11, and the second end of the second secondary coil 232 is coupled to to a twelfth node N12. In some embodiments, both the first transformer 220 and the second transformer 230 may be formed on the same iron core (not shown).

The output rectifier circuit 240 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, a tenth transistor A transistor M11, a twelfth transistor M12, a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5. For example, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor The crystals M12 can each be an N-type metal oxide semiconductor field effect transistor.

The fifth transistor M5 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the control terminal of the fifth transistor M5 The terminal is used to receive a first control potential VC1, the first terminal of the fifth transistor M5 is coupled to the seventh node N7, and the second terminal of the fifth transistor M5 is coupled to the output node NOUT. The sixth transistor M6 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the control terminal of the sixth transistor M6 The terminal is used to receive a second control potential VC2, the first terminal of the sixth transistor M6 is coupled to a thirteenth node N13, and the second terminal of the sixth transistor M6 is coupled to the seventh node N7 . For example, the first control potential VC1 and the second control potential VC2 may have substantially complementary logic levels. The seventh transistor M7 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the control terminal of the seventh transistor M7 The terminal is used to receive the second control potential VC2, the first terminal of the seventh transistor M7 is coupled to the eighth node N8, and the second terminal of the seventh transistor M7 is coupled to the output node NOUT. The eighth transistor M8 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the control terminal of the eighth transistor M8 The terminal is used to receive the first control potential VC1, the first terminal of the eighth transistor M8 is coupled to the thirteenth node N13, and the second terminal of the eighth transistor M8 is coupled to the eighth node N8.

The ninth transistor M9 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the control terminal of the ninth transistor M9 The terminal is used to receive the first control potential VC1, the first terminal of the ninth transistor M9 is coupled to the eleventh node N11, and the second terminal of the ninth transistor M9 is coupled to the thirteenth node N13. The tenth transistor M10 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the control terminal of the tenth transistor M10 The terminal is used to receive the second control potential VC2, the first terminal of the tenth transistor M10 is coupled to a common node NCM, and the second terminal of the tenth transistor M10 is coupled to the eleventh node N11. For example, the common node NCM can be regarded as another ground potential, which can be the same as or different from the aforementioned ground potential VSS. The eleventh transistor M11 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the eleventh transistor M11 The control terminal is used to receive the second control potential VC2, the first terminal of the eleventh transistor M11 is coupled to the twelfth node N12, and the second terminal of the eleventh transistor M11 is coupled to the tenth Three nodes N13. The twelfth transistor M12 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the twelfth transistor M12 The control terminal is used to receive the first control potential VC1, the first terminal of the twelfth transistor M12 is coupled to the common node NCM, and the second terminal of the twelfth transistor M12 is coupled to the twelfth node N12.

The third capacitor C3 has a first terminal and a second terminal, wherein the first terminal of the third capacitor C3 is coupled to the output node NOUT, and the second terminal of the third capacitor C3 is coupled to the thirteenth node N13 . The fourth capacitor C4 has a first terminal and a second terminal, wherein the first terminal of the fourth capacitor C4 is coupled to the thirteenth node N13, and the second terminal of the fourth capacitor C4 is coupled to the common node NCM. . The fifth capacitor C5 has a first terminal and a second terminal, wherein the first terminal of the fifth capacitor C5 is coupled to the output node NOUT, and the second terminal of the fifth capacitor C5 is coupled to the common node NCM.

The input rectifier circuit 250 includes a third transformer 260, a fourth transformer 270, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a A sixth capacitor C6, a seventh capacitor C7, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4.

The third transformer 260 includes a third main coil 261 and a third auxiliary coil 262. The third main coil 261 can be located on one side of the third transformer 260 (for example, the primary side), and the third auxiliary coil 262 can be located on one side of the third transformer 260. The opposite side of the third transformer 260 (for example, the secondary side). In detail, the third main coil 261 has a first end and a second end, wherein the first end of the third main coil 261 is coupled to the input node NIN, and the second end of the third main coil 261 is coupled to the input node NIN. Connected to the second node N2. The third secondary coil 262 has a first end and a second end, wherein the first end of the third secondary coil 262 is coupled to a fourteenth node N14, and the second end of the third secondary coil 262 is coupled to to ground potential VSS. The first diode D1 has an anode and a cathode, wherein the anode of the first diode D1 is coupled to the fourteenth node N14, and the cathode of the first diode D1 is coupled to a fifteenth node. N15. The first resistor R1 has a first terminal and a second terminal, wherein the first terminal of the first resistor R1 is coupled to the ground potential VSS, and the second terminal of the first resistor R1 is coupled to the tenth Five nodes N15. The sixth capacitor C6 has a first terminal and a second terminal, wherein the first terminal of the sixth capacitor C6 is coupled to the ground potential VSS, and the second terminal of the sixth capacitor C6 is coupled to the fifteenth node N15 To provide a first capacitor potential VP1. The second diode D2 has an anode and a cathode, wherein the anode of the second diode D2 is coupled to the fifteenth node N15, and the cathode of the second diode D2 is coupled to a sixteenth node. N16. The second resistor R2 has a first terminal and a second terminal, wherein the first terminal of the second resistor R2 is coupled to the sixteenth node N16 , and the second terminal of the second resistor R2 is coupled to A first control node NC1 is used to output a first control potential VC1.

The fourth transformer 270 includes a fourth main coil 271 and a fourth auxiliary coil 272. The fourth main coil 271 can be located on one side of the fourth transformer 270 (for example, the primary side), and the fourth auxiliary coil 272 can be located on one side of the fourth transformer 270. The opposite side of the fourth transformer 270 (eg, the secondary side). In detail, the fourth main coil 271 has a first end and a second end, wherein the first end of the fourth main coil 271 is coupled to the input node NIN, and the second end of the fourth main coil 271 is coupled to the input node NIN. Connected to the fourth node N4. The fourth secondary coil 272 has a first end and a second end, wherein the first end of the fourth secondary coil 272 is coupled to a seventeenth node N17, and the second end of the fourth secondary coil 272 is coupled to to ground potential VSS. The third diode D3 has an anode and a cathode, wherein the anode of the third diode D3 is coupled to the seventeenth node N17, and the cathode of the third diode D3 is coupled to an eighteenth node. N18. The third resistor R3 has a first terminal and a second terminal, wherein the first terminal of the third resistor R3 is coupled to the ground potential VSS, and the second terminal of the third resistor R3 is coupled to the tenth Eight-node N18. The seventh capacitor C7 has a first terminal and a second terminal, wherein the first terminal of the seventh capacitor C7 is coupled to the ground potential VSS, and the second terminal of the seventh capacitor C7 is coupled to the eighteenth node N18 To provide a second capacitor potential VP2. The fourth diode D4 has an anode and a cathode, wherein the anode of the fourth diode D4 is coupled to the eighteenth node N18, and the cathode of the fourth diode D4 is coupled to a nineteenth node. N19. The fourth resistor R4 has a first terminal and a second terminal, wherein the first terminal of the fourth resistor R4 is coupled to the nineteenth node N19, and the second terminal of the fourth resistor R4 is coupled to A second control node NC2 is used to output a second control potential VC2.

The microcontroller 280 continuously monitors the first capacitor potential VP1 and the second capacitor potential VP2 of the input rectifier circuit 250 . Then, the microcontroller 280 can further generate the aforementioned first clock potential VA1 and second clock potential VA2 according to the first capacitor potential VP1 and the second capacitor potential VP2.

Figure 3 shows a potential waveform diagram of the first clock potential VA1 and the second clock potential VA2 according to an embodiment of the present invention, in which the horizontal axis represents time and the vertical axis represents the potential level. As shown in FIG. 3 , the power supply 200 can alternately operate in a first phase T1 and a second phase T2, and the principle thereof can be described as follows.

During the first phase T1, the first clock potential VA1 is a high logic level to enable the first transistor M1 and the fourth transistor M4, and the second clock potential VA2 is a low logic level to disable the second transistor M1. Transistor M2 and third transistor M3. At this time, the energy of the input potential VIN can be transferred to the sixth capacitor C6 through the third transformer 260, thereby simultaneously raising the first capacitor potential VP1 and the first control potential VC1. Therefore, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9, and the twelfth transistor M12 are also in the enabled state during the first phase T1.

During the second phase T2, the first clock potential VA1 is at a low logic level to disable the first transistor M1 and the fourth transistor M4, and the second clock potential VA2 is at a high logic level to enable the second transistor M1 and the fourth transistor M4. Transistor M2 and third transistor M3. At this time, the energy of the input potential VIN can be transferred to the seventh capacitor C7 via the fourth transformer 270, thereby simultaneously raising the second capacitor potential VP2 and the second control potential VC2. Therefore, the sixth transistor M6, the seventh transistor M7, the tenth transistor M10, and the eleventh transistor M11 are also in the enabled state during the second phase T2.

It must be noted that there is an intermediate stage ΔT between the first stage T1 and the second stage T2. During this intermediate period ΔT, both the first clock potential VA1 and the second clock potential VA2 are maintained at a low logic level. According to the actual measurement results, this design can prevent the power supply 200 from malfunctioning and improve the overall reliability.

Figure 4 shows the potential waveform diagram of the first capacitor potential VP1 and the second capacitor potential VP2 according to an embodiment of the present invention, in which the horizontal axis represents time and the vertical axis represents the potential level. After the end of the first stage T1, the first capacitor potential VP1 will gradually discharge and decline. If it is detected that the drop of the first capacitor potential VP1 reaches a critical potential difference ΔVTH, the microcontroller 280 will raise the second clock potential VA2 to a high logic level. For example, the critical potential difference ΔVTH may be approximately 15V, but is not limited thereto. On the contrary, after the end of the second stage T2, the second capacitor potential VP2 will gradually discharge and decline. If it is detected that the drop in the second capacitor potential VP2 reaches the aforementioned critical potential difference ΔVTH, the microcontroller 280 can also raise the first clock potential VA1 to a high logic level. In other words, the time length of the aforementioned intermediate stage ΔT will be determined by the relevant time constant of the sixth capacitor C6 and the seventh capacitor C7. In some embodiments, the time length of the mediation phase ΔT can be set according to the following equation (1):

…………………………(1) Among them, “ΔT” represents the time length of the intermediate stage ΔT, “R1” represents the resistance value of the first resistor R1, and “R3” represents the resistance value of the third resistor R3. , "C6" represents the capacitance value of the sixth capacitor C6, and "C7" represents the capacitance value of the seventh capacitor C7.

Figure 5 shows a current waveform diagram of the first rectified current IR1, the second rectified current IR2, and the total rectified current IRT according to an embodiment of the present invention, in which the horizontal axis represents time and the vertical axis represents the current value. According to the measurement results in FIG. 5 , after the total rectified current IRT is divided, the energy of the first rectified current IR1 and the second rectified current IR2 can be transmitted to the output rectifier circuit 240 via the first transformer 220 and the second transformer 230 respectively. On the other hand, since the output rectifier circuit 240 also includes a parallel combination of the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5, it can withstand a higher output potential VOUT than the traditional design.

The present invention proposes a novel power supply. According to the actual measurement results, the conversion efficiency of the power supply using the above-mentioned design can be greatly improved, so it is very suitable for application in various types of devices.

It is worth noting that the above-mentioned potential, current, resistance value, inductance value, capacitance value, and other component parameters are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The power supply of the present invention is not limited to the state shown in Figures 1-5. The present invention may only include any one or multiple features of any one or multiple embodiments of Figures 1-5. In other words, not all features shown in the figures need to be implemented in the power supply of the present invention at the same time. Although the embodiment of the present invention uses a metal oxide semi-field effect transistor as an example, the present invention is not limited thereto. Those skilled in the art can use other types of transistors, such as junction field effect transistors or fins. type field effect transistor, etc., without affecting the effect of the present invention.

The ordinal numbers in this specification and the scope of the patent application, such as "first", "second", "third", etc., have no sequential relationship with each other. They are only used to distinguish two items with the same Different components with names.

Although the present invention is disclosed above in terms of preferred embodiments, they are not intended to limit the scope of the present invention. Anyone skilled in the art can make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100,200:Power supply 110,210: Input rectifier circuit 120,220:First transformer 121,221: first main coil 122,222: first secondary coil 130,230: Second transformer 131,231: Second main coil 132,232: Second secondary coil 140,240: Output rectifier circuit 150,250: Input control circuit 180,280:Microcontroller 260:Third transformer 261:Third main coil 262: The third secondary coil 270:The fourth transformer 271:Fourth main coil 272: The fourth secondary coil C1: first capacitor C2: Second capacitor C3: The third capacitor C4: The fourth capacitor C5: fifth capacitor C6: The sixth capacitor C7: The seventh capacitor D1: first diode D2: Second diode D3: The third diode D4: The fourth diode IR1: first rectified current IR2: second rectified current IRT: total rectified current LM1: First exciting inductor LM2: Second exciting inductor LR1: First leakage inductor LR2: Second leakage inductor M1: the first transistor M2: Second transistor M3: The third transistor M4: The fourth transistor M5: The fifth transistor M6: The sixth transistor M7: The seventh transistor M8: The eighth transistor M9: Ninth transistor M10: The tenth transistor M11: The eleventh transistor M12: Twelfth transistor N1: first node N2: second node N3: The third node N4: fourth node N5: fifth node N6: The sixth node N7: The seventh node N8: The eighth node N9: Ninth node N10: tenth node N11: The eleventh node N12: Twelfth node N13: The thirteenth node N14: The fourteenth node N15: The fifteenth node N16: The sixteenth node N17: The seventeenth node N18: The eighteenth node N19:Nineteenth node NC1: first control node NC2: second control node NCM: common node NIN: input node NOUT: output node R1: first resistor R2: second resistor R3: The third resistor R4: The fourth resistor VA1: first clock potential VA2: second clock potential VC1: first control potential VC2: second control potential VIN: input potential VOUT: output potential VP1: first capacitor potential VP2: second capacitor potential T1: first stage T2: The second stage VSS: ground potential ΔT: Intermediary stage ΔVTH: critical potential difference

Figure 1 is a schematic diagram of a power supply according to an embodiment of the present invention. Figure 2 is a circuit diagram showing a power supply according to an embodiment of the present invention. Figure 3 is a potential waveform diagram showing the first clock potential and the second clock potential according to an embodiment of the present invention. FIG. 4 shows potential waveforms of the first capacitor potential and the second capacitor potential according to an embodiment of the present invention. Figure 5 is a current waveform diagram showing the first rectified current, the second rectified current, and the total rectified current according to an embodiment of the present invention.

100:Power supply 110:Input rectifier circuit 120:First transformer 121: First main coil 122: First secondary coil 130:Second transformer 131: Second main coil 132: Second secondary coil 140:Output rectifier circuit 150:Input control circuit 180:Microcontroller C1: first capacitor C2: Second capacitor IR1: first rectified current IR2: second rectified current LM1: First exciting inductor LM2: Second exciting inductor LR1: First leakage inductor LR2: Second leakage inductor VA1: first clock potential VA2: second clock potential VC1: first control potential VC2: second control potential VIN: input potential VOUT: output potential

Claims (10)

A power supply with high conversion efficiency includes: an input rectifier circuit that generates a first rectified current and a second rectified current according to a first clock potential and a second clock potential; an input control circuit that couples is connected to the input rectifier circuit and generates a first control potential and a second control potential according to an input potential; a first transformer includes a first main coil and a first auxiliary coil, wherein the first transformer A first leakage inductor and a first exciting inductor are constructed, and the first main coil receives the first rectified current through the first leakage inductor; a first capacitor is coupled to the first exciting inductor. ; A second transformer, including a second main coil and a second auxiliary coil, wherein the second transformer has a built-in second leakage inductor and a second exciting inductor, and the second main coil is connected through the first Two leakage inductors receive the second rectified current; a second capacitor is coupled to the second exciting inductor; an output rectifier circuit is coupled to the first secondary coil and the second secondary coil, and is configured according to the first secondary coil. a control potential and the second control potential to generate an output potential; and a microcontroller that monitors the input control circuit and generates the first clock potential and the second clock potential accordingly; wherein the input potential is Comes from an external input power source. The power supply of claim 1, wherein the input rectifier circuit includes: A first transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is used to receive the first clock potential, and the control terminal of the first transistor The first terminal is coupled to a first node, and the second terminal of the first transistor is coupled to a second node; a second transistor has a control terminal, a first terminal, and a a second terminal, wherein the control terminal of the second transistor is used to receive the second clock potential, the first terminal of the second transistor is coupled to a ground potential, and the second terminal of the second transistor is coupled to a ground potential. The second terminal is coupled to the first node; a third transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is used to receive the a second clock potential, the first terminal of the third transistor is coupled to a third node, and the second terminal of the third transistor is coupled to a fourth node; and a fourth voltage A crystal has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth transistor is used to receive the first clock potential, and the first terminal of the fourth transistor is is coupled to the ground potential, and the second terminal of the fourth transistor is coupled to the third node; wherein the first node is used to output a total rectified current, and the total rectified current is divided into the first rectified current and the second rectified current. The power supply of claim 2, wherein the first leakage inductor has a first terminal and a second terminal, and the first terminal of the first leakage inductor is coupled to the first node to receive the first rectifying current, the second terminal of the first leakage inductor is coupled to a fifth node, the first main coil has a first terminal and a second terminal, the first main coil The first end of the coil is coupled to the fifth node, the second end of the first main coil is coupled to a sixth node, and the first exciting inductor has a first end and a second end, The first terminal of the first exciting inductor is coupled to the fifth node, the second terminal of the first exciting inductor is coupled to the sixth node, the first capacitor has a first terminal and a second end, the first end of the first capacitor is coupled to the third node, the second end of the first capacitor is coupled to the sixth node, the first secondary coil has a first The first end of the first secondary coil is coupled to a seventh node, and the second end of the first secondary coil is coupled to an eighth node. The power supply of claim 3, wherein the second leakage inductor has a first terminal and a second terminal, and the first terminal of the second leakage inductor is coupled to the first node to receive the second rectifying current, the second terminal of the second leakage inductor is coupled to a ninth node, the second main coil has a first terminal and a second terminal, and the first terminal of the second main coil is Coupled to the ninth node, the second end of the second main coil is coupled to a tenth node, the second exciting inductor has a first end and a second end, and the second exciting inductor has a first end and a second end. The first terminal is coupled to the ninth node, the second terminal of the second exciting inductor is coupled to the tenth node, the second capacitor has a first terminal and a second terminal, the The first terminal of the two capacitors is coupled to the third node, the second terminal of the second capacitor is coupled to the tenth node, and the second secondary coil has a first terminal and a second terminal, The first end of the second secondary coil is coupled to an eleventh node, and the second end of the second secondary coil is coupled to a twelfth node. The power supply of claim 4, wherein the output rectifier circuit includes: A fifth transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fifth transistor is used to receive the first control potential, and the third terminal of the fifth transistor One terminal is coupled to the seventh node, and the second terminal of the fifth transistor is coupled to an output node; a sixth transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the sixth transistor is used to receive the second control potential, the first terminal of the sixth transistor is coupled to a thirteenth node, and the sixth transistor The second terminal is coupled to the seventh node; a seventh transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the seventh transistor is used to receive the third terminal. two control potentials, the first terminal of the seventh transistor is coupled to the eighth node, and the second terminal of the seventh transistor is coupled to the output node; and an eighth transistor has A control terminal, a first terminal, and a second terminal, wherein the control terminal of the eighth transistor is used to receive the first control potential, and the first terminal of the eighth transistor is coupled to the A thirteenth node, and the second terminal of the eighth transistor is coupled to the eighth node. The power supply of claim 5, wherein the output rectifier circuit further includes: a ninth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the ninth transistor is For receiving the first control potential, the first terminal of the ninth transistor is coupled to the eleventh node, and the second terminal of the ninth transistor is coupled to the thirteenth node; A tenth transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the tenth transistor is used to receive the second control potential, and the third terminal of the tenth transistor One terminal is coupled to a common node, and the second terminal of the tenth transistor is coupled to the eleventh node; an eleventh transistor has a control terminal, a first terminal, and a a second terminal, wherein the control terminal of the eleventh transistor is used to receive the second control potential, the first terminal of the eleventh transistor is coupled to the twelfth node, and the tenth The second terminal of a transistor is coupled to the thirteenth node; a twelfth transistor has a control terminal, a first terminal, and a second terminal, wherein the twelfth transistor The control terminal is used to receive the first control potential, the first terminal of the twelfth transistor is coupled to the common node, and the second terminal of the twelfth transistor is coupled to the tenth two nodes; a third capacitor having a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the output node, and the second terminal of the third capacitor is coupled to the thirteenth node; a fourth capacitor having a first terminal and a second terminal, wherein the first terminal of the fourth capacitor is coupled to the thirteenth node, and the fourth capacitor has a first terminal and a second terminal. The second terminal is coupled to the common node; and a fifth capacitor has a first terminal and a second terminal, wherein the first terminal of the fifth capacitor is coupled to the output node to output the output potential. , and the second terminal of the fifth capacitor is coupled to the common node. The power supply of claim 2, wherein the input control circuit includes a third transformer and a fourth transformer, the third transformer includes a third main coil and a third secondary coil, and the fourth transformer includes a third transformer. Four main coils and a fourth auxiliary coil. The power supply of claim 7, wherein the input control circuit further includes: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a fourteenth node , and the cathode of the first diode is coupled to a fifteenth node; a first resistor has a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the ground potential, and the second terminal of the first resistor is coupled to the fifteenth node; a sixth capacitor having a first terminal and a second terminal, wherein the sixth capacitor The first terminal is coupled to the ground potential, and the second terminal of the sixth capacitor is coupled to the fifteenth node to provide a first capacitance potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to the fifteenth node, and the cathode of the second diode is coupled to a sixteenth node; and a second resistor, Having a first end and a second end, wherein the first end of the second resistor is coupled to the sixteenth node, and the second end of the second resistor is coupled to a first control the node to output the first control potential; The third main coil has a first end and a second end, the first end of the third main coil is coupled to an input node to receive the input potential, and the second end of the third main coil is coupled to the second node, the third secondary coil has a first end and a second end, the first end of the third secondary coil is coupled to the fourteenth node, the third secondary coil The second terminal is coupled to the ground potential. The power supply of claim 8, wherein the input control circuit further includes: a third diode having an anode and a cathode, wherein the anode of the third diode is coupled to a seventeenth node , and the cathode of the third diode is coupled to an eighteenth node; a third resistor has a first terminal and a second terminal, wherein the first terminal of the third resistor is coupled to the ground potential, and the second terminal of the third resistor is coupled to the eighteenth node; a seventh capacitor having a first terminal and a second terminal, wherein the seventh capacitor The first terminal is coupled to the ground potential, and the second terminal of the seventh capacitor is coupled to the eighteenth node to provide a second capacitor potential; a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the eighteenth node, and the cathode of the fourth diode is coupled to a nineteenth node; and a fourth resistor, Having a first end and a second end, wherein the first end of the fourth resistor is coupled to the nineteenth node, and the second end of the fourth resistor is coupled to a second control the node to output the second control potential; The fourth main coil has a first end and a second end, the first end of the fourth main coil is coupled to the input node to receive the input potential, and the second end of the fourth main coil is coupled to the fourth node, the fourth secondary coil has a first end and a second end, the first end of the fourth secondary coil is coupled to the seventeenth node, the fourth secondary coil The second terminal is coupled to the ground potential. For example, the power supply of claim 9, wherein the microcontroller is used to monitor the first capacitor potential and the second capacitor potential. If the drop of the first capacitor potential reaches a critical potential difference, the microcontroller will The potential level of the second clock potential will be raised, and if the drop in the second capacitor potential reaches the critical potential difference, the microcontroller will raise the potential level of the first clock potential.

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