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TWI814524B - 電子封裝件及其製法與電子結構及其製法 - Google Patents

電子封裝件及其製法與電子結構及其製法 Download PDF

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TWI814524B
TWI814524B TW111129577A TW111129577A TWI814524B TW I814524 B TWI814524 B TW I814524B TW 111129577 A TW111129577 A TW 111129577A TW 111129577 A TW111129577 A TW 111129577A TW I814524 B TWI814524 B TW I814524B
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electronic
conductive material
thermal
manufacturing
bumps
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TW202407936A (zh
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陳以鈴
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矽品精密工業股份有限公司
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Priority to CN202210967409.5A priority patent/CN117558689A/zh
Priority to US18/063,115 priority patent/US20240047420A1/en
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Abstract

一種電子封裝件,其製法係將一上表面具有複數導電凸塊與導熱體之電子結構藉由其下表面之外接凸塊設於一承載結構上,以當回銲該些外接凸塊時,藉由該導熱體將熱源接頭之熱源自該電子結構之上表面傳導至下表面之外接凸塊,以利於加熱回銲該些外接凸塊,避免銲錫未濕潤的不良問題。

Description

電子封裝件及其製法與電子結構及其製法
本發明係有關一種半導體裝置,尤指一種具TSV元件之電子封裝件及其製法。
為了確保電子產品和通信設備的持續小型化和多功能,半導體封裝需朝尺寸微小化發展,以利於多引腳之連接,為此,業界發展出諸多先進製程封裝技術。例如,於先進製程封裝中,常用的封裝型式如2.5D封裝製程、扇出(Fan-Out)佈線配合嵌埋橋接(Embedded Bridge)元件之製程(簡稱FO-EB)等。
圖1係為習知半導體封裝件之製法之剖面示意圖。如圖1所示,該半導體封裝件之製法係於一承載板1b上之佈線結構14上設置一具有導電矽穿孔(Through-silicon via,簡稱TSV)110之電子結構1a,且該電子結構1a之矽板體11之表面上形成有一電性連接該導電矽穿孔110之線路重佈結構(Redistribution layer,簡稱RDL)12。具體地,該線路重佈結構12係包含介電層120及形成於該介電層120上之線路層121,且該線路層121電性連接該導電矽穿孔110,並形成一防銲層13 於該線路重佈結構12上,且該防銲層13外露部分該線路層121,以結合複數導電凸塊161。
再者,可形成另一防銲層15於該矽板體11上,且該防銲層15外露該些導電矽穿孔110之端面,以結合複數銲錫凸塊122於該些導電矽穿孔110之端面上,且該銲錫凸塊122電性連接該導電矽穿孔110與該佈線結構14之電性接觸墊140,其中,可選擇性於該導電矽穿孔110之端面上形成供接置該銲錫凸塊122之凸塊底下金屬層(Under Bump Metallurgy,簡稱UBM)17。
又,該電子結構1a係藉由保護膜10包覆複數導電凸塊161。
習知半導體封裝件之製法中,該電子結構1a於結合到該佈線結構14時,需加熱回銲該些銲錫凸塊122,但於加熱過程中,回銲設備之熱源接頭8所提供之熱源Q係堆積於上方之保護膜10,而無法有效傳遞至下方之銲錫凸塊122,造成該些銲錫凸塊122發生銲錫未濕潤(non-wetting)的不良問題。
因此,如何克服上述習知技術的問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失,本發明係提供一種電子結構,係包括:電子主體,係為半導體基材,其具有相對之第一表面與第二表面;複數導電凸塊,係設於該電子主體之第一表面上;以及導熱體,係設於該電子主體之第一表面上且包含一接觸該複數導電凸塊周面以包覆該複數導電凸塊之第一導熱材、及一鄰接該第一導熱材之第二導熱材,其中,該第二導熱材之導熱係數係大於該第一導熱材之導熱係數。
本發明亦提供一種電子結構之製法,係包括:提供一半導體基材以作為電子主體,其具有相對之第一表面與第二表面;將複數導電凸塊形成於該電子主體之第一表面上;於該電子主體之第一表面之其中一部分區域上形成第一導熱材,以令該第一導熱材包覆該複數導電凸塊,其中,該第一導熱材係外露出該電子主體之第一表面之另一部分區域;以及於該電子主體之第一表面之該另一部分區域上形成鄰接該第一導熱材之第二導熱材,以令該第一導熱材與該第二導熱材作為導熱體,其中,該第二導熱材之導熱係數係大於該第一導熱材之導熱係數。
前述之電子結構及其製法中,該第一導熱材之楊氏模數係小於該第二導熱材之楊氏模數。
前述之電子結構及其製法中,該第一導熱材相對該導電凸塊周面之厚度係至少為5微米。
前述之電子結構及其製法中,該第一導熱材與該導電凸塊係於該電子主體之第一表面上呈同心圓配置。
前述之電子結構及其製法中,該第二導熱材於該第一表面上之佈設面積與該第一導熱材於該第一表面上之佈設面積的比值係大於或等於70%。
本發明再提供一種電子封裝件,係包括:線路結構,係具有相對之第一側與第二側;前述之電子結構,係以其電子本體之第一表面設於該線路結構之第一側上;以及複數電子元件,係設於該線路結構之第二側上以電性連接該線路結構,其中,該電子結構係藉由該複數導電凸塊電性連接該線路結構,以電性橋接該複數電子元件之至少二者。
本發明另提供一種電子封裝件之製法,係包括:提供一線路結構及至少一前述之電子結構,其中,該線路結構係具有相對之第一側與第二側;將該電子結構以其電子本體之第一表面設於該線路結構之第一側上;以及將複數 電子元件設於該線路結構之第二側上,以令該複數電子元件電性連接該線路結構,其中,該電子結構係藉由該複數導電凸塊電性連接該線路結構,以電性橋接該複數電子元件之至少二者。
前述之電子封裝件及其製法中,復包括包覆該電子結構之包覆層。
前述之電子封裝件及其製法中,復包括包覆該複數電子元件之封裝層。
前述之電子封裝件及其製法中,復包括將該電子結構以其電子主體之第二表面接置於一承載結構上,使該電子結構電性連接該承載結構。例如,該電子結構以其電子主體之第二表面藉由複數外接凸塊接置該承載結構。或者,可包括形成複數導電柱於該承載結構上,以令該複數導電柱電性連接該承載結構。進一步,該複數導電柱係圍繞該電子結構。
由上可知,本發明之電子封裝件及其製法與電子結構及其製法中,主要藉由該導熱體包覆該複數導電凸塊,使具有較高導熱係數之第二導熱材能提高該電子結構的熱傳導效率,以避免該外接凸塊發生銲錫未濕潤(non-wetting)的不良問題。
再者,藉由較軟材質的第一導熱材圍繞覆蓋該導電凸塊,可達到緩衝保護該導電凸塊的作用。
1a,2a:電子結構
1b:承載板
10:保護膜
11:矽板體
110:導電矽穿孔
12:線路重佈結構
120,240:介電層
121,241:線路層
122:銲錫凸塊
13,15:防銲層
14:佈線結構
140,202:電性接觸墊
161,211,261:導電凸塊
17,272:凸塊底下金屬層
19:封裝基板
190:銲球
2,3,4:電子封裝件
20:線路結構
20a:第一側
20b:第二側
200,220:絕緣層
201:線路重佈層
21:電子主體
21a:第一表面
21b:第二表面
210:導電穿孔
211a,23a:端面
211c:周面
22:線路部
221:導電跡線
222:外接凸塊
223:結合層
23:導電柱
24:承載結構
25:包覆層
25a:表面
26:電子元件
26a,38a:上表面
260,271:銲錫材料
262:底膠
27:導電元件
270:金屬凸塊
28,38:封裝層
29:導熱體
29a:頂面
291:第一導熱材
292:第二導熱材
8:熱源接頭
9:承載件
90:離型層
91:金屬層
A,B:部分區域
d:厚度
Q:熱源
S:切割路徑
圖1係為習知半導體封裝件之剖視示意圖。
圖2A至圖2C係為本發明之電子結構之製法之剖視示意圖。
圖2C-1係為圖2C之上視平面示意圖。
圖2C-2係為圖2C-1之另一態樣之上視平面示意圖。
圖2D係為圖2C之另一態樣之剖視示意圖。
圖3A至圖3F係為本發明之電子封裝件之製法之剖視示意圖。
圖3G係為圖3F之另一態樣之剖視示意圖。
圖4係為本發明之電子封裝件之其它實施例之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「第一」、「第二」、「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
圖2A至圖2C係為本發明之電子結構2a之製法的剖面示意圖。
如圖2A所示,提供一半導體基材以作為電子主體21,其具有相對之第一表面21a與第二表面21b,再於該電子主體21之第一表面21a上形成複數導電凸塊211。接著,於該電子主體21之第一表面21a上形成第一導熱材291,以令該第一導熱材291包覆該複數導電凸塊211。
於本實施例中,該電子主體21係為半導體晶片,其內形成有複數連通該第一表面21a與第二表面21b之導電穿孔210,以令該導電穿孔210電性連接該複數導電凸塊211。例如,該導電穿孔210係為導電矽穿孔(Through-silicon via,簡稱TSV),且可依需求於該電子主體21之第一表面21a及/或第二表面21b上形成線路部22(於本實施例中係於第二表面21b上形成線路部22),其包含至少一絕緣層220及結合該絕緣層220之導電跡線221,以令該導電跡線221電性連接該導電穿孔210。應可理解地,有關具有該導電穿孔210之半導體元件之態樣繁多,並無特別限制。
再者,該導電凸塊211係為如銅柱之金屬柱,以令該第一導熱材291係接觸該導電凸塊211之周面211c與端面211a。
又,該第一導熱材291係為如聚對二唑苯(Polybenzoxazole,簡稱PBO)、聚醯亞胺(Polyimide,簡稱PI)、預浸材(Prepreg,簡稱PP)或其它等之介電材。
另外,該電子主體21之第二表面21b(或該線路部22)上可依需求形成複數外接凸塊222。例如,該外接凸塊222係包含銅凸塊,且該些外接凸塊222係電性連接該導電穿孔210(或導電跡線221),並可依需求利用非導電膜(Non-Conductive Film,簡稱NCF)作為結合層223,以包覆該些外接凸塊222。應可理解地,有關該外接凸塊222之態樣繁多,並不限於上述。
如圖2B所示,進行圖案化製程,以移除該第一導熱材291之部分材質,使該第一導熱材291僅形成於該電子主體21之第一表面21a之其中一部分區域A上,而使該第一導熱材291外露出該電子主體21之第一表面21a之另一部分區域B。
於本實施例中,該第一導熱材291相對該導電凸塊211周面之剩餘厚度d係至少為5微米,且該第一導熱材291與該導電凸塊211係於該電子主體21之第一表面21a上呈同心圓配置,如圖2C-1所示。
如圖2C所示,於該電子主體21之第一表面21a上形成鄰接該第一導熱材291之第二導熱材292,且令該第一導熱材291與該第二導熱材292作為導熱體29,以形成本發明之電子結構2a,其中,該導熱體29係為複合式絕緣層,且該第二導熱材292之導熱係數係大於該第一導熱材291之導熱係數。
於本實施例中,係採用如氮化矽(SiN)之氮化物或其它絕緣材作為該第二導熱材292,以填滿該第一表面21a之部分區域B。例如,該第一導熱材291之導熱係數係小於1W/mK(如PI材),且該第二導熱材292之導熱係數為25W/mK(如SiN材)。
再者,該第一導熱材291之楊氏模數(Young's modulus)係小於該第二導熱材292之楊氏模數,使該第一導熱材291較軟而視為軟質材,且該第二導熱材292較硬而視為硬質材。例如,該第一導熱材291之楊氏模數為3.3GPa(如PI材),且該第二導熱材292之楊氏模數為265GPa(如SiN材)。
又,雖然該第二導熱材292所使用的比例分布愈高,整體導熱效果將愈好,但因該導電凸塊211的周面211c需包覆如第一導熱材291之薄膜,其厚度d至少為5微米,以達到保護該導電凸塊211之效果,故該第二導熱材292於該第一表面21a上之佈設面積與該第一導熱材291於該第一表面21a上之佈設面積的比值係較佳為大於或等於70%(即≧0.7)。具體地,如圖2C-1所示,當圖2B之圖案化製程所移除之該第一導熱材291之材質夠多而使該第一導熱材291僅以厚度5微米環繞該導電凸塊211時,該第二導熱材292於該第一表面21a上之佈設面積係最大化;或者,如圖2C-2所示,當圖2B之圖案化製程所移除之該第一導熱材291之 材質較少而使該第一導熱材291僅外露出各該導電凸塊211之間的第一表面21a時,該第二導熱材292於該第一表面21a上之佈設面積係最小化。
另外,該第二導熱材292係覆蓋該第一導熱材291,以提升熱傳導效率。或者,於另一實施例中,該第二導熱材292未覆蓋該第一導熱材291,如圖2D所示,其熱傳導效率較圖2C所示之第二導熱材292之熱傳導效率差。
圖3A至圖3F係為本發明之電子封裝件2之製法的剖面示意圖。於本實施例中,係採用圖2C所示之電子結構2a。
如圖3A所示,提供一承載件9,並於該承載件9上配置至少一電子結構2a及複數導電柱23。
所述之承載件9例如為半導體材質(如矽或玻璃)之板體,其上以例如塗佈方式依序形成有一離型層90與一如鈦/銅之金屬層91,以供一承載結構24形成於該金屬層91上,其中,該電子結構2a係以其電子主體21之第二表面21b面向該承載件9而接置於該承載結構24上。
於本實施例中,該承載結構24係例如具有核心層之封裝基板(substrate)或無核心層(coreless)式封裝基板,其包含至少一介電層240及結合該介電層240之線路層241。例如,形成該介電層240之材質係如聚對二唑苯(Polybenzoxazole,簡稱PBO)、聚醯亞胺(Polyimide,簡稱PI)、預浸材(Prepreg,簡稱PP)或其它等之介電材,且可採用線路重佈層(redistribution layer,簡稱RDL)製程形成該線路層241與該介電層240。
所述之電子結構2a係以該電子主體21之第二表面21b藉由複數外接凸塊222接置於該承載結構24之線路層241上。
於本實施例中,係藉由回銲該些外接凸塊222,以將該電子結構2a固接於該承載結構24上,其中,利用該第二導熱材292的高導熱特性,可將回銲設備之熱源接頭8所提供之熱源Q自該電子本體21之第一表面21a傳導至該些外 接凸塊222,以利於加熱回銲該些外接凸塊222,因而能避免銲錫未濕潤(non-wetting)的不良問題。
再者,若於製作該電子結構2a時未先製得作為結合層223之非導電膜(NCF),則可於該電子結構2a接置於該承載結構24上後,採用如底膠或其它易於黏著該介電層240之材質作為結合層223,以包覆該些外接凸塊222。
所述之導電柱23係設於該承載結構24上並電性連接該線路層241。
於本實施例中,形成該導電柱23之材質係為如銅之金屬材或銲錫材。例如,藉由曝光顯影方式,於該線路層241上電鍍形成該些導電柱23。
如圖3B所示,形成一包覆層25於該承載結構24上,以令該包覆層25包覆該電子結構2a、該導熱體29與該些導電柱23,且令該導熱體29之頂面29a、該導電凸塊211之端面211a與該導電柱23之端面23a外露出該包覆層25之表面25a。
於本實施例中,該包覆層25係為絕緣材,如聚醯亞胺(polyimide,簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)。例如,該包覆層25之製程可選擇液態封膠(liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression molding)等方式形成於該承載結構24上。
再者,可藉由整平製程,使該包覆層25之表面25a齊平該導熱體29之頂面29a、該導電柱23之端面23a與該導電凸塊211之端面211a,以令該導電柱23之端面23a與該導電凸塊211之端面211a外露出該包覆層25之表面25a。例如,該整平製程係藉由研磨方式,移除該導熱體29之部分材質、該導電柱23之部分材質、該導電凸塊211之部分材質與該包覆層25之部分材質。
如圖3C所示,形成一線路結構20於該包覆層25上,以令該線路結構20電性連接該複數導電柱23與該複數導電凸塊211,其中,該線路結構20係具有相對之第一側20a與第二側20b,以令該電子結構2a以其電子本體21之第一表面21a設於該線路結構20之第一側20a上。
於本實施例中,該線路結構20係包括至少一絕緣層200及設於該絕緣層200上之線路重佈層(redistribution layer,簡稱RDL)201,以令該線路重佈層201電性連接該複數導電柱23與該複數導電凸塊211,其中,最外層之絕緣層200可作為防銲層,且令最外層之線路重佈層201外露出該防銲層,俾供作為電性接觸墊202,如微墊(micro pad,俗稱μ-pad)。
再者,形成該線路重佈層201之材質係為銅,且形成該絕緣層200之材質係為如聚對二唑苯(Polybenzoxazole,簡稱PBO)、聚醯亞胺(Polyimide,簡稱PI)、預浸材(Prepreg,簡稱PP)等之介電材、或如綠漆、油墨等之防銲材。
如圖3D所示,設置複數電子元件26於該線路結構20之第二側20b上,再以一封裝層28包覆該些電子元件26。
於本實施例中,該電子元件26係為主動元件、被動元件或其二者組合,且該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。於一實施態樣中,該電子元件26係例如為圖形處理器(graphics processing unit,簡稱GPU)、高頻寬記憶體(High Bandwidth Memory,簡稱HBM)等半導體晶片,且該電子結構2a係作為橋接元件(Bridge die),其藉由該些導電凸塊211電性連接該線路結構20,進而電性橋接至少二電子元件26。
再者,該電子元件26係具有複數如銅柱之導電凸塊261,以藉由複數如銲錫凸塊之銲錫材料260電性連接該電性接觸墊202。於本實施例中,可形成 一凸塊底下金屬層(Under Bump Metallurgy,簡稱UBM)(圖略)於該電性接觸墊202或該電子元件26上,以利於結合該銲錫材料260或該導電凸塊261。
又,該封裝層28係為絕緣材,如聚醯亞胺(polyimide,簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound),其可用壓合(lamination)或模壓(molding)之方式形成於該線路結構20上。應可理解地,形成該封裝層28之材質可相同或相異該包覆層25之材質。
另外,可先形成底膠262於該電子元件26與該線路結構20之間以包覆該些導電凸塊261與銲錫材料260,再形成該封裝層28以包覆該底膠262與該電子元件26。或者,於其它實施例中,該封裝層28可同時包覆該些電子元件26與該些導電凸塊261,而無需形成該底膠262。
如圖3E所示,移除該承載件9及其上之離型層90,再移除該金屬層91,以外露出該承載結構24。
於本實施例中,於剝離該離型層90時,藉由該金屬層91作為阻障之用,以避免破壞該承載結構24之介電層240,且待移除該承載件9及其上之離型層90後,再以蝕刻方式移除該金屬層91,使該線路層241外露。
如圖3F所示,沿如圖3E所示之切割路徑S進行切單製程,且形成複數導電元件27於該承載結構24上,使該些導電元件27電性連接該線路層241,以製得電子封裝件2。
於本實施例中,該導電元件27係包含一如銅材之金屬凸塊270及形成於該金屬凸塊270上之銲錫材料271。例如,該線路層241上可形成凸塊底下金屬層(Under Bump Metallization,簡稱UBM)272,以利於結合該金屬凸塊270。應可理解地,當該接點(IO)之數量不足時,仍可藉由RDL製程進行增層作業,以重新配置該承載結構24之IO數量及其位置。
再者,如圖3G所示,可藉由整平製程,如研磨方式,移除封裝層38之部分材質,使該封裝層38之上表面38a齊平該電子元件26之上表面26a,以令該電子元件26外露出該封裝層28,以製得電子封裝件3。
又,該電子封裝件2可藉由該些導電元件27設置於一如封裝基板或電路板之電子裝置(圖略)上。
因此,本發明之製法,主要藉由該導熱體29包覆該複數導電凸塊211,使具有較高導熱係數之第二導熱材292能提高該電子結構2a的熱傳導效率,以避免該外接凸塊222發生銲錫未濕潤(non-wetting)的不良問題。
再者,藉由較軟材質的第一導熱材291圍繞覆蓋該導電凸塊211,以達到緩衝保護的作用,故於進行如圖3B所示之整平製程時,藉由研磨該第一導熱材291(緩衝材)能緩解研磨過程所造成的多種介面應力不均之問題。
另外,請配合參閱圖4,亦可將電子結構2a設於線路結構20之一側上,並於線路結構20另一側設置複數電子元件26,以製得電子封裝件4。
本發明係提供一種電子封裝件2,3,4,係包括:一電子結構2a、複數電子元件26以及一線路結構20,其中,所述之電子結構2a係包括:一電子主體21、複數導電凸塊211以及導熱體29。
所述之電子主體21係為半導體基材,其具有相對之第一表面21a與第二表面21b。
所述之導電凸塊211係設於該電子主體21之第一表面21a上。
所述之導熱體29係設於該電子主體21之第一表面21a上且包含一接觸該複數導電凸塊211周面211c以包覆該複數導電凸塊211之第一導熱材291、及一鄰接該第一導熱材291之第二導熱材292,其中,該第二導熱材292之導熱係數係大於該第一導熱材291之導熱係數。
於一實施例中,該第一導熱材291之楊氏模數係小於該第二導熱材292之楊氏模數。
於一實施例中,該第一導熱材291相對該導電凸塊211周面之厚度d係至少為5微米。
於一實施例中,該第一導熱材291與該導電凸塊211係於該電子主體21之第一表面21a上呈同心圓配置。
於一實施例中,該第二導熱材292於該第一表面21a上之佈設面積與該第一導熱材291於該第一表面21a上之佈設面積的比值係大於或等於70%。
於一實施例中,所述之電子封裝件2,3復包括承載結構24,係承載該電子結構2a,以令該電子結構2a以其電子主體21之第二表面21b接置於該承載結構24上,使該電子結構2a電性連接該承載結構24。
進一步,該電子結構2a以其電子主體21之第二表面21b藉由複數外接凸塊222接置該承載結構24。
或者,所述之電子封裝件2,3復包括複數設於該承載結構24上以電性連接該承載結構24之導電柱23。例如,該複數導電柱23係圍繞該電子結構2a。
所述之線路結構20係具有相對之第一側20a與第二側20b。
所述之電子結構2a係以其電子本體21之第一表面21a設於該線路結構20之第一側20a上。
所述之電子元件26係設於該線路結構20之第二側20b上以電性連接該線路結構20,其中,該電子結構2a係藉由該複數導電凸塊211電性連接該線路結構20,以電性橋接該複數電子元件26之至少二者。
於一實施例中,所述之電子封裝件2,3,4復包括包覆該電子結構2a之包覆層25。
於一實施例中,所述之電子封裝件2,3,4復包括包覆該複數電子元件26之封裝層28,38。
綜上所述,本發明之電子封裝件及其製法,係藉由該導熱體之設計,不僅能達到緩衝保護的作用,且能提高該電子結構的熱傳導效率,故本發明能提升產品之良率。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
2a:電子結構
21:電子主體
21a:第一表面
21b:第二表面
222:外接凸塊
223:結合層
23:導電柱
24:承載結構
240:介電層
241:線路層
29:導熱體
291:第一導熱材
292:第二導熱材
8:熱源接頭
9:承載件
90:離型層
91:金屬層
Q:熱源

Claims (24)

  1. 一種電子結構,係包括:電子主體,係為半導體基材,其具有相對之第一表面與第二表面;複數導電凸塊,係設於該電子主體之第一表面上以供進行電性連接之用;以及導熱體,係設於該電子主體之第一表面上,且包含一接觸該複數導電凸塊周面以包覆該複數導電凸塊之第一導熱材,以及一鄰接該第一導熱材之第二導熱材,其中,該第二導熱材之導熱係數係大於該第一導熱材之導熱係數。
  2. 如請求項1所述之電子結構,其中,該第一導熱材之楊氏模數係小於該第二導熱材之楊氏模數。
  3. 如請求項1所述之電子結構,其中,該第一導熱材相對該導電凸塊周面之厚度係至少為5微米。
  4. 如請求項1所述之電子結構,其中,該第一導熱材與該導電凸塊係於該電子主體之第一表面上呈同心圓配置。
  5. 如請求項1所述之電子結構,其中,該第二導熱材於該第一表面上之佈設面積與該第一導熱材於該第一表面上之佈設面積的比值係大於或等於70%。
  6. 一種電子封裝件,係包括:線路結構,係具有相對之第一側與第二側;如請求項1至5之任一者所述之電子結構,係以其電子本體之第一表面設於該線路結構之第一側上;以及 複數電子元件,係設於該線路結構之第二側上以電性連接該線路結構,其中,該電子結構係藉由該複數導電凸塊電性連接該線路結構,以電性橋接該複數電子元件之至少二者。
  7. 如請求項6所述之電子封裝件,復包括包覆該電子結構之包覆層。
  8. 如請求項6所述之電子封裝件,復包括包覆該複數電子元件之封裝層。
  9. 如請求項6所述之電子封裝件,復包括承載該電子結構之承載結構,以令該電子結構以其電子主體之第二表面接置於該承載結構上,並使該電子結構電性連接該承載結構。
  10. 如請求項9所述之電子封裝件,其中,該電子結構以其電子主體之第二表面藉由複數外接凸塊接置該承載結構。
  11. 如請求項9所述之電子封裝件,復包括複數設於該承載結構上以電性連接該承載結構之導電柱。
  12. 如請求項11所述之電子封裝件,其中,該複數導電柱係圍繞該電子結構。
  13. 一種電子結構之製法,係包括:提供一半導體基材以作為電子主體,其具有相對之第一表面與第二表面;形成複數供進行電性連接用之導電凸塊於該電子主體之第一表面上;於該電子主體之第一表面之其中一部分區域上形成第一導熱材,以令該第一導熱材包覆該複數導電凸塊,且令該第一導熱材係外露出該電子主體之第一表面之另一部分區域;以及 於該電子主體之第一表面之該另一部分區域上形成鄰接該第一導熱材之第二導熱材,以令該第一導熱材與該第二導熱材作為導熱體,其中,該第二導熱材之導熱係數係大於該第一導熱材之導熱係數。
  14. 如請求項13所述之電子結構之製法,其中,該第一導熱材之楊氏模數係小於該第二導熱材之楊氏模數。
  15. 如請求項13所述之電子結構之製法,其中,該第一導熱材相對該導電凸塊周面之厚度係至少為5微米。
  16. 如請求項13所述之電子結構之製法,其中,該第一導熱材與該導電凸塊係於該電子主體之第一表面上呈同心圓配置。
  17. 如請求項13所述之電子結構之製法,其中,該第二導熱材於該第一表面上之佈設面積與該第一導熱材於該第一表面上之佈設面積的比值係大於或等於70%。
  18. 一種電子封裝件之製法,係包括:提供一線路結構及至少一如請求項1至5之任一者所述之電子結構,其中,該線路結構係具有相對之第一側與第二側;將該電子結構以其電子本體之第一表面設於該線路結構之第一側上;以及將複數電子元件設於該線路結構之第二側上,以令該複數電子元件電性連接該線路結構,其中,該電子結構係藉由該複數導電凸塊電性連接該線路結構,以電性橋接該複數電子元件之至少二者。
  19. 如請求項18所述之電子封裝件之製法,復包括形成包覆該電子結構之包覆層。
  20. 如請求項18所述之電子封裝件之製法,復包括形成包覆該複數電子元件之封裝層。
  21. 如請求項18所述之電子封裝件之製法,復包括將該電子結構以其電子主體之第二表面接置於一承載結構上,使該電子結構電性連接該承載結構。
  22. 如請求項21所述之電子封裝件之製法,其中,該電子結構以其電子主體之第二表面藉由複數外接凸塊接置該承載結構。
  23. 如請求項21所述之電子封裝件之製法,復包括形成複數導電柱於該承載結構上,以令該複數導電柱電性連接該承載結構。
  24. 如請求項23所述之電子封裝件之製法,其中,該複數導電柱係圍繞該電子結構。
TW111129577A 2022-08-05 2022-08-05 電子封裝件及其製法與電子結構及其製法 TWI814524B (zh)

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Publication number Priority date Publication date Assignee Title
US20210375719A1 (en) * 2018-01-10 2021-12-02 Intel Corporation Stacked die architectures with improved thermal management
US20210375716A1 (en) * 2020-06-01 2021-12-02 Intel Corporation Hybrid thermal interface material (tim) with reduced 3d thermal resistance
TW202209582A (zh) * 2020-08-27 2022-03-01 矽品精密工業股份有限公司 電子封裝件及其製法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210375719A1 (en) * 2018-01-10 2021-12-02 Intel Corporation Stacked die architectures with improved thermal management
US20210375716A1 (en) * 2020-06-01 2021-12-02 Intel Corporation Hybrid thermal interface material (tim) with reduced 3d thermal resistance
TW202209582A (zh) * 2020-08-27 2022-03-01 矽品精密工業股份有限公司 電子封裝件及其製法

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