TWI859946B - Method of manufacturing dram cell - Google Patents

Abstract

The method for manufacturing a dynamic random access memory cell according to an embodiment of the present invention may include: forming an insulating layer on a substrate; forming a channel layer on the insulating layer; performing a high pressure heat treatment in an oxygen environment; forming a trench in a portion of the channel layer and the insulating layer; and forming a channel layer on the channel layer with the trench in between. The present invention further comprises the steps of forming a first gate structure and a second gate structure on the layer; forming a first source and a first drain with the first gate structure in between; forming a second source and a second drain with the second gate structure in between; and forming a storage node line electrically connecting the first drain and the second gate structure.

Description

Dynamic random access memory unit manufacturing method

The present invention relates to a method for manufacturing a semiconductor memory cell, and more specifically, to a method for manufacturing a dynamic random access memory (DRAM) cell using a transistor.

In semiconductor memory devices, which are widely used in high-performance electronic systems, semiconductor memory modules include volatile memory chips (e.g., dynamic random access memory (DRAM)) or non-volatile memory chips (e.g., read-only memory (ROM), hard disk, NAND, NOR). Semiconductor memory devices send and receive data and share power with external memory controllers through channels.

A dynamic random access memory device includes an array of multiple dynamic random access memory (DRAM) cells, each of which stores data bits. To store the data bits, each dynamic random access memory (DRAM) cell includes a capacitor and an access transistor. In the dynamic random access memory (DRAM) cell, logical "1" and logical "0" can be expressed depending on whether the capacitor is charged or not. A semiconductor device that uses a capacitor to store data bits is disclosed in Korean Patent Publication No. 10-2022-0012120.

In a DRAM cell, the charge stored in the capacitor will leak over time. Therefore, in order to maintain the data stored in the DRAM cell, multiple DRAM cells need to be periodically refreshed by rewriting.

Recently, the use of 3D DRAM devices has been increasing. Therefore, there is a need to reduce the size (scalability) of 3D DRAM cells.

The purpose of this specification is to provide a method for manufacturing a dynamic random access memory (DRAM) cell composed only of transistors without a storage capacitor.

The purpose of this specification is to provide a method for manufacturing a dynamic random access memory (DRAM) cell that can prevent charge leakage.

The purpose of this specification is to provide a method for manufacturing a dynamic random access memory (DRAM) cell that is smaller in size than before and has high performance.

The purpose of this specification is not limited to the above-mentioned purpose. A person skilled in the art of the present invention can more clearly understand other purposes and advantages of this specification that are not mentioned from the embodiments of this specification described below. Moreover, the purposes and advantages of this specification can be achieved through the structural elements and their combinations described in the scope of the invention application.

The method for manufacturing a dynamic random access memory (DRAM) unit according to an embodiment of the present invention may include: forming an insulating layer on a substrate; forming a channel layer on the insulating layer; performing a high pressure heat treatment in an oxygen environment; forming a trench in a portion of the channel layer and the insulating layer; and forming a plurality of channels on the substrate with the trench in between. The method comprises the steps of forming a first gate structure and a second gate structure on the channel layer; forming a first source and a first drain with the first gate structure in between; forming a second source and a second drain with the second gate structure in between; and forming a storage node line electrically connecting the first drain and the second gate structure.

According to an embodiment, a dynamic random access memory (DRAM) cell composed only of transistors without a storage capacitor can be fabricated.

According to an embodiment, leakage of charge can be prevented during driving of a dynamic random access memory (DRAM) cell.

According to the embodiments, a dynamic random access memory (DRAM) cell with a smaller size than before and high performance can be manufactured.

Hereinafter, the present invention will be described in detail with reference to the attached drawings so that a person skilled in the art can easily understand and reproduce the embodiments of the present invention. In the process of describing the present invention, when it is determined that the specific description of the relevant known functions or structures makes the subject of the embodiments of the present invention unclear, the detailed description thereof will be omitted. The terms used in this specification can be fully transformed according to the intention, convention, etc. of the user or the user, and therefore, the definition of each term should be issued based on the overall content of this specification.

Furthermore, the embodiments of the inventions added above will become more clearly understood through the embodiments described below. In this specification, even if the embodiments or the structures of the embodiments described selectively are shown as a single combined structure in the drawings, unless otherwise described, it should be understood that they can be freely combined with each other if there is no technical contradiction with the skilled person.

Therefore, the embodiments described in this specification and the structures shown in the drawings are merely preferred embodiments of the present invention, and do not replace the technical ideas of the present invention. Therefore, at the time of this application, there may be multiple equivalent technical solutions and variations that can replace these.

FIG. 1 is a diagram illustrating a method for fabricating a dynamic random access memory (DRAM) cell according to an embodiment.

As shown in FIG1 , a method for manufacturing a dynamic random access memory (DRAM) cell according to an embodiment may include the following step (a): forming an insulating layer 110 on a substrate 100. For example, the insulating layer 110 may include SiO ₂ , but the composition of the insulating layer 110 is not limited thereto. The insulating layer 110 may prevent electric current from flowing toward the substrate 100.

In one embodiment, a high pressure oxygen heat treatment step may be performed after forming the insulating layer 110. In particular, the high pressure oxygen heat treatment may be performed on a plasma enhanced chemical vapor deposition (PECVD) low quality oxide film of _SiO2 evaporated under low temperature conditions.

In another embodiment, another insulating layer may be formed between the substrate 100 and the insulating layer 110. For example, an insulating layer containing an aluminum oxide (Al ₂ O ₃ ) component may be additionally formed, thereby improving the insulating effect.

A method for manufacturing a dynamic random access memory (DRAM) cell according to an embodiment may include the following step (b): forming a channel layer 120 on an insulating layer 110. The channel layer 120 may be an amorphous semiconductor (a-IGZO) including indium, gallium, zinc, and oxide.

The thickness of the channel layer 120 may vary according to the embodiment. According to the thickness of the channel layer 120, the threshold voltage value (V _th ) may vary.

The method for manufacturing a dynamic random access memory (DRAM) cell of an embodiment may further include the following step (c): performing a high pressure heat treatment on the channel layer 120 in an oxygen environment, thereby reducing the concentration of oxygen vacancies.

When manufacturing an indium gallium zinc oxide thin film transistor (IGZO TFT), if oxygen vacancies generated in the channel layer 120 are minimized, the threshold voltage value (V _th ) is maintained in a positive direction, and thus, the leakage current of a dynamic random access memory (DRAM) cell can be substantially reduced.

The step (c) of performing high pressure heat treatment on the channel layer 120 in an oxygen environment may be performed at a temperature range of 100° C. to 600° C., preferably, at a temperature range of 200° C. to 400° C. Furthermore, the step (c) of performing high pressure heat treatment on the channel layer 120 in an oxygen environment may be performed at a pressure range of 2 atmospheres to 30 atmospheres, preferably, at a pressure range of 5 atmospheres to 20 atmospheres.

A method for manufacturing a dynamic random access memory (DRAM) cell according to an embodiment may include the following step (d): forming a trench T by etching a portion of the channel layer 120 and the insulating layer 110 to expose the substrate. The trench may be a boundary for distinguishing a write transistor and a read transistor described below. The trench may perform a function of interrupting channel formation.

Although not shown, in another embodiment, an insulating material (eg, Al ₂ O ₃ ) may be filled in the trench T. Filling with the insulating material can maximize the insulating effect.

A method for manufacturing a dynamic random access memory (DRAM) cell of an embodiment may include the following step (f): forming a first gate structure G1 and a second gate structure G2 on a channel layer 120 with a trench therebetween. The first gate structure G1 and the second gate structure G2 may include a semiconductor oxide layer (e.g., Al ₂ O ₃ ) and an electrode layer. The semiconductor oxide layer may also be referred to as an anti-diffusion film layer. The first gate structure G1 and the second gate structure G2 may have the same composition and/or size. The first gate structure G1 and the second gate structure G2 may be electrically connected to a word line (not shown).

A method for manufacturing a dynamic random access memory (DRAM) cell according to an embodiment may include the following step (g): forming a first source S1 and a first drain D1 with a first gate structure in between, and forming a second source S2 and a second drain D2 with a second gate structure in between.

The first transistor T1 may include a first gate structure G1, a first source S1, a first drain D1, and an insulating layer 110. The second transistor T2 may include a second gate structure G2, a second source S2, a second drain D2, and an insulating layer 110. The first transistor T1 may perform a function of a write transistor, and the second transistor T2 may perform a function of a read transistor. The first transistor T1 and the second transistor T2 may share a substrate 100.

A method for manufacturing a dynamic random access memory (DRAM) cell according to an embodiment may include the following step (h): forming a storage node line 130 electrically connecting the first drain D1 and the second gate structure G2. The storage node line 130 is composed of a conductor and can perform the function of transmitting a write/read control signal from the first transistor T1 to the second transistor T2.

Due to the formation of the trench T and the storage node line 130, the channel formation from the first drain D1 to the second source S2 is isolated, and the write/read control signal can be transmitted from the first drain D1 to the second gate structure G2.

A method for manufacturing a dynamic random access memory (DRAM) cell according to an embodiment may include the following step (i): performing a high pressure heat treatment in a hydrogen environment. Exemplarily, the step (i) of performing the high pressure heat treatment in a hydrogen environment may be performed after the step (h) of forming a storage node line. However, the step (i) of performing the high pressure heat treatment in a hydrogen environment does not necessarily have to be performed after the step (h) of forming the storage node line.

The step (i) of performing high pressure heat treatment in a hydrogen environment can be performed at a temperature range of 100°C to 600°C, preferably, at a temperature range of 200°C to 400°C. Furthermore, the step (i) of performing high pressure heat treatment in a hydrogen environment can be performed at a pressure range of 2 atmospheres to 30 atmospheres, preferably, at a pressure range of 5 atmospheres to 20 atmospheres. The high pressure heat treatment is performed in a hydrogen environment, whereby an appropriate amount of hydrogen will penetrate into the interface between the hydrogen source region and the drain region. Thus, the resistance value of the junction of the source region or the drain region can be restored to the level before the heat treatment is performed in the above-mentioned oxygen environment.

As described above, when manufacturing an indium gallium zinc oxide thin film transistor (IGZO TFT), if the oxygen vacancies generated in the channel layer 120 are minimized, the threshold voltage value ( _Vth ) is maintained in the positive direction, thereby, the leakage current of the dynamic random access memory (DRAM) unit can be sufficiently reduced. However, it is necessary to maintain a sufficient number of oxygen vacancies at the contact of the source region or the drain region to sufficiently reduce the resistance value of the dynamic random access memory (DRAM). Therefore, the characteristics of the channel layer and the characteristics of the source region and the drain region cannot be satisfied at the same time by only the heat treatment in the above oxygen environment.

To solve this problem, in an embodiment of the present invention, after the channel layer is heat treated in an oxygen environment under low temperature and high pressure conditions, an anti-diffusion film is formed on the gate structure. Thereafter, the source region and the drain region are heat treated in a hydrogen environment under low temperature and high pressure conditions. Thus, the electrical characteristics of the channel layer and the electrical characteristics of the source region and the drain region can be improved respectively.

Experiments have shown that the higher the pressure in a hydrogen environment, the better the electron mobility and subthreshold swing (SS) characteristics. By passivating oxygen vacancy defects, the carrier can be increased.

A plurality of DRAM cells are connected with word lines and/or bit lines to form a DRAM device.

FIG. 3 is a graph showing performance characteristics of a dynamic random access memory (DRAM) cell fabricated by high pressure heat treatment in a hydrogen environment according to one embodiment.

Part (a) of Figure 3 is a graph showing the electron mobility characteristics based on pressure, and Part (b) of Figure 3 is a graph showing the subthreshold swing (SS) characteristics based on pressure. As shown in Part (a) of Figure 3, it can be seen that in a hydrogen environment with a pressure range of 2 to 30 atmospheres, the electron mobility can be generally increased with the increase in pressure. In particular, it can be seen that the electron mobility increases significantly up to 20 atmospheres, and the electron mobility is saturated above 20 atmospheres.

Furthermore, as shown in part (b) of Figure 3, it can be seen that in a hydrogen environment within a pressure range of 2 to 30 atmospheres, the subthreshold swing (SS) decreases as the pressure increases. In particular, the subthreshold swing (SS) decreases significantly within a range of 10 to 20 atmospheres.

FIG. 4 is a diagram showing a circuit diagram of a dynamic random access memory (DRAM) cell composed of two transistors according to an embodiment.

As shown in the figure, the write transistor T1 and the read transistor T2 are electrically connected to form a dynamic random access memory (DRAM) cell 1000.

In the write transistor T1, electrons move from the first drain D1 to the first source S1 or do not move to the first source S1 through the switching operation of the first gate structure G1. In one embodiment, the first source S1 may be electrically connected to the write bit line, and the first gate structure G1 may be electrically connected to the write word line.

The first drain D1 may be electrically connected to the second gate structure G2 of the read transistor T2 through the storage node line 130. In one embodiment, the second source S2 and the second drain D2 of the read transistor T2 may be electrically connected to the read bit line and the read word line, respectively. In another embodiment, the second source S2 and the second drain D2 of the read transistor T2 may be electrically connected to the read word line and the read bit line, respectively.

In one embodiment, in order to perform a write operation, a voltage of 1V corresponding to "1" is input to the second source S2 and a voltage of 0V corresponding to data "0" is applied to the second drain D2. A voltage of 1V may be applied to the first gate structure G1, and a voltage of 1V or 0V may be applied to the first source S1. Thus, the change of the output voltage value (VSN) presented in the storage node line may be used to write data "1" or data "0" in the read transistor T2.

In one embodiment, in order to perform a reading operation, a voltage of -2V may be applied to the first gate structure G1, and a voltage of 1V or 0V may be applied to the first source S1, while a voltage of 1V corresponding to data "1" is applied to the second source S2 and a voltage of 0V corresponding to data "0" is applied to the second drain D2. Thus, the data "1" or data "0" written in the read transistor T2 is read by utilizing the change in the output voltage value (VSN) presented in the storage node line.

The above-mentioned writing operation and reading operation are merely an example, and can be modified in many ways by ordinary technicians in the technical field to which the present invention belongs.

As described above, unlike the existing DRAM cell, the DRAM cell manufactured according to the embodiment does not include a storage capacitor but only includes two transistors. Therefore, current leakage can be prevented during the driving process.

Furthermore, according to the above-mentioned embodiment, in the process of manufacturing a dynamic random access memory (DRAM) unit, a heat treatment is performed in an oxygen or hydrogen environment at a low temperature (100°C to 600°C, preferably 200°C to 400°C) and a high pressure (2 atmospheres to 30 atmospheres, preferably 5 atmospheres to 20 atmospheres). By this heat treatment, the oxygen vacancies are passivated, so that the carrier can be increased, and the electron mobility and subthreshold swing (SS) characteristics can be improved.

As described above, the embodiments are described with reference to the drawings, but the present invention is not limited to the embodiments and drawings described in this specification, and various modifications can be made by ordinary technicians in the technical field to which the present invention belongs. In the process of describing the embodiments, even if the effects based on the inventive structure are not described by explicit description, other effects that can be predicted by the corresponding structure should also be recognized.

100: substrate 110: insulating layer 120: channel layer 130: storage node line 1000: dynamic random access memory (DRAM) cell D1: first drain D2: second drain G1: first gate structure G2: second gate structure S1: first source S2: second source T: trench T1: first transistor T2: second transistor

FIG. 1 and FIG. 2 are diagrams showing a method for manufacturing a dynamic random access memory (DRAM) cell according to an embodiment. FIG. 3 is a diagram showing performance characteristics of a dynamic random access memory (DRAM) cell manufactured by high pressure heat treatment in a hydrogen environment according to an embodiment. Part (a) of FIG. 3 shows the electron mobility characteristics based on pressure, and part (b) of FIG. 3 shows the subthreshold swing (SS) characteristics based on pressure. FIG. 4 is a diagram showing a circuit diagram of a dynamic random access memory (DRAM) cell composed of two transistors according to an embodiment.

100: Substrate

110: Insulation layer

120: Channel layer

130:Store node lines

D1: First drain

D2: Second drain

G1: First grid structure

G2: Second grid structure

S1: First source

S2: Second source

T1: First transistor

T2: Second transistor

Claims (8)

A method for manufacturing a dynamic random access memory cell includes: forming an insulating layer on a substrate; forming a channel layer on the insulating layer; performing a heat treatment in an oxygen environment; forming a trench in the channel layer and a portion of the insulating layer; forming a first gate structure and a second gate structure on the channel layer with the trench in between; The steps of forming a first source and a first drain with the first gate structure in between; forming a second source and a second drain with the second gate structure in between; performing a heat treatment in a hydrogen environment with a pressure range of 2 atmospheres to 30 atmospheres or 5 atmospheres to 20 atmospheres; and forming a storage node line electrically connecting the first drain and the second gate structure. As in claim 1, the method for manufacturing a dynamic random access memory cell, wherein the step of performing heat treatment in an oxygen environment is performed within a temperature range of 100°C to 600°C. A method for manufacturing a dynamic random access memory cell as claimed in claim 1, wherein the step of performing heat treatment in the above oxygen environment is performed within a pressure range of 2 atmospheres to 30 atmospheres. As in claim 1, the method for manufacturing a dynamic random access memory cell, wherein the step of performing heat treatment in the above-mentioned oxygen environment is performed within a temperature range of 200°C to 400°C. A method for manufacturing a dynamic random access memory cell as claimed in claim 1, wherein the step of performing heat treatment in the above oxygen environment is performed within a pressure range of 5 atmospheres to 20 atmospheres. As in claim 1, the method for manufacturing a dynamic random access memory cell, wherein the step of performing heat treatment in the above-mentioned hydrogen environment is performed within a temperature range of 100°C to 600°C. As in claim 1, the method for manufacturing a dynamic random access memory cell, wherein the step of performing heat treatment in the above-mentioned hydrogen environment is performed within a temperature range of 200°C to 400°C. The method for manufacturing a dynamic random access memory cell as claimed in claim 1, wherein the step of forming the first gate structure and the second gate structure includes: the step of forming an anti-diffusion film on the first gate structure and the second gate structure.