TWI736996B - Method for performing signal adjustment and associated timing controller - Google Patents

Abstract

The present invention provides a method for performing signal adjustment and associated timing controller, which is applicable to a controller of a display apparatus. The display apparatus comprises the timing controller, a plurality of data lines, a plurality of scan lines, and a plurality of display units, wherein the timing controller generates multiple control signals according to a clock signal to control the display apparatus, and the method may include performing associated adjustment, to control the charging time of a data line during different horizontal periods tend to be consistent. For example, the aforementioned associated adjustment may include adjust a predetermined configuration or a modulation rate of the clock signal.

Description

Method for signal adjustment and related timing controller

The present invention relates to signal control, in particular to a method for signal adjustment and a related timing controller, wherein the method is applicable to a timing controller of a display device.

At a signal output end, a fixed-frequency clock signal is the main source of electromagnetic interference (Electromagnetic Interference can be referred to as EMI). Among them, Spread Spectrum Clock technology can effectively reduce EMI through clock modulation. Peak. However, the control signals of the display panel may also be spread, causing the frequency of these control signals to change over time, so that the signal lines on the display panel have different charging times under different frame periods, causing the display screen to scroll. The water ripples thus bring a poor user experience to the user. Therefore, a novel method and related architecture are needed to solve related technical problems without side effects or less likely to cause side effects.

An object of the present invention is to provide a method for signal adjustment and a related timing controller to solve the above-mentioned problems.

Another object of the present invention is to provide a method for signal adjustment and a related timing controller to control the charging time trend of a data line in different horizontal cycles without side effects or less likely to cause side effects. Yu unanimous.

At least one embodiment of the present invention provides a method for signal adjustment, wherein the method is applicable to a timing controller of a display device including the A timing controller, a plurality of data lines, a plurality of scan lines, and a plurality of display units, and the method may include: detecting an overall average period of a clock signal, wherein the timing controller generates a plurality of Control signals to control the display device; respectively detect the average period during which the clock signal is in each of the plurality of scan lines; respectively compare the average periods with the overall average period to generate comparison results respectively ; According to the comparison results, respectively adjust the predetermined settings of the plurality of scan lines to determine the pulse widths of the gate control signals on the plurality of scan lines respectively, wherein the pulse widths correspond to the The predetermined settings of a plurality of scan lines; and dynamically adjusting the predetermined settings to control the charging time of a data line in different horizontal periods to be consistent.

At least one embodiment of the present invention provides a timing controller for a display device, wherein the display device may include the timing controller, a plurality of data lines, a plurality of scan lines, and a plurality of display units. The timing controller can include at least one detection circuit, at least one comparison circuit, and at least one adjustment circuit, wherein the at least one detection circuit can be used to detect an overall average period of the clock signal and the plurality of For the average period of each period of the scan line, the at least one comparison circuit can be used to compare the average periods with the overall average period to respectively generate comparison results, and the at least one adjustment circuit can be used to compare the average periods according to the The comparison results respectively adjust the predetermined settings of the plurality of scan lines to determine the pulse widths of the gate control signals on the plurality of scan lines respectively, wherein the pulse widths correspond to those of the plurality of scan lines. The predetermined settings, for example, the at least one adjustment circuit can dynamically adjust the predetermined settings to control the charging time of a data line in different horizontal periods to be consistent.

At least one embodiment of the present invention provides a method for signal adjustment, wherein the method can be applied to a timing controller of a display device. The display device includes the timing controller, a plurality of data lines, A plurality of scanning lines and a plurality of display units, and the method may include: detecting a horizontal-line frequency (H-line frequency) of the display device, wherein the horizontal-line frequency is determined by the frame of the display device Frequency (frame rate) and the The row count of a plurality of display units is determined; the clock signal is adjusted according to the horizontal line frequency, wherein the timing controller generates a plurality of control signals according to the clock signal to control the display device; dynamically adjusts the clock signal The clock signal is used to control the charging time of a data line in different horizontal periods to be consistent.

At least one embodiment of the present invention provides a timing controller for a display device, wherein the display device may include the timing controller, a plurality of data lines, a plurality of scan lines, and a plurality of display units. The timing controller may include a spread spectrum clock (Spread Spectrum Clock, SSC) generator, at least one detection circuit, and at least one adjustment circuit, wherein the spread spectrum clock generator can be used to generate the clock signal, the At least one detection circuit can be used to detect a horizontal-line frequency (H-line frequency) of the display device, where the horizontal-line frequency is determined by the frame rate of the display device and the plurality of displays The row count of the unit is determined, and the at least one adjusting circuit can be used to adjust the clock signal according to the horizontal line frequency, wherein the timing controller generates a plurality of control signals according to the clock signal to control the display device, For example, the at least one adjustment circuit can dynamically adjust the clock signal to control the charging time of a data line in different horizontal periods to be consistent.

One of the advantages of the present invention is that the present invention can perform related adjustments to control the charging time of a data line in different horizontal periods to be consistent. The related adjustments may include adjusting a predetermined setting or the modulation frequency of the clock signal. In addition, the implementation according to the related embodiments of the present invention does not increase a lot of additional costs. Therefore, the related technical problems can be solved, and the overall cost will not increase too much. Compared with the related technology, the present invention can control the charging time of a data line in different level cycles to be consistent without side effects or less likely to cause side effects.

310, 320, 330, 340, 610, 620: steps

100: display device

120, 200, 500: timing controller

140: source driver

160: gate driver

220: Spread spectrum clock generator

240, 540: detection circuit

260: comparison circuit

280, 580: Adjust the circuit

DU _1,1 ,DU _1,2 ,...,DU _1,M ,DU _2,1 ,DU _2,2 ,...,DU _2,M ,...,DU _N,1 ,DU _{N, 2} ,...DU _N,M : display unit

DL ₁ ,DL ₂ ,...,DL _M : data line

SL ₁ ,SL ₂ ,...,SL _N : scan line

G _EN , G _EN ': gate enable signal

G ₁ ,G ₂ ,...,G _N ,G ₁ ',G ₂ ',...,G _N ': gate control signal

L ₁ ,L ₂ ,...,L _N : period

TP, MR_1, MR_2, MR_3: signal

FIG. 1 is a schematic diagram of a display device according to an embodiment of the invention.

Figure 2 is a schematic diagram of a timing controller according to an embodiment of the invention.

Figure 3 is a workflow of the timing controller shown in Figure 2 operating according to an embodiment of the present invention.

Figure 4 is an example of signal adjustment results according to an embodiment of the present invention.

Figure 5 is a schematic diagram of a timing controller according to another embodiment of the present invention.

Fig. 6 is a workflow of the timing controller shown in Fig. 5 operating according to another embodiment of the present invention.

Fig. 7 is an example of the result of modulation frequency adjustment according to another embodiment of the present invention.

The embodiment of the present invention provides a method for signal adjustment and a related timing controller. In particular, the method can be applied to a timing controller of a display device. For ease of understanding, the method can be through the operation example of the timing controller To illustrate, the present invention is not limited to this. Figure 1 is a schematic diagram of a display device 100 according to an embodiment of the present invention. The display device 100 may include a timing controller 120, a source driver 140, a gate driver 160, and a plurality of data lines {DL ₁ , DL ₂ , ...,DL _M }, a plurality of scan lines {SL ₁ ,SL ₂ ,...,SL _N }, and a plurality of display units {DU _1,1 ,DU _1,2 ,...,DU _{1, M} ,DU _2,1 ,DU _2,2 ,...,DU _2,M ,...,DU _N,1 ,DU _N,2 ,...DU _N,M }, the symbols M and N are both A positive integer, where the timing controller can generate multiple control signals (such as multiple gate control signals and gate enable signals (such as G _EN )) to perform display control and control the multiple display units separately {DU _1,1 ,DU _1,2 ,...,DU _1,M ,DU _2,1 ,DU _2,2 ,...,DU _2,M ,...,DU _N,1 ,DU _N,2 ,... .DU _N,M }Charging time. Please note that this structure is for illustrative purposes only, and is not a limitation of the present invention.

FIG. 2 is a schematic diagram of a timing controller 200 according to an embodiment of the present invention. The timing controller 200 can be used as an example of the timing controller 120 shown in FIG. 1, but the present invention is not limited to this. The timing controller 200 may include a Spread Spectrum Clock generator 220, a detection circuit 240, a comparison circuit 260, and an adjustment circuit 280. In order to suppress the influence of electromagnetic interference (EMI), the spread spectrum clock generator 220 can modulate the frequency of its generated clock signal CK to effectively reduce the peak value of electromagnetic interference. However, according to the clock signal CK The generated multiple gate control signals are therefore applied with a corresponding spread spectrum effect. Assuming that the above-mentioned corresponding spread-spectrum effect is not further processed, the above-mentioned corresponding spread-spectrum effect may cause the frequency of each of the plurality of gate control signals to change with time, thereby affecting the plurality of display units {DU _1,1 ,DU _1,2 ,...,DU _1,M ,DU _2,1 ,DU _2,2 ,...,DU _2,M ,...,DU _N,1 ,DU _N,2 ,...DU _N,M }Charging time. The architecture of the present invention may include an adjustment mechanism that is opposite to the frequency change to eliminate the above-mentioned corresponding spreading effect. Therefore, the plurality of display units {DU _1,1 ,DU _1,2 ,...,DU _{1, M} ,DU _2,1 ,DU _2,2 ,...,DU _2,M ,...,DU _N,1 ,DU _N,2 ,...DU _N,M } The charging time can maintain normal, And there is no adverse effect caused by the above-mentioned corresponding spreading effect.

Figure 3 is a workflow 300 of the timing controller 200 operating according to an embodiment of the present invention.

Step 310: Detect the overall average period of a clock signal. In this embodiment, although the period (or frequency) of the clock signal CK will vary with time, from a slightly longer period of time (for example, corresponding to the time period of switching screens), the period of the clock signal CK is one Average value, the detection circuit 240 can detect the overall average period T_AVG of the clock signal CK as a reference.

Step 320: Detect the average period of the clock signal in each of the plurality of scan lines. In this embodiment, the detection circuit 240 can respectively detect the clock signal CK during the period when the signal of the scan line {SL ₁ , SL ₂ ,..., SL _N } is enabled, and the corresponding average The periods are {T_AVG ₁ , T_AVG ₂ ,..., T_AVG _N } respectively.

Step 330: Compare the averaging periods with the overall averaging period to generate comparison results respectively. In this embodiment, the comparison circuit 260 can respectively compare the averaging period {T_AVG ₁ , T_AVG ₂ ,..., T_AVG _N } detected by the detection circuit 240 in step 320 and the detection circuit 240 in step 310 The detected overall average period T_AVG is compared to generate comparison results {CR ₁ ,CR ₂ ,...,CR _N } respectively.

Step 340: According to the comparison results, respectively adjust the predetermined settings of the plurality of scan lines. In this embodiment, the adjustment circuit 280 can adjust the presets corresponding to the scan lines {SL ₁ , SL ₂ ,..., SL _{N } according to the comparison results {CR 1} , CR ₂ ,...,CR _{N }.} Setting, wherein the predetermined settings can respectively determine the pulse widths of the gate control signals on the _{scan lines {SL 1} , SL ₂ ,..., SL _{N }, and the pulse widths correspond to} The predetermined settings of the plurality of scan lines. For example, the predetermined settings respectively indicate the number of cycles {CYCLE ₁ ,CYCLE ₂ ,...,CYCLE _N } corresponding to the pulse widths of the gate control signals, where the number of cycles {CYCLE ₁ ,CYCLE ₂ ,...,CYCLE _N } respectively represent the number of cycles of the clock signal.

For example, when the comparison result CR ₁ indicates that the clock signal CK is in the enabled state during the signal of the _{scan line SL 1 , the corresponding average period T_AVG 1 is} smaller than the overall average period T_AVG, and the adjustment circuit 280 can increase the corresponding number of cycles cYCLE _1; as another example, when the comparison result CR ₂ noted that the clock signal CK to the scan line SL signal ₂ for the duration of the activated state, the average period corresponding T_AVG ₂ than the overall average period T_AVG large, the adjustment circuit 280 may be Reduce the corresponding number of cycles CYCLE ₂ .

In this embodiment, the timing controller 200 can control a data by repeatedly executing the workflow 300 and dynamically adjusting the predetermined settings (such as the number of cycles {CYCLE ₁ ,CYCLE ₂ ,...,CYCLE _{N })} The charging time of lines (such as any one of the data lines {DL ₁ , DL ₂ ,..., DL _M }) in different horizontal periods (or different frame periods) tends to be the same, especially, the timing controller 300 and 200 may be dynamically adjusted through setting the plurality of predetermined work flow is repeatedly executed (as the number of cycles _{{cYCLE 1, cYCLE 2, ...} , cYCLE N}), to control the data line coupled to the {DL ₁ , DL ₂ ,..., DL _M } (for example, data line DL ₁ ) of multiple display units (for example, display units {DU _1,1 ,DU _2,1 ,...,DU _{N, 1} }) The charging time in different horizontal periods (or different frame periods) tends to be the same, but the present invention is not limited to this.

Figure 4 is an example of signal adjustment results according to an embodiment of the present invention. The upper part of Figure 4 is the control signal before signal adjustment, which is the gate enable signal G _{EN , the gate control signal G 1} on the scan line SL ₁ , and the gate on the scan line SL ₂ . pole control signals G _2, ... on the scanning line and the gate electrode control signal SL _N G _N, while the lower half of FIG. 4 is a control signal after the signal is adjusted, in order, is to enable the gate signal G _EN ' , the gate electrode of the _scanning line SL control signal G ₁ ', the scan line SL on the gate electrode _2, the control signal G _2', ... and the scan line SL on the gate electrode control signal _N G _N ', wherein the gate The pole control signal {G ₁ , G ₂ ,..., G _N } (or the gate control signal {G ₁ ',G ₂ ',...,G _N '}) can respectively represent the scan line {SL ₁ , SL ₂ ,...,SL _N } During the activation period, _{the numbers marked on the gate enable signals G EN} and G _EN 'represent the number of cycles of the corresponding clock signal CK in each period (such as {CYCLE ₁ ,CYCLE ₂ ,...,CYCLE _N }). As shown in Figure 4, before the signal adjustment, the number of cycles {CYCLE ₁ ,CYCLE ₂ ,...,CYCLE _N } is set to 2000 cycles, however, due to the average of the clock signal CK in each activation period The periods are not consistent, so that _{the pulse widths of the gate control signals {G 1} , G ₂ ,..., G _N } are not consistent and the charging time is not consistent. According to this embodiment, for example, the comparison circuit 260 can indicate that the average period T_AVG _{1 of the clock signal CK during L 1 is} smaller than the overall average period T_AVG, and the adjustment circuit 280 adjusts the number of cycles CYCLE ₁ from 2000 to 2003; for another example, The comparison circuit 260 can indicate that the average period T_AVG _{2 of the clock signal CK during L 2 is} larger than the overall average period T_AVG, and the adjustment circuit 280 adjusts the number of cycles CYCLE ₂ from 2000 to 1997; and so on. Thus, the timing controller 200 can dynamically adjust the number of cycles {CYCLE ₁ ,CYCLE ₂ ,...,CYCLE _N } to control the gate control signal {G ₁ ',G ₂ ',...,G _N '} The pulse wave width tends to be the same, so that the charging time tends to be the same, but the present invention is not limited to this.

FIG. 5 is a schematic diagram of a timing controller 500 according to another embodiment of the present invention. The timing controller 500 can be used as an example of the timing controller 120 shown in FIG. 1, but the present invention is not limited to this. The timing controller 500 may include a spread spectrum clock generator 220, a detection circuit 540, and an adjustment circuit 580. The related operations can be illustrated in the subsequent embodiments.

FIG. 6 is a workflow 600 of the timing controller 500 operating according to another embodiment of the present invention.

Step 610: Detect the horizontal line frequency of the display device 100. The detection circuit 540 can detect a horizontal-line frequency (H-line frequency) of the display device 100, where the horizontal-line frequency is determined by the frame rate of the display device 100 and the display unit {DU _{1, 1} ,DU _1,2 ,...,DU _1,M ,DU _2,1 ,DU _2,2 ,...,DU _2,M ,...,DU _N,1 ,DU _N,2 ,. ..DU _N,M } is determined by the row count. For example, when the display device 100 is operating, the frame frequency is 60 Hz and the number of rows of the display unit is 2000 (that is, when N is 2000) , The horizontal line frequency is 60×2000=120kHz.

Step 620: Adjust the clock signal according to the detected horizontal line frequency. For example, when the detection circuit 540 detects that the horizontal line frequency is 120kHz, the adjustment circuit 580 can control the spread spectrum clock generator 220 to adjust the modulation rate of the clock signal CK to 120Hz (or 120kHz). Integer multiples), so that the frequency of the horizontal line is consistent (or synchronized) with the modulation frequency of the clock signal CK. In addition, the timing controller 500 can dynamically adjust the modulation frequency of the clock signal CK by repeatedly executing the workflow 600 to control a data line (such as data lines {DL ₁ , DL ₂ ,..., DL _M } The charging time of any one of them) in different horizontal periods (or different frame periods) tends to be the same. In particular, the timing controller 500 can dynamically adjust the frequency of the clock signal CK by repeatedly executing the workflow 600 rate, to control the data line coupled to the _{{DL 1, DL 2, ...} , DL M} is any one (e.g., data line DL ₁₎ of the plurality of display units (such as a display unit {DU _1,1, The charging time of DU _2,1 ,...,DU _N,1 }) tends to be the same in different horizontal periods (or different frame periods), but the present invention is not limited to this.

According to some embodiments, the timing controller 500 can dynamically adjust the modulation frequency of the clock signal CK by repeatedly executing the workflow 600 to control a data line (such as data lines {DL ₁ , DL ₂ ,... , DL _M } any one) in different horizontal periods (or different frame periods), the charging time tends to be the same. In particular, the timing controller 500 can dynamically adjust the clock signal by repeatedly executing the workflow 600 CK is frequency modulation to control coupled to the data lines _{{DL 1, DL 2, ...} , DL M} is any one (e.g., data line DL ₁₎ of the plurality of display units (display unit {DU e.g. _1,1 ,DU _2,1 ,...,DU _N,1 }) in different horizontal periods (or different frame periods), the charging time or the amount of jitter tends to be the same, but the present invention is not limited to this.

Fig. 7 is an example of the result of modulation frequency adjustment according to another embodiment of the present invention. Hypothetical The sequence controller 500 generates a pulse on the signal TP every time after charging a row of display units. Therefore, the frequency of the signal TP can represent the horizontal line frequency of the display device 100, but the invention is not limited to this. The frequency variation curves MR_1, MR_2, and MR_3 of the clock signal CK can respectively represent the frequency variation of the clock signal CK at different modulation frequencies. Please note that the signal TP shown in Figure 7 is the signal size (for example: voltage value) ) A schematic diagram of the change with time, and the frequency change curves MR_1, MR_2, and MR_3 are schematic diagrams of the frequency of the clock signal CK changing with time. The modulation frequency of the clock signal CK is smaller than the frequency of the signal TP (or the horizontal line frequency of the display device 100), as shown in the frequency variation curve MR_2, or the modulation frequency of the clock signal CK is higher than the frequency of the signal TP (or display The horizontal line frequency of the device 100 is large. As shown by the frequency change curve MR_3, the clock signal CK has a different average frequency in the charging interval of the display unit of each row, so that the charging time of the display unit of each row is not consistent; The modulation frequency is equal to (or close to) the frequency of the signal TP (or the horizontal line frequency of the display device 100). As shown by the frequency change curve MR_1, the clock signal CK can have the same ( Or approximate) the average frequency, so that the charging time of each row of display units tends to be the same; or, the modulation frequency of the clock signal CK is equal to (or close to) the frequency of the signal TP (or the horizontal line frequency of the display device 100) Integer multiples (for brevity, not shown separately in Figure 7). Similarly, the charging interval of the clock signal CK in each row of the display unit can have the same (or approximate) average frequency, so that the average frequency of each row The charging time of the display unit tends to be the same, but the present invention is not limited to this.

In summary, the present invention can selectively adjust the predetermined setting to control the number of cycles of the clock signal CK corresponding to the gate control signal on each scan line or the modulation frequency of the clock signal CK to control a data line The charging time of different level cycles tends to be the same. In addition, the implementation according to the related embodiments of the present invention does not increase a lot of additional costs. Therefore, the related technical problems can be solved, and the overall cost will not increase too much. Compared with the related technology, the present invention can control the charging time of a data line in different level cycles to be consistent without side effects or less likely to cause side effects. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

200: timing controller

220: Spread spectrum clock generator

240: Detection circuit

260: comparison circuit

280: adjustment circuit

Claims (2)

A method for signal adjustment can be applied to a timing controller of a display device. The display device includes the timing controller, a plurality of data lines, a plurality of scan lines, and a plurality of display units, The method includes detecting a horizontal-line frequency (H-line frequency) of the display device, where the horizontal-line frequency is determined by the frame rate of the display device and the rows of the plurality of display units A clock signal is adjusted according to the horizontal line frequency, wherein the timing controller generates a plurality of control signals to control the display device according to the clock signal, and the clock signal is a spread-spectrum clock (Spread Spectrum Clock, SSC) signal; wherein the step of adjusting the clock signal according to the horizontal line frequency further includes: adjusting a modulation rate of the spread spectrum clock signal so that the modulation frequency is equal to the horizontal line frequency Or an integer multiple of the horizontal line frequency. A timing controller for a display device. The display device includes the timing controller, a plurality of data lines, a plurality of scan lines, and a plurality of display units. The timing controller includes: a spread spectrum clock (Spread Spectrum Clock, SSC). ) A generator for generating the clock signal; at least one detection circuit for detecting a horizontal-line frequency (H-line frequency) of the display device, wherein the horizontal-line frequency is determined by the display device The frame rate and the row count of the plurality of display units are determined; and at least one adjustment circuit for adjusting the clock signal according to the horizontal line frequency, wherein the timing controller is based on the time The pulse signal generates a plurality of control signals to control the display device; wherein the at least one adjustment circuit adjusts a modulation rate of the clock signal so that The modulation frequency is equal to the horizontal line frequency or an integer multiple of the horizontal line frequency.

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