TW201342347A - Liquid crystal display device, panel driver and control circuit - Google Patents

Abstract

A liquid crystal display device capable of removing constant frequency noise comprises a control circuit, a backlight module, a panel and a driving circuit. The control circuit comprises a main board, a power plate and a time control unit. The main board receives an image signal and generates a low voltage differential signal determining the screen refresh frequency and a pulse width modulation signal. The frequency of the pulse width modulation signal is odd time of half of the screen refresh frequency. The power plate is electrically connected to the main board to receive the pulse width modulation signal and accordingly output a control current to the backlight module to adjust the illumination brightness. The time control unit is electrically connected to the main board to receive the low voltage differential signal and, according to the screen refresh frequency, output a time sequence to the driving circuit to drive the panel.

Description

Liquid crystal display device, panel driving device and control circuit

The present invention relates to a device and a circuit, and more particularly to a liquid crystal display device, a panel driving device, and a control circuit.

A liquid crystal display device (not shown) of the prior art determines a frame update rate by a low voltage differential signal (LVDS) and is modulated by a pulse width modulation PWM ( Pulse-width modulation) determines the brightness of the picture.

However, the conventional liquid crystal display device has the following disadvantages: the displayed picture is subject to constant frequency noise interference, and it is more common because the low voltage differential signal LVDS and the pulse width modulation signal PWM have different frequencies, often Interference with each other. As shown in FIG. 1, since the low voltage differential signal LVDS is a continuous signal, when the low voltage differential signal LVDS is interfered by a certain frequency of noise, a periodic change in brightness is displayed on the displayed picture. From the human eye, it becomes a strip of horizontal stripes.

Accordingly, it is an object of the present invention to provide a liquid crystal display, a panel driving device, and a control circuit that can reduce fixed frequency noise.

Therefore, the liquid crystal display device of the present invention comprises a control circuit, a panel, a backlight module and a driving circuit. The control circuit has a main board, a power board and a time control unit.

The motherboard is configured to receive an image signal, and generate a low voltage differential signal and a pulse width modulation signal that determine a picture update frequency, and the frequency of the pulse width modulation signal is one-half of the update frequency of the picture. It is an odd multiple and has a duty-conducting ratio. The power board is electrically connected to the main board to receive the pulse width modulation signal and accordingly output a control current of a magnitude related to the responsible conduction ratio. The time control unit is electrically connected to the main board to receive the low voltage differential signal, and generates a timing signal according to the picture update frequency.

The backlight module is electrically connected to the power board to receive the control current, and is controlled by the control current to adjust the brightness of the light. The driving circuit is electrically connected to the time control unit to receive the timing signal, and is controlled by the timing signal to drive the panel.

The panel driving device of the present invention is suitable for driving a panel, and comprises a control circuit, a backlight module and a driving circuit. The control circuit includes a main board, a power board and a time control unit.

The motherboard is configured to receive an image signal, and generate a low voltage differential signal and a pulse width modulation signal that determine a picture update frequency, and the frequency of the pulse width modulation signal is one-half of the update frequency of the picture. It is an odd multiple and has a duty-conducting ratio. The power board is electrically connected to the main board to receive the pulse width modulation signal and accordingly output a control current of a magnitude related to the responsible conduction ratio. The time control unit is electrically connected to the main board to receive the low voltage differential signal, and generates a timing signal according to the picture update frequency.

The backlight module is electrically connected to the power board to receive the control current, and is controlled by the control current to adjust the brightness of the light. The driving circuit is electrically connected to the time control unit to receive the timing signal, and is controlled by the timing signal to drive the panel.

The control circuit of the present invention is applied to a liquid crystal display device. The liquid crystal display device comprises a backlight module, a panel, and a driving circuit. The backlight module adjusts the brightness of the light according to a control current, and the driving circuit is subjected to a timing signal. The panel is controlled to drive, and the control circuit comprises a motherboard, a power board and a time control unit.

The motherboard is configured to receive an image signal, and generate a low voltage differential signal and a pulse width modulation signal that determine a picture update frequency, and the frequency of the pulse width modulation signal is one-half of the update frequency of the picture. It is an odd multiple and has a duty-conducting ratio. The power board is electrically connected to the main board to receive the pulse width modulation signal and accordingly output a control current of a magnitude related to the responsible conduction ratio. The time control unit is electrically connected to the main board to receive the low voltage differential signal, and generates a timing signal according to the picture update frequency.

In the present invention, by adjusting the frequency setting of the pulse width modulation signal, the interference received by the low voltage differential signal is inverted in every two consecutive pictures, and the noise on the picture is reduced.

The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments.

Referring to FIG. 2, a preferred embodiment of the liquid crystal display device having the function of eliminating the fixed frequency noise of the present invention comprises a panel driving device 6 and a panel 3. The panel driving device 6 includes a control circuit 2, a backlight module 4, and a driving circuit 5.

The control circuit 2 includes a main board 21, a power board 22, and a time control unit 23.

The main board 21 receives an image signal (from a signal source, such as a computer display card), and generates a low voltage differential signal LVDS that determines the picture update frequency and a pulse width modulation signal PWM that has a responsible conduction ratio. . The power board 22 is electrically connected to the main board 21 to receive the pulse width modulation signal PWM and output a control current of a magnitude related to the responsible conduction ratio. The time control unit 23 is electrically connected to the main board 21 to receive the low voltage differential signal LVDS, and generates a timing signal according to the picture update frequency.

The backlight module 4 is electrically connected to the power board 22 to receive the control current, and is controlled by the control current to adjust the brightness of the light. The driving circuit 5 is electrically connected to the time control unit 23 to receive the timing signal, and is driven by the timing signal to drive the panel 3.

In order to solve the problem that the low voltage differential signal LVDS and the pulse width modulation signal PWM interfere with each other, the frequency of the pulse width modulation signal PWM is set to an odd multiple of one-half of the update frequency of the picture. The frequency of the wave width modulation signal PWM = (2n + 1) × the picture update frequency / 2, n is an integer). Referring to FIG. 3 and FIG. 4, the low voltage differential signal LVDS is switched between a picture data level T1 and a vertical synchronous pulse level T2. When the picture data level T1 is at the picture data level, the driving circuit 5 The panel 3 is driven to display a picture 01; when at the vertical sync pulse level T2, the display of the picture 01 is ended and the next picture 02 is ready to be displayed, so the frequency of the vertical sync pulse level T2 is equal to the picture update frequency. The pulse width modulation signal PWM shown in the figure takes the 50% duty-conducting ratio as an example. At this time, the pulse width modulation signal PWM interference received by the picture 01 and the picture 02 is inverted, and the panel 3 displays Interference Due to the persistence of the human eye, after the two frames 01 and 02 are superimposed and averaged, it appears to be a uniform background light without a periodic horizontal stripes.

When the duty-conducting ratio of the pulse width modulation signal PWM is not 50%, setting the frequency to an odd multiple of one-half of the picture update frequency also has the effect of reducing the interference. As shown in FIG. 5, after the two consecutive frames 01 and 02 are superimposed and averaged, the light lines having a frequency of twice are displayed.

Referring to FIG. 2, the frequency of the pulse width modulation signal PWM can be adjusted by the main board 21, and a more precise frequency setting can be achieved by adding a phase locked loop 24. At this time, the main board 21 has a scalar processor 211 and a phase locked loop 24. The scalar processor 211 receives the image signal and extracts a clock information related to the update frequency of the picture from the image signal, and generates the low voltage differential signal LVDS according to the clock information and a frequency equal to the picture update. Frequency reference signal. The phase locked loop 24 receives an adjustment signal having a multiple set value, and is electrically connected to the scalar processor 211 to receive the reference signal, and generates the pulse width according to the multiple set value and the frequency of the reference signal. The modulation signal PWM, wherein the multiple setting is actually equivalent to an odd multiple of one-half.

As shown in FIG. 6, the phase locked loop 24 has a frequency divider 244, a frequency phase detector 241, a low pass filter 242, and a voltage controlled oscillator 243. The frequency divider 244 receives the pulse width modulation signal PWM and the adjustment signal, and generates a feedback signal according to an operation. The frequency of the feedback signal is the frequency of the pulse width modulation signal PWM divided by the frequency Multiple setting value. The frequency phase detector 241 is electrically connected to the scalar processor 211 and the frequency divider 244 to receive the reference signal and the feedback signal, and compares the reference signal with the feedback signal by frequency phase to generate A comparison of the results. The low pass filter 242 is electrically coupled to the frequency phase detector 241 to receive the comparison result and filter out high frequency components to obtain a control voltage. The voltage controlled oscillator 243 is electrically connected to the low pass filter 242 to receive the control voltage, and accordingly generates the pulse width modulation signal PWM, and the frequency of the pulse width modulation signal PWM is controlled by the control voltage. .

In summary, the above embodiment has the following advantages:

1. The frequency setting of the pulse width modulation signal PWM is used to solve the problem of fixed frequency noise interference. Regardless of where the interference occurs in the liquid crystal display device, as long as the frequency of the pulse width modulation signal PWM is an odd multiple of one-half of the update frequency of the picture, the phase inversion of the interference signal can be reduced to reduce the panel. The noise displayed on the 3 is indeed the object of the present invention.

2. The phase-locked loop 24 is directly used to adjust the frequency without time-consuming debugging on the motherboard 21 with complicated wiring.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.

LVDS. . . Low voltage differential signal

PWM. . . Pulse width modulation signal

T1. . . Picture data level

T2. . . Vertical sync pulse level

01. . . Picture

02. . . Picture

03. . . Picture

2. . . Control circuit

twenty one. . . Motherboard

211. . . Scalar processor

twenty two. . . Power Board

twenty three. . . Time control unit

twenty four. . . Phase-locked loop

241. . . Frequency phase detector

242. . . Low pass filter

243. . . Voltage controlled oscillator

244. . . Frequency divider

3. . . panel

4. . . Backlight module

5. . . Drive circuit

6. . . Panel drive

1 is a schematic diagram showing interference of a screen displayed by a conventional liquid crystal display device;

2 is a system block diagram of a preferred embodiment of a liquid crystal display device of the present invention;

3 is a waveform diagram of a low voltage differential signal and a pulse width modulation signal in the preferred embodiment;

4 is a schematic diagram of a screen displayed in the preferred embodiment, illustrating a situation in which interference is reduced when the duty-conductance ratio of the pulse width modulation signal is 50%;

FIG. 5 is a schematic diagram showing interference of a picture displayed in the preferred embodiment, illustrating a situation in which interference is reduced when the duty-to-conduction ratio is not 50%; and

Figure 6 is a system block diagram of a phase locked loop of the preferred embodiment.

LVDS. . . Low voltage differential signal

PWM. . . Pulse width modulation signal

2. . . Control circuit

twenty one. . . Motherboard

211. . . Scalar processor

twenty two. . . Power Board

twenty three. . . Time control unit

twenty four. . . Phase-locked loop

3. . . panel

4. . . Backlight module

5. . . Drive circuit

6. . . Panel drive

Claims (10)

A control circuit is applied to a liquid crystal display device. The liquid crystal display device comprises a backlight module, a panel, and a driving circuit. The backlight module adjusts the brightness of the light according to a control current, and the driving circuit is subjected to a timing signal. Controlling to drive the panel, and the control circuit comprises: a main board for receiving an image signal, and generating a low voltage differential signal and a pulse width modulation signal for determining a picture update frequency, the pulse width modulation The frequency of the signal is an odd multiple of one-half of the update frequency of the picture, and the pulse width modulation signal has a responsible conduction ratio; a power board electrically connected to the main board to receive the pulse width modulation signal and According to this, a control current of a size related to the responsible conduction ratio is output; and a time control unit electrically connects the main board to receive the low voltage differential signal, and generates the timing signal according to the picture update frequency. The control circuit of claim 1, wherein the main board comprises: a scalar processor, receiving the image signal and extracting a clock information related to the update frequency of the picture from the image signal, and according to The clock information generates the low voltage differential signal and a reference signal having a frequency equal to the update frequency of the picture; and a phase locked loop receiving an adjustment signal having a multiple of the set value and electrically connected to the scalar processor Receiving the reference signal, and generating the pulse width modulation signal according to the multiple set value and the frequency of the reference signal, wherein the multiple set value is actually equivalent to an odd multiple of one-half. The control circuit of claim 2, wherein the phase-locked loop has: a frequency divider, receiving the pulse width modulation signal and the adjustment signal, and generating a feedback signal according to the operation, The frequency of the feedback signal is the frequency of the pulse width modulation signal divided by the multiple setting value; a frequency phase detector electrically connected to the scalar processor and the frequency divider to receive the reference signal and the The signal is feedbacked, and the reference signal is compared with the feedback signal by frequency phase to generate a comparison result; a low pass filter is electrically connected to the frequency phase detector to receive the comparison result and filter out the high Frequency component to obtain a control voltage; and a voltage controlled oscillator electrically connected to the low pass filter to receive the control voltage, and accordingly generate the pulse width modulation signal, the frequency of the pulse width modulation signal It is controlled by the control voltage. A liquid crystal display device comprising: a control circuit comprising: a main board for receiving an image signal, and generating a low voltage differential signal and a pulse width modulation signal for determining a picture update frequency, the pulse width modulation The frequency of the variable signal is an odd multiple of one-half of the update frequency of the picture, and has a responsible conduction ratio; a power board electrically connected to the main board to receive the pulse width modulation signal and output a size correlation accordingly The control current of the duty-conducting ratio; and a time control unit electrically connecting the main board to receive the low-voltage differential signal, and generating a timing signal according to the update frequency of the picture; a backlight module electrically connected to the power board Receiving the control current, and adjusting the brightness of the light by the control of the control current; a panel; and a driving circuit electrically connected to the time control unit to receive the timing signal, and being controlled by the timing signal to drive the panel . The liquid crystal display device of claim 4, wherein the main board has: a scalar processor, receives the image signal, and extracts a clock information related to the update frequency of the picture from the image signal, and Generating the low voltage differential signal and a reference signal having a frequency equal to the update frequency of the picture according to the clock information; and a phase locked loop receiving an adjustment signal having a multiple set value and electrically connecting to the scalar processor Receiving the reference signal, and generating the pulse width modulation signal according to the multiple setting value and the frequency of the reference signal, wherein the multiple setting value is substantially equivalent to an odd multiple of one-half. The liquid crystal display device of claim 5, wherein the phase-locked loop has: a frequency divider, receiving the pulse width modulation signal and the adjustment signal, and generating a feedback signal according to the operation The frequency of the feedback signal is the frequency of the pulse width modulation signal divided by the multiple setting value; a frequency phase detector electrically connected to the scalar processor and the frequency divider to receive the reference signal and The feedback signal is compared with the feedback signal by frequency phase comparison to generate a comparison result; a low pass filter is electrically connected to the frequency phase detector to receive the comparison result and filter out a high frequency component to obtain a control voltage; and a voltage controlled oscillator electrically connected to the low pass filter to receive the control voltage, and accordingly generating the pulse width modulation signal, the pulse width modulation signal The frequency is controlled by the control voltage. A panel driving device is adapted to drive a panel, and comprises: a control circuit comprising: a main board for receiving an image signal, and generating a low voltage differential signal for determining a picture update frequency and a pulse width modulation a signal, the frequency of the pulse width modulation signal is an odd multiple of one-half of the update frequency of the picture, and has a responsible conduction ratio; a power board electrically connected to the main board to receive the pulse width modulation signal And outputting a control current of a size related to the responsible conduction ratio; and a time control unit electrically connecting the main board to receive the low voltage differential signal, and generating a timing signal according to the update frequency of the picture; a backlight module, Electrically connected to the power board to receive the control current, and controlled by the control current to adjust the brightness of the light; and a driving circuit electrically connected to the time control unit to receive the timing signal and controlled by the timing signal To drive the panel. The panel driving device of claim 7, wherein the motherboard comprises: a scalar processor, receiving the image signal and extracting a clock information related to the update frequency of the picture from the image signal, and Generating the low voltage differential signal and a reference signal having a frequency equal to the update frequency of the picture according to the clock information; and a phase locked loop receiving an adjustment signal having a multiple set value and electrically connecting to the scalar processor Receiving the reference signal, and generating the pulse width modulation signal according to the multiple setting value and the frequency of the reference signal, wherein the multiple setting value is substantially equivalent to an odd multiple of one-half. The panel driving device of claim 8, wherein the phase locked loop has: a frequency divider, receiving the pulse width modulation signal and the adjustment signal, and generating a feedback signal according to the operation The frequency of the feedback signal is the frequency of the pulse width modulation signal divided by the multiple setting value; a frequency phase detector electrically connected to the scalar processor and the frequency divider to receive the reference signal and The feedback signal is compared with the feedback signal by frequency phase comparison to generate a comparison result; a low pass filter is electrically connected to the frequency phase detector to receive the comparison result and filter out a high frequency component to obtain a control voltage; and a voltage controlled oscillator electrically connected to the low pass filter to receive the control voltage, and accordingly generating the pulse width modulation signal, the pulse width modulation signal The frequency is controlled by the control voltage. The panel driving device according to claim 7, wherein the duty conduction ratio is set to 50%.