TWI707411B - Connection system of semiconductor packages - Google Patents

Abstract

A connection system of semiconductor packages includes: a printed circuit board having a first surface, and a second surface, opposing the first surface; a first semiconductor package disposed on the first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; and a second semiconductor package disposed on the second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures. The first semiconductor package includes an application processor (AP) and a power management integrated circuit (PMIC) disposed side by side, and the second semiconductor package includes a memory.

Description

Connection system for semiconductor package

[Cross reference of related applications]

This application claims the Korean patent application No. 10-2017-0099219 filed with the Korean Intellectual Property Office on August 4, 2017, and the Korean patent application filed with the Korean Intellectual Property Office on September 27, 2017 The priority rights of No. 10-2017-0125377, the disclosure content of the application is incorporated into this case for reference.

The present disclosure relates to a connection system of semiconductor packages, and more specifically, to a system in which a plurality of semiconductor packages are connected to each other using a printed circuit board.

Recently, with the development of smart devices, the specifications of corresponding components of smart devices have increased. Specifically, the specifications of application processors (AP) and core integrated circuits (IC) of smart devices have developed rapidly. In order to meet such high specifications, package-on-package (POP) methods have recently been used to use application processor packages and memory packages.

At the same time, recently, the size of the application processor package has shrunk, and the number of input/output (I/O) of the memory has increased. Therefore, all the balls connected to the memory package may not only be arranged in the fan-out area of the application processor package. Therefore, an interposer can be arranged between the memory package and the application processor package to connect the memory package and the application processor package to each other, or a separate backside rewiring layer can be formed on the top surface of the application processor package to connect The application processor package is connected to the memory package.

In addition, a power management integrated circuit (power management IC, PMIC) is arranged on the printed circuit board separately from the application processor package and the memory package to manage power.

The aspect of the present disclosure can provide a semiconductor package connection system, in which the application processor (AP) and the memory can be connected to each other through a short path without using a separate interposer or back-side heavy wiring layer, and in the best design In this case, a power management integrated circuit (PMIC) can be configured.

According to aspects of the present disclosure, a semiconductor package connection system can be provided, in which an application processor (AP) and a power management integrated circuit (PMIC) are arranged side by side and one package is mounted on a surface of a printed circuit board, And the memory package is mounted on the other surface of the printed circuit board.

100: Semiconductor package/First semiconductor package

100A, 100B, 100C, 100D: the first semiconductor package

110, 210, 310: core components

110H, 210H: through hole

111a, 211a: first insulating layer/insulating layer

111b, 211b: second insulating layer/insulating layer

111c, 211c: third insulating layer

112a, 212a: first wiring layer/wiring layer

112b, 212b: second wiring layer/wiring layer

112c, 212c: third wiring layer/wiring layer

112d, 212d: fourth wiring layer/wiring layer

113a, 213a, 243a: first through hole/through hole

113b, 213b, 243b: second through hole/through hole

113c, 213c: third through hole

120A: Application processor

120AP, 120BP, 2122, 2222: connection pad

120B: Power management integrated circuit

130, 230, 2130: encapsulated body

140, 240, 2140, 2240: connecting member

140B: heat dissipation member

141, 241, 321, 2141, 2241: insulating layer

142, 242, 2142: redistribution layer

143, 243, 2143, 2243: through hole

150, 250, 330, 340, 2150, 2223, 2250: passivation layer

155, 350, 360, 460: passive components

160, 260, 2160, 2260: Metal under bump

170, 270: electrical connection structure

200, 200A, 200B, 200C, 200D, 200E, 200F: second semiconductor package

220: memory

221: memory/first memory

221P: the first connection pad

221W, 222W: bonding wire

222: Memory/Secondary Memory

222P: second connection pad

223: memory/third memory

223P: third connection pad

224: Memory/Fourth Memory

224P: Fourth connection pad

280: Bonding component

280a: The first bonding member

280b: Second bonding member

300, 300A, 300B, 440: printed circuit board

311: core layer

312, 322, 322a, 322b: circuit layer

313: Through wiring

320: No core substrate

320a, 320b: stacked components

321a, 321b: multilayer

323, 323a, 323b: via layer

400, 500, 500A: connection system

410: Application processor package

420: Intermediary Layer

430: memory package

450: Power management integrated circuit package

610: Resin layer

620: Shield

630: radiator

1000: Electronic device

1010, 1110: Motherboard

1020: Chip related components

1030: Network related components

1040: other components

1050, 1130: camera module

1060: Antenna

1070: display device

1080: battery

1090: signal line

1100: smart phone

1101, 2121, 2221: body

1120: Electronic components

2100: Fan-out semiconductor package

2120, 2220: semiconductor wafer

2170, 2270: solder ball

2200: Fan-in semiconductor package

2242: Wiring pattern

2243h: Through hole

2251: opening

2280: underfill resin

2290: molding material

2301, 2302: Intermediary substrate

2500: Motherboard

P: Electricity

S: signal

Reading the following detailed description in conjunction with the accompanying drawings will give a clearer understanding of the above and other aspects, features and advantages of this disclosure. In the accompanying drawings: FIG. 1 is a schematic block diagram showing an example of an electronic device system.

FIG. 2 is a schematic perspective view showing an example of an electronic device.

3A and 3B are schematic cross-sectional views showing the state of the fan-in semiconductor package before and after being packaged.

4 is a schematic cross-sectional view showing the packaging process of the fan-in semiconductor package.

5 is a schematic cross-sectional view showing a situation where the fan-in semiconductor package is mounted on the intermediate substrate and finally mounted on the main board of the electronic device.

6 is a schematic cross-sectional view showing a situation where the fan-in type semiconductor package is embedded in the intermediate substrate and finally mounted on the motherboard of the electronic device.

FIG. 7 is a schematic cross-sectional view showing a fan-out semiconductor package.

FIG. 8 is a schematic cross-sectional view showing a situation in which the fan-out semiconductor package is mounted on the motherboard of the electronic device.

FIG. 9 is a schematic cross-sectional view illustrating a connection system of a semiconductor package according to an exemplary embodiment in the present disclosure.

10A to 10D are schematic cross-sectional views showing various examples of the first semiconductor package of the connection system of the semiconductor package of FIG. 9.

11A to 11F are schematic cross-sectional views showing various examples of the second semiconductor package of the connection system of the semiconductor package of FIG. 9.

12A and 12B are schematic cross-sectional views showing various examples of the printed circuit board of the connection system of the semiconductor package of FIG. 9.

FIG. 13 is a schematic cross-sectional view showing several effects of the connection system of the semiconductor package according to the layout of the present disclosure.

14 is a schematic cross-sectional view showing related problems of the connection system of a semiconductor package that does not follow the layout of the present disclosure.

Hereinafter, each exemplary embodiment in the present disclosure will be described with reference to the accompanying drawings. In the drawings, the shape and size of each component may be exaggerated or reduced for clarity.

In this article, the lower side, the lower part, the lower surface, etc. are used to refer to the direction toward the mounting surface of the fan-out semiconductor package with respect to the cross section of the drawing, and the upper side, the upper part, the upper surface, etc. are used to Refers to the direction opposite to the stated direction. However, these directions are defined for the convenience of explanation, and the patent scope of this application is not particularly limited by the directions defined above.

In the description, the meaning of "connection" between a component and another component includes indirect connection via an adhesive layer and direct connection between two components. In addition, "electrical connection" means the concept including physical connection and physical disconnection. It should be understood that when "first" and "second" are used to refer to elements, the elements are not limited thereby. The use of "first" and "second" may only be used for the purpose of distinguishing the elements from other elements, and may not limit the order or importance of the elements. In some cases, the first element may be referred to as the second element without departing from the scope of the patent application proposed herein. Similarly, the second element can also be referred to as the first element.

The term "exemplary embodiment" used herein does not refer to the same exemplary embodiment, but is provided to emphasize a specific feature or characteristic different from that of another exemplary embodiment. However, the exemplary embodiments provided herein are considered to be able to be implemented by being combined integrally or partially with each other. For example In other words, even if an element set forth in a specific exemplary embodiment is not described in another exemplary embodiment, unless a contrary or contradictory description is provided in another exemplary embodiment, the element may also be It is understood as a description related to another exemplary embodiment.

The terms used herein are used only to illustrate exemplary embodiments and not to limit the present disclosure. In this case, unless otherwise explained in the context, the singular form includes the plural form.

Electronic device

FIG. 1 is a schematic block diagram showing an example of an electronic device system.

1, a motherboard 1010 can be accommodated in the electronic device 1000. The motherboard 1010 may include chip-related components 1020, network-related components 1030, and other components 1040 that are physically or electrically connected to the motherboard 1010. These components can be connected to other components described below to form various signal lines 1090.

Chip related components 1020 may include: memory chips, such as volatile memory (such as dynamic random access memory (DRAM)), non-volatile memory (such as read only memory, ROM)) or flash memory, etc.; application processor chips, such as central processing units (e.g. central processing unit (CPU)), graphics processing units (e.g. graphics processing unit, GPU) ), digital signal processor, cryptographic processor (cryptographic processor), microprocessor or microcontroller, etc.; and logic chip, such as analog-to-digital converter (ADC) or application-specific integrated circuit (application-specific integrated circuit, ASIC), etc. However, the chip-related components 1020 are not limited to this, but can also include other types of chip-related components. In addition, the wafer-related components 1020 may be combined with each other.

The network-related components 1030 may include, for example, the following protocols: wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, etc.), worldwide interoperable microwave access (worldwide) interoperability for microwave access, WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (long term evolution, LTE), only support for data evolution (evolution data only, Ev-DO), high speed packet access + (high speed) packet access +, HSPA+), high speed downlink packet access + (HSDPA+), high speed uplink packet access + (high speed uplink packet access +, HSUPA+), enhanced data GSM environment (enhanced data GSM) environment, EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G protocol, 4G protocol, 5G protocol, and subsequent agreements Any other wireless and wired protocols specified later. However, the network-related components 1030 are not limited to this, but can also include various other wireless standards or protocols or wired standards or protocols. In addition, the network The related components 1030 can be combined with each other together with the wafer related components 1020 set forth above.

Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, and low temperature co-fired ceramics. LTCC), electromagnetic interference (EMI) filters or multilayer ceramic capacitors (MLCC), etc. However, other components 1040 are not limited to this, but may also include passive components for various other purposes. In addition, other components 1040 can be combined with the chip-related components 1020 or the network-related components 1030 described above.

Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that can be physically or electrically connected to the motherboard 1010, or other components that may not be physically or electrically connected to the motherboard 1010. These other components may include, for example, camera module 1050, antenna 1060, display device 1070, battery 1080, audio codec (not shown), video codec (not shown), power amplifier (not shown), Compass (not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage unit (such as hard drive) (not shown), compact disc (not shown) disk, CD) drive (not shown) or digital versatile disk (DVD) drive (not shown), etc. However, these other components are not limited to this, but depending on the type of the electronic device 1000, other components used for various purposes can also be included.

The electronic device 1000 can be a smart phone, a personal digital assistant (personal digital assistant) digital assistant, PDA), digital camera, digital still camera, network system, computer, monitor, tablet PC, notebook PC, netbook PC , TV, video game machine, smart watch or car components, etc. However, the electronic device 1000 is not limited to this, and can be any other electronic device that processes data.

FIG. 2 is a schematic perspective view showing an example of an electronic device.

2, the semiconductor package may be used for various purposes in various electronic devices 1000 described above. For example, the motherboard 1110 can be accommodated in the main body 1101 of the smart phone 1100, and various electronic components 1120 can be physically or electrically connected to the motherboard 1110. In addition, other components (such as the camera module 1130) that may be physically connected or electrically connected to the motherboard 1110 or may not be physically or electrically connected to the motherboard 1110 (for example, the camera module 1130) may be accommodated in the body 1101. Some electronic components in the electronic component 1120 may be chip-related components, and the semiconductor package 100 may be, for example, an application processor in the chip-related components, but it is not limited to this. The electronic device need not be limited to the smart phone 1100, but may be other electronic devices as described above.

Semiconductor packaging

Generally speaking, many sophisticated circuits are integrated in a semiconductor chip. However, the semiconductor wafer itself may not be able to serve as a completed semiconductor product, and may be damaged due to external physical or chemical influences. Therefore, the semiconductor chip may not be used alone, but can be packaged and used in electronic devices and the like in a packaged state.

Here, due to the electrical connection between the semiconductor chip and the motherboard of the electronic device The difference in circuit width in connection requires semiconductor packaging. In detail, the size of the connection pads of the semiconductor chip and the spacing between the connection pads of the semiconductor chip are extremely precise, but the size of the component mounting pads of the motherboard used in electronic devices and the spacing between the component mounting pads of the motherboard are significantly larger than The size and spacing of the connection pads of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the motherboard, and packaging technology for buffering the difference in circuit width between the semiconductor chip and the motherboard is required.

Depending on the structure and purpose of the semiconductor package, the semiconductor package manufactured by packaging technology can be classified into a fan-in semiconductor package or a fan-out semiconductor package.

The fan-in semiconductor package and the fan-out semiconductor package will be described in more detail below with reference to the drawings.

Fan-in semiconductor package

3A and 3B are schematic cross-sectional views showing the state of the fan-in semiconductor package before and after being packaged.

4 is a schematic cross-sectional view showing the packaging process of the fan-in semiconductor package.

With reference to the drawings, the semiconductor chip 2220 may be, for example, an integrated circuit (IC) in a bare state. The semiconductor chip 2220 includes a body 2221 containing silicon (Si), germanium (Ge) or gallium arsenide ( GaAs), etc.; connection pads 2222 formed on a surface of the body 2221 and containing conductive materials such as aluminum (Al); and a passivation layer 2223, such as an oxide film or a nitride film, etc., formed on a surface of the body 2221 And covers at least part of the connection pad 2222. In this case, because the connection pad 2222 is significantly small, it is difficult to integrate the integrated circuit (IC) It is installed on the intermediate printed circuit board (PCB) and the main board of the electronic device.

Therefore, depending on the size of the semiconductor wafer 2220, a connection member 2240 is formed on the semiconductor wafer 2220 to rewire the connection pad 2222. The connecting member 2240 can be formed by the following steps: forming an insulating layer 2241 on the semiconductor wafer 2220 using an insulating material such as a photoimagable dielectric (PID) resin, forming a through hole 2243h opening the connecting pad 2222, and then A wiring pattern 2242 and a through hole 2243 are formed. Next, a passivation layer 2250 for protecting the connection member 2240 may be formed, an opening 2251 may be formed, and an under bump metal layer 2260 may be formed. That is, a fan-in semiconductor package 2200 including, for example, a semiconductor chip 2220, a connecting member 2240, a passivation layer 2250, and an under bump metal layer 2260 can be manufactured through a series of manufacturing processes.

As described above, the fan-in semiconductor package can have a package form in which all the connection pads (such as input/output (I/O) terminals) of the semiconductor chip are arranged in the semiconductor chip, and can have excellent electrical characteristics and Can be produced at low cost. Therefore, many components installed in smart phones have been manufactured in the form of fan-in semiconductor packages. In detail, many components installed in smart phones have been developed to achieve fast signal transmission and at the same time have a compact size.

However, since all input/output terminals in the fan-in semiconductor package need to be arranged inside the semiconductor chip, the fan-in semiconductor package has a large space limitation. Therefore, it is difficult to apply this structure to a semiconductor wafer having a large number of input/output terminals or a semiconductor wafer having a compact size. In addition, due to the above shortcomings, the fan The embedded semiconductor package may not be directly installed and used on the motherboard of the electronic device. Here, even in the case of increasing the size of the input/output terminals of the semiconductor chip and the interval between the input/output terminals of the semiconductor chip by the rewiring process, the size of the input/output terminals of the semiconductor chip and the size of the semiconductor chip The spacing between the input/output terminals may still be insufficient for the fan-in semiconductor package to be directly mounted on the motherboard of the electronic device.

5 is a schematic cross-sectional view showing a situation where the fan-in semiconductor package is mounted on the intermediate substrate and finally mounted on the main board of the electronic device.

6 is a schematic cross-sectional view showing a situation where the fan-in type semiconductor package is embedded in the intermediate substrate and finally mounted on the motherboard of the electronic device.

Referring to the drawings, in the fan-in semiconductor package 2200, the connection pads 2222 (that is, input/output terminals) of the semiconductor chip 2220 can be rewired via the interposer substrate 2301, and the fan-in semiconductor package 2200 can be mounted thereon It is finally mounted on the motherboard 2500 of the electronic device in the state on the intermediate substrate 2301. In this case, the solder balls 2270 and the like can be fixed by an underfill resin 2280 and the like, and the outside of the semiconductor chip 2220 can be covered with a molding material 2290 and the like. Alternatively, the fan-in semiconductor package 2200 can be embedded in a separate intermediate substrate 2302, and the connection pads 2222 (that is, input/output terminals) of the semiconductor chip 2220 can be embedded in the intermediate substrate 2302 in the fan-in semiconductor package 2200. In the middle state, rewiring is performed by the intermediate substrate 2302, and the fan-in semiconductor package 2200 can be finally mounted on the main board 2500 of the electronic device.

As mentioned above, it may be difficult to directly install and use Use fan-in semiconductor package. Therefore, the fan-in semiconductor package can be mounted on a separate intermediate substrate and then mounted on the motherboard of the electronic device by the packaging process, or the fan-in semiconductor package can be embedded in the intermediate substrate with the fan-in semiconductor package Install and use on the motherboard of the electronic device.

Fan-out semiconductor package

FIG. 7 is a schematic cross-sectional view showing a fan-out semiconductor package.

With reference to the drawings, in the fan-out semiconductor package 2100, for example, the outer side of the semiconductor chip 2120 can be protected by the encapsulant 2130, and the connection pad 2122 of the semiconductor chip 2120 can be turned toward the semiconductor chip 2120 by the connection member 2140. Rewiring outside. In this case, a passivation layer 2150 may be further formed on the connection member 2140, and a metal under bump layer 2160 may be further formed in the opening of the passivation layer 2150. A solder ball 2170 may be further formed on the under-bump metal layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121, a connection pad 2122, a passivation layer (not shown), and the like. The connection member 2140 may include an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2141, and a through hole 2143 that electrically connects the connection pad 2122 and the redistribution layer 2142 to each other.

As described above, the fan-out type semiconductor package may have a form in which the input/output terminals of the semiconductor chip are rewired by connecting members formed on the semiconductor chip and are arranged out of the semiconductor chip. As described above, in the fan-in semiconductor package, all input/output terminals of the semiconductor chip need to be arranged in the semiconductor chip. Therefore, when the size of the semiconductor chip is reduced, the size and pitch of the ball must be reduced, which may make the standardized ball layout impossible. Used in fan-in semiconductor packages. On the other hand, as described above, the fan-out type semiconductor package has a form in which the input/output terminals of the semiconductor chip are rewired by connecting members formed on the semiconductor chip and are arranged outside the semiconductor chip. Therefore, even when the size of the semiconductor chip is reduced, the standardized ball layout can still be used in the fan-out semiconductor package, so that the fan-out semiconductor package can be mounted on the motherboard of the electronic device without using a separate intermediate substrate. , As described below.

FIG. 8 is a schematic cross-sectional view showing a situation in which the fan-out semiconductor package is mounted on the motherboard of the electronic device.

Referring to the drawings, the fan-out semiconductor package 2100 can be mounted on the motherboard 2500 of the electronic device via solder balls 2170 and the like. That is, as described above, the fan-out semiconductor package 2100 includes the connection member 2140 formed on the semiconductor chip 2120 and capable of rewiring the connection pad 2122 to the fan-out area outside the semiconductor chip 2120, thereby making standardized balls The layout can still be used in the fan-out semiconductor package 2100. Therefore, the fan-out semiconductor package 2100 can be mounted on the main board 2500 of the electronic device without using a separate intermediate substrate or the like.

As described above, since the fan-out semiconductor package can be mounted on the main board of the electronic device without using a separate interposer substrate, the fan-out semiconductor package can be implemented to have a thickness smaller than that of the fan-in semiconductor package using the interposer substrate . Therefore, the fan-out semiconductor package can be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal and electrical characteristics, which makes the fan-out semiconductor package particularly suitable for mobile products. Therefore, the fan-out semiconductor package can be implemented in a more compact form than the general stacked package (POP) type using a printed circuit board (PCB). Formula, and can solve the problem of warpage (warpage) phenomenon.

Meanwhile, the fan-out semiconductor package means the packaging technology used to mount the semiconductor chip on the motherboard of an electronic device and protect the semiconductor chip from external influences as described above, and the fan-out semiconductor package is printed with, for example, an intermediate substrate. The concept of a printed circuit board (PCB) is a different concept. The printed circuit board has specifications and purposes different from those of the fan-out semiconductor package, and the fan-in semiconductor package is embedded in the printed circuit board.

Connection system for semiconductor package

FIG. 9 is a schematic cross-sectional view illustrating a connection system of a semiconductor package according to an exemplary embodiment in the present disclosure.

Referring to the drawings, the semiconductor package connection system 500 according to the exemplary embodiment of the present disclosure may include: a printed circuit board 300; a first semiconductor package 100 disposed on a first surface of the printed circuit board 300; and a second The semiconductor package 200 is disposed on the second surface of the printed circuit board 300; and the passive component 350 is disposed on the second surface of the printed circuit board 300. The first semiconductor package 100 may include an application processor (AP) 120A and a power management integrated circuit (PMIC) 120B. The application processor 120A and the power management integrated circuit 120B may be arranged side by side in the first semiconductor package 100. The second semiconductor package 200 may include a memory 220. The first semiconductor package 100 can be electrically connected to the printed circuit board 300 through the electrical connection structure 170. The second semiconductor package 200 can be electrically connected to the printed circuit board 300 through the electrical connection structure 270.

The application processor 120A and power management product of the first semiconductor package 100 The bulk circuits 120B can be electrically connected to each other through the rewiring layer in the first semiconductor package 100. For example, the output power of the power management integrated circuit 120B can be transmitted to the power input/output (I/O) of the application processor 120A through the rewiring layer. The second semiconductor package 200 including memory can be arranged on the second surface of the printed circuit board 300 opposite to the first surface on which the first semiconductor package 100 is arranged, and can be used by the circuits and through holes of the printed circuit board 300 It is electrically connected to the first semiconductor package 100 to transmit signals to and receive signals from the application processor 120A. That is, the first semiconductor package 100 and the second semiconductor package 200 may be configured to face each other with the printed circuit board 300 interposed between the first semiconductor package 100 and the second semiconductor package 200. In this case, the application processor 120 and the memory 220 may be configured to face each other with a printed circuit board 300 sandwiched between the application processor 120 and the memory 220. The output power of the power management integrated circuit 120B can also be connected to the memory 220 through the printed circuit board 300. The first semiconductor package 100 and/or the second semiconductor package 200 can also be electrically connected to the passive component 350 through the printed circuit board 300.

In the connection system 500 of the semiconductor package with such a structure, the memory 200 generally has a large number of inputs/outputs, and the second semiconductor package 200 including the memory 220 is connected to the first semiconductor package 100 through the printed circuit board 300, so The connection system 500 of the semiconductor package may not be affected by the number of inputs/outputs of the memory 220. In addition, there is no need to use a separate stacked package structure, and there is no need for a back-side heavy wiring layer or an intermediate substrate. Therefore, the connection system 500 of the semiconductor package can be thinned, and the signal path of the connection system 500 of the semiconductor package can be simplified. In addition, since the application processor 120A and the power management integrated circuit 120B are arranged side by side in one In one package 100, the power path can also be significantly shortened. Since the application processor 120A and the power management integrated circuit 120B that generate a lot of heat are arranged in one package 100, the heat and power management integrated circuit of the processor 120A The heat of 120B can be effectively dissipated at the same time by the heat dissipating member disposed on the package 100 and the like.

At the same time, the first semiconductor package 100 can be designed using a panel level package (PLP) method or a wafer level package (WLP) method as described below, and the second semiconductor package 200 can be designed at a wafer level Package (chip scale package, CSP) method, wafer level packaging method or panel level packaging method, etc. are designed.

In addition, the passive component 350 may be a multilayer ceramic capacitor (MLCC), a low inductance chip capacitor (LICC), an inductor, a bead, or various known filters. The number of passive components 350 is not particularly limited, but may be more than the number shown in the drawing or may be less than the number shown in the drawing.

In addition, the printed circuit board 300 may be a main board of an electronic device, and in some cases may be a daughter board. The printed circuit board 300 may include multiple build-up layers, multiple circuit layers, and multiple layers of through holes for electrical connection, and the multiple layers of through holes may be stacked through holes to significantly shorten the first semiconductor package 100 and The electrical path of the second semiconductor package 200 is not limited to this. In some cases, the core substrate may be configured in a printed circuit board. In addition to the above components, other components, modules, packages, etc. can also be further mounted on the printed circuit board 300. The thickness of the printed circuit board 300 may be greater than the thickness of the connecting member described below with reference to FIGS. 10A to 10D and below with reference to FIG. 11A To the thickness of another connecting member described in FIG. 11F.

10A to 10D are schematic cross-sectional views showing various examples of the first semiconductor package of the connection system of the semiconductor package of FIG. 9.

10A, the first semiconductor package 100A may include: an application processor 120A having an active surface on which a connection pad 120AP is disposed and a non-active surface opposite to the active surface; a power management integrated circuit 120B having The active surface of the connection pad 120BP and the non-active surface opposite to the active surface; the encapsulation body 130 encapsulates at least part of each of the application processor 120A and the power management integrated circuit 120B; the connection member 140 is configured On the active surface of the application processor 120A and the active surface of the power management integrated circuit 120B, and includes an insulating layer 141, a redistribution layer 142 disposed on the insulating layer 141 and a through hole 143 in the insulating layer 141; a passivation layer 150 , Arranged on the connecting member 140; the under-bump metal layer 160, arranged in the opening of the passivation layer 150, and electrically connected to the redistribution layer 142 of the connecting member 140; and the electrical connection structure 170, by under the bump The metal layer 160 is electrically connected to the redistribution layer 142 of the connection member 140. If necessary, passive components 155, such as capacitors or inductors, can be further disposed on the passivation layer 150.

Each of the application processor 120A and the power management integrated circuit 120B may be an integrated circuit (IC) that integrates hundreds to millions or more of components in a single chip. In this case, the base material of the body of each of the application processor 120A and the power management integrated circuit 120B may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. . Various circuits can be formed on the body. The corresponding connection pads 120AP and 120BP can connect the application processor 120A and power management integrated circuit The circuit 120B is electrically connected to other components. The material of each of the connection pads 120AP and 120BP may be a conductive material such as aluminum (Al). A passivation layer exposing the connection pads 120AP and 120BP may be formed on each of the bodies, and the passivation layer may be an oxide film, a nitride film, etc., or a double layer composed of an oxide layer and a nitride layer. An insulating layer or the like can be further arranged on each of other required positions, and if necessary, an insulating layer and a rewiring layer can also be formed.

The encapsulation body 130 can protect the application processor 120A and the power management integrated circuit 120B. The encapsulation form of the encapsulation body 130 is not particularly limited, and may be a form in which the encapsulation body 130 surrounds at least part of the application processor 120A and the power management integrated circuit 120B. For example, the encapsulation body 130 may cover the non-active surface and side surfaces of the application processor 120A and the power management integrated circuit 120B, and cover at least part of the active surface of the application processor 120A and the power management integrated circuit 120B. The encapsulation body 130 may include an insulating material. The insulating material may be a material containing inorganic filler and insulating resin, for example, thermosetting resin, such as epoxy resin; thermoplastic resin, such as polyimide resin; having a reinforcing material impregnated in thermosetting resin and thermoplastic resin ( For example, inorganic filler resins, such as Ajinomoto Build up Film (ABF), FR-4, or Bismaleimide Triazine (BT). In addition, known molding materials, such as epoxy molding compound (EMC), etc. may also be used. As another option, a photosensitive imaging dielectric resin on which a photolithography process can be performed can also be used as the insulating material. Alternatively, an insulating resin such as thermosetting resin or thermoplastic resin may be impregnated with inorganic filler and/or glass fiber (or glass cloth, or glass fiber). Core materials such as cloth) are used as insulating materials to control warpage or maintain rigidity.

The connection member 140 can rewire the connection pad 120AP of the application processor 120A and the connection pad 120BP of the power management integrated circuit 120B. In addition, the connection member 140 can electrically connect the connection pads 120AP and 120BP to each other. Dozens to hundreds of connection pads 120AP and 120BP with various functions can be rewired by the connection member 140, and can be physically or electrically connected to the outside by the electrical connection structure 170 depending on the function. The connection member 140 may include an insulating layer 141, a redistribution layer 142 disposed on the insulating layer 141, and a via 143 penetrating the insulating layer 141 and connected to the redistribution layer 142. The connection member 140 may be formed of a single layer, or may be formed of a plurality of layers having a larger number than shown in the drawings.

The material of each of the insulating layers 141 may be an insulating material. In this case, photosensitive insulating materials such as photosensitive imaging dielectric resins can also be used as insulating materials. That is, the insulating layer 141 may be a photosensitive insulating layer. When the insulating layer 141 has photosensitive properties, the insulating layer 141 can be formed to have a smaller thickness, and the fine pitch of the through hole 143 can be achieved more easily. The insulating layer 141 may be a photosensitive insulating layer including an insulating resin and an inorganic filler. When the insulating layer 141 has multiple layers, the materials of the insulating layer 141 may be the same as each other, and may also be different from each other if necessary. When the insulating layer 141 is a multilayer, the insulating layers 141 can be integrated with each other depending on the manufacturing process, so that the boundary between the insulating layers can also be inconspicuous.

The rewiring layer 142 can be used to substantially rewire the connection pads 120AP and 120BP, and can electrically connect the connection pads 120AP and 120BP to each other. The material of each of the redistribution layers 142 may be a conductive material, such as copper (Cu), aluminum (Al), Silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or alloys thereof. The redistribution layer 142 can perform various functions depending on the design of the corresponding layer. For example, the redistribution layer 142 may include a ground (GND) pattern, a power supply (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signals, such as data signals, other than ground (GND) patterns, power (PWR) patterns, etc. In addition, the rewiring layer 142 may include via pads, electrical connection structure pads, and the like.

The via 143 can electrically connect the redistribution layer 142, the connection pads 120AP and 120BP, etc. formed on different layers, thereby forming an electrical path in the first semiconductor package 100A. The material of each of the through holes 143 may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb) , Titanium (Ti) or its alloys. Each of the through holes 143 may be completely filled with a conductive material, or a conductive material may also be formed along the wall of each of the through holes. In addition, each of the through holes 143 may have all shapes known in the related art, such as a tapered shape, a cylindrical shape, and the like.

If necessary, the heat dissipation member 140B may be formed on the area of the connection member 140 connected to the active surface of the power management integrated circuit 120B. The heat dissipation member 140B may include a plurality of layers of heat dissipation through holes densely formed at a very short distance, but is not limited to this, and may include metal blocks or the like instead of the heat dissipation through holes. The thermal conductivity of the plurality of layers of the heat dissipation member 140B and the heat dissipation through holes or metal blocks thereof may be greater than the thermal conductivity of the insulating layer 141, and the plurality of layers and the heat dissipation through holes or the metal blocks thereof of the heat dissipation member 140B may be The same material used to form the rewiring layer 142 and the through hole 143, or Any other suitable metal or metal alloy is formed. In the case where the plurality of layers of the heat dissipation member 140B and the heat dissipation through holes or metal blocks thereof are formed of the same material used to form the rewiring layer 142 and the through holes 143, such a material included in the heat dissipation member 140B The volume and/or density of may be greater than any other continuous portion in the connecting member 140 with the same size as the heat dissipation member 140B. The layers of the heat dissipation member 140B and the heat dissipation through holes or metal blocks thereof may not be used to transmit power to the application processor 120A and the memory 220. The multiple layers of the heat dissipation member 140B and the heat dissipation through holes or metal blocks thereof may be electrically floating or electrically connected to a ground (GND) pattern. When the heat dissipation member 140B is formed, the heat of the power management integrated circuit 120B that generates a large amount of heat may be effectively transferred to the printed circuit board 300, and thus the first semiconductor package 100A may have an excellent heat dissipation effect.

The passivation layer 150 may protect the connection member 140 from external physical or chemical damage. The passivation layer 150 may have an opening exposing at least part of the redistribution layer 142 of the connection member 140. The number of openings formed in the passivation layer 150 may be tens to thousands. The passivation layer 150 may include insulating resin and inorganic filler, but may not include glass fiber. For example, the passivation layer 150 may be formed of a film made of Ajinomoto, but it is not limited to this.

The under-bump metal layer 160 can improve the connection reliability of the electrical connection structure 170 to improve the board-level reliability of the first semiconductor package 100A. The under-bump metal layer 160 may be connected to the redistribution layer 142 of the connection member 140 exposed through the opening of the passivation layer 150. The under-bump metal layer 160 can be formed in the opening of the passivation layer 150 by a known metalization method using a known conductive material (such as metal), but not Not limited to this.

The electrical connection structure 170 may be additionally configured to physically or electrically connect the first semiconductor package 100A to the outside. For example, the first semiconductor package 100A can be mounted on the printed circuit board 300 through the electrical connection structure 170. Each of the electrical connection structures 170 may be formed of conductive materials such as solder. However, this is only an example, and the material of each of the electrical connection structures 170 is not limited to this. Each of the electrical connection structures 170 may be a land, a ball, a pin, or the like. The electrical connection structure 170 may be formed as a multi-layer structure or a single-layer structure. When the electrical connection structure 170 is formed as a multilayer structure, the electrical connection structure 170 may include copper (Cu) pillars and solder. When the electrical connection structure 170 is formed as a single-layer structure, the electrical connection structure 170 may include tin-silver solder or copper (Cu). However, this is only an example, and the electrical connection structure 170 is not limited to this.

The number, interval, arrangement form, etc. of the electrical connection structures 170 are not particularly limited, but can be fully modified by those skilled in the art depending on the specific details of the design. For example, the number of electrical connection structures 170 can be set to tens to thousands according to the number of connection pads 120AP and 120BP, or can be set to tens to thousands or more, or tens to thousands. Or less.

At least one of the electrical connection structures 170 may be disposed in the fan-out area. The fan-out area is an area other than the area where the application processor 120A and the power management integrated circuit 120B are configured. Compared with the fan-in package, the fan-out package can have excellent reliability, can implement multiple input/output (I/O) terminals, and can facilitate three-dimensional (3D) interconnection. In addition, compared to ball grid array (BGA) package or connection For land grid array (LGA) packages, etc., fan-out packages can be manufactured with a small thickness and can be price competitive.

Referring to FIG. 10B, the first semiconductor package 100B may further include a core member 110 having a through hole 110H. The application processor 120A and the power management integrated circuit 120B can be arranged side by side in the through hole 110H of the core component 110. The core member 110 can improve the rigidity of the first semiconductor package 100B depending on certain materials, and can be used to ensure the thickness uniformity of the encapsulation body 130. The side surfaces of the application processor 120A and the power management integrated circuit 120B may be surrounded by the core component 110. However, this form is only an example, and various modifications can be made to have other forms, and the core component 110 can perform another function depending on this form.

The material of the core member 110 is not particularly limited. For example, an insulating material may be used as the material of the core member 110. In this case, the insulating material may be a thermosetting resin, such as epoxy resin; a thermoplastic resin, such as polyimide resin; wherein the thermosetting resin or thermoplastic resin and inorganic filler are immersed in, for example, glass fiber (or glass cloth or glass The resin in the core material such as fiber cloth), such as prepreg, Ajinomoto film, FR-4 or bismaleimide triazine, etc. As another option, photosensitive imaging dielectric resin can also be used as the insulating material. The other configurations overlap with the above-mentioned configurations, and therefore detailed descriptions thereof are omitted.

10C, in the first semiconductor package 100C, the core member 110 may include: a first insulating layer 111a contacting the connecting member 140; a first wiring layer 112a contacting the connecting member 140 and embedded in the first insulating layer 111a; and second The wiring layer 112b is arranged on the first insulating layer 111a and the first insulating layer 111a is embedded with the first wiring layer One surface of 112a is opposite to the other surface; the second insulating layer 111b is disposed on the first insulating layer 111a and covers the second wiring layer 112b; and the third wiring layer 112c is disposed on the second insulating layer 111b. The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c may be electrically connected to the connection pads 120AP and 120BP through at least the redistribution layer 142 of the connection member 140. The first wiring layer 112a and the second wiring layer 112b, and the second wiring layer 112b and the third wiring layer 112c can pass through the first through hole 113a and the second through hole 113b respectively penetrating the first insulating layer 111a and the second insulating layer 111b Electrically connected to each other.

When the first wiring layer 112a is embedded in the first insulating layer 111a, the step due to the thickness of the first wiring layer 112a may be significantly reduced, and thus the insulation distance of the connection member 140 may become constant. That is, the distance from the redistribution layer 142 of the connection member 140 to the lower surface of the first insulating layer 111a and the distance from the redistribution layer 142 of the connection member 140 to the connection pad 120AP and the connection pad 120A of the application processor 120A and the power management integrated circuit 120B The difference between the distances of 120BP may be smaller than the thickness of the first wiring layer 112a. Therefore, the high-density wiring design of the connection member 140 may be easy.

The lower surface of the first wiring layer 112a of the core component 110 may be located at a level higher than the lower surface of the connection pads 120AP and 120BP of the application processor 120A and the power management integrated circuit 120B. In addition, the distance between the redistribution 142 of the connecting member 140 and the first wiring layer 112a of the core member 110 may be greater than the redistribution layer 142 of the connecting member 140 and the connection pad 120AP and the connection pad 120A of the application processor 120A and the power management integrated circuit 120B. The distance between 120BP. Here, the first wiring layer 112a may be recessed in the first insulating layer 111a. As described above, when the first wiring layer 112a is recessed In the first insulating layer 111a, when there is a step between the lower surface of the first insulating layer 111a and the lower surface of the first wiring layer 112a, the material of the encapsulant 130 can be prevented from permeating and contaminating the first wiring layer 112a. phenomenon. The second wiring layer 112b of the core component 110 may be located at a level between the active surface and the inactive surface of the application processor 120A and the power management integrated circuit 120B. The core member 110 may be formed to have a thickness corresponding to the thickness of the application processor 120A and the power management integrated circuit 120B. Therefore, the second wiring layer 112b formed in the core component 110 can be disposed at the level between the active surface and the inactive surface of the application processor 120A and the power management integrated circuit 120B.

The thickness of the wiring layers 112a, 112b, and 112c of the core member 110 may be greater than the thickness of the redistribution layer 142 of the connection member 140. Since the thickness of the core member 110 may be equal to or greater than the thickness of the application processor 120A and the power management integrated circuit 120B, the wiring layers 112a, 112b, and 112c may be formed relatively large depending on the specifications of the core member 110. On the other hand, the redistribution layer 142 of the connection member 140 may be formed to have a size relatively smaller than that of the wiring layers 112a, 112b, and 112c to achieve thinness.

The material of each of the insulating layers 111a and 111b is not particularly limited. For example, an insulating material may be used as the material of each of the insulating layers 111a and 111b. In this case, the insulating material may be a thermosetting resin, such as epoxy resin; a thermoplastic resin, such as polyimide resin; a resin in which a thermosetting resin or a thermoplastic resin is mixed with an inorganic filler, or a thermosetting resin or a thermoplastic resin The resin and the inorganic filler are immersed in, for example, glass fiber (or glass cloth, or glass fiber Resins in core materials such as Weibu), such as prepregs, Ajinomoto film, FR-4 or bismaleimide triazine, etc. As another option, photosensitive imaging dielectric resin can also be used as the insulating material.

The wiring layers 112a, 112b, and 112c can be used to rewire the connection pads 120AP and 120BP of the application processor 120A and the power management integrated circuit 120B. The material of each of the wiring layers 112a, 112b, and 112c may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), Lead (Pb), titanium (Ti) or their alloys. The wiring layers 112a, 112b, and 112c can perform various functions depending on the design of their corresponding layers. For example, the wiring layers 112a, 112b, and 112c may include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) pattern may include various signals, such as data signals, other than ground (GND) patterns, power (PWR) patterns, etc. In addition, the wiring layers 112a, 112b, and 112c may include through-hole pads, wire pads, electrical connection structure pads, and the like.

The through holes 113a and 113b can electrically connect the wiring layers 112a, 112b, and 112c formed on different layers to each other, thereby forming electrical paths in the core component 110. The material of each of the through holes 113a and 113b may be a conductive material. Each of the through holes 113a and 113b may be completely filled with a conductive material, or the conductive material may also be formed along the wall of each of the through holes. In addition, each of the through hole 113a and the through hole 113b may have all shapes known in the related art, such as a tapered shape, a cylindrical shape, and the like. When the holes of the first through hole 113a are formed, some of the pads of the first wiring layer 112a can serve as stoppers, which can be beneficial to the manufacturing process. Let each of the first through holes 113a have a tapered shape with an upper surface width greater than a lower surface width. In this case, the first through hole 113a may be integrated with the pad pattern of the second wiring layer 112b. In addition, when the holes of the second through hole 113b are formed, some of the pads of the second wiring layer 112b can serve as termination elements, which can facilitate the manufacturing process, so that each of the second through holes 113b has a larger upper surface width than a lower surface. Conical shape with surface width. In this case, the second through hole 113b may be integrated with the pad pattern of the third wiring layer 112c. The other configurations overlap with the above-mentioned configurations, and therefore detailed descriptions thereof are omitted.

10D, in the first semiconductor package 100D, the core member 110 may include: a first insulating layer 111a; a first wiring layer 112a and a second wiring layer 112b, respectively disposed on opposite surfaces of the first insulating layer 111a; The two insulating layers 111b are arranged on the first insulating layer 111a and cover the first wiring layer 112a; the third wiring layer 112c is arranged on the second insulating layer 111b; the third insulating layer 111c is arranged on the first insulating layer 111a And cover the second wiring layer 112b; and the fourth wiring layer 112d, arranged on the third insulating layer 111c. The first wiring layer 112a, the second wiring layer 112b, the third wiring layer 112c, and the fourth wiring layer 112d may be electrically connected to the connection pads 120AP and 120BP through at least the redistribution layer 142 of the connection member 140. Since the core member 110 can include a large number of wiring layers 112a, 112b, 112c, and 112d, the connection member 140 can be further simplified. Therefore, the problem of a decrease in yield caused by defects in the process of forming the connecting member 140 can be suppressed. At the same time, the first wiring layer 112a, the second wiring layer 112b, the third wiring layer 112c, and the fourth wiring layer 112d can pass through the first insulating layer 111a, the second insulating layer 111b, and the third insulating layer 111c, respectively. A through hole 113a, a second through hole 113b, and a third through hole 113c are electrically connected to each other.

The thickness of the first insulating layer 111a may be greater than the thickness of the second insulating layer 111b and the thickness of the third insulating layer 111c. The first insulating layer 111a may be substantially relatively thick to maintain rigidity, and the second insulating layer 111b and the third insulating layer 111c may be introduced to form a larger number of wiring layers 112c and 112d. The insulating material contained in the first insulating layer 111a may be different from the insulating material of the second insulating layer 111b and the insulating material of the third insulating layer 111c. For example, the first insulating layer 111a may be, for example, a prepreg including a core material, a filler, and an insulating resin, and the second insulating layer 111b and the third insulating layer 111c may be Ajinomoto constituting films including filler and insulating resin. Or photosensitive imaging dielectric film. However, the material of the first insulating layer 111a and the materials of the second insulating layer 111b and the third insulating layer 111c are not limited to this. Similarly, the diameter of the first through hole 113a penetrating through the first insulating layer 111a may be larger than the diameter of the second through hole 113b and the third through hole 113c penetrating through the second insulating layer 111b and the third insulating layer 111c, respectively.

The lower surface of the third wiring layer 112a of the core component 110 may be located higher than the lower surface of the connection pads 120AP and 120BP of the application processor 120A and the power management integrated circuit 120B. In addition, the distance between the redistribution 142 of the connecting member 140 and the third wiring layer 112c of the core member 110 may be smaller than the redistribution layer 142 of the connecting member 140 and the connection pad 120AP and the connection pad 120A of the application processor 120A and the power management integrated circuit 120B. The distance between 120BP. Here, the third wiring layer 112c may be configured in a protruding form on the second insulating layer 111b, and a thin passivation layer may be further formed on the connection pads 120AP and 120BP of the application processor 120A and the power management integrated circuit 120B. The first wiring layer 112a and the second wiring layer of the core component 110 112b may be located at the level between the active surface and the inactive surface of the application processor 120A and the power management integrated circuit 120B. The core member 110 may be formed to have a thickness corresponding to the thickness of the application processor 120A and the power management integrated circuit 120B. Therefore, the first wiring layer 112a and the second wiring layer 112b formed in the core component 110 can be arranged at a level between the active surface and the inactive surface of the application processor 120A and the power management integrated circuit 120B.

The thickness of the wiring layers 112a, 112b, 112c, and 112d of the core member 110 may be greater than the thickness of the redistribution layer 142 of the connection member 140. Since the thickness of the core member 110 may be equal to or greater than the thickness of the application processor 120A and the power management integrated circuit 120B, the wiring layers 112a, 112b, 112c, and 112d may be formed relatively large. On the other hand, the rewiring layer 142 of the connection member 140 may be formed to have a relatively small size to achieve thinness. The other configurations overlap with the above-mentioned configurations, and therefore detailed descriptions thereof are omitted.

11A to 11F are schematic cross-sectional views showing various examples of the second semiconductor package of the connection system of the semiconductor package of FIG. 9.

11A, in the second semiconductor package 200A, a plurality of memories 221 and 222 may be stacked on the connection member 240 and may be encapsulated by the encapsulation body 230. That is, the second semiconductor package 200A may include: a connection member 240 including a redistribution layer 242 and a through hole 243; a first memory 221 is disposed on the connection member 240 and is electrically connected to the redistribution layer by a bonding wire 221W 242; The second memory 222 is configured on the first memory 221 and is electrically connected to the redistribution layer 242 by the bonding wire 222W; the encapsulation body 230 encapsulates the first memory 221 and the second memory 222 Of every At least part of one; the passivation layer 250 is disposed on the connection member 240; the under-bump metal layer 260 is formed in the opening of the passivation layer 250 and is electrically connected to the redistribution layer 242; and the electrical connection structure 270, by The under-bump metal layer 260 is electrically connected to the redistribution layer 242. The connecting member 240 may be manufactured in the form of an interposer, but is not limited to this. The other configurations overlap with the above-mentioned configurations, and therefore detailed descriptions thereof are omitted.

11B, the second semiconductor package 200B may include: a core member 210 having a through hole 210H; a first memory 221 is disposed in the through hole 210H, and has an active surface on which a first connection pad 221P is disposed and a The active surface is opposite to the non-active surface; the second memory 222 is disposed on the first memory 221 in the through hole 210H, and has an active surface on which the second connection pad 222P is disposed and a non-active surface opposite to the active surface The active surface; the encapsulation body 230 encapsulates the core member 210 and at least part of the first memory body 221 and the second memory body 222; and the connecting member 240 is disposed on the core member 210 and the first memory body 221 and the second memory The active surface of the body 222. The second semiconductor package 200B may further include: a passivation layer 250 disposed on the connection member 240; an under-bump metal layer 260 formed in the opening of the passivation layer 250 and electrically connected to the redistribution layer 242 of the connection member 240; and The electrical connection structure 270 is electrically connected to the redistribution layer 242 of the connection member 240 through the under-bump metal layer 260.

The connection member 240 may include a redistribution layer 242 electrically connected to the first connection pad 221P and the second connection pad 222P. The active surface of the second memory 222 can be attached to the inactive surface of the first memory 221, and the second memory 222 can be disposed on the first memory 221 and configured to be offset relative to the first memory 221, So that the second connection pad 222P is exposed. The phrase "configured as offset" means the first memory The side surface of the 221 and the side surface of the second memory 222 do not overlap each other so that the connection pad 222P of the second memory 222 disposed on the first memory 221 can be exposed by the first memory 221. The redistribution layer 242 of the connection member 240 may be connected to the first connection pad 221P and the second connection pad 222P through the first through hole 243a and the second through hole 243b, respectively. The second through hole 243b may be higher than the first through hole 243a.

Meanwhile, recently, a technology of stacking a plurality of memory chips in multiple stages to increase the capacity of the memory has been developed. For example, there may be a two-stage (or three-stage) stacking of multiple memory chips, mounting the stacked memory chips on an intermediate substrate, and then using a molding material to mount the stacked memory chips on the intermediate substrate. The memory chip is molded to be used in packaged form. In this case, the stacked memory chips are electrically connected to the intermediate substrate through bonding wires. However, in this structure, there is a thinness limitation due to the significant thickness of the intermediate substrate. In addition, when manufacturing an interposer substrate based on silicon, significant costs are required. In addition, when the reinforcing material for fixing the stacked memory chips is not separately included, reliability problems may occur due to warpage. In addition, since the stacked memory chips are electrically connected to the intermediate substrate by bonding wires, the input/output (I/O) is rewired, so the signal path is significantly long, and signal loss may occur frequently.

On the other hand, in the second semiconductor package 200B according to another exemplary embodiment of the present disclosure, the core member 210 may be introduced, and a plurality of stacked memories 221 and 221 may be disposed in the through hole 210H of the core member 210. 222. In addition, the connection member 240 including the rewiring layer 242 may be formed instead of introducing an interposer substrate. Specifically, the plurality of stacked memories 221 and 222 can be formed by multiples having different heights. The stepped via holes 243a and 243b are connected to the redistribution layer 242 of the connection member 240 instead of bonding wires. Therefore, the thickness of the connecting member 240 can be significantly reduced, and the thickness of the backside encapsulation or the thickness of the stacked wafer can also be significantly reduced. In addition, the signal path from the stacked memories 221 and 222 to the electrical connection structure 270 can be significantly shortened to reduce signal loss, thereby improving the electrical characteristics of the signal. In addition, the warpage can be controlled by the core member 210, and thus the reliability can be improved.

The stacked first memory 221 and the second memory 222 can be disposed in the through hole 210H of the core member 210. The core member 210 can improve the rigidity of the second semiconductor package 200B depending on certain materials, and can be used to ensure the thickness uniformity of the encapsulation body 230. The side surfaces of the stacked first memory body 221 and the second memory body 222 may be surrounded by the core member 210. However, this form is only an example, and various modifications can be made to have other forms, and the core component 210 can perform another function depending on this form.

The material of the core member 210 is not particularly limited. For example, an insulating material may be used as the material of the core member 210. In this case, the insulating material may be a thermosetting resin, such as epoxy resin; a thermoplastic resin, such as polyimide resin; wherein the thermosetting resin or thermoplastic resin and inorganic filler are immersed in, for example, glass fiber (or glass cloth or glass The resin in the core material such as fiber cloth), such as prepreg, Ajinomoto film, FR-4 or bismaleimide triazine, etc. As another option, photosensitive imaging dielectric resin can also be used as the insulating material.

The memories 221 and 222 may be integrated circuits (ICs) that integrate hundreds to millions or more of components in a single chip. The integrated circuit can be memory, such as volatile memory (such as dynamic random access memory), non-volatile memory (Such as read-only memory) or flash memory, but not limited to this. The active surfaces of the memories 221 and 222 refer to the surfaces of the memories 221 and 222 on which the connection pads 221P and 222P are arranged, and the inactive surfaces of the memories 221 and 222 refer to the active surfaces of the memories 221 and 222. surface. The memories 221 and 222 can be formed on an active wafer basis. In this case, the base material of the body of each of the memories 221 and 222 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits can be formed on the body. The connection pads 221P and 222P can electrically connect the memory 221 and 222 to other components. The material of each of the connection pads 221P and 222P may be a conductive material such as aluminum (Al). If necessary, a passivation layer exposing the connection pads 221P and 222P can be formed on each body, and the passivation layer can be an oxide film, a nitride film, etc., or a double layer composed of an oxide layer and a nitride layer. Floor. It is also possible to further dispose an insulating layer etc. in a desired position.

The memories 221 and 222 can be connected to the redistribution layer 242 of the connection member 240 through through holes 243a and 243b having different heights. In this case, the first through hole 243 a may not penetrate the encapsulation body 230, and the second through hole 243 b may penetrate the encapsulation body 230. That is, the first through hole 243a may not contact the encapsulation body 230, and the second through hole 243b may contact the encapsulation body 230. The active surface of the second memory body 222 may include: a first side portion, which faces the inactive surface of the first memory body 221; a central portion, which faces the inactive surface of the first memory body 221; and a second side portion, The central part of the active surface of the second memory body 222 is symmetrical with the first side part, and is at least partially outside the inactive surface of the first memory body 221. In this case, the second connection pad 222P can be disposed on the second side portion of the active surface of the second memory body 222. That is, the memory 221 and 222 can be configured to be offset from each other in the form of steps, and the second connection pad 222P can be configured on the second side portion of the active surface of the second memory 222, so that multi-level through holes 243a and different heights can be used. 243b.

The memories 221 and 222 can be attached to each other by the adhesive member 280. The adhesive member 280 is not particularly limited, but may be a material that can attach the memories 221 and 222 to each other, such as known tapes or adhesives. In some cases, the adhesive member 280 may also be omitted. At the same time, the configuration of the memories 221 and 222 is not limited to the form shown in the drawings. That is, the memories 221 and 222 can also be configured in a form different from that shown in the plan view, as long as the memories 221 and 222 can be configured to be offset from each other and multi-level vias 243a and 243b can be applied.

The encapsulation body 230 can protect the memories 221 and 222. The encapsulation form of the encapsulation body 230 is not particularly limited, and may be a form in which the encapsulation body 230 surrounds at least part of the memories 221 and 222. For example, the encapsulation body 230 may cover the non-active surfaces and side surfaces of the memories 221 and 222, and cover at least part of the active surfaces of the memories 221 and 222. In addition, the encapsulation body 230 may cover the core member 210 and may fill at least part of the through hole 210H. The encapsulation body 230 may include an insulating material. The insulating material may be a material containing inorganic filler and insulating resin, for example, thermosetting resin, such as epoxy resin; thermoplastic resin, such as polyimide resin; having a reinforcing material impregnated in thermosetting resin and thermoplastic resin ( Such as inorganic filler) resin, such as Ajinomoto constitution film, FR-4 or bismaleimide triazine, etc. In addition, known molding materials such as epoxy molding compounds (EMC) and the like can also be used. As another option, a photosensitive imaging dielectric resin that can be subjected to a photolithography process can also be used as the insulation. Edge material. Alternatively, a material in which insulating resin such as thermosetting resin or thermoplastic resin is impregnated in inorganic filler and/or core material such as glass fiber (or glass cloth, or glass fiber cloth) can also be used as the insulating material. Control warpage or maintain rigidity.

The connection member 240 can rewire the connection pads 221P and 222P of the memories 221 and 222. In addition, the connection member 240 can electrically connect the connection pads 221P and 222P to each other. Dozens to hundreds of connection pads 221P and 222P with various functions can be rewired by the connection member 240, and can be physically or electrically connected to the outside by the electrical connection structure 270 depending on the function. The connection member 240 may include an insulating layer 241, a redistribution layer 242 disposed on the insulating layer 241, and through holes 243a and 243b penetrating the insulating layer 241 and connected to the redistribution layer 242. The connection member 240 may be formed of a single layer, or may be formed of a plurality of layers having a larger number than shown in the drawings.

The material of each of the insulating layers 241 may be an insulating material. In this case, photosensitive insulating materials such as photosensitive imaging dielectric resins can also be used as insulating materials. That is, the insulating layer 241 may be a photosensitive insulating layer. When the insulating layer 241 has photosensitive properties, the insulating layer 241 can be formed to have a smaller thickness, and the fine pitch of the through holes 243a and 243b can be achieved more easily. The insulating layer 241 may be a photosensitive insulating layer including an insulating resin and an inorganic filler. When the insulating layer 241 has multiple layers, the materials of the insulating layer 241 may be the same as each other, and may also be different from each other if necessary. When the insulating layer 241 is a multilayer, the insulating layers 241 can be integrated with each other depending on the manufacturing process, so that the boundary between the insulating layers can also be inconspicuous.

The redistribution layer 242 can be used to substantially perform the connection pads 221P and 222P Rewiring, and can electrically connect the connection pads 221P and 222P to each other. The material of each of the redistribution layers 242 may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb) ), titanium (Ti) or its alloys. The redistribution layer 242 can perform various functions depending on the design of its corresponding layer. For example, the redistribution layer 242 may include a ground (GND) pattern, a power supply (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signals, such as data signals, other than ground (GND) patterns, power (PWR) patterns, etc. In addition, the rewiring layer 242 may include via pads, electrical connection structure pads, and the like.

The through holes 243a and the through holes 243b can electrically connect the redistribution layer 242, the connection pads 221P and 222P, etc. formed on different layers to each other, thereby forming an electrical path in the second semiconductor package 200B. The material of each of the through holes 243a and the through holes 243b may be conductive materials, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), Lead (Pb), titanium (Ti) or their alloys. Each of the through hole 243a and the through hole 243b may be completely filled with a conductive material, or the conductive material may also be formed along the wall of each of the through holes. In addition, each of the through hole 243a and the through hole 243b may have all shapes known in the related art, such as a tapered shape, a cylindrical shape, and the like.

The passivation layer 250 may protect the connection member 240 from external physical or chemical damage. The passivation layer 250 may have an opening exposing at least part of the redistribution layer 242 of the connection member 240. The number of openings formed in the passivation layer 250 may be tens to thousands. The passivation layer 250 may include insulating resin and inorganic filler, but may not include glass fiber. For example, the passivation layer 250 may be formed of a film made of Ajinomoto, but not Not limited to this.

The under-bump metal layer 260 can improve the connection reliability of the electrical connection structure 270 to improve the board-level reliability of the second semiconductor package 200B. The under-bump metal layer 260 may be connected to the redistribution layer 242 of the connection member 240 exposed through the opening of the passivation layer 250. The under-bump metal layer 260 can be formed in the opening of the passivation layer 250 using a known conductive material (such as metal) by a known metalization method, but it is not limited to this.

The electrical connection structure 270 may be additionally configured to physically or electrically connect the second semiconductor package 200B to the outside. For example, the second semiconductor package 200B can be mounted on the printed circuit board 300 by the electrical connection structure 270. Each of the electrical connection structures 270 may be formed of conductive materials such as solder. However, this is only an example, and the material of each of the electrical connection structures 270 is not limited to this. Each of the electrical connection structures 270 can be a pin, a ball, a pin, or the like. The electrical connection structure 270 may be formed as a multi-layer structure or a single-layer structure. When the electrical connection structure 270 is formed as a multilayer structure, the electrical connection structure 270 may include copper pillars and solder. When the electrical connection structure 270 is formed as a single-layer structure, the electrical connection structure 270 may include tin-silver solder or copper (Cu). However, this is only an example, and the electrical connection structure 270 is not limited to this.

The number, interval, arrangement form, etc. of the electrical connection structures 270 are not particularly limited, but can be fully modified by those skilled in the art depending on the specific details of the design. For example, the number of electrical connection structures 270 can be set to tens to thousands according to the number of connection pads 221P and 222P, or can be set to tens to thousands or more, or tens to thousands. Or less.

At least one of the electrical connection structures 270 may be disposed in the fan-out area. The fan-out area is an area other than the area where the memories 221 and 222 are disposed. Compared with the fan-in package, the fan-out package can have excellent reliability, can implement multiple input/output (I/O) terminals, and can facilitate three-dimensional (3D) interconnection. In addition, compared to a ball grid array (BGA) package or a pin grid array (LGA) package, etc., the fan-out package can be manufactured with a small thickness and can be price competitive. The other configurations overlap with the above-mentioned configurations, and therefore detailed descriptions thereof are omitted.

11C, in the second semiconductor package 200C, the core member 210 may include: a first insulating layer 211a contacting the connecting member 240; a first wiring layer 212a contacting the connecting member 240 and embedded in the first insulating layer 211a; and second The wiring layer 212b is disposed on the other surface of the first insulating layer 211a opposite to the surface of the first insulating layer 211a embedded with the first wiring layer 212a; the second insulating layer 211b is disposed on the first insulating layer 211a It covers the second wiring layer 212b; and the third wiring layer 212c, which is disposed on the second insulating layer 211b. The first wiring layer 212a, the second wiring layer 212b, and the third wiring layer 212c may be electrically connected to the connection pads 221P and 222P through at least the redistribution layer 242 of the connection member 240. The first wiring layer 212a and the second wiring layer 212b, and the second wiring layer 212b and the third wiring layer 212c can pass through the first through hole 213a and the second through hole 213b respectively penetrating the first insulating layer 211a and the second insulating layer 211b Electrically connected to each other.

When the first wiring layer 212a is embedded in the first insulating layer 211a, the step due to the thickness of the first wiring layer 212a may be significantly reduced, and thus the insulation distance of the connection member 240 may become constant. That is, the weight of the self-connecting member 240 The difference between the distance between the wire layer 242 and the lower surface of the first insulating layer 211a and the distance from the redistribution layer 242 of the connection member 240 to the connection pad 221P of the memory 221 may be smaller than the thickness of the first wiring layer 212a. Therefore, the high-density wiring design of the connection member 240 may be easy.

The lower surface of the first wiring layer 212 a of the core member 210 may be arranged at a level higher than the lower surface of the connection pad 221P of the memory 221. In addition, the distance between the redistribution layer 242 of the connection member 240 and the first wiring layer 212a of the core member 210 may be greater than the distance between the redistribution layer 242 of the connection member 240 and the connection pad 221P of the memory 221. Here, the first wiring layer 212a may be recessed in the first insulating layer 211a. As described above, when the first wiring layer 212a is recessed in the first insulating layer 211a, so that there is a step between the lower surface of the first insulating layer 211a and the lower surface of the first wiring layer 212a, the encapsulation body 230 can be prevented The phenomenon that the material infiltrates and contaminates the first wiring layer 212a.

The thickness of the wiring layers 212a, 212b, and 212c of the core member 210 may be greater than the thickness of the redistribution layer 242 of the connection member 240. Since the thickness of the core member 210 may be equal to or greater than the thickness of the memories 221 and 222, the wiring layers 212a, 212b, and 212c may be formed relatively large depending on the specifications of the core member 210. On the other hand, the redistribution layer 242 of the connection member 240 may be formed to have a size relatively smaller than that of the wiring layers 212a, 212b, and 212c to achieve thinness.

The material of each of the insulating layers 211a and 211b is not particularly limited. For example, an insulating material may be used as the material of each of the insulating layers 211a and 211b. In this case, the insulating material may be a thermosetting resin, for example Such as epoxy resin; thermoplastic resin, such as polyimide resin; resin in which thermosetting resin or thermoplastic resin and inorganic filler are mixed or thermosetting resin or thermoplastic resin and inorganic filler are immersed in, for example, glass fiber (or glass cloth, Or glass fiber cloth) and other core materials such as resin, such as prepreg, Ajinomoto film, FR-4 or bismaleimide triazine, etc. As another option, photosensitive imaging dielectric resin can also be used as the insulating material.

The wiring layers 212a, 212b, and 212c can be used to rewire the connection pads 221P and 222P of the memories 221 and 222. The material of each of the wiring layers 212a, 212b, and 212c may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), Lead (Pb), titanium (Ti) or their alloys. The wiring layers 212a, 212b, and 212c can perform various functions depending on the design of their corresponding layers. For example, the wiring layers 212a, 212b, and 212c may include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) pattern may include various signals, such as data signals, other than ground (GND) patterns, power (PWR) patterns, etc. In addition, the wiring layers 212a, 212b, and 212c may include through-hole pads, wire bonding pads, electrical connection structure pads, and the like.

The through holes 213a and 213b can electrically connect the wiring layers 212a, 212b, and 212c formed on different layers to each other, thereby forming electrical vias in the core component 210. The material of each of the through holes 213a and 213b may be a conductive material. Each of the through holes 213a and the through holes 213b may be completely filled with a conductive material, or the conductive material may also be formed along the wall of each of the through holes. In addition, each of the through hole 213a and the through hole 213b may have all shapes known in the related art, such as a tapered shape. Shape, cylindrical shape, etc. When the holes of the first through holes 213a are formed, some of the pads of the first wiring layer 212a can serve as terminating elements, which can facilitate the manufacturing process, so that each of the first through holes 213a has an upper surface width greater than a lower surface width Cone shape. In this case, the first through hole 213a may be integrated with the pad pattern of the second wiring layer 212b. In addition, when the holes of the second through holes 213b are formed, some of the pads of the second wiring layer 212b can serve as terminating elements, which may facilitate the manufacturing process, so that each of the second through holes 213b has an upper surface width larger than a lower surface. Conical shape with surface width. In this case, the second through hole 213b may be integrated with the pad pattern of the third wiring layer 212c. The other configurations overlap with the above-mentioned configurations, and therefore detailed descriptions thereof are omitted.

11D, in the second semiconductor package 200D, the core member 210 may include: a first insulating layer 211a; a first wiring layer 212a and a second wiring layer 212b, respectively disposed on opposite surfaces of the first insulating layer 211a; The second insulating layer 211b is disposed on the first insulating layer 211a and covers the first wiring layer 212a; the third wiring layer 212c is disposed on the second insulating layer 211b; the third insulating layer 211c is disposed on the first insulating layer 211a It covers the second wiring layer 212b; and the fourth wiring layer 212d, which is disposed on the third insulating layer 211c. The first wiring layer 212a, the second wiring layer 212b, the third wiring layer 212c, and the fourth wiring layer 212d may be electrically connected to the connection pads 221P and 222P through at least the redistribution layer 242 of the connection member 240. Since the core member 210 can include a large number of wiring layers 212a, 212b, 212c, and 212d, the connection member 240 can be further simplified. Therefore, the problem of a decrease in yield caused by defects in the process of forming the connecting member 240 can be suppressed. At the same time, the first wiring layer 212a, the second wiring layer 212b, the third wiring layer 212c, and the fourth wiring layer 212d can The first through holes 213a, the second through holes 213b, and the third through holes 213c that penetrate the first insulating layer 211a, the second insulating layer 211b, and the third insulating layer 211c are electrically connected to each other.

The thickness of the first insulating layer 211a may be greater than the thickness of the second insulating layer 211b and the thickness of the third insulating layer 211c. The first insulating layer 211a may be substantially relatively thick to maintain rigidity, and the second insulating layer 211b and the third insulating layer 211c may be introduced to form a larger number of wiring layers 212c and 212d. The insulating material included in the first insulating layer 211a may be different from the insulating materials of the second insulating layer 211b and the third insulating layer 211c. For example, the first insulating layer 211a may be, for example, a prepreg including a core material, a filler, and an insulating resin, and the second insulating layer 211b and the third insulating layer 211c may be Ajinomoto constituent films including a filler and an insulating resin. Or photosensitive imaging dielectric film. However, the material of the first insulating layer 211a and the materials of the second insulating layer 211b and the third insulating layer 211c are not limited to this. Similarly, the diameter of the first through hole 213a penetrating the first insulating layer 211a may be larger than the diameter of the second through hole 213b and the third through hole 213c penetrating the second insulating layer 211b and the third insulating layer 211c, respectively.

The lower surface of the third wiring layer 212c of the core member 210 may be arranged at a level lower than the lower surface of the connection pad 222P of the memory 222. In addition, the distance between the redistribution 242 of the connection member 240 and the third wiring layer 212c of the core member 210 may be greater than the distance between the redistribution layer 242 of the connection member 240 and the connection pads 221P and 222P of the memories 221 and 222. Here, the third wiring layer 212c may be configured in a protruding form on the second insulating layer 211b, while a thin passivation layer may be further formed on the connection pad 221P of the memory 221.

The thickness of the wiring layers 212a, 212b, 212c, and 212d of the core member 210 The degree may be greater than the thickness of the redistribution layer 242 of the connection member 240. Since the thickness of the core member 210 may be equal to or greater than the thickness of the memories 221 and 222, the wiring layers 212a, 212b, 212c, and 212d may be formed to be relatively large. On the other hand, the redistribution layer 242 of the connection member 240 may be formed to have a relatively low thickness. The other configurations overlap with the above-mentioned configurations, and therefore detailed descriptions thereof are omitted.

Referring to FIG. 11E, unlike the second semiconductor package 200B shown in FIG. 11B, in the second semiconductor package 200E, the horizontal cross-sectional area of the second memory body 222 may be greater than that of the first memory body 221. That is, the active surface of the second memory 222 may be wider than the inactive surface of the first memory 221. In this case, the active surface of the second memory body 222 may include: a first side portion at least partially outside the inactive surface of the first memory body 221; a central portion facing the non-active surface of the first memory body 221 Active surface; and a second side portion, the central portion is symmetrical with the first side portion, and at least partially outside the inactive surface of the first memory 221, and the second connection pad 222P can be configured on the second memory 222 On both the first side portion and the second side portion of the active surface. That is, the memories 221 and 222 can be configured to be offset from each other in a form where the memories 221 and 222 have different horizontal cross-sectional areas, and the second connection pad 222P can be arranged on the active surface of the second memory 222 On the first side portion and on the second side portion, so that multi-step through holes 243a and 243b can be applied. The other configurations overlap with the above-mentioned configurations, and therefore detailed descriptions thereof are omitted. Meanwhile, the core component 210 shown in FIGS. 11C and 11D can also be used in the second semiconductor package 200E.

11F, unlike the second semiconductor package 200B shown in FIG. 11B, the second semiconductor package 200F may further include: a third memory 223, and a first memory 221 is arranged side by side in the through hole 210H, and has an active surface on which the third connection pad 223P is arranged and an inactive surface opposite to the active surface; and a fourth memory 224 arranged in the through hole 210H. 223, and has an active surface on which the fourth connection pad 224P is disposed and an inactive surface opposite to the active surface. The active surface of the fourth memory body 224 can be attached to the inactive surface of the third memory body 223, and the fourth memory body 224 can be arranged on the third memory body 223 in a step form relative to the third memory body 223 Offset so that the fourth connection pad 224P is exposed. The redistribution layer 242 of the connection member 240 may be connected to the third connection pad 223P and the fourth connection pad 224P through the first through hole 243a and the second through hole 243b, respectively. Even in a structure in which the memories 221, 222, 223, and 224 are connected to each other in a two-level parallel structure, multi-level through holes 243a and 243b can be applied. The first memory body 221 and the second memory body 222 and the third memory body 223 and the fourth memory body 224 may be connected to each other by a first adhesive member 280a and a second adhesive member 280b, respectively. The other configurations overlap with the above-mentioned configurations, and therefore detailed descriptions thereof are omitted. Meanwhile, the core component 210 shown in FIGS. 11C and 11D can also be used in the second semiconductor package 200F.

12A and 12B are schematic cross-sectional views showing various examples of the printed circuit board of the connection system of the semiconductor package of FIG. 9.

12A, the printed circuit board 300A may have a form of a coreless substrate 320, and passivation layers 330 and 340 are formed on the opposite surfaces of the coreless substrate 320, respectively. In more detail, the printed circuit board 300A may have a form in which the passivation layers 330 and 340 are respectively formed on the opposite surfaces of the coreless substrate 320. The coreless substrate 320 includes an insulating layer 321, a plurality of circuit layers 322, and a plurality of through holes. Layer 323, insulating layer 321 It is formed by stacking a plurality of build-up layers, the plurality of circuit layers 322 are formed on the respective build-up layers, and the plurality of via layers 323 penetrate the respective build-up layers to connect the circuit layers 322 to each other. The material of each of the build-up layers of the insulating layer 321 may be a known insulating material such as epoxy resin or polyimide and an inorganic filler, and the material of each of the circuit layer 322 and the via layer 323 may be For example, known conductive materials such as copper (Cu). The material of each of the passivation layers 330 and 340 may be solder resist or the like. However, the materials of the build-up layer, the circuit layer 322 and the via layer 323, and the passivation layers 330 and 340 are not limited to this. If necessary, various components can be embedded in the printed circuit board 300A.

12B, the printed circuit board 300B may have the form of a core substrate, wherein the accumulation members 320a and 320b are respectively disposed on the opposite surfaces of the core member 310, and the passivation layers 330 and 340 are respectively disposed on the accumulation members 320a and 320b. The core member 310 may include a core layer 311, a circuit layer 312 formed on opposite surfaces of the core layer 311, and a through wiring 313 penetrating the core layer 311. Each of the build-up members 320a and 320b may include build-up layers 321a and 321b, circuit layers 322a and 322b formed on build-up layers 321a and 321b, respectively, and via layers 323a and 323b penetrating through build-up layers 321a and 321b, respectively. It is also possible to form a larger number of layers. The core layer 311 may be introduced by a copper clad laminate (CCL) or the like, and may be formed of a prepreg or the like, but is not limited to this. The other configurations overlap with the above-mentioned configurations, and therefore detailed descriptions thereof are omitted.

FIG. 13 is a schematic cross-sectional view showing several effects of the connection system of the semiconductor package according to the layout of the present disclosure.

With reference to the drawings, the semiconductor device according to the exemplary embodiment in this disclosure In the connection system 500A of the bulk package, the memory 220 of the second semiconductor package 200F is disposed directly under the application processor 120A of the first semiconductor package 100B relative to the printed circuit board 300A, and therefore the transmission path of the signal S can be significantly shortened Moreover, the application processor 120A and the power management integrated circuit 120B of the first semiconductor package 100B are packaged side by side in one package 100B, and therefore the transmission path of the power P can be optimized. For example, the power P can be transmitted from the power management integrated circuit 120B to the application processor 120A via the path in the connecting member of the first semiconductor package 100B instead of via the path of the printed circuit board 300A, so as to shorten the self-power management product. The power transmission path from the body circuit 120B to the application processor 120A, thereby reducing the power used in the power transmission. In addition, the known resin layer 610 can be used to attach the shielding cover 620 to the first semiconductor package 100B including the application processor 120A that generates a lot of heat and the power management integrated circuit 120B, and for example, can be configured with metal blocks or heat sinks. The heat sink 630 such as a tube is placed on the shield 620 to effectively dissipate the heat of the application processor 120A and the power management integrated circuit 120B that generate a large amount of heat at the same time. In addition, the passive component 360 and the second semiconductor package 200F can be arranged on the same surface of the printed circuit board 300A.

14 is a schematic cross-sectional view showing related problems of the connection system of a semiconductor package that does not follow the layout of the present disclosure.

With reference to the drawings, in the semiconductor package connection system 400 not in accordance with the present disclosure, the memory package 430 may be arranged on the application processor package 410 in the form of a stacked package and between the memory package 430 and the application processor package 410 An interposer 420 is sandwiched, and this stacked package structure can be disposed on one of the printed circuit boards 440 On the surface. In addition, the power management integrated circuit package 450 and the passive component 460 can be disposed on the other surface of the printed circuit board 440. In this structure, the application processor and the power management integrated circuit are far away from each other, so a complicated heat dissipation structure is required, and the transmission path of the signal S and the power P is extended.

As described above, according to the exemplary embodiments of the present disclosure, a semiconductor package connection system can be provided, in which an application processor and a memory can be connected to each other through a short path without using a separate interposer or a back-side rewiring layer , And can configure the power management integrated circuit under the best design situation.

Although exemplary embodiments have been shown and described above, it will be obvious to those skilled in the art that modifications can be made without departing from the scope of the invention defined by the scope of the appended application And variants.

100‧‧‧Semiconductor Package/First Semiconductor Package

120A‧‧‧Application Processor

120B‧‧‧Power Management Integrated Circuit

170‧‧‧Electrical connection structure

200‧‧‧Second semiconductor package

220‧‧‧Memory

270‧‧‧Electrical connection structure

300‧‧‧Printed Circuit Board

350‧‧‧Passive Components

500‧‧‧Connecting system

Claims (24)

A connection system for a semiconductor package includes: a printed circuit board having a first surface and a second surface opposite to the first surface; a first semiconductor package arranged on the first surface of the printed circuit board, And is connected to the printed circuit board by a first electrical connection structure; and a second semiconductor package is disposed on the second surface of the printed circuit board and is connected to the printed circuit board by a second electrical connection structure The printed circuit board, wherein the first semiconductor package includes: an application processor (AP) and a power management integrated circuit (PMIC), the application processor and the power management integrated circuit are arranged side by side and each have the above configuration An active surface with connection pads and an inactive surface opposite to the active surface; an encapsulation body that encapsulates at least part of each of the application processor and the power management integrated circuit Connection member, the connection member is configured on the active surface of the application processor and the active surface of the power management integrated circuit, and the connection member includes the application processor and the The rewiring layer in which the corresponding connection pads of the power management integrated circuit are electrically connected to each other; and the first electrical connection structure, and the connection member is configured with the application processor And on the opposite surface of the power management integrated circuit, and electrically connect the redistribution layer to the printed circuit board, and The second semiconductor package includes memory. The connection system of the semiconductor package according to claim 1, wherein the first semiconductor package and the second semiconductor package are arranged to face each other and the first semiconductor package and the second semiconductor package The printed circuit board is sandwiched between. The connection system of the semiconductor package according to claim 1, wherein the application processor and the memory are arranged to face each other, and the application processor and the memory are sandwiched述printed circuit board. The connection system of the semiconductor package according to claim 1, wherein the first semiconductor package further includes a core member having a through hole, and the application processor and the power management integrated circuit are arranged side by side in The through hole. The connection system of the semiconductor package according to the claim 4, wherein the core member includes: a first insulating layer, the first insulating layer contacts the connection member; a first wiring layer, the first wiring Layer in contact with the connecting member and embedded in the first insulating layer; and a second wiring layer disposed on the first insulating layer and embedded in the first insulating layer One surface of a wiring layer is on the opposite surface, and the first wiring layer and the second wiring layer are electrically connected to the corresponding connection pads of the application processor and the power management integrated circuit . According to the semiconductor package connection system described in claim 5, the core member further includes: a second insulating layer, the second insulating layer being disposed on the first insulating layer and covering the second insulating layer Wiring layer; and a third wiring layer, the third wiring layer is disposed on the second insulating layer, and the third wiring layer is electrically connected to the application processor and the power management integrated circuit Corresponding to the connection pad. The connection system of the semiconductor package according to claim 4, wherein the core member includes a first insulating layer and a first wiring layer and a second wiring layer respectively disposed on opposite surfaces of the first insulating layer , And the first wiring layer and the second wiring layer are electrically connected to the corresponding connection pads of the application processor and the power management integrated circuit. According to the semiconductor package connection system described in claim 7, wherein the core component further includes: a second insulating layer, the second insulating layer being disposed on the first insulating layer and covering the first insulating layer A wiring layer; a third wiring layer, the third wiring layer is disposed on the second insulating layer; a third insulating layer, the third insulating layer is disposed on the first insulating layer and covering the second Wiring layer; and a fourth wiring layer, the fourth wiring layer is disposed on the third insulating layer, and the third wiring layer and the fourth wiring layer are electrically connected to the application processor and the The corresponding connection pad of the power management integrated circuit. The connection system of the semiconductor package as described in the scope of patent application 1, wherein the connection member of the first semiconductor package includes a heat dissipation member. The connection system of the semiconductor package according to claim 1, wherein the first semiconductor package includes an integrated body configured with the application processor and the power management unit disposed on the connection member and the connection member A passive component on the opposite surface of the circuit on the other surface. The connection system of the semiconductor package according to claim 1, wherein power is transmitted from the power management integrated circuit via the connection member of the first semiconductor package, not via the printed circuit board, to the The processor is applied, and the power management integrated circuit is transmitted to the memory at least through the printed circuit board. The connection system of the semiconductor package according to claim 1, wherein the second semiconductor package includes: a connection member, the connection member includes a redistribution layer; a first memory, the first memory is arranged in The connecting member is electrically connected to the redistribution layer; a second memory, the second memory is disposed on the first memory and is electrically connected to the redistribution layer; an encapsulation body , The encapsulating body encapsulates at least part of the first memory and the second memory; and the second electrical connection structure, the second electrical connection structure being disposed on the connecting member The first memory and the second memory are configured with the connecting member One surface of the body is on the opposite surface, and the redistribution layer is electrically connected to the printed circuit board. According to the connection system of the semiconductor package described in claim 12, the first memory and the second memory are respectively connected to the redistribution layer by bonding wires. The connection system of the semiconductor package according to the 12th patent application, wherein the first memory and the second memory are connected to the redistribution layer through vias. The connection system of the semiconductor package according to claim 12, wherein the second semiconductor package further includes a core member having a through hole, and the first memory and the second memory are arranged in the Through hole. The connection system of the semiconductor package according to the 15th patent application, wherein the core member includes: a first insulating layer, the first insulating layer contacts the connection member; a first wiring layer, the first wiring Layer in contact with the connecting member and embedded in the first insulating layer; and a second wiring layer disposed on the first insulating layer and embedded in the first insulating layer One surface of a wiring layer is on the opposite surface, and the first wiring layer and the second wiring layer are electrically connected to the first memory and the second memory. The connection system of the semiconductor package as described in item 16 of the scope of patent application System, wherein the core member further includes: a second insulating layer disposed on the first insulating layer and covering the second wiring layer; and a third wiring layer, the third wiring The layer is configured on the second insulating layer, and the third wiring layer is electrically connected to the first memory and the second memory. The connection system of the semiconductor package according to the 15th patent application, wherein the core member includes a first insulating layer and a first wiring layer and a second wiring layer respectively disposed on opposite surfaces of the first insulating layer , And the first wiring layer and the second wiring layer are electrically connected to the first memory and the second memory. The semiconductor package connection system according to the 18th patent application, wherein the core component further includes: a second insulating layer, the second insulating layer being disposed on the first insulating layer and covering the first insulating layer A wiring layer; a third wiring layer, the third wiring layer is disposed on the second insulating layer; a third insulating layer, the third insulating layer is disposed on the first insulating layer and covering the second A wiring layer; and a fourth wiring layer, the fourth wiring layer is disposed on the third insulating layer, and the third wiring layer and the fourth wiring layer are electrically connected to the first memory and The second memory. The connection system of the semiconductor package as described in item 1 of the scope of patent application The system further includes a plurality of passive components arranged on the second surface of the printed circuit board. As described in the first item of the scope of patent application, the semiconductor package connection system further includes a heat sink covering the application processor and the power management integrated circuit. A connection system for a semiconductor package includes: a printed circuit board having a first surface and a second surface opposite to the first surface; a first semiconductor package arranged on the first surface of the printed circuit board, And includes a first connecting member, a first semiconductor chip and a power management integrated circuit (PMIC) arranged side by side along the first surface; and a second semiconductor package, arranged on the second surface of the printed circuit board , And includes a second semiconductor chip, wherein the pads of the first semiconductor chip and the power management integrated circuit and the pads of the second semiconductor chip face the printed circuit board, and the power management integrated circuit The circuit and the pads of the first semiconductor chip are electrically connected to each other by at least the rewiring layer of the first connection member, and the power management integrated circuit and the pads of the second semiconductor chip are electrically connected to each other. The pads are electrically connected to each other by at least the printed circuit board, wherein the second semiconductor package includes: a second connecting member, the second connecting member having the pad electrically connected to the second semiconductor chip The rewiring layer; A second encapsulating body, the second encapsulating body encapsulating at least a part of the second semiconductor chip; and a second electrical connection structure, the second electrical connection structure connecting all of the second connection member The rewiring layer is electrically connected to the printed circuit board. The connection system of the semiconductor package according to the 22nd patent application, wherein the first semiconductor package includes: a first encapsulation body encapsulating the first semiconductor chip and the power supply Managing at least part of each of the integrated circuits; and a first electrical connection structure that electrically connects the redistribution layer of the first connection member to the printed circuit board. The connection system of the semiconductor package according to claim 22, wherein the second semiconductor chip is in the direction along which the second semiconductor package, the printed circuit board, and the first semiconductor package are stacked Overlap with the first semiconductor wafer.

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