TWI705574B - Solar cell structure and method of manufacturing the same - Google Patents

Abstract

A solar cell structure includes a semiconductor substrate, a passivation layer, a tunneling layer and a doped crystalline silicon layer. The semiconductor substrate has opposite first side and second side. The passivation layer is at the first side of the semiconductor substrate. The tunneling layer is at the second side of the semiconductor substrate. The doped crystalline silicon layer is at the side of the tunneling layer far away from the semiconductor substrate. The doped crystalline silicon layer includes polysilicon crystals, and the crystallinity of the doped crystalline silicon layer is about 50% to 90%.

Description

Solar cell structure and manufacturing method thereof

The invention relates to a solar cell structure and a manufacturing method thereof, and particularly a solar cell structure with polycrystalline silicon crystals and a manufacturing method thereof.

In the semiconductor-related industries, passivation structures and processes are indispensable and important structures and processes. Take the solar cell industry as an example. Traditional back surface field (BSF) solar cells, Passivated emitter and rear cell (PERC) solar cells, heterojunction with intrinsic thin layer ; HIT) solar cells, or tunnel oxide passivated contact (tunnel oxide passivated contact; TOPcon) solar cells, etc. all have a passivation layer. For example, the doped crystalline silicon layer used in the high-efficiency silicon-based solar cell structure is produced by a high-temperature process, which affects the quality of the tunnel layer and reduces product performance and yield.

One object of the present invention is to provide a solar cell structure, which has a higher metaphorical open circuit voltage than the conventional solar cell structure (implied open-circuit voltage) and carrier life cycle, so that the overall performance is improved. Another object of the present invention is to provide a manufacturing method of the solar cell structure.

According to the above objective, the present invention provides a solar cell structure, which includes a semiconductor substrate, a passivation layer, a tunneling layer and a doped crystalline silicon layer. The semiconductor substrate has opposite first and second sides. The passivation layer is located on the first side of the semiconductor substrate. The tunneling layer is located on the second side of the semiconductor substrate. The doped crystalline silicon layer is located on the side of the tunneling layer far away from the semiconductor substrate. It contains polycrystalline silicon crystals and has a crystallinity of 50% to 90%.

According to an embodiment of the present invention, the doped crystalline silicon layer includes a first doped crystalline silicon layer and a second doped crystalline silicon layer stacked on each other, and the first doped crystalline silicon layer is located between the tunnel layer and the Between the second doped crystalline silicon layers, and the doping concentration of the second doped crystalline silicon layer is greater than that of the first doped crystalline silicon layer.

According to another embodiment of the present invention, the doping concentration of the first doped crystalline silicon layer is about 10 ¹³ / cm ^ 3 to 10 ¹⁷ / cm ^ 3, and the doping concentration of the second doped crystalline silicon layer The impurity concentration is about 10 ¹⁷ /cm ^ 3 to 10 ²¹ /cm ^ 3.

According to another embodiment of the present invention, the thickness of each of the first doped crystalline silicon layer and the second doped crystalline silicon layer is about 10 nanometers (nm) to 50 nanometers.

According to another embodiment of the present invention, the material of the passivation layer is aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, silicon nitride, or a combination of the foregoing.

According to another embodiment of the present invention, the thickness of the tunnel layer is about 0.1 nanometers to 3 nanometers.

According to another embodiment of the present invention, the thickness of the doped crystalline silicon layer is about 20 nanometers to 100 nanometers.

According to the above objective, the present invention further provides a method for fabricating a solar cell structure, which includes: providing a semiconductor substrate; forming a tunnel layer on the first side of the semiconductor substrate through high temperature oxidation or chemical vapor deposition; In the process, a doped crystalline silicon layer is formed on the side of the tunneling layer away from the semiconductor substrate, which contains polysilicon crystals and has a crystallinity of 50%~90%; and by the second deposition process, the semiconductor substrate is opposite to The second side of the first side forms a passivation layer.

According to another embodiment of the present invention, forming the doped crystalline silicon layer on the side of the tunneling layer away from the semiconductor substrate includes: forming a first doping on the side of the tunneling layer away from the semiconductor substrate The doping concentration of the crystalline silicon layer is about 10 ¹³ /cm ^3 to 10 ¹⁷ /cm ^ 3; and the second doping crystal is formed on the side of the first doped crystalline silicon layer away from the tunnel layer The doping concentration of the silicon layer is about 10 ¹⁷ /cm ^ 3 to 10 ²¹ /cm ^ 3.

According to another embodiment of the present invention, the above-mentioned first deposition process includes forming a first doped crystalline silicon layer and a second doped crystalline silicon layer, wherein the process gas of the second doped crystalline silicon layer is relative to the first doped crystalline silicon layer. The process gas of the sub-doped crystalline silicon layer increases the reaction gas of the dopant.

100‧‧‧Solar cell structure

102‧‧‧Semiconductor substrate

102A‧‧‧First side

102B‧‧‧Second side

104‧‧‧Tunnel layer

106‧‧‧Doped crystalline silicon layer

106A‧‧‧First doped crystalline silicon layer

106B‧‧‧Second doping of crystalline silicon layer

108、110‧‧‧Passivation layer

112‧‧‧Anti-reflective layer

114、116‧‧‧electrode layer

300‧‧‧Method

S302, S304, S306, S308‧‧‧Step

T ₁₀₆ , T _106A , T _106B ‧‧‧Thickness

In order to fully understand the embodiments and their advantages, now refer to the following description in conjunction with the accompanying drawings, in which: [FIG. 1] is a cross-sectional view of the solar cell structure of an embodiment of the present invention; [FIG. 2] is a partial cross-sectional view of the solar cell structure of [FIG. 1]; and [FIG. 3] is a flowchart of a method of manufacturing a solar cell structure according to an embodiment of the present invention.

The embodiments of the present invention are discussed in detail below. However, it is understandable that the embodiments provide many applicable inventive concepts, which can be implemented in various specific contents. The specific embodiments discussed are for illustration only, and are not intended to limit the scope of the invention.

It can be understood that although terms such as "first" and "second" may be used herein to describe various elements, parts, regions, and/or parts, these terms should not limit these elements, parts, regions, and / Or part. These terms are only used to distinguish one element, part, region and/or part from another element, part, region and/or part.

The terms used in this text are only for describing specific embodiments and not for limiting the scope of patent applications. Unless otherwise restricted, the term "one" or "the" in the singular form can also be used to indicate the plural form. In addition, the use of the terms of spatial relativity is to describe the different orientations of the components during use or operation, and is not limited to the directions shown in the drawings. Elements can also be oriented in other ways (rotated by 90 degrees or in other directions), and the spatial relativity description used here can also be interpreted in the same way.

Please refer to FIG. 1, which is a cross-sectional view of a solar cell structure 100 according to an embodiment of the present invention. As shown in FIG. 1, the solar cell structure 100 is a tunnel oxide passivated contact (tunnel oxide passivated contact; TOPcon) solar cell structure, and it includes a semiconductor substrate 102, a tunneling layer 104, a doped crystalline silicon layer 106, a passivation layer 108, 110, an anti-reflection layer 112, and an electrode layer 114, 116.

According to the application of the solar cell structure 100, the semiconductor substrate 102 may be an N-type doped crystalline silicon substrate or a P-type doped crystalline silicon substrate. The tunneling layer 104 is surface-treated on the first side 102A of the semiconductor substrate 102 by a radio frequency plasma equipment, and the tunneling layer 104 is formed on the first side 102A of the semiconductor substrate 102. The tunnel layer 104 may be a silicon oxide film, the thickness of which may be about 0.1 nanometer (nm) to 3 nanometers, and the defect density may be substantially lower than 10 ¹¹ /cm². The doped crystalline silicon layer 106 is located on the side of the tunnel layer 104 away from the semiconductor substrate 102. The doped crystalline silicon layer 106 may include monocrystalline silicon crystals and/or polycrystalline silicon crystals, and its thickness T ₁₀₆ may be about 20 nanometers to 100 nanometers, and its crystallinity may be about 50% to 90% to reduce contact with the electrode The interface resistance between the layers 114 and avoid damage to the tunnel layer 104. In addition, corresponding to the type of the semiconductor substrate 102, the doped crystalline silicon layer 106 may be an N-type doped crystalline silicon layer or a P-type doped crystalline silicon layer. For example, if the semiconductor substrate 102 is an N-type doped crystalline silicon substrate, the doped crystalline silicon layer 106 may be an N+ type doped crystalline silicon layer.

The passivation layers 108 and 110 and the anti-reflection layer 112 are sequentially stacked on the second side 102B of the semiconductor substrate 102. The material of each passivation layer 108, 110 can be aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, silicon nitride, a combination of the foregoing, or other suitable materials. For example, the passivation layers 108 and 110 may be an aluminum oxide layer and a silicon oxide layer, respectively. The material of the anti-reflective layer 112 can be silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, titanium oxide, a combination of the above, or other suitable materials.

The electrode layers 114, 116 are respectively located on the side of the doped crystalline silicon layer 106 away from the tunneling layer 104 and the second side 102A of the semiconductor substrate 102, wherein the electrode layer 116 extends upward and penetrates the passivation layers 108, 110 and the anti-reflection layer 112 . The material of the electrode layers 114 and 116 may be silver, copper, aluminum, a combination of the above, or other suitable metals or conductive materials. In some embodiments, the electrode layer 114 is a transparent conductive oxide layer, and its material may be indium tin oxide (ITO), indium zinc oxide (IZO) or other suitable transparent conductive materials.

FIG. 2 is a partial cross-sectional view of the solar cell structure 100 of FIG. 1. As shown in FIG. 2, the doped crystalline silicon layer 106 includes a first doped crystalline silicon layer 106A and a second doped crystalline silicon layer 106B stacked on top of each other, wherein the first doped crystalline silicon layer 106A is located in the tunnel layer The side of 104 is away from the semiconductor substrate 102, and the second doped crystalline silicon layer 106B is on the side of the first doped crystalline silicon layer 106A away from the tunnel layer 104. Taking the implementation of the semiconductor substrate 102 as an N-type doped crystalline silicon substrate as an example, the first doped crystalline silicon layer 106A and the second doped crystalline silicon layer 106B may both be formed of polycrystalline silicon and have N-type dopants, such as phosphorus. , Arsenic, antimony and/or other similar dopants. The doping concentration of the second doped crystalline silicon layer 106B is greater than the doping concentration of the first doped crystalline silicon layer 106A. Since the first doped crystalline silicon layer 106A is adjacent to the tunneling layer 104, the first doped crystalline silicon layer 106A with a lower doping concentration can prevent the dopants from diffusing into the tunneling layer 104, thus improving the penetration The reliability of the tunnel layer 104. In addition, the second doped crystalline silicon layer 106B is adjacent to the electrode layer 114, so that the second doped crystalline silicon layer 106B with a higher doping concentration can increase the effect of ohmic contact with the electrode layer 114 . In some embodiments, the doping concentration of the first doped crystalline silicon layer 106A is about 10 ¹³ /cm ^ 3 to 10 ¹⁷ /cm ^ 3. The doping concentration of the second doped crystalline silicon layer 106B is about 10 ¹⁷ /cm ^ 3 to 10 ²¹ /cm ^ 3. In addition, in some embodiments, the thicknesses T _106A and T _{106B of} the first doped crystalline silicon layer 106A and the second doped crystalline silicon layer 106B are about 10 nm to 50 nm, respectively. The thickness T _106A and the thickness T _106B may be the same or different. The definition of the first doped crystalline silicon layer 106A and the second doped crystalline silicon layer 106B can be determined by the amount of doping concentration. In one embodiment, in the graph of the relationship between the doped crystalline silicon layer 106 and the doping concentration, the doped crystalline silicon layer 106 is on the x-axis coordinate. The left side is adjacent to the tunnel layer 104, and the right side is adjacent to the electrode layer 114. The impurity concentration is on the y-axis coordinate. The interface between the first doped crystalline silicon layer 106A and the second doped crystalline silicon layer 106B is located at the position corresponding to the intermediate doping concentration in the interval where the doping concentration changes the most.

In some embodiments, the doped crystalline silicon layer 106 may have three or more sub-doped crystalline silicon layers, and the doping concentration relationship of these sub-doped crystalline silicon layers may be stepwise, farther away The direction of the tunnel layer 104 decreases. The thickness of these sub-doped crystalline silicon layers can be the same or different from each other. In other embodiments, the doped crystalline silicon layer 106 may have a continuous doping concentration change, and its doping concentration may gradually decrease in the direction away from the tunneling layer 104; near the junction with the tunneling layer 104 The doping concentration of the surface is about 10 ¹³ / cm ^ 3 to 10 ¹⁷ / cm ^ 3, and the doping concentration near the interface with the conductive layer 114 is about 10 ¹⁷ / cm ^ 3 to 10 ²¹ / cm ^ 3 .

Compared with the conventional solar cell structure, the implied open-circuit voltage of the solar cell structure of the present invention It can reach more than 700 millivolts (mV), and its carrier lifetime can be increased to more than 1600 microseconds, so the overall performance can be increased by at least 5%. In addition, the solar cell structure of the present invention can also increase the photoelectric conversion efficiency of the tunnel oxide passivation contact solar cell structure to more than 24%.

3 is a flowchart of a method 300 for manufacturing a solar cell structure according to an embodiment of the present invention. For the convenience of description, the following description of the steps of the method 300 is based on the formation of the solar cell structure 100 of FIGS. 1 and 2 as an example, but the present invention is not limited to this, and it can also be used to form other solar cell structures or similar semiconductors. structure.

In the method 300, step S302 is first performed to provide the semiconductor substrate 102. According to various design requirements, the semiconductor substrate 102 may be a P-type doped crystalline silicon substrate or an N-type doped crystalline silicon substrate.

Next, step S304 is performed to form a tunnel layer 104 on the first side 102A of the semiconductor substrate 102. The tunneling layer 104 can use high temperature oxidation or chemical vapor deposition. In one embodiment, the tunnel layer 104 is formed by chemical vapor deposition using radio frequency plasma equipment. If the semiconductor substrate 102 provided is a silicon substrate, and the process gas introduced by the RF plasma equipment is oxygen, ozone or other gases composed of oxygen atoms, the plasma oxygen ions will break bonds with the surface of the semiconductor substrate 102 The silicon atoms are combined into silicon oxide, thereby forming a silicon oxide film (ie, tunnel layer 104). The thickness of the silicon oxide film formed by the radio frequency plasma equipment can be about 0.1 nm to 3 nm, and the defect density can be substantially lower than 10 ¹¹ /cm².

After that, step S306 is performed to form a doped crystalline silicon layer 106 on the side of the tunnel layer 104 away from the semiconductor substrate 102. The doped crystalline silicon layer 106 may be formed on the tunnel layer 104 by performing a chemical vapor deposition (CVD) process, such as a plasma enhanced chemical vapor deposition (PECVD) process, which The thickness can be about 20 nanometers to 100 nanometers. In the chemical vapor deposition process for forming the doped crystalline silicon layer 106, the process pressure can be about 400 Torr, the RF power can be about 30 milliwatts/cm² (mW/cm ² ), and the semiconductor substrate 102 The temperature can be about 300 degrees Celsius. The doped crystalline silicon layer 106 may include single crystal silicon crystal or polycrystalline silicon crystal. After the chemical vapor deposition process is completed, an annealing process can be followed to form polysilicon crystals in the doped crystalline silicon layer 106, and the crystallinity of the doped crystalline silicon layer 106 is about 50% to 90%. In addition, corresponding to the type of the semiconductor substrate 102, the doped crystalline silicon layer 106 may be an N-type doped crystalline silicon layer or a P-type doped crystalline silicon layer. For example, if the semiconductor substrate 102 is an N-type doped crystalline silicon substrate, the doped crystalline silicon layer 106 may be an N+ type doped crystalline silicon layer.

Further, the formed doped crystalline silicon layer 106 includes a first doped crystalline silicon layer 106A and a second doped crystalline silicon layer 106B stacked on top of each other, wherein the first doped crystalline silicon layer 106A is located in the tunnel layer 104 The side away from the semiconductor substrate 102, and the second doped crystalline silicon layer 106B is located on the side away from the tunnel layer 104 of the first doped crystalline silicon layer 106A. Taking the semiconductor substrate 102 implemented as an N-type doped crystalline silicon substrate as an example, the first doped crystalline silicon layer 106A and the second doped crystalline silicon layer 106B may both have polysilicon crystals and both have N-type dopants, for example Phosphorus, arsenic, antimony and/or other similar dopants. During the formation of the first doped crystalline silicon layer 106A, the process gas used in the chemical vapor deposition process can be silyl methane and hydrogen, and during the formation of the second doped crystalline silicon layer 106B, the chemical gas is used In addition to silyl methane and hydrogen, the process gas of the phase deposition process is a reaction gas that adds dopants, such as phosphine. The doping concentration of the first doped crystalline silicon layer 106A is greater than the doping concentration of the second doped crystalline silicon layer 106B. In some embodiments, the doping concentration of the first doping crystalline silicon layer 106A is about 10 ¹⁷ /cm ^ 3 to 10 ²¹ /cm ^ 3, and the doping concentration of the second doping crystalline silicon layer 106B is about It ranges from 10 ¹³ pieces/cm ^3 to 10 ¹⁷ pieces/cm ^3. By controlling the time of the chemical vapor deposition process, the thickness of the first doped crystalline silicon layer 106A and the second doped crystalline silicon layer 106B can be about 10 nm to 50 nm.

In some embodiments, the formed doped crystalline silicon layer 106 may have three or more sub-doped crystalline silicon layers, and the chemical vapor deposition process for forming the sub-doped crystalline silicon layer may be adjusted by For the process gas, the doping concentration relationship of the sub-doped crystalline silicon layer may decrease gradually in the direction away from the tunnel layer 104. In other embodiments, by appropriately controlling the chemical vapor deposition process, the formed doped crystalline silicon layer 106 can have a continuous doping concentration change, and its doping concentration can gradually move away from the tunnel layer 104. Decrease in direction.

After the doped crystalline silicon layer 106 is formed, step S308 is then performed to form a passivation layer 108 on the second side 102B of the semiconductor substrate 102 (that is, the side of the semiconductor substrate 102 away from the tunnel layer 104). The passivation layer 108 can be performed by a chemical vapor deposition process, a physical vapor deposition (PVD) process, or an atomic layer deposition (atomic layer deposition) process. The deposition; ALD) process is formed on the semiconductor substrate 102. The material of the passivation layer 108 may be aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, silicon nitride, a combination of the above, or other suitable materials.

After step S308 is completed, the subsequent corresponding steps can be performed according to the type of semiconductor structure. Taking the solar cell structure 100 as an example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process can be followed to form a passivation layer 110 on the passivation layer 108. Similarly, the passivation layer 110 may be formed of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, silicon nitride, a combination of the above, or other suitable materials. After that, a deposition process or a coating process is performed to form an anti-reflection layer 112 on the passivation layer 110. The anti-reflective layer 112 may be formed of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, titanium oxide, a combination of the above, or other suitable materials. Then, an evaporation, sputtering or electroplating process is performed to form electrode layers 114 and 116 on the doped crystalline silicon layer 106 and the second side 102B of the semiconductor substrate 102, respectively. Before forming the electrode layer 116, an etching process may be performed to form notches on the passivation layers 108, 110 and the anti-reflection layer 112, and then the electrode layer 116 is formed in the notches. The electrode layers 114 and 116 may be formed of silver, copper, aluminum, a combination of the above, or other metals or conductive materials. In other embodiments, the electrode layers 114 and 116 can also be formed by screen printing.

In some embodiments, if the electrode layer 114 is formed of a metal material, a doped silicon film and a metal material film may be sequentially formed on the side of the tunnel layer 104 away from the semiconductor substrate, and then an annealing process may be performed. To form the doped crystalline silicon layer 106 and the metal layer 114 at the same time.

The advantage of the method of fabricating the solar cell structure of the embodiment of the present invention is at least that by controlling the doping concentration in the doped crystalline silicon layer, it can avoid The quality of the tunnel-free layer is affected by the high-temperature manufacturing process, thereby ensuring product performance and yield.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100‧‧‧Solar cell structure

102‧‧‧Semiconductor substrate

102A‧‧‧First side

102B‧‧‧Second side

104‧‧‧Tunnel layer

106‧‧‧Doped crystalline silicon layer

108、110‧‧‧Passivation layer

112‧‧‧Anti-reflective layer

114、116‧‧‧electrode layer

T ₁₀₆ ‧‧‧Thickness

Claims (9)

A solar cell structure includes: a semiconductor substrate having a first side and a second side opposite to each other; a passivation layer located on the first side of the semiconductor substrate; a tunnel layer located on the second side of the semiconductor substrate And a doped crystalline silicon layer located on the side of the tunneling layer away from the semiconductor substrate, the doped crystalline silicon layer includes polycrystalline silicon crystals, and the crystallinity of the doped crystalline silicon layer is 50% to 90%, And the thickness of the doped crystalline silicon layer is about 20 nanometers to 100 nanometers. According to the solar cell structure described in claim 1, wherein the doped crystalline silicon layer includes a first doped crystalline silicon layer and a second doped crystalline silicon layer stacked on each other, the first doped crystalline silicon layer The heterocrystalline silicon layer is located between the tunneling layer and the second doped crystalline silicon layer, and the doping concentration of the second doped crystalline silicon layer is greater than that of the first doped crystalline silicon layer . For the solar cell structure described in item 2 of the scope of patent application, the doping concentration of the first doped crystalline silicon layer is about 10 ¹³ /cm ^ 3 to 10 ¹⁷ /cm ^ 3, and the second doping The doping concentration of the heterocrystalline silicon layer is about 10 ¹⁷ /cm ^ 3 to 10 ²¹ /cm ^ 3. The solar cell structure according to the second item of the patent application, wherein the thickness of each of the first doped crystalline silicon layer and the second doped crystalline silicon layer is about 10 nanometers (nm) to 50 Nano. According to the solar cell structure described in item 1 of the scope of patent application, the material of the passivation layer is aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, silicon nitride or a combination of the above. According to the solar cell structure described in claim 1, wherein the thickness of the tunneling layer is about 0.1 nanometer to 3 nanometers. A method for manufacturing a solar cell structure includes: providing a semiconductor substrate; forming a tunnel layer on a first side of the semiconductor substrate through high-temperature oxidation or chemical vapor deposition; and using a first deposition process in the A doped crystalline silicon layer is formed on the side of the tunneling layer away from the semiconductor substrate, wherein the doped crystalline silicon layer includes polycrystalline silicon crystals, the crystallinity of the doped crystalline silicon layer is 50%~90%, and the doping The thickness of the crystalline silicon layer is about 20 nanometers to 100 nanometers; and a passivation layer is formed on a second side of the semiconductor substrate opposite to the first side by a second deposition process. According to the method of claim 7, wherein forming the doped crystalline silicon layer on the side of the tunneling layer away from the semiconductor substrate includes: forming a layer on the side of the tunneling layer away from the semiconductor substrate Doping the crystalline silicon layer for the first time, wherein the doping concentration of the first doping crystalline silicon layer is about 10 ¹³ /cm ^ 3 to 10 ¹⁷ /cm ^ 3; and in the first doping of the crystalline silicon layer A second doped crystalline silicon layer is formed on the side away from the tunneling layer, wherein the doping concentration of the second doped crystalline silicon layer is about 10 ¹⁷ /cm ^ 3 to 10 ²¹ /cm ^ 3. The method according to claim 7, wherein the first deposition process includes forming a first doped crystalline silicon layer and a second doped crystalline silicon layer, wherein the second doped crystalline silicon layer Compared with the process gas of the first doping of the crystalline silicon layer, the process gas increases the reaction gas of the dopant.

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