CN112133769A - Solar cell and method for manufacturing same - Google Patents
Solar cell and method for manufacturing same Download PDFInfo
- Publication number
- CN112133769A CN112133769A CN201910549523.4A CN201910549523A CN112133769A CN 112133769 A CN112133769 A CN 112133769A CN 201910549523 A CN201910549523 A CN 201910549523A CN 112133769 A CN112133769 A CN 112133769A
- Authority
- CN
- China
- Prior art keywords
- layer
- silicon substrate
- doped polysilicon
- metal layer
- solar cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 119
- 239000002184 metal Substances 0.000 claims abstract description 119
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 114
- 229920005591 polysilicon Polymers 0.000 claims abstract description 79
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 78
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 77
- 239000010703 silicon Substances 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 27
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 27
- 230000005641 tunneling Effects 0.000 claims abstract description 26
- 229910017052 cobalt Inorganic materials 0.000 claims abstract description 17
- 239000010941 cobalt Substances 0.000 claims abstract description 17
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims abstract description 17
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical group [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910021334 nickel silicide Inorganic materials 0.000 claims abstract description 6
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 5
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 5
- 238000000137 annealing Methods 0.000 claims description 31
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 14
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- 239000010937 tungsten Substances 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- 239000011135 tin Substances 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 4
- 229910052725 zinc Inorganic materials 0.000 claims description 4
- 239000011701 zinc Substances 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims description 3
- 229910021478 group 5 element Inorganic materials 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 190
- 239000010408 film Substances 0.000 description 19
- 238000011282 treatment Methods 0.000 description 15
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- -1 deposition time Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
- H01L31/0264—Inorganic materials
- H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
- H01L31/0288—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/074—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a heterojunction with an element of Group IV of the Periodic Table, e.g. ITO/Si, GaAs/Si or CdTe/Si solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Sustainable Development (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Energy (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Photovoltaic Devices (AREA)
Abstract
The application discloses a solar cell and a method of manufacturing the same. The solar cell includes a silicon substrate; the tunneling layer is formed on one side surface of the silicon substrate; the doped polycrystalline silicon layer is formed on the surface of one side, away from the silicon substrate, of the tunneling layer and forms a heterojunction with the silicon substrate; and a gate line electrode; the grid line electrode comprises a first grid line electrode formed on the doped polycrystalline silicon layer and an upper second grid line electrode formed on the doped polycrystalline silicon layer or the silicon substrate; the gate line electrode includes: a first metal layer directly formed on the doped polysilicon layer or the silicon substrate; and a second metal layer formed on the first metal layer; forming metal silicide at the interface between the first metal layer and the doped polysilicon layer or the silicon substrate; the metal silicide is nickel silicide, cobalt silicide, titanium silicide or tungsten silicide. The application reduces the production cost of the solar cell and improves the photoelectric conversion efficiency of the solar cell.
Description
Technical Field
The invention relates to the field of photovoltaics, in particular to the field of photovoltaic power generation, and particularly relates to a solar cell and a manufacturing method thereof.
Background
The crystalline silicon solar cell is the highest solar cell in the market at present due to high energy conversion efficiency.
The existing crystalline silicon solar cell has low photoelectric conversion rate and is difficult to reduce the production cost.
Disclosure of Invention
In view of the above-mentioned drawbacks and deficiencies of the prior art, it is desirable to provide a solar cell with high photoelectric conversion efficiency and low production cost and a method for manufacturing the same.
In a first aspect, the solar cell of the present invention comprises:
a silicon substrate;
the tunneling layer is formed on one side surface of the silicon substrate;
the doped polycrystalline silicon layer is formed on the surface of one side, away from the silicon substrate, of the tunneling layer and forms a heterojunction with the silicon substrate;
and a gate line electrode;
the grid line electrode comprises a first grid line electrode formed on the doped polycrystalline silicon layer and a second grid line electrode formed on the doped polycrystalline silicon layer or the silicon substrate;
the gate line electrode includes:
a first metal layer directly formed on the doped polysilicon layer or the silicon substrate; the first metal layer contains at least one of nickel, cobalt, titanium and tungsten;
and a second metal layer formed on the first metal layer;
forming a metal silicide at an interface between the first metal layer and the doped polysilicon layer or the silicon substrate; the metal silicide is nickel silicide, cobalt silicide, titanium silicide or tungsten silicide.
Optionally, the second metal layer is any one or a combination of copper, cobalt, tungsten, tin or zinc.
Optionally, the second metal layer is a composite layer, and the second metal layer has a stack structure formed by two or three layers of different metals.
Optionally, the tunneling layer is a doped dielectric layer; the doping elements in the doped dielectric layer are group III and/or group V elements.
Optionally, the thickness of the first metal layer is less than 2 microns.
Optionally, the doped polysilicon layer includes a plurality of n-type doped polysilicon regions and a plurality of p-type doped polysilicon regions, and the n-type doped polysilicon regions are electrically isolated from the adjacent p-type doped polysilicon regions; the first grid line electrode corresponds to the n-type doped polycrystalline silicon region; the second grid line electrode corresponds to the p-type doped polycrystalline silicon region.
Optionally, the n-type doped polysilicon region and the adjacent p-type doped polysilicon region are electrically isolated by a trench or an intrinsic polysilicon.
Optionally, a first dielectric layer is formed on a side of the doped polysilicon layer facing away from the silicon substrate, a first opening region is disposed on a position of the first dielectric layer opposite to the n-type doped polysilicon region and the p-type doped polysilicon region to expose the doped polysilicon layer, and the first metal layer is formed in the first opening region.
Optionally, the doped polycrystalline silicon layer is an n-type doped polycrystalline silicon layer, and the silicon substrate is a p-type monocrystalline silicon substrate; the second gate line electrode is formed on the silicon substrate.
Optionally, a region of the silicon substrate corresponding to the second gate line electrode is a p + + region.
Optionally, a region except for the p + + region on a surface of the silicon substrate on a side close to the second gate line electrode is set as a p + region.
In a second aspect, the present invention provides a method for manufacturing a solar cell, comprising the steps of:
forming a tunneling layer on a silicon substrate;
forming a doped polysilicon layer on the tunneling layer;
forming a first metal layer on part of the surface of the doped polycrystalline silicon layer;
forming a second metal layer on the first metal layer;
and annealing the first metal layer to form a metal silicide at the interface between the first metal layer and the doped polysilicon layer.
Optionally, the number of times of annealing is more than one.
Optionally, the temperature of the annealing treatment is 300-.
Optionally, the number of annealing times is two, and the temperature of the subsequent annealing treatment is higher than that of the previous annealing treatment.
According to the technical scheme provided by the embodiment of the application, the expensive TCO (Transparent Conductive Oxide) and Conductive silver paste are replaced by the low-cost metal layer, the production cost of the solar cell is reduced, the doped polycrystalline silicon layer and the silicon substrate form a heterojunction structure, the photoelectric conversion efficiency of the solar cell is improved, and the problems of high production cost and low photoelectric conversion efficiency of the existing solar cell can be solved.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
fig. 1 is a schematic structural diagram of a solar cell without a contact layer and a second metal layer according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a solar cell according to an embodiment of the present invention;
fig. 3 is a schematic structural view of a solar cell according to another embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a solar cell without a contact layer and a second metal layer according to yet another embodiment of the present invention;
fig. 5 is a schematic structural view of a solar cell according to yet another embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a solar cell without a contact layer and a second metal layer according to yet another embodiment of the present invention;
fig. 7 is a schematic structural diagram of a solar cell provided with a p + + region and a p + region according to still another embodiment of the present invention.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
Referring to fig. 1 to 7, one embodiment of the present invention is a solar cell, including:
a silicon substrate 10;
a tunneling layer 50 formed on one side surface of the silicon substrate 10;
the doped polycrystalline silicon layer 20 is formed on the surface of one side of the tunneling layer 50, which is far away from the silicon substrate 10, and forms a heterojunction with the silicon substrate 10;
and a gate line electrode; the gate line electrode includes a first gate line electrode formed on the doped polysilicon layer 20 and an upper second gate line electrode formed on the doped polysilicon layer 20 or the silicon substrate 10;
the gate line electrode includes:
a first metal layer 30 directly formed on the doped polysilicon layer 20 or the silicon substrate 10; the first metal layer 30 contains at least one of nickel, cobalt, titanium, and tungsten;
and a second metal layer 40, the second metal layer 40 formed on the first metal layer 30;
forming a metal silicide at the interface between the first metal layer 30 and the doped polysilicon layer 20 or the silicon substrate 10; the metal silicide is nickel silicide, cobalt silicide, titanium silicide or tungsten silicide.
It should be noted that the first grid line electrode is one of the positive electrode and the negative electrode of the solar cell, and the second grid line electrode is the other of the positive electrode and the negative electrode. That is, when the first gate line electrode is a positive electrode, the second gate line electrode is a negative electrode; when the first grid line electrode is a negative electrode, the second grid line electrode is a positive electrode.
According to the solar cell, the doped polycrystalline silicon layer 20 and the silicon substrate 10 form a heterojunction structure, the photoelectric conversion efficiency of the solar cell is improved, expensive TCO and conductive silver paste are replaced by the low-cost metal layer, and the production cost of the solar cell is reduced.
Metal atoms (e.g., nickel, cobalt, titanium, tungsten) in the first metal layer 30 diffuse into the doped polysilicon layer 20 or the silicon substrate 10, reacting with the silicon atoms therein to form a metal silicide concentrated at the interface of the first metal layer 30 and the doped polysilicon layer 20 or the silicon substrate 10. The formation of the metal silicide facilitates ohmic contact between the first metal layer 30 and the doped polysilicon layer 20 or the silicon substrate 10, and facilitates reduction of contact resistance and series resistance of the photovoltaic device.
When the first metal layer is nickel, the metal silicide is nickel silicide; when the first metal layer is cobalt, the metal silicide is cobalt silicide; when the first metal layer is titanium, the metal silicide is titanium silicide; when the first metal layer is tungsten, the metal silicide is tungsten silicide.
Further, the thickness of the first metal layer 30 is less than 2 μm. This is beneficial to maintaining good ohmic contact and also helps to reduce the overall resistance of the electrode grid line.
Further, the second metal layer 40 is any one or a combination of copper, cobalt, tungsten, tin or zinc.
Further, the second metal layer 40 is a composite layer, and the second metal layer 40 is a stack structure formed by two or three layers of different metals.
In the invention, the second metal layer can be a single layer of copper, silver, cobalt, tungsten, tin or zinc, or can be a stacked layer of copper/silver, cobalt/copper/silver, and the like, so that the usage amount of silver can be reduced, even silver is not used, and the production cost of the solar cell is reduced.
The first metal layer is formed in a manner including, but not limited to, the following: a first metal layer can be deposited on the doped polycrystalline silicon layer or the silicon substrate 10, annealing treatment is carried out, and metal silicide is formed on the part of the contact interface of the doped polycrystalline silicon layer or the silicon substrate and the first metal layer; or coating a first metal layer on the doped polycrystalline silicon layer or the silicon substrate, activating the first metal layer and annealing the first metal layer to enable the first metal layer and the doped polycrystalline silicon layer or the silicon substrate to react at an interface to generate metal silicide.
The second metal layer is formed in a manner including, but not limited to, the following: the conductive paste may be printed on the first metal layer and sintered to form a second metal layer; the second metal layer may also be formed by low temperature deposition on the surface of the first metal layer. The low-temperature deposition mode comprises sputtering, physical vapor deposition, chemical vapor deposition or atomic layer deposition.
The silicon substrate may be a monocrystalline silicon wafer or a polycrystalline silicon wafer. The silicon substrate may be either p-type or n-type. The doped polysilicon layer 20 may be either p-type or n-type; when the cell is an IBC cell (as is the case in fig. 1-3), the doped polysilicon layer 20 is divided into a p-type region and an n-type region. When the electrodes of the cell are on both sides (as is the case in fig. 4-7), the silicon substrate is doped opposite to the doped polysilicon layer.
Further, the tunneling layer 50 is a doped dielectric layer, and the doped elements in the doped dielectric layer are group iii and/or group v elements. The tunneling layer 50 is a doped dielectric layer, and quantum tunneling points are formed by doping, so that transition of electrons and current transmission are facilitated, and short-circuit current and open-circuit voltage are improved; meanwhile, the method is beneficial to simplifying the process, and extra mask manufacturing or process flow is not needed.
In an embodiment of the present invention, the dielectric matrix in the tunneling layer is silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, silicon carbide or amorphous silicon. The thickness of the tunneling layer is preferably 1-5 nm.
In another embodiment, the tunneling layer is a compound film having an elemental concentration gradient configuration, such as the tunneling layer being oxygen-rich on a side proximate to the silicon substrate and nitrogen or aluminum-rich on a side distal from the silicon substrate. Can be controlled by adjusting the parameters of the deposition parameter group, such as the flow ratio of different gases, deposition time, atmosphere, electric power and the like.
The tunneling layer may be grown as a thin oxide film using chemical oxidation or thermal oxidation. The tunneling layer may also be deposited using PECVD or ALD to form a thin film of oxide, nitride, carbide, oxynitride or oxycarbide, such as aluminum oxide, aluminum nitride, aluminum oxynitride, and the like.
Referring to fig. 1-3, in one embodiment, the solar cell is an IBC cell, the doped polysilicon layer 20 includes a plurality of n-type doped polysilicon regions 21 and a plurality of p-type doped polysilicon regions 22, and the n-type doped polysilicon regions 21 are electrically isolated from adjacent p-type doped polysilicon regions 22; the first grid electrode corresponds to the n-type doped polysilicon region 21; the second gate electrode corresponds to the p-doped polysilicon region 22.
Further, the n-type doped polysilicon region 21 and the adjacent p-type doped polysilicon region 22 are electrically isolated by a trench or intrinsic polysilicon.
In particular, referring to fig. 2, the n-type doped polysilicon region 21 is electrically isolated from the adjacent p-type doped polysilicon region 22 by a trench. The grooves may be implemented by laser grooving or the like.
Referring to fig. 3, n-type doped polysilicon region 21 is electrically isolated from adjacent p-type doped polysilicon region 22 by intrinsic polysilicon. Under the condition of electrical isolation through intrinsic polycrystalline silicon, a polycrystalline silicon layer can be deposited firstly, and then p-type doping is carried out on a part of region to form a p-type doped polycrystalline silicon region; carrying out n-type doping on the other part of the region to form an n-type doped polycrystalline silicon region; the part between the p-type doped polycrystalline silicon region and the n-type doped polycrystalline silicon region is not doped, namely the intrinsic polycrystalline silicon state is kept, and then the electrical isolation through the intrinsic polycrystalline silicon is realized.
Referring to fig. 1-3, a first dielectric layer 60 is formed on a side of the doped polysilicon layer 20 opposite to the silicon substrate 10, a first open film region 61 is disposed on the first dielectric layer 60 opposite to the n-type doped polysilicon region 21 and the p-type doped polysilicon region 22 to expose the doped polysilicon layer 20, and a first metal layer 30 is formed on the first open film region 61.
The first dielectric layer is a passivation layer. The first dielectric layer may be a silicon oxide layer having a thickness of 1-10 nm; the first dielectric layer may also be a silicon oxide layer and a stack of layers such as a silicon nitride layer or an aluminum oxide layer or both disposed on the silicon oxide layer. The first dielectric layer may also be a combined stack layer including any one or more of a silicon nitride layer, a silicon oxide layer, an aluminum oxide layer, silicon carbide, silicon oxynitride, aluminum nitride, aluminum oxynitride, and silicon carbonitride. The first open film region may be formed by patterning the first dielectric layer, wherein the patterning may be laser machining or chemical etching, and the doped polysilicon layer is exposed from the first open film region to facilitate electrical contact in the first open film region.
Referring to fig. 4 and 5, another embodiment of the present invention is that, unlike fig. 1-3, positive and negative electrodes are respectively located on both sides of the solar cell, i.e., one of the positive and negative electrodes is on the light-facing side of the solar cell and the other is on the backlight side of the solar cell.
Further preferably, the doped polysilicon layer 20 is an n-type doped polysilicon layer, the silicon substrate 10 is a p-type monocrystalline silicon substrate, and the second gate line electrode is formed on the silicon substrate 10. The doped polysilicon layer is disposed on the back side of the cell to form an emitter region, and the doped polysilicon layer 20 forms a heterojunction structure with the silicon substrate 10.
Further, the doping concentration of the doped polysilicon layer is preferably 1 × 1019～5×1021cm-3。
For convenience of description, the first metal layer in electrical contact with the silicon substrate 10 is named a front side first metal layer 31, and the first metal layer in electrical contact with the doped polysilicon layer 20 is named a back side first metal layer 32. Similarly, the second metal layer 40 on the front first metal layer 31 is named a front second metal layer 41, and the second metal layer 40 on the back first metal layer 32 is named a back second metal layer 42.
A front dielectric layer 64 is formed on one side of the silicon substrate 10 opposite to the doped polysilicon layer 20, the front dielectric layer 64 is provided with a front open film region 65, the silicon substrate 10 is exposed from the front open film region 65, and the front first metal layer 31 and the front second metal layer 41 are formed in the front open film region 65.
A back side dielectric layer 66 is formed on a side of the doped polysilicon layer 20 opposite to the silicon substrate 10, the back side dielectric layer 66 is provided with a back side open film region 67, the doped polysilicon layer 20 is exposed from the back side open film region 67, and the back side first metal layer 32 and the back side second metal layer 42 are formed in the back side open film region 67.
And patterning the front dielectric layer to form a front film opening area, and patterning the back dielectric layer to form a back film opening area, wherein the patterning can be laser processing or chemical etching. The doped polycrystalline silicon layer is exposed from the back film opening area, so that a contact layer is formed in the back film opening area conveniently. The silicon substrate is exposed from the front surface film opening area, so that a contact layer is formed on the front surface film opening area conveniently. The front dielectric layer and the back dielectric layer comprise any one or a combination lamination of a plurality of silicon nitride layers, silicon oxide layers, aluminum oxide layers, silicon carbide, silicon oxynitride, aluminum nitride, aluminum oxynitride and silicon carbonitride.
Referring to fig. 6-7, on the basis of fig. 4-5, further, the region of the silicon substrate 10 corresponding to the second gate line electrode is a p + + region 11. The region of the silicon substrate corresponding to the second grid line electrode is heavily doped, so that the carrier recombination of the region corresponding to the second grid line electrode can be reduced.
In an embodiment of the present invention, the doping concentration of the p + + region is preferably 1019～1021cm-3。
Further, a region on the surface of the silicon substrate 10 on the side close to the second gate line electrode, excluding the p + + region 11, is set as a p + region 12. I.e. the silicon substrate 10 is lightly doped except for the p + + region 11. Thus, a front surface field can be formed on the silicon substrate, and the efficiency of the solar cell can be effectively improved.
The invention also provides a manufacturing method of the solar cell, which comprises the following steps:
forming a tunneling layer on a silicon substrate;
forming a doped polysilicon layer on the tunneling layer;
forming a first metal layer on part of the surface of the doped polycrystalline silicon layer;
forming a second metal layer on the first metal layer;
and annealing the first metal layer to form metal silicide at the interface between the first metal layer and the doped polysilicon layer.
Further, the temperature of the annealing treatment is 300-600 ℃.
In an embodiment of the present invention, the first metal layer is nickel, and the first annealing treatment is performed as an example: the annealing temperature is 370 ℃, and the annealing time is 3 min; the temperature of the annealing treatment is 500 ℃, and the time of the annealing treatment is 30s, as long as the first metal layer and the doped polysilicon layer or the silicon substrate can form good ohmic contact.
In another embodiment, the number of anneals is greater than one.
Furthermore, the annealing times are two times, and the temperature of the later annealing treatment is higher than that of the former annealing treatment.
Taking the first metal layer as nickel as an example for detailed description, the low-resistance nickel silicide is formed by two annealing treatments, wherein the first annealing temperature is 260-310 ℃ for 30 seconds, and the second annealing temperature is 400-500 ℃ for 30 seconds.
Taking the first metal layer as cobalt as an example for detailed description, cobalt silicide is formed by two annealing treatments, wherein the first annealing treatment temperature is 400-550 ℃, and the second annealing treatment temperature is 700-850 ℃.
The two annealing treatments can effectively inhibit ion diffusion and reduce the damage to the silicon substrate, so that the generated metal silicide contact layer has small resistivity and uniform property, and smooth metal silicide and silicon substrate appearances can be formed.
The steps of forming the tunneling layer, forming the doped polysilicon layer, forming the first and second metal layers, etc. have already been described above, and are not repeated herein, as can be understood by referring to the foregoing.
The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (15)
1. A solar cell, comprising:
a silicon substrate;
the tunneling layer is formed on one side surface of the silicon substrate;
the doped polycrystalline silicon layer is formed on the surface of one side, away from the silicon substrate, of the tunneling layer and forms a heterojunction with the silicon substrate;
and a gate line electrode;
the grid line electrode comprises a first grid line electrode formed on the doped polycrystalline silicon layer and a second grid line electrode formed on the doped polycrystalline silicon layer or the silicon substrate;
the gate line electrode includes:
a first metal layer directly formed on the doped polysilicon layer or the silicon substrate; the first metal layer contains at least one of nickel, cobalt, titanium and tungsten;
and a second metal layer formed on the first metal layer;
forming a metal silicide at an interface between the first metal layer and the doped polysilicon layer or the silicon substrate; the metal silicide is nickel silicide, cobalt silicide, titanium silicide or tungsten silicide.
2. The solar cell of claim 1, wherein the second metal layer is any one or combination of copper, cobalt, tungsten, tin, or zinc.
3. The solar cell of claim 1, wherein the second metal layer is a composite layer, and the second metal layer is a stack structure formed by two or three layers of different metals.
4. The solar cell of claim 1, wherein the tunneling layer is a doped dielectric layer; the doping elements in the doped dielectric layer are group III and/or group V elements.
5. The solar cell of claim 1, wherein the thickness of the first metal layer is less than 2 microns.
6. The solar cell of any of claims 1-5, wherein the doped polysilicon layer comprises a plurality of n-type doped polysilicon regions and a plurality of p-type doped polysilicon regions, the n-type doped polysilicon regions being electrically isolated from adjacent p-type doped polysilicon regions; the first grid line electrode corresponds to the n-type doped polycrystalline silicon region; the second grid line electrode corresponds to the p-type doped polycrystalline silicon region.
7. The solar cell of claim 6, wherein the n-type doped polysilicon region is electrically isolated from adjacent p-type doped polysilicon regions by a trench or intrinsic polysilicon.
8. The solar cell of claim 6, wherein a first dielectric layer is formed on a side of the doped polysilicon layer facing away from the silicon substrate, a first opening region is formed on the first dielectric layer opposite to the n-type doped polysilicon region and the p-type doped polysilicon region to expose the doped polysilicon layer, and the first metal layer is formed in the first opening region.
9. The solar cell according to any of claims 1-5, wherein the doped polysilicon layer is an n-type doped polysilicon layer and the silicon substrate is a p-type single crystal silicon substrate; the second gate line electrode is formed on the silicon substrate.
10. The solar cell according to claim 9, wherein a region of the silicon substrate corresponding to the second gate line electrode is a p + + region.
11. The solar cell according to claim 10, wherein a region excluding the p + + region on a surface of the silicon substrate on a side close to the second gate line electrode is a p + region.
12. A method for manufacturing a solar cell according to claim 1, comprising the steps of:
forming a tunneling layer on a silicon substrate;
forming a doped polysilicon layer on the tunneling layer;
forming a first metal layer on part of the surface of the doped polycrystalline silicon layer;
forming a second metal layer on the first metal layer;
and annealing the first metal layer to form a metal silicide at the interface between the first metal layer and the doped polysilicon layer.
13. The method as claimed in claim 12, wherein the annealing temperature is 300-600 ℃.
14. The method of claim 12, wherein the annealing is performed more than once.
15. The method according to claim 14, wherein the annealing is performed twice, and a temperature of a subsequent annealing is higher than a temperature of a previous annealing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910549523.4A CN112133769A (en) | 2019-06-24 | 2019-06-24 | Solar cell and method for manufacturing same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910549523.4A CN112133769A (en) | 2019-06-24 | 2019-06-24 | Solar cell and method for manufacturing same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112133769A true CN112133769A (en) | 2020-12-25 |
Family
ID=73849310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910549523.4A Pending CN112133769A (en) | 2019-06-24 | 2019-06-24 | Solar cell and method for manufacturing same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112133769A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113629155A (en) * | 2021-08-06 | 2021-11-09 | 常州时创能源股份有限公司 | Crystalline silicon solar cell |
| CN115274913A (en) * | 2021-04-30 | 2022-11-01 | 泰州中来光电科技有限公司 | Preparation method of IBC solar cell with passivation contact structure, cell, module and system |
| CN117594674A (en) * | 2024-01-19 | 2024-02-23 | 金阳(泉州)新能源科技有限公司 | Back contact battery, preparation method thereof and battery assembly |
| CN118016733A (en) * | 2024-04-08 | 2024-05-10 | 天合光能股份有限公司 | Solar cell and method for manufacturing solar cell |
-
2019
- 2019-06-24 CN CN201910549523.4A patent/CN112133769A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115274913A (en) * | 2021-04-30 | 2022-11-01 | 泰州中来光电科技有限公司 | Preparation method of IBC solar cell with passivation contact structure, cell, module and system |
| CN115274913B (en) * | 2021-04-30 | 2023-11-10 | 泰州中来光电科技有限公司 | Preparation method of IBC solar cell with passivation contact structure, and cell, component and system |
| CN113629155A (en) * | 2021-08-06 | 2021-11-09 | 常州时创能源股份有限公司 | Crystalline silicon solar cell |
| WO2023010858A1 (en) * | 2021-08-06 | 2023-02-09 | 常州时创能源股份有限公司 | Crystalline silicon solar cell |
| CN117594674A (en) * | 2024-01-19 | 2024-02-23 | 金阳(泉州)新能源科技有限公司 | Back contact battery, preparation method thereof and battery assembly |
| CN117594674B (en) * | 2024-01-19 | 2024-05-07 | 金阳(泉州)新能源科技有限公司 | Back contact battery, preparation method thereof and battery assembly |
| CN118016733A (en) * | 2024-04-08 | 2024-05-10 | 天合光能股份有限公司 | Solar cell and method for manufacturing solar cell |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2023045347A1 (en) | Back-contact cell and manufacturing method therefor | |
| JP5213134B2 (en) | Solar cell | |
| CN115241298B (en) | Solar cell, preparation method thereof and photovoltaic module | |
| US9666732B2 (en) | High-efficiency solar cell structures and methods of manufacture | |
| US20120285517A1 (en) | Schottky barrier solar cells with high and low work function metal contacts | |
| JP6599769B2 (en) | Photoelectric conversion device | |
| CN112133769A (en) | Solar cell and method for manufacturing same | |
| WO2008098407A1 (en) | Hybrid silicon solar cells and method of fabricating same | |
| EP2811539B1 (en) | Solar cell with multilayered structure and manufacturing method thereof | |
| KR101886818B1 (en) | Method for manufacturing of heterojunction silicon solar cell | |
| EP3902019A1 (en) | Tandem solar cell | |
| CN112310233A (en) | Solar cell, production method and cell module | |
| CN210200743U (en) | Solar cell | |
| TWI424582B (en) | Method of fabricating solar cell | |
| CN118099245A (en) | Back contact solar cell, preparation method thereof and photovoltaic module | |
| CN115642203A (en) | Back junction solar cell and preparation method thereof | |
| EP3371833A1 (en) | Photovoltaic device and method for manufacturing the same | |
| CN218788382U (en) | High-efficiency heterojunction solar cell | |
| JP2011061020A (en) | Back contact solar cell element, and method of manufacturing the same | |
| KR20140011462A (en) | Solar cell and method for manufacturing the same | |
| US20100224238A1 (en) | Photovoltaic cell comprising an mis-type tunnel diode | |
| CN111584670B (en) | Laminated solar cell and preparation method thereof | |
| CN114695583B (en) | Solar cell, production method and photovoltaic module | |
| CN112349801A (en) | Intermediate series layer of laminated battery, production method and laminated battery | |
| CN111864014A (en) | Solar cell and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |