TWI778886B - Recognition system and sram cell thereof - Google Patents

Abstract

A static random-access memory (SRAM) cell includes a first inverter and a second inverter being cross-coupled; a first access transistor that accesses an output of the first inverter under control of a word line; a second access transistor that accesses an output of the second inverter under control of the word line; a first passage transistor that passes a common-mode voltage, controlled by the output of the first inverter; a second passage transistor that passes an input signal, controlled by the output of the second inverter; and a capacitor switchably coupled to receive the common-mode voltage and the input signal through the first passage transistor and the second passage transistor respectively.

Description

Identification system and its static random access memory unit

The present invention relates to identification technology, in particular to an identification system using a neural network.

Voice activity detection (VAD) can be used to detect or recognize human speech. Voice activity detection can trigger voice-based applications, such as Apple's virtual assistant Siri (Speech Interpretation and Recognition Interface). Voice activity detection is a front end device, which is usually an always-on and low power system.

Modern computer architecture was proposed by John von Neumann in 1945, but the shared bus between program memory and data memory creates a von Neumann bottleneck. Since a single bus can only access either the program memory or the data memory at a single time, the processing capability is much lower than the operating speed of the central processing unit. When the central processing unit is required to process a large amount of data, the effective processing rate of the central processing unit will be severely limited. The central processing unit is constantly forced to wait before it can move the required data to or from memory.

Computing-in-Memory (CIM) is a technology that integrates computing and memory. Embedding operations into memory reduces data movement, making energy use more efficient, and saving bandwidth for massively parallel operations. In-memory computing contributes to edge computing, which is a decentralized computing method that stores computing and data close to the data source, and can be applied to machine learning in the Internet of Things (IoT).

Therefore, there is a need for a novel mechanism to improve the performance of low power or/and high bandwidth systems such as speech recognition systems.

In view of the above, one of the objectives of the embodiments of the present invention is to provide an identification system including a Static Random Access Memory (SRAM) cell, which adopts the principle of charge redistribution to generate accumulation signal with low power consumption or/and increased bandwidth.

According to an embodiment of the present invention, the identification system includes a complex SRAM unit and a quantizer. The SRAM cells are arranged in rows, the SRAM cells of each row respectively receive corresponding input signals and generate corresponding output signals, which are connected to generate sub-signals, and the sub-signals of all rows are connected to generate accumulation Signal. A quantizer receives the accumulated signal to generate a digital output, the quantizer includes at least one capacitor array, which is shared with the SRAM cell.

The first figure A shows a schematic diagram of an (artificial) neural network suitable for a recognition system according to an embodiment of the present invention. A neural network can include connected nodes (or neurons) with weights between the connected nodes, which can be obtained by training a dataset. The recognition system can be adapted for speech recognition to recognize whether the input signal is speech or noise. As illustrated in Figure A, the nodes of the input layer receive input signals (eg Vin1~Vin6), which represent the extraction features of different channels, and the nodes of the output layer can identify whether the input signal is speech or noise. Nodes of one or more hidden layers (eg, the first layer shown) receive the output of the previous layer, and thereby generate output to send to the subsequent layer.

The first diagram B shows a block diagram of the identification system 100 according to the embodiment of the present invention. The recognition system 100 illustrated in the first B figure is applicable to the input layer of the first A figure. According to one of the features of the present embodiment, the identification system 100 uses computing in memory (CIM) technology, which integrates computing and memory, thereby reducing power consumption and saving bandwidth.

The identification system 100 of the present embodiment may include a plurality of static random access memory (SRAM) cells 11 arranged in a row. For each row, the SRAM cells 11 respectively receive corresponding input signals (eg Vin1 to Vin6 ) and generate corresponding (weighted) output signals, which are connected (added) to generate sub-signals. Then, the sub-signals of all rows are connected to generate the accumulation signal Vmac, which represents the output signal obtained by multiply-accumulate the input signal by the complex SRAM unit 11 .

The second diagram A shows a circuit diagram of the SRAM cell 11 (the first diagram B) according to the embodiment of the present invention. In this embodiment, the SRAM cell 11 may include eight transistors (eg, metal oxide semiconductor field effect transistors (MOSFETs)) and one capacitor (ie, 8T1C). The SRAM cell 11 of the present embodiment may include a first inverter, which includes a first transistor M1 (eg, an N-type metal oxide semiconductor field effect transistor) and a second transistor M2 (eg, a P-type transistor) The metal oxide semiconductor field effect transistor) is connected in series between the ground and the power supply, wherein the type of the second transistor M2 is opposite to that of the first transistor M1. The SRAM cell 11 further includes a second inverter, which includes a third transistor M3 (eg, an N-type metal oxide semiconductor field effect transistor) and a fourth transistor M4 (eg, a P-type metal oxide semiconductor field effect transistor) A field effect transistor) is connected in series between the ground and the power supply, wherein the type of the fourth transistor M4 is opposite to that of the third transistor M3. The first inverters (M1, M2) are cross-coupled with the second inverters (M3, M4). That is, the output Q of the first inverter (M1, M2) is coupled to the input of the second inverter (M3, M4), and the (inverted) output Qb of the second inverter (M3, M4) coupled to the inputs of the first inverters (M1, M2).

The SRAM cell 11 may include a first access transistor including a fifth transistor M5 (eg, an N-type metal oxide semiconductor field effect transistor) controlled by a word line WL to The output Q of the first inverter (M1, M2) is accessed, which is transmitted through the first bit line BL. The SRAM cell 11 also includes a second access transistor, which includes a sixth transistor M6 (eg, an N-type metal oxide semiconductor field effect transistor), controlled by the word line WL to access the second access transistor The (inverted) output Qb of the inverters (M3, M4) is transmitted through the second bit line BLb.

According to one of the features of the present embodiment, the SRAM cell 11 may include a first pass transistor, which includes a seventh transistor M7 (eg, an N-type metal-oxide-semiconductor field effect transistor), whose gate ) is controlled by the output Q of the first inverters (M1, M2) to pass the common-mode voltage Vcm (via the drain). The SRAM cell 11 also includes a second pass transistor, which includes an eighth transistor M8 (eg, an N-type metal-oxide-semiconductor field effect transistor), whose gate is controlled by a second inverter The output Qb of (M3, M4) is used to pass the input signal Vin (via the drain). The seventh transistor M7 and the output (at the source) of the eighth transistor M8 are connected together.

According to another feature of the present embodiment, the SRAM cell 11 may include a capacitor C, which is switchably coupled to the common mode voltage Vcm and the input signal through the seventh transistor M7 and the eighth transistor M8, respectively. Vin. In this embodiment, the capacitor C is switched to receive the outputs of the first/second pass transistors M7/M8 through the switch SW1, and the switch SW1 is controlled by the sampling clock signal CLKs. Notably, the values (or weights) of capacitors C of different rows (of the identification system 100) are different from each other. The capacitors C of the SRAM cells 11 in different rows have binary-weighted values (eg, C, 2C, 4C, and 8C), respectively.

The second diagram B shows a circuit diagram of the SRAM cell 11 (the first diagram B) according to another embodiment of the present invention. In this embodiment, the SRAM cell 11 may include ten transistors and one capacitor (ie, 10T1C). The SRAM cell 11 of the second picture B is similar to the second picture A, and the differences are described as follows. As shown in the second diagram B, the SRAM cell 11 further includes a first switching transistor, which includes a ninth transistor M9 (eg, an N-type metal oxide semiconductor field effect transistor), which is connected in series with the first path a transistor M7; and a second switching transistor including a tenth transistor M10 (eg, an N-type metal oxide semiconductor field effect transistor), connected in series with the second pass transistor M8. Thereby, the first pass transistor M7 indirectly receives the common mode voltage Vcm through the first switching transistor M9 (the gate of which is controlled by the sampling clock signal CLKs); and the second pass transistor M8 passes through the second pass transistor M8. The switching transistor M10 (the gate of which is controlled by the sampling clock signal CLKs) is used to indirectly receive the input signal Vin. However, the capacitor C is not directly connected to the output of the first/second pass transistor M7/M8 through the switch SW1. Therefore, the first switching transistor M9 and the second switching transistor M10 together act as a switch, so that the capacitor C can switch to receive the common mode voltage Vcm and input the input through the first pass transistor M7 and the second pass transistor M8 respectively. signal Vin.

In operation, the switch SW1 (or the first/second switching transistor M9/M10) is turned on during the sampling phase, so that the lower plate of the capacitor C (from the output of the first/second pass transistor M7/M8) is sampled analogously voltage, and the upper plate of the capacitor C is coupled to the common mode voltage Vcm. The switch SW1 (or the first/second switching transistor M9/M10) is turned off in the quantization stage, and the lower plate of the capacitor C is switched to be coupled to the reference voltage Vref (eg, a positive reference voltage) through the reverse switch SW2 Vrefp or negative reference voltage Vrefn), the reverse switch SW2 is controlled by the reverse sampling clock signal CLKsb (which has the opposite polarity with respect to the sampling clock signal CLKs), and the upper plate of the capacitor C obtains the previous sampling voltage.

FIG. 3 A shows a circuit diagram of a successive approximation register analog-to-digital converter (SAR ADC) 200A as a quantizer in the identification system 100 according to an embodiment of the present invention. The successive asymptotic analog-to-digital converter 200A converts the continuous analog wave into discrete digital values, which performs a binary search at all quantization levels, finally converging to obtain the digital output Dout at each conversion. The progressive analog-to-digital converter 200A acts as a quantizer, and can cooperate with the SRAM cell 11 of the first B picture during operation. The progressive analog-to-digital converter 200A may include a first digital-to-analog converter (DAC) 21, including a capacitor array, and a second digital-to-analog converter (DAC) 22, including a capacitor array. The capacitor arrays of the first digital-to-analog converter (DAC) 21 and the second digital-to-analog converter (DAC) 22 are switchably coupled to the input signals (eg Vin1 - Vin6 ) and the common mode voltage Vcm. The progressive analog-to-digital converter 200A may include a comparator 23 that receives (at the non-inverting input node) the output of a first digital-to-analog converter (DAC) 21 and (at the inverting input node) a first The output of a two-digit-to-analog converter (DAC) 22 . In addition, the comparator 23 also receives the accumulation signal Vmac. The step-by-step analog-to-digital converter 200A may include a step-by-step logic 24 that receives the comparison result of the comparator 23 to generate a digital output Dout accordingly. According to one of the features of the present embodiment, the capacitor arrays of the first digital-to-analog converter (DAC) 21 and the second digital-to-analog converter (DAC) 22 are compatible with the static random access memory cell 11 of the first diagram B shared.

FIG. 3 B shows a circuit diagram of a successive asymptotic analog-to-digital converter (SAR ADC) 200B as a quantizer in the identification system 100 according to another embodiment of the present invention. The SAR ADC 200B of Figure 3 B is similar to the SAR ADC 200A of Figure 3 A, with the differences described below. In this embodiment, the first digital-to-analog converter (DAC) 21 and the second digital-to-analog converter (DAC) 22 further include a first dummy (dummy or replica) capacitor 211 and a second dummy (dummy or replica) capacitor 211 , respectively. ) capacitor 221, which is switched to connect to the input signal (eg Vin1-Vin6) and the common mode voltage Vcm.

Figure 4 A shows the equivalent circuit of the SAR ADC 200B in the first sampling stage, and Figure 4 B shows the SAR ADC 200B at Equivalent circuit of the second sampling stage. The fourth diagram C and the fourth diagram D respectively show the successive asymptotic analog-to-digital converter (SAR ADC) 200B in the first quantization stage and the second quantization stage and when (the first digital-to-analog converter (DAC) 21 ) Vip is an equivalent circuit when Vip is greater than Vin (of the second digital-to-analog converter (DAC) 22 ). The fourth diagram E and the fourth diagram F show the successive asymptotic analog-to-digital converter (SAR ADC) 200B in the first quantization stage and the second quantization stage, respectively, and when (the first digital-to-analog converter (DAC) 21 ) Vip is an equivalent circuit when Vip is less than Vin (of the second digital-to-analog converter (DAC) 22 ).

According to the above-mentioned embodiment, the SRAM cell 11 adopts the charge redistribution principle to generate the accumulated signal Vmac instead of the charge sharing principle of the conventional system. Therefore, compared with the conventional system, the timing sequence of the above-mentioned embodiment of the present invention is simplified, and a reset phase is not required. In addition, the capacitor array of the successive asymptotic analog-to-digital converter 200A/B can be used in the sampling phase to generate the accumulated signal Vmac. Furthermore, the successive asymptotic analog-to-digital converter 200B in Figure 3 B uses dummy capacitors so that the signal swing can approach the full range.

The fifth A-diagram shows a circuit diagram of a digital-to-analog converter (DAC) 500, which represents the nodes of the first layer of the first A-diagram. The fifth diagram B and the fifth diagram C show the equivalent circuit diagrams of the digital-to-analog converter 500 in the reset phase and the output phase, respectively, and the fifth diagram D illustrates the timing diagram of the related signals of the fifth diagram B and the fifth diagram C . In this embodiment, digital-to-analog converter (DAC) 500 may include a capacitor array including complex capacitors (eg, C, 2C, 4C, and 8C). The upper plates of the capacitors are connected together as the output DACout of a digital-to-analog converter (DAC) 500 . The lower plate of the capacitor switches to receive the digital output of the previous layer or the reversed digital output. Among them, bit0~bit3 represent the digital output generated by the successive asymptotic logic 24 of the previous layer (such as the input layer of the first A picture), and bit0b~bit3b represent the reverse digital output, and their polarities are opposite to the digital output bit0~ bit3. For example, the digital outputs bit0 and bit0b are electrically coupled to corresponding capacitors through switches SW and SWb, respectively (wherein the operation of switch SW is opposite to that of switch SWb), and the switches SW/SWb are controlled by pre-trained and pre-stored Weights. Next, the output DACout of the digital-to-analog converter (DAC) 500 is sent to a comparator (eg, a node at the output layer) for speech or noise recognition.

The above descriptions are only preferred embodiments of the present invention and are not intended to limit the scope of the patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed in the invention shall be included in the following within the scope of the patent application.

100: Identification System 11: Static random access memory unit 200A: Progressive Analog-to-Digital Converter 200B: Sequential Asymptotic Analog-to-Digital Converters 21: First digital to analog converter 211: First virtual capacitor 22: Second digital to analog converter 221: Second virtual capacitor 23: Comparator 24: Sequential Asymptotic Logic Vin: input signal Vin1~Vin6: Input signal CLKs: sampling clock signal CLKsb: reverse sampling clock signal Vcm: common mode voltage Vmac: Accumulate signal SRAM: Static Random Access Memory M1: first transistor M2: second transistor M3: The third transistor M4: Fourth transistor M5: Fifth transistor/first access transistor M6: sixth transistor/second access transistor M7: seventh transistor/first pass transistor M8: Eighth Transistor/Second Pass Transistor M9: ninth transistor/first switching transistor M10: Tenth Transistor/Second Switching Transistor Q: output Qb: output BL: first element line BLb: Second bit line WL: word line SW1: switch SW2: reverse switch C: capacitor Vref: reference voltage Vrefp: Positive reference voltage Vrefn: negative reference voltage Dout: digital output DACout: output bit0~bit3: digital output bit0b~bit3b: Reverse digital output SW: switch SWb: switch Reset: reset signal Reset_b: reverse reset signal

The first figure A shows a schematic diagram of an (artificial) neural network suitable for a recognition system according to an embodiment of the present invention. The first Figure B shows a block diagram of an identification system according to an embodiment of the present invention. The second diagram A shows a circuit diagram of the SRAM cell (the first diagram B) according to an embodiment of the present invention. The second diagram B shows a circuit diagram of a SRAM cell (the first diagram B) according to another embodiment of the present invention. Figure 3 A shows a circuit diagram of a successive asymptotic analog-to-digital converter (SAR ADC) according to an embodiment of the present invention as a quantizer in a recognition system. Figure 3 B shows a circuit diagram of a successive asymptotic analog-to-digital converter (SAR ADC) as a quantizer in an identification system according to another embodiment of the present invention. Figure 4A shows the equivalent circuit of the successive asymptotic analog-to-digital converter (SAR ADC) in the first sampling stage. Figure 4 B shows the equivalent circuit of the successive asymptotic analog-to-digital converter (SAR ADC) in the second sampling stage. The fourth graph C and the fourth graph D show the successive asymptotic analog-to-digital converter (SAR ADC) in the first quantization stage and the second quantization stage respectively and when the Vip (of the first digital-to-analog converter (DAC)) Equivalent circuit when greater than Vin (of the second digital-to-analog converter (DAC)). The fourth diagram E and the fourth diagram F show the successive asymptotic analog-to-digital converter (SAR ADC) in the first quantization stage and the second quantization stage respectively and when the Vip (of the first digital-to-analog converter (DAC)) Equivalent circuit for less than Vin (of the second digital-to-analog converter (DAC)). The fifth A-diagram shows a circuit diagram of a digital-to-analog converter (DAC) representing the nodes of the first layer of the first A-diagram. The fifth diagram B and the fifth diagram C show the equivalent circuit diagrams of the digital-to-analog converter in the reset stage and the output stage, respectively. The fifth D diagram illustrates the timing diagram of the correlation signals of the fifth B diagram and the fifth C diagram.

11: Static random access memory unit

Vin: input signal

CLKs: sampling clock signal

CLKsb: reverse sampling clock signal

Vcm: common mode voltage

M1: first transistor

M2: second transistor

M3: The third transistor

M4: Fourth transistor

M5: Fifth transistor/first access transistor

M6: sixth transistor/second access transistor

M7: seventh transistor/first pass transistor

M8: Eighth Transistor/Second Pass Transistor

Q: output

Qb: output

BL: first element line

BLb: Second bit line

WL: word line

SW1: switch

SW2: reverse switch

C: capacitor

Vref: reference voltage

Claims (16)

A static random access memory unit, comprising: a first inverter connected between a ground and a power source; a second inverter connected between the ground and the power source, the first inverter connected to the power source The second inverter is cross-coupled; a first access transistor is controlled by the word line to access the output of the first inverter, which is transmitted through the first word line; a first Two access transistors controlled by the word line to access the output of the second inverter, which are transmitted through the second bit line; a first pass transistor controlled by the first the output of the inverter is used to pass the common mode voltage; a second pass transistor is controlled by the output of the second inverter to allow the input signal to pass; and a capacitor is respectively connected to the first The pass transistor and the second pass transistor are switched and coupled to the common mode voltage and the input signal. The SRAM cell of claim 1, further comprising: a switch for switching the capacitor connected to the outputs of the first pass transistor and the second pass transistor, the switch being controlled by a sampling clock Signal. The SRAM cell of claim 2, wherein the switch is turned on in the sampling phase, so that the lower plate of the capacitor is sampled to obtain a sampling voltage, and the upper plate of the capacitor is coupled to the common-mode voltage; the The switch is turned off in the quantization stage, and the lower plate of the capacitor is switched to be coupled to the reference voltage through a reverse switch, and the reverse switch is controlled by the reverse sampling clock signal, which has an opposite relative to the sampling clock signal. polarity, and the upper plate of the capacitor gets the sampling voltage. The SRAM cell of claim 1, further comprising: a first switching transistor connected in series with the first pass transistor; and A second switching transistor connected in series with the second pass transistor; wherein the first pass transistor receives the common-mode voltage indirectly through the first switching transistor, and the first switching transistor is controlled by sampling and the second pass transistor receives the input signal indirectly through the second switching transistor, and the second switching transistor is controlled by the sampling clock signal. The SRAM cell of claim 4, wherein the first switching transistor and the second switching transistor are turned on in the sampling stage, so that the lower plate of the capacitor is sampled to obtain a sampling voltage, and the capacitor The upper plate is coupled to the common-mode voltage; the first switching transistor and the second switching transistor are disconnected in the quantization stage, and the lower plate of the capacitor is switched and coupled to the reference voltage through a reverse switch, and the reverse The direction switch is controlled by the reverse sampling clock signal, which has the opposite polarity with respect to the sampling clock signal, and the upper plate of the capacitor obtains the sampling voltage. The SRAM cell of claim 1, wherein the first inverter comprises a first transistor and a second transistor connected in series between the ground and the power supply, wherein the type of the second transistor is Opposite to the first transistor; the second inverter includes a third transistor and a fourth transistor connected in series between the ground and the power supply, wherein the fourth transistor is of the opposite type to the third transistor crystal. An identification system, comprising: a plurality of static random access memory units arranged in rows, the static random access memory units of each row respectively receive corresponding input signals and generate corresponding output signals, which are connected to generate sub-signals, and all rows The sub-signals are connected to generate an accumulated signal; and a quantizer receives the accumulated signal to generate a digital output, the quantizer includes at least one capacitor array; wherein the at least one capacitor array is shared with the complex SRAM cell ; wherein each of the plurality of static random access memory units includes: a first inverter, connected between the ground and the power supply; A second inverter is connected between the ground and the power supply, the first inverter is cross-coupled with the second inverter; a first access transistor is controlled by the word line to store Take the output of the first inverter, which is transmitted through the first bit line; a second access transistor is controlled by the word line to access the output of the second inverter, which The transmission is carried out through the second bit line; a first pass transistor is controlled by the output of the first inverter to pass the common mode voltage; a second pass transistor is controlled by the first inverter. The outputs of the two inverters are used for passing the input signal; and a capacitor is switched to couple the common mode voltage and the input signal through the first pass transistor and the second pass transistor, respectively. The identification system of claim 7, wherein the quantizer comprises a progressive analog-to-digital converter. The identification system of claim 8, wherein the progressive analog-to-digital converter comprises: a first digital-to-analog converter comprising a capacitor array; a second digital-to-analog converter comprising a capacitor array; a a comparator, which receives the output of the first digital-to-analog converter, the output of the second digital-to-analog converter, and the accumulated signal; and a continuous asymptotic logic, which receives the comparison result of the comparator, and generates accordingly the digital output. The identification system of claim 7, comprising a neural network comprising: an input layer, the nodes of which receive the input signal; a first layer, the nodes of which receive the output of the input layer; and an output layer, the nodes of which receive the input signal The output of the first layer is used to identify the input signal; wherein the plurality of SRAM cells constitute the nodes of the input layer. The identification system of claim 10, wherein each node of the first layer comprises: a digital-to-analog converter including a capacitor array including a plurality of capacitors; wherein upper plates of the plurality of capacitors are connected together as the digital-to-analog converter The output of the analog converter; the lower plate switch of the complex capacitor receives the digital output of the input layer or the inverse digital output. The identification system of claim 7, wherein the capacitors of the plurality of SRAM cells of different rows respectively have weighted binary values. The identification system of claim 12, wherein the SRAM cell further comprises: a switch for switching the capacitor connected to the outputs of the first pass transistor and the second pass transistor, the switch being controlled for sampling the clock signal. The identification system of claim 13, wherein the switch is turned on in the sampling stage, so that the lower plate of the capacitor is sampled to obtain the sampling voltage, and the upper plate of the capacitor is coupled to the common-mode voltage; the switch in the quantization stage is disconnected, the lower plate of the capacitor is switched and coupled to the reference voltage through a reverse switch, the reverse switch is controlled by the reverse sampling clock signal, which has the opposite polarity with respect to the sampling clock signal, and the capacitor The sampling voltage is obtained from the upper plate of the . The identification system of claim 12, wherein the SRAM cell further comprises: a first switching transistor connected in series with the first pass transistor; and a second switching transistor connected in series with the second pass a transistor; wherein the first pass transistor receives the common mode voltage indirectly through the first switching transistor, the first switching transistor is controlled by a sampling clock signal; and the second pass transistor is The second switching transistor receives the input signal indirectly, and the second switching transistor is controlled by the sampling clock signal. The identification system of claim 15, wherein the first switching transistor and the second switching transistor are turned on in the sampling phase, so that the lower plate of the capacitor is sampled to obtain the sampling voltage, and the upper plate of the capacitor is coupled to the common mode voltage; the first switching transistor and the second switching transistor are disconnected in the quantization stage, and the lower plate of the capacitor is switched and coupled to the reference voltage through a reverse switch, and the reverse switch is controlled by The reverse sampling clock signal has opposite polarity with respect to the sampling clock signal, and the upper plate of the capacitor obtains the sampling voltage.

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