CN106067817A - 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate gradual approaching A/D converter - Google Patents

Abstract

The invention belongs to the technical field of integrated circuits, and specifically relates to a 1.5-bit redundancy accelerated successive approximation analog-to-digital converter based on a controllable asymmetrical dynamic comparator. The analog-to-digital converter structure provided by the present invention includes two identical gate voltage bootstrap switches, a group of symmetrical N-bit binary capacitor arrays, two controllable asymmetric dynamic comparators, a common dynamic comparator and the digital Logic circuit modules. The invention introduces 1.5-bit redundant acceleration technology, which shortens the time for waiting for the first few bits to be completely established, accelerates the conversion rate of the analog-to-digital converter, increases redundancy, reduces code errors and missing codes, and improves precision. Compared with traditional technology, it can greatly simplify the circuit scale, especially omit the reference voltage generation circuit, thereby reducing the power consumption and area of the analog-to-digital converter, quickly changing the equivalent reference voltage value, and speeding up the conversion speed of the analog-to-digital converter , and is universal, and can be applied to other 0.5-bit application scenarios.

Description

1.5-bit redundant accelerated successive approximation based on controllable asymmetric dynamic comparator ADC

technical field

The invention belongs to the technical field of integrated circuits, and in particular relates to a 1.5-bit redundant accelerated successive approximation digital-to-analog converter based on a controllable asymmetric dynamic comparator.

Background technique

The 1.5-bit technology is widely used in pipelined analog-to-digital converters, and the accuracy of the analog-to-digital converters caused by small-magnitude static offset errors is eliminated by increasing redundancy. The first application of 1.5-bit technology in successive approximation analog-to-digital converters was first published by Chun-Cheng Liu and Soon-Jyh Chang at the Symposium on VLSI circuits in 2010, although there was no The concept of 1.5 bits is proposed, but the redundant method implemented therein is indeed a 1.5-bit approach. Figure 1 is a schematic diagram of the structure of a 10MS/s, 10bit top plate sampling successive approximation analog-to-digital converter published by Chun-Cheng Liu at the conference. Fig. 1 mainly includes two gate voltage bootstrap switches 101, which are connected with the input signal and the top plate of the 10-bit binary capacitor array 102 and nodes 103, 104; the 10-bit binary capacitor array 102, and the top plate of the capacitor array are connected together Compared with the dynamic comparator 105, 106, 107 connected to the nodes 103, 104, and the structure of the traditional top plate sampling successive approximation analog-to-digital converter, the first four bits of the capacitance array 102 of Fig. 1 are split into equal The two parts of the quantity, the steering of the bottom plate level are controlled separately; dynamic comparators 105, 106, 107, the number of dynamic comparators in Figure 1 is no longer one in the traditional structure, but is expanded to three, of which 106 , 107 are used for 1.5-bit comparison and establishment; a six-bit digital-to-analog converter 108 generates a reference voltage for each level of 1.5-bit comparison by flipping the bottom plate of the capacitor. This part of the circuit is not available in traditional successive approximation analog-to-digital converters ; SAR ADC logic circuit module 109, clock generation method, control level conversion direction and output code combination logic are also different from traditional successive approximation analog-to-digital converters.

The first four 1.5 bits of the structure shown in FIG. 1 are realized by two dynamic comparators 106, 107 and a six-bit sub-digital-to-analog converter. The two dynamic comparators 106, 107 are respectively connected to the top plate of the symmetrical 10-bit capacitor array and the six-bit digital-to-analog converter 108, that is, the input ends of the two dynamic comparators 106, 107 are respectively connected to the nodes 103, 110 and the node 104 , 110. The reference voltage range generated by the six-bit sub-analog-to-digital converter 108 is one-half of the common-mode voltage to fifteen-sixteenths of the common-mode voltage. When the plate voltages on the two capacitor arrays are higher than the reference voltage , the low plate of the capacitor group of this bit does not flip; when the upper plate voltage of the two capacitor arrays is lower than the reference voltage and the other is higher than the reference voltage, the bottom plate of the high side capacitor group is grounded, and the bottom plate of the low side capacitor group is grounded. The plate is connected to the reference voltage.

The above circuit works as follows. When CK is at a high level, the gate voltage bootstrap switch 101 is turned on, and the input signal is sampled to the top plate of the binary capacitor array 102 of the analog-to-digital converter. At this time, the bottom plates of the capacitor groups C _1a ~ C _4a are grounded, The remaining capacitor groups (C _1b ~C _4b and C ₅ ~C ₉ ) are connected to the reference voltage, the dynamic comparators 105, 106, 107 are all turned off, and the analog-to-digital converter is in the sampling phase. When CK is at low level, the gate voltage bootstrap switch 101 is turned off, the capacitor array 102 is suspended, the charge remains unchanged, the input signal at the falling edge moment is kept on the capacitor array 102, and the analog-to-digital converter is in the quantization stage. The held input signal is compared with the reference voltage by two dynamic comparators 106 and 107 respectively, the data of the comparator is transmitted to the logic circuit module 109 of the SAR ADC, and the logic control signal is generated through the combinational logic to control the first capacitor group C _1a and C _1b The reverse direction of the bottom plate, after a period of time is completely established, start the next 1.5-bit comparison until the fourth bit. After the comparison of the fourth bit is completed, the dynamic comparators 106 and 107 will be turned off until the next quantization cycle, the establishment of the fourth bit is completed, and the dynamic comparator 105 is turned on, and the comparison of the subsequent six bits is completed until the tenth bit. The data quantized by the dynamic comparators 105, 106, and 107 are processed in the logic circuit module 109 of the SAR ADC to generate ten-bit binary codes through digital logic operations, stored in registers, and output at the next rising edge of the external sampling clock.

It can be known from the foregoing that the first four 1.5-bit comparisons built by Chun-Cheng Liu are based on the 10MS/s, 10-bit top plate sampling successive approximation analog-to-digital converter. There is no speed increase, and the redundancy that can be increased is very limited. Moreover, the technology used in this design is 0.18um CMOS technology, and the unit capacitance value is 5fF. With the development of the technology, the linearity of the metal line is better. The unit capacitance value constructed under the 65nm C MOS process is basically 1fF, which means that the total capacitance value of the capacitor array with the same number of digits is reduced to one-fifth. The flat settling time is greatly shortened, so the use of four 1.5-bit ten-bit successive approximation comparators consumes more hardware and delays. This design uses a six-bit digital-to-analog converter 108 to generate the reference voltage, which not only consumes a certain area and power consumption, but also easily interferes with the establishment of the level on the capacitor array 102 of the successive approximation comparator, and may introduce an offset. case has a greater impact. This also limits the rate of the successive approximation comparator under this structure.

Contents of the invention

The purpose of the present invention is to propose a new structure of a 1.5-bit redundant accelerated successive approximation analog-to-digital converter based on a controllable asymmetrical dynamic comparator. It is characterized by the introduction of 1.5-bit redundant acceleration technology after the first bit. After the level of the bottom plate of the MSB capacitor is reversed, the level of the top plate of the capacitor array is not fully established. The level of the top plate is cross-input Two controllable asymmetric dynamic comparators are used for comparison, and according to the result, the bottom plate of the group of capacitors is selected to be connected to the high level of the reference voltage, the low level of the reference voltage or to maintain the common mode level. The 1.5-bit redundant acceleration technology introduced by the present invention not only shortens the time for waiting for the first few bits to be completely established, accelerates the conversion rate of the analog-to-digital converter, but also increases redundancy, reduces bit errors and missing bits, and improves accuracy .

The structure of the 1.5-bit redundant accelerated successive approximation analog-to-digital converter based on the controllable asymmetric dynamic comparator provided by the present invention is shown in FIG. 2 . Its circuit includes: two identical gate voltage bootstrap switches 201, a group of symmetrical N-bit binary capacitor arrays 202, two controllable asymmetric dynamic comparators 205, 206, a common dynamic comparator 207 and the digital logic circuit module 208; wherein:

The gate voltage bootstrap switch 201 includes a signal input terminal, a clock input terminal, and an output terminal;

The N-bit binary capacitor array 202 contains N groups of capacitors, wherein the capacitor value of the Nth group is equal to the capacitor value of the N-1 group, both of which are unit capacitors. From the N-1 group to the first group, the capacitance value is twice the same ratio Incremental; the top plates of each group of capacitors are connected to nodes 203 and 204, and the bottom plates of each group of capacitors are connected to three groups of transmission gate switches 210 and 211;

Each transmission gate 210, 211 includes an N-type field effect transistor and a P-type field effect transistor, the channels of the two are arranged in parallel, the drain terminals of the two are connected to each other to form the drain terminal of the transmission gate circuit, and the source terminals are connected to each other to form a transmission gate circuit. The source terminal of the transmission gate circuit, the gate terminal of the N-type field effect transistor constitutes the N gate terminal of the transmission gate circuit, and the gate terminal of the P-type field effect transistor constitutes the P gate terminal of the transmission gate circuit;

Each controllable asymmetric dynamic comparator 205, 206 has a positive input terminal, a negative input terminal, a clock input terminal, a positive output terminal and a negative output terminal;

Each ordinary dynamic comparator 207 has two input terminals regardless of polarity, a clock control terminal, and two corresponding output terminals;

The digital logic circuit block 208 of the SAR ADC includes:

A clock generation module generates clock signals 222 and 223 according to the data streams of the three comparators;

The digital logic processing module is used to generate the logical control signals 220, 221 for level inversion of the bottom plate of the N-bit binary capacitor array 202 and the register module to store the output data code;

In the present invention, the two grid voltage bootstrap switch signal inputs are respectively connected to the differential signal input, the clock input terminals are connected to the external control clock of the entire successive approximation comparator, and the sample and hold clock, and the output terminal is connected to a symmetrical N-bit binary capacitor array The top plate of 202 and the nodes 203 and 204, in the sampling stage, the input signal is collected on the top plate of the capacitor array, and then the switch is turned off, and the voltage value is stored on the top plate of the capacitor array;

In the present invention, the top plate of each group of capacitors in the N-bit binary capacitor array 202 is interconnected with the grid voltage bootstrap switch 201, the input terminals 205, 206 of two controllable asymmetric dynamic comparators, and the input terminals 205 and 206 of an ordinary dynamic comparator. Input terminal 207 and nodes 203 and 204; the bottom plates of each group of capacitors are connected to three groups of transmission gate switches 210 and 211, and the logic control generated by the logic circuit module 208 of the SAR ADC is connected to the reference voltage high level and the reference voltage low level In this way, the comparison result of the level of the top plate of each capacitor array is processed by the logic circuit module 208 of the SAR ADC to generate the level reversal control signals 220 and 221 of the bottom plate of the capacitor to control the current capacitor. The bottom plate of the group is connected to the reference voltage high level, the reference voltage low level or the common mode level to generate the comparison level of the next bit on the top plate of the capacitor array;

In the present invention, the positive and negative input terminals of the two controllable asymmetrical dynamic comparators 205, 206 cross-input the two top plate voltages of the N-bit binary capacitor array 202, and the cross-connection nodes 203, 204; the clock input connection The control signals 220 and 221 generated by the logic circuit module 208 of the SAR ADC control the opening and closing of the controllable asymmetrical dynamic comparators 205 and 206; the controllable asymmetrical comparators 205 and 206 utilize the load of the latch in the comparator Asymmetry or asymmetry between the input of the comparator and the threshold of the tube, an adjustable reference voltage is superimposed on the input signal of one side of the comparator. This connection is equivalent to connecting the two top plates of the N-bit binary capacitor array 202 The differential voltage is compared with the adjustable reference voltage to generate a 1.5-bit output code to achieve 1.5-bit redundant acceleration; the output code is transmitted to the logic circuit module 208 of the SAR ADC to generate the control clocks 222 and 223 of the comparator and the bottom electrode of the capacitor Board level flip control signals 220, 221;

In the present invention, an ordinary dynamic comparator 207 input terminal is connected to the two top plate voltages of the N-bit binary capacitor array 202, and the access nodes 203, 204; the clock input is connected to the control signal 220 generated by the logic circuit module 208 of the SAR ADC , 221, control the opening and closing of the ordinary dynamic comparator 207; control and compare the two top plate voltages of the N-bit binary capacitor array 202, and generate a 1-bit output code; the output code is transmitted to the logic circuit module 208 of the SAR ADC , generating comparator control clocks 222, 223, and capacitor bottom plate level inversion control signals 220, 221;

In the present invention, the comparison between the first bit and the M to N bits is compared by the ordinary dynamic comparator 207 to trigger the establishment of the next bit, and the comparison between the second bit and the M bit is performed by two controllable asymmetric dynamic comparators 205, 206 comparison triggers the establishment of the next bit;

In the present invention, the digital logic circuit module 208 of the SAR ADC generates the clock signals 222, 223 according to the data streams of the three comparators, the logic control signals 220, 221 for level inversion of the bottom plate of the N-bit binary capacitor array 202, and stores the output data code;

The present invention further provides the workflow of a 1.5-bit redundant accelerated successive approximation analog-to-digital converter based on a controllable asymmetric dynamic comparator, specifically as follows:

When CK is at a high level, the gate voltage bootstrap switch 201 is turned on, and the input signal is sampled to the top plate of the binary capacitor array 202 of the analog-to-digital converter. Modulus level V _cm , the ordinary dynamic comparator 207 and the controllable asymmetric comparator 205, 206 are all turned off, and the analog-to-digital converter is in the sampling phase;

When CK is at a low level, the gate voltage bootstrap switch 201 is turned off, the capacitor array 202 is suspended, and the amount of charge remains unchanged, the input signal at the time of the falling edge is kept on the capacitor array 202, and the analog-to-digital converter is in the quantization stage;

The ordinary dynamic comparator 207 compares the input signal held under the control of the clock signals 222 and 223 generated by the logic circuit module 208 of the SAR ADC, the data of the dynamic comparator 207 is transmitted to the logic circuit module 208 of the SAR ADC, and combined The logic generates logic control signals 220, 221, through three groups of transmission gate switches 210 to control the symmetrical flip direction of the bottom plate of the first capacitor group, the reference voltage is high or the reference voltage is low; after a short delay, this When the level establishment of the first bit has not been completed, the two controllable asymmetric dynamic comparators start the comparison of 1.5 bits, and the symmetrical top plate level is cross-input to the two controllable asymmetric dynamic comparators 205, 206. 203, 204 are cross-connected to the positive input terminal and negative input terminal of two controllable asymmetric dynamic comparators 205, 206, and the establishment signal is compared under the control of the clock signal 222, 223 generated by the logic circuit module 208 of the SAR ADC , the two controllable asymmetrical dynamic comparators 205, 206 transmit data to the logic circuit module 208 of the SAR ADC, the logic control signals 220, 221 are generated through combinational logic, and the second group of capacitors are controlled by three groups of transmission gate switches 210 The bottom plate is connected to the high level of the reference voltage, the low level of the reference voltage or maintains the common mode level, and repeats this step until the last bit is at the 1.5-bit level;

After the last 1.5 bit-level comparison is completed, the controllable asymmetric dynamic comparators 205 and 206 will be turned off until the next quantization period. After the bit level is completely established, the ordinary dynamic comparator 207 is turned on. Compare until N bits;

The data quantized by the dynamic comparators 205, 206, and 207 are processed in the logic circuit module 208 of the SAR ADC to generate an N-bit binary code through digital logic operations, stored in the register, and output at the rising edge of the next external sampling clock.

The controllable asymmetric dynamic comparator for realizing 1.5 bits in the present invention is shown in FIG. 3 . There are two ways to realize the controllable asymmetric dynamic comparator, and the structure of the controllable asymmetric dynamic comparator in different realization methods is slightly different. The first is a dynamic comparator latch load controllable asymmetry, including input pair transistors 301, 302, which are N-type transistors M1, M2 in FIG. 3; tail current source transistor 303, which is an N-type transistor in FIG. 3 M3; latch 304, two end-to-end inverters are formed, in Fig. 3 by P-type transistors M6, M7 and N-type transistors M4, M5; reset transistors 305, 306, 307, 308, in Fig. 3 are P-type transistors M9, M10, M11, M12; output buffers 309A, 309B are composed of P-type transistors M14, M15 and N-type transistors M12, M13 in FIG. 3; controllable asymmetric dynamic comparator The latch output nodes 310, 311; 312A, 312B are latch output controllable capacitor arrays of controllable asymmetric dynamic comparators. The implementation method is as follows: the latch 304 of the dynamic comparator is connected to the nodes 310 and 311 with the capacitive load arrays 312A and 312B with switches, and by controlling the on and off of the switches 331 and 332, the load difference between the two ends of the latch 304 is constructed and collected. , The difference in the flipping threshold voltage of the latch is constructed through the difference in load size, which is equivalent to the input terminal, artificially creating a mismatch in the input threshold value, and creating the effect of superimposing a reference voltage on the input signal at one end. By adjusting the difference between the loads at both ends of the comparator latch 304 , different reference voltage effects can be adjusted. The second implementation method is the controllable asymmetry of the threshold voltage of the dynamic comparator input pair transistors, including the input pair transistors 301 and 302, which are N-type transistors M1 and M2 in FIG. 3; the tail current source transistor 303 is N-type transistor M3; latch 304, composed of two end-to-end inverters, constituted by P-type transistors M6, M7 and N-type transistors M4, M5 in FIG. , in Fig. 3 are P-type transistors M9, M10, M11, M12; output buffers 309A, 309B are composed of P-type transistors M14, M15 and N-type transistors M12, M13 in Fig. 3; controllable asymmetry The latch output nodes 310, 311 of the dynamic comparator; the input of the controllable asymmetric dynamic comparator are externally connected to the bulk terminal voltages 320, 321 of the transistor. The implementation method is as follows: lead out the body terminals of the input pair tubes 301 and 302, connect the external voltage, adjust the threshold voltage of the input pair tubes 301 and 302 by changing the voltage difference between the source terminal and the body terminal of the MOS tube, and create an input signal superimposed on one end. effect of the reference voltage. By adjusting the voltage difference between the input and the tube body, the effect of different reference voltages can be adjusted. But one thing to note is that using the second method requires the input pair to be a P-type transistor or a deep-well N-type transistor. Although the method provided by the present invention cannot construct an accurate reference voltage value, it will be explained in detail later. In the 1.5-bit redundant acceleration circuit, the reference voltage value does not need to be particularly accurate, but only needs to be within a certain range. This 1.5-bit implementation method based on a controllable asymmetric dynamic comparator is compared with two four-input comparators plus a corresponding reference voltage or two two-input comparators plus a redundant reference voltage generation circuit required by the traditional 1.5-bit implementation , can greatly simplify the circuit scale, especially omit the reference voltage generation circuit, and then reduce the power consumption and area of the analog-to-digital converter, and can quickly change to establish an equivalent reference voltage value (if necessary), speeding up the conversion of the analog-to-digital converter Speed, and universal, can be applied to other 0.5-bit application scenarios.

The foregoing content generally describes the features and technical advantages of the present invention, and the following examples are given to illustrate the idea of the present invention more clearly. Anyone skilled in the art should be able to understand that the concepts and specific embodiments disclosed in the present invention can be modified or designed to achieve the same purpose of the structure of the present invention, such equivalent structure does not exceed the appended claims of the present invention spirit and scope as defined.

Description of drawings

Figure 1 is a schematic diagram of the structure of the first four 1.5-bit successive approximation analog-to-digital converters published by Chun-Cheng Liu in 2010.

FIG. 2 is a schematic structural diagram of a 1.5-bit redundant accelerated successive approximation analog-to-digital converter based on a controllable asymmetric dynamic comparator provided by the present invention.

Fig. 3 is a circuit diagram of the controllable asymmetric dynamic comparator provided by the present invention.

Fig. 4 is an example provided by the present invention, the second bit is a schematic diagram of establishment of the top board voltage during the quantization process of the successive approximation analog-to-digital converter accelerated by 1.5 bits redundancy.

Fig. 5 is an example provided by the present invention, the second bit is the digital calibration logic of the 1.5-bit redundancy accelerated successive approximation analog-to-digital converter.

Labels in the figure:

101 is the two gate voltage bootstrap switches 101 of the first four 1.5-bit successive approximation analog-to-digital converters published by Chun-Cheng Liu in 2010; 102 is the 10-bit binary capacitor array of the SAR ADC, and the capacitors 103 and 104 are The top plate of the array is connected together with the node connected to the dynamic comparator; 105, 106, 107 are three dynamic comparators of the SAR ADC, wherein 106, 107 are used for 1.5 bit comparison establishment; 108 is the six of the SAR ADC A bit digital-to-analog converter generates a reference voltage established by 1.5-bit comparison for each level by flipping the bottom plate of the capacitor; 108 is a logic circuit module of the SAR ADC.

201 is two identical gate voltage bootstrap switches of the 1.5-bit redundant acceleration successive approximation analog-to-digital converter based on controllable asymmetric dynamic comparator; 202 is the N-bit binary capacitor array of the invention; 203, 204 capacitor arrays 205, 206 are two controllable asymmetric dynamic comparators of the invention; 207 is a common dynamic comparator of the invention; 208 is the SAR ADC of the invention 210 and 211 are the bottom plate transmission gate switches of the N-bit binary capacitor of the invention; 220 and 221 are the logic control signals generated by the digital logic circuit module of the SAR ADC of the invention; 222 and 223 of the invention The digital logic circuit block of the SAR ADC generates the dynamic comparator clock signal.

301 and 302 are the input pair tubes of the controllable asymmetric dynamic comparator provided by the present invention, and in Fig. 3 are the deep-well N-type transistors M1 and M2 whose body terminal voltage is drawn; Tail current source tube, N-type transistor M3; 304 is the latch of the controllable asymmetric dynamic comparator; 305, 306, 307, 308 are reset transistors of the controllable asymmetric dynamic comparator, P-type transistors M9, M10, M11, M12; 309A, 309B are the output buffers of the controllable asymmetric dynamic comparator; 310, 311 are the latch output nodes of the controllable asymmetric dynamic comparator; 312A, 312B are the controllable asymmetric dynamic comparator The latch outputs a controllable capacitor array; 320 and 321 are the input to the body terminal voltage of the controllable asymmetric dynamic comparator.

401 is a schematic diagram of establishing the top plate voltage of the successive approximation analog-to-digital converter of traditional top plate sampling, wherein 410 is the first established redundancy of the successive approximation analog-digital converter of traditional top plate sampling; 402 It is an example provided by the present invention, the second bit is a schematic diagram of the establishment of the top board voltage in the quantization process of the successive approximation analog-to-digital converter of 1.5 bit redundancy acceleration, wherein 411 is the second bit is the successive approximation model of 1.5 bit redundancy acceleration The redundancy established by the first bit of the digital converter, 412 is the redundancy established by the second bit of the successive approximation type analog-to-digital converter for 1.5 bit redundancy acceleration; 403 is an example provided by the present invention, The second is the dynamic comparator group of the successive approximation analog-to-digital converter of 1.5 bit redundant acceleration, 413 is a controllable asymmetric dynamic comparator, 414 is a common dynamic comparator; 404 is an example provided by the present invention, the second The bits are the control clocks of the dynamic comparator group of the successive approximation analog-to-digital converter with 1.5-bit redundant acceleration, wherein 415 is the clock for controlling two controllable asymmetric dynamic comparators, and 416 is the clock for controlling the dynamic comparators.

501 is an example provided by the present invention, and the second bit is the data of single-stage one bit in the successive approximation analog-to-digital converter of 1.5 bit redundancy acceleration; 502 is the second bit is the successive approximation modulus of 1.5 bit redundancy acceleration 1.5 bits per level of data in the converter; 503 is the output data of the second successive approximation analog-to-digital converter accelerated by 1.5 bits of redundancy.

detailed description

The correction method provided by the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that the successive approximation analog-to-digital converter of 1.5 bit redundant acceleration provided by the present invention has different indexes and performance realization methods, and the 1.5 bit realization based on the controllable asymmetric dynamic comparator in the present invention can also have many application scenarios. The following example provides a typical implementation circuit of the present invention, which is only used to illustrate the formation and use of the present invention, and is not intended to limit the present invention.

The example of the 1.5-bit redundant acceleration primary and secondary approximation analog-to-digital converter based on the controllable asymmetric dynamic comparator provided by the present invention, the implementation goal is to realize a 150MS/s second-bit 1.5-bit redundant acceleration top plate sampling Sampling rate, 10-bit precision successive approximation analog-to-digital converter, the specific structure diagram is shown in Figure 2. The structure includes two identical gate voltage bootstrap switches 201, a group of symmetrical 10-bit binary capacitor arrays 202, two controllable asymmetric dynamic comparators 205, 206, a common dynamic comparator 207 and a SAR ADC. digital logic circuit module 208; wherein:

The two gate voltage bootstrap switch signal inputs are respectively connected to the differential signal input, the clock input terminals are connected to the external control clock of the entire successive approximation comparator, and the sample and hold clock, and the output terminal is connected to the top pole of the symmetrical 10-bit binary capacitor array 202 plate, the input terminals of two controllable asymmetric dynamic comparators 205, 206, the input terminals of a common dynamic comparator 207 and nodes 203, 204, and the switch is disconnected after the input signal is collected on the top plate of the capacitor array in the sampling phase , the voltage value is stored on the top plate of the capacitor array; the bottom plate of each group of capacitors in the 10-bit binary capacitor array 202 is connected to three groups of transmission gate switches 210, 211, and the logic control generated by the logic circuit module 208 of the SAR ADC 220, 221 are connected to the reference voltage high level, the reference voltage low level or the common mode level; the positive and negative input terminals of the two controllable asymmetrical dynamic comparators 205, 206 are cross-input to two of the N-bit binary capacitor array 202 The top plate voltage, and the cross access nodes 203, 204; the clock input is connected to the control signal 222, 223 generated by the logic circuit module 208 of the SAR ADC, to control the opening and closing of the controllable asymmetric dynamic comparator 205, 206; the controllable The asymmetry comparator 205, 206 utilizes the asymmetry of the load of the latch in the comparator or the asymmetry of the input of the comparator to the threshold value of the tube, and superimposes an adjustable reference voltage on one side of the comparator input signal, such The connection method is equivalent to comparing the differential voltage of the two top plates of the 10-bit binary capacitor array 202 with the adjustable reference voltage to generate a 1.5-bit output code to achieve 1.5-bit redundant acceleration; the output code is transmitted to the logic circuit of the SAR ADC The module 208 generates the control clocks 222 and 223 of the comparator, and the level inversion control signals 220 and 221 of the bottom plate of the capacitor. In this example, the comparison between the first digit and the third to ten digits is compared and triggered by the ordinary dynamic comparator 207, and the next digit is established, while the comparison at the second digit is triggered by the comparison of two controllable asymmetric dynamic comparators 205, 206. next build;

The working sequence of the dynamic comparator of this example is shown as 415 and 416 in Figure 4, and its working process is explained as follows in conjunction with the sequence diagram:

(1) When CK is high, the gate voltage bootstrap switch 201 is turned on when CK is high, and the gate voltage bootstrap switch 201 is turned on to input The signal is sampled to the top plate of the binary capacitor array 202 of the analog-to-digital converter. At this time, the bottom plate of each group of capacitor groups in the capacitor array is connected to the common mode level V _cm , and the common dynamic comparator 207 and the controllable asymmetric comparison Both the devices 205 and 206 are turned off, and the analog-to-digital converter is in the sampling phase;

(2) When CK is at low level, the gate voltage bootstrap switch 201 is turned off, the capacitor array 202 is suspended, the charge remains unchanged, the input signal at the falling edge moment is kept on the capacitor array 202, and the analog-to-digital converter is in quantization stage. Under the control of the clock signals 222 and 223 generated by the logic circuit module 208 of the SAR ADC, the ordinary dynamic comparator 207 compares the input signal held when the signal 416 is high, and the data of the dynamic comparator 207 is transmitted to the logic of the SAR ADC. In the circuit module 208, the logical control signals 220 and 221 are generated by combinational logic, and the three sets of transmission gate switches 210 are used to control the symmetrical inversion direction of the bottom plate of the first capacitor group, the reference voltage is high or the reference voltage is low;

(3) After a short period of delay, the establishment of the level of the first bit has not yet been completed, and the two controllable asymmetric dynamic comparators start the 1.5-bit comparison of the second bit, and the symmetrical top plate level is cross-input Two controllable asymmetric dynamic comparators 205, 206, that is, nodes 203, 204 are cross-connected to the positive and negative input terminals of the two controllable asymmetric dynamic comparators 205, 206, in the logic circuit module 208 of the SAR ADC Under the control of the generated clock signals 222, 223, and when the signal 415 is at a high level, the set-up signals are compared, and the data of the two controllable asymmetric dynamic comparators 205, 206 are transmitted to the logic circuit module 208 of the SAR ADC. The logic generates logic control signals 220 and 221, and controls the bottom plate of the second group of capacitors to be connected to the reference voltage high level, the reference voltage low level or maintain the common mode level through three sets of transmission gate switches 210, controllable asymmetry The dynamic comparators 205, 206 will be turned off until the next quantization cycle;

(4) After a period of delay, after the second bit level is completely established, when the signal 416 is high, the ordinary dynamic comparator 207 is turned on, and the established signal is compared, and the data of the dynamic comparator 207 is transmitted to the logic circuit of the SAR ADC In module 208, logical control signals 220 and 221 are generated through combinational logic, and the three groups of transmission gate switches 210 are used to control the symmetrical inversion direction of the bottom plate of the first capacitor group, the reference voltage is high or the reference voltage is low;

(5) The data B2H and B2L quantized by the dynamic comparators 205 and 206, and the data B1, B3~B10 quantized by 207 are operated in the logic circuit module 208 of the SAR ADC according to the logical operation method in FIG. 5 to generate 10-bit binary The code is stored in the register and output on the rising edge of the next external sampling clock.

Although the content and advantages of the present invention have been disclosed in detail above, it must be noted that the scope of the present invention is not limited to specific embodiments such as methods and steps described in the description, and the scope of the present invention can be achieved without departing from the spirit and scope of the present invention. , any person of ordinary skill in the art can make many variations and modifications according to the content disclosed in the present invention, and these should also be regarded as the protection scope of the present invention.

Claims (7)

1. 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate a gradual approaching A/D converter, and it is special Levying and be, its circuit comprises: two identical boot-strapped switch (201), one group of symmetrical N position binary capacitor array (202), two controlled asymmetric dynamic comparators (205,206), a common dynamic comparer (207) and the number of SAR ADC Word application of logic circuit module (208)；Wherein:

Boot-strapped switch (201) contains a signal input part, an input end of clock, an outfan；

The group electric capacity Han N in N position binary capacitor array (202), wherein, N group capacitance and N-1 group capacitance are equal, all For unit electric capacity, from N-1 group to first group, two times of geometric ratios of capacitance are incremented by；The top plate of each group of electric capacity is mutually coupled with two Node (203,204), the sole plate of each group of electric capacity connects three groups of transmission gate switches (210,211)；

Each transmission gate switch (210,211) comprises a n type field effect transistor and a p type field effect transistor, both raceway grooves Parallel arrangement, both drain electrode ends are interconnected to constitute the drain electrode end of transmission gate circuit, and source terminal is interconnected to constitute transmission gate The source terminal of circuit, the gate terminal of n type field effect transistor constitutes the N gate terminal of transmission gate circuit, p type field effect transistor The P-gate that gate terminal constitutes transmission gate circuit is extreme；

Each controlled asymmetric dynamic comparator (205,206) has a positive input terminal, a negative input end, a clock input End, a positive output end and a negative output terminal；

Each common dynamic comparer (207) has the input of two not polarities, a clock control end, have two corresponding Outfan；

The Digital Logical Circuits module (208) of SAR ADC comprises:

Clock generation module, according to data miscarriage generating clock signal (222,223) of three comparators；

Digital Logic processing module, is used for producing the logic control letter of N position binary capacitor array (202) sole plate level upset Number (220,221) and register module storage output numeric data code.

2. 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate successive approximation ratio Relatively device, it is characterised in that two boot-strapped switch signal inputs connect differential signal input respectively, and input end of clock all connects whole The external control clock of successive approximation comparator, and sampling holding clock, the N position binary capacitor array that output termination is symmetrical (202) top plate and two nodes (203,204), sample phase by input signal collection on capacitor array top plate after open Closing and disconnect, magnitude of voltage is saved on the top plate of capacitor array.

3. 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate successive approximation ratio Relatively device, it is characterised in that in N position binary capacitor array (202), the top plate of each group of electric capacity is mutually coupled with boot-strapped switch (201), the input (205,206) of two controlled asymmetric dynamic comparators, the input of a common dynamic comparer And node (203,204) (207)；The sole plate of each group of electric capacity connects three groups of transmission gate switches (210,211), by SAR ADC's The logic control that application of logic circuit module (208) produces connects reference voltage high level, reference voltage low level or common mode electrical level；This Sample, the comparative result of each capacitor array top plate level processes via the application of logic circuit module (208) of SAR ADC and produces electricity Hold sole plate level upset control signal (220,221), control when the sole plate of the capacitance group of position connects reference voltage high level, ginseng Examine voltage low level or common mode electrical level, to produce the comparative level of next bit on capacitor array top plate.

4. 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate successive approximation ratio Relatively device, it is characterised in that the positive-negative input end intersection input N position two of two controlled asymmetry dynamic comparers (205,206) Two top plate voltages of system capacitor array (202), and intersection two nodes (203,204) of access；Clock input meets SAR The control signal (220,221) that the application of logic circuit module (208) of ADC produces, control controlled asymmetry dynamic comparer (205, 206) cut-off；Controlled asymmetry comparator (205,206) utilizes the load of latch in comparator asymmetric or ratio Compared with asymmetric to pipe threshold of input of device, one adjustable reference voltage of superposition in the side input signal of comparator, so Connection be equivalent to by the differential voltage of (202) two top plate of N position binary capacitor array and adjustable reference voltage ratio relatively, produce The output code of raw 1.5 bits, it is achieved 1.5 redundancy bits accelerate；The code of output is transferred to the application of logic circuit module of SAR ADC (208), the control clock (222,223) of comparator, and electric capacity sole plate level upset control signal (220,221) are produced.

5. 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate successive approximation ratio Relatively device, it is characterised in that two tops of a common dynamic comparer (207) input termination N position binary capacitor array (202) Polar plate voltage, and access two nodes (203,204)；Clock input connects the control that the application of logic circuit module (208) of SAR ADC produces Signal processed (220,221), controls cut-offfing of common dynamic comparer (207)；To N position binary capacitor array (202) two Top plate voltage compares in control, produces the output code of 1 bit；The code of output is transferred to the application of logic circuit module of SAR ADC (208), the control clock (222,223) of comparator, and electric capacity sole plate level upset control signal (220,221) are produced.

6. 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate successive approximation ratio Relatively device, it is characterised in that first is compared triggering next bit with the comparison of M to N position by common dynamic comparer (207) and build Vertical, and compared by two controlled asymmetric dynamic comparators (205,206) in the comparison of second to M position and trigger next bit and build Vertical.

7. 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate successive approximation ratio Relatively device, it is characterised in that its workflow is as follows:

When CK is high level, boot-strapped switch (201) is opened, and input signal samples the binary capacitor of analog-digital converter On the top plate of array (202), now the sole plate often organizing capacitance group of capacitor array meets common mode electrical level V_cm, common Dynamic comparison Device (207) and two controlled asymmetric comparators (205,206) are turned off, and analog-digital converter is in sample phase；

When CK is low level, boot-strapped switch (201) turns off, and binary capacitor array (202) is unsettled, and the quantity of electric charge is constant, under Dropping the input signal along the moment to be just held on capacitor array (202), analog-digital converter is in quantization stage；

Two clock signals that common dynamic comparer (207) produces in the application of logic circuit module (208) of SAR ADC (222, 223) comparing, under control, the input signal kept, the data of common dynamic comparer (207) are transferred to SAR ADC's In application of logic circuit module (208), combined logic produces two logic control signals (220,221), is opened by three groups of transmission gates Close (210) and control the symmetrical reverses direction of first capacitance group sole plate, reference voltage high level or reference voltage low level；Warp The delay of one period of short time, the most primary level sets up and not yet completes, two controlled asymmetric dynamic comparators (205, 206) start the comparison of 1.5 bits, symmetrical top plate level cross input two controlled asymmetric dynamic comparators (205, 206), two nodes (203,204) will intersect and access the positive input terminal of two controlled asymmetric dynamic comparators (205,206) And negative input end, right under the control of two clock signals (222,223) produced in the application of logic circuit module (208) of SAR ADC Setting up signal to compare, two controlled asymmetric dynamic comparator (205,206) data are transferred to the logic circuit of SAR ADC In module (208), combined logic produces two logic control signals (220,221), is controlled by three groups of transmission gate switches (210) The sole plate of second group of electric capacity is connect reference voltage high level, reference voltage low level or maintains common mode electrical level by system, repeats This step, until last position 1.5 bit-level；

After last position 1.5 bit-level compares end, two controlled asymmetric dynamic comparators (205,206) will be off, directly To the next quantization cycle；After this bit level is set up completely, common dynamic comparer (207) is opened, the ratio of figure place after completing Relatively, until N position；

The data that two controlled asymmetric dynamic comparators (205,206), common dynamic comparers (207) quantify are at SAR In the application of logic circuit module (208) of ADC through digital logical operation produce N position binary code, be stored in depositor, under The rising edge output of one external sampling clock.