TWI751807B - Vertical light-emitting diode structure with high current dispersion and high reliability - Google Patents
Vertical light-emitting diode structure with high current dispersion and high reliability Download PDFInfo
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Abstract
一種具高電流分散性且高信賴度的垂直式發光二極體結構,其包含一具有一中央區與一側邊區的導電基板;一發光半導體層設置於該中央區上;一歐姆接觸金屬層設置於該發光半導體層的中心處;一N型電極則設置於該側邊區,並透過一N型電極跨接結構連接該歐姆接觸金屬層與該N型電極;據此一工作電流為由該發光半導體層的中心處開始擴散而具有高電流分散性,而能夠解決該N型電極置放於邊緣設計所產生之局部高電流的散熱問題,又供打線的該N型電極設置於該側邊區的設計,可避免該N型電極置中造成之封裝體金導線干擾,同時該發光半導體層沒有受到應力破壞而脆裂的問題,後續製程也沒有打線牽扯而造成該發光半導體層裂痕或分離之風險而可增加信賴度。A vertical light-emitting diode structure with high current dispersion and high reliability, which comprises a conductive substrate with a central region and a side region; a light-emitting semiconductor layer is disposed on the central region; an ohmic contact metal The layer is arranged in the center of the light-emitting semiconductor layer; an N-type electrode is arranged in the side region, and the ohmic contact metal layer and the N-type electrode are connected through an N-type electrode bridging structure; accordingly, a working current is It starts to diffuse from the center of the light-emitting semiconductor layer and has high current dispersion, which can solve the heat dissipation problem of local high current caused by the design of the N-type electrode placed on the edge. The design of the side area can avoid the interference of the gold wires of the package caused by the centering of the N-type electrode. At the same time, the light-emitting semiconductor layer is not damaged by stress and is not brittle, and the subsequent process does not involve wire bonding to cause cracks in the light-emitting semiconductor layer. or risk of separation to increase reliability.
Description
本發明有關於發光二極體,尤其有關於具高電流分散性且高信賴度的垂直式發光二極體結構。 The present invention relates to light emitting diodes, and more particularly, to a vertical light emitting diode structure with high current dispersion and high reliability.
垂直式發光二極體,可發出高效率之軸向光,非常適用於需高工作電流與高光照度之應用。產品可使用於高光度殺菌(紫外光)、車用頭燈與尾燈(藍黃紅光)、投影機光源(藍綠紅)、紅外線安防偵測(紅外線)。優秀的高功率發光二極體(LED)元件除了高發光度與發光密度外,也需要有良好的信賴度。以汽車頭燈模組為例,一旦LED失效,會影響夜間安全,以車用LED之高標準規範,即使1ppm之微量失效,在汽車業也是需要改善。 Vertical light-emitting diodes can emit high-efficiency axial light, which is very suitable for applications requiring high operating current and high illuminance. Products can be used for high-light sterilization (ultraviolet light), vehicle headlights and taillights (blue-yellow-red light), projector light sources (blue-green-red), and infrared security detection (infrared). In addition to high luminosity and luminous density, excellent high-power light-emitting diode (LED) components also need to have good reliability. Take the car headlight module as an example, once the LED fails, it will affect the safety at night. With the high standards of automotive LEDs, even if a small amount of 1ppm fails, it needs to be improved in the automotive industry.
傳統的高功率垂直式發光二極體,晶片尺寸約1mm x 1mm,工作電流為1A或更高電流,其普遍之結構設計具有如下特徵:電極墊位於發光半導體層上方,提供打線使用,通常以較粗之金線有利大電流通過。具有輔助線(Finger)以指叉狀位於發光半導體層上方,越多輔助線設置於發光半導體層上,電流分散越佳,但也會增加遮光面積。P電極與封裝體的連結材料,為求良好導電與散熱,需使用AuSn(金錫合金),其底部有高平整度與低孔洞率之要求,以降低電流聚集與增加散熱性。 Traditional high-power vertical light-emitting diodes have a chip size of about 1mm x 1mm and an operating current of 1A or higher. The general structural design has the following characteristics: the electrode pads are located above the light-emitting semiconductor layer for wire bonding, usually with Thicker gold wires are more conducive to the passage of large currents. There are auxiliary lines (finger) located above the light-emitting semiconductor layer in a fork shape. The more auxiliary lines are arranged on the light-emitting semiconductor layer, the better the current dispersion is, but the light-shielding area is also increased. AuSn (gold-tin alloy) should be used as the connecting material between the P electrode and the package for good electrical conductivity and heat dissipation. The bottom has high flatness and low porosity to reduce current accumulation and increase heat dissipation.
當電極墊形成於發光半導體層之中心處,會具最佳之電流分散,不但可以提高發光效率,更具有良好的散熱性,避免電流集中的局部發熱問題。但電極墊在打線製程後,因封裝使用之粗金線會遮光與干擾光均勻性,目前取捨之後通常是將電極墊擺至發光半導體層之最側邊。但置於側 邊之電極墊,於高工作電流時,發光與發熱會集中在側邊,無法達到置中設計之良好電流分散效果。 When the electrode pad is formed in the center of the light-emitting semiconductor layer, it will have the best current dispersion, which can not only improve the luminous efficiency, but also have good heat dissipation and avoid the local heating problem of current concentration. However, after the wire bonding process of the electrode pad, since the thick gold wire used in the package will block light and interfere with light uniformity, the current choice is usually to place the electrode pad to the most side of the light-emitting semiconductor layer. but on the side The electrode pads on the side, when the working current is high, the light and heat will be concentrated on the side, and the good current dispersion effect of the center design cannot be achieved.
目前,垂直式發光二極體之失效模式,大致為以下四項:(1)電極墊偏邊設計於高工作電流時,因擴散不佳與邊緣高熱,造成發光不均與電極燒毀。(2)打線製程於發光半導體層表面上之電極墊進行打線,存在打傷發光半導體層之問題,降低信賴度。(3)於電極墊上之金導線,當封裝膠材被拉扯時,間接拉動發光半導體層,使其形成微裂痕或薄膜剝離,造成封裝體失效或不穩定。(4)若P電極與封裝體連結不平整或存在過多孔隙時,於高工作電流下形成局部熱點,進一步引發材料惡化,造成元件燒毀。 At present, the failure modes of vertical light-emitting diodes are roughly as follows: (1) When the electrode pad is biased and designed at high operating current, due to poor diffusion and high edge heat, uneven light emission and electrode burnout are caused. (2) Wire bonding process The electrode pad on the surface of the light-emitting semiconductor layer is wired, which has the problem of damaging the light-emitting semiconductor layer and reduces reliability. (3) When the gold wire on the electrode pad is pulled, the light-emitting semiconductor layer is indirectly pulled to form micro-cracks or film peeling, resulting in failure or instability of the package. (4) If the connection between the P electrode and the package body is uneven or there are too many pores, local hot spots will be formed under high operating current, which will further cause material deterioration and cause component burnout.
因此,如美國專利第US 8,319,250 B2號專利,其揭露了一種多導電柱技術,為讓N電極作為底部電極並延伸多根側壁絕緣的垂直向導電柱穿過P型半導體層、量子井層,並進入N型半導體層,使工作電流均勻分散至N型半導體層內,而P電極則設置側邊,以供封裝製程的打線使用。此一設計可藉由多導電柱讓工作電流得到最佳的分散性,且封裝製程的打線也不會衝擊到發光半導體層,因而改善了垂直式發光二極體之失效模式之(1)(2)(3)。但此結構包含數量多且精密之導電柱,其直徑通常為20-30μm,其內圓柱壁鍍極薄之絕緣物質,圓柱中心層為沉積高導電金屬。此結構精細但脆弱、製程複雜、成本高、製程條件窄、且失效品不易檢測,最嚴重的是當外部應力過大時(如物理性碰觸表面、封裝體製程之形變應力時..),導電柱會發生微裂痕,形成微導通道,造成元件立即失效或長期信賴度問題。 Therefore, such as US Patent No. US 8,319,250 B2, which discloses a multi-conductive pillar technology, in order to make the N electrode as the bottom electrode and extend a plurality of vertical conductive pillars with sidewall insulation through the P-type semiconductor layer, the quantum well layer, and Enter the N-type semiconductor layer, so that the working current is evenly dispersed into the N-type semiconductor layer, and the P electrode is provided with a side for the wire bonding of the packaging process. This design can obtain the best dispersion of the operating current through the multiple conductive pillars, and the wire bonding in the packaging process will not impact the light-emitting semiconductor layer, thus improving the failure mode of the vertical light-emitting diode (1)( 2)(3). However, this structure includes a large number of precise conductive pillars, the diameter of which is usually 20-30 μm, the inner cylindrical wall is plated with a very thin insulating material, and the central layer of the cylinder is deposited with highly conductive metal. The structure is fine but fragile, the process is complicated, the cost is high, the process conditions are narrow, and the failed products are not easy to detect. Conductive pillars can micro-crack, forming micro-conducting channels, causing immediate component failure or long-term reliability issues.
爰此,本發明之主要目的在於揭露具高電流分散性且高信賴度的垂直式發光二極體結構,以滿足高軸向性、高亮度與高信賴度的使用需求。 Therefore, the main purpose of the present invention is to disclose a vertical light emitting diode structure with high current dispersion and high reliability, so as to meet the application requirements of high axiality, high brightness and high reliability.
本發明為一種具高電流分散性且高信賴度的垂直式發光二極體結構,其包含一P型電極、一導電基板、一發光半導體層、一歐姆接觸金屬層、一N型電極跨接結構以及一N型電極;其中該導電基板的一側設置該P型電極,而該導電基板的另一側具有一中央區與一側邊區,且該側邊區相鄰該中央區。該發光半導體層設置於該導電基板的該中央區上,且該發光半導體層包含一P型半導體層、一量子井層(MQW)與一N型半導體層,該P型半導體層設置於該導電基板上,該量子井層(MQW)設置於該P型半導體層上,該N型半導體層設置於該量子井層上。而該歐姆接觸金屬層設置於該N型半導體層的中心處且歐姆接觸該N型半導體層。該N型電極跨接結構具有一跨接絕緣層與一跨接導電層,該跨接絕緣層橫跨設置於該N型半導體層與該導電基板的該側邊區上,且該跨接絕緣層緊鄰該歐姆接觸金屬層,而該跨接導電層設置於該跨接絕緣層上,且該跨接導電層一端連接該歐姆接觸金屬層,該跨接導電層另一端延伸至該導電基板的該側邊區。該N型電極為供打線製程使用,該N型電極設置於該跨接導電層上且位於該側邊區的上方。 The present invention is a vertical light-emitting diode structure with high current dispersion and high reliability, which comprises a P-type electrode, a conductive substrate, a light-emitting semiconductor layer, an ohmic contact metal layer, and an N-type electrode bridged The structure and an N-type electrode; wherein one side of the conductive substrate is provided with the P-type electrode, and the other side of the conductive substrate has a central area and a side area, and the side area is adjacent to the central area. The light-emitting semiconductor layer is disposed on the central region of the conductive substrate, and the light-emitting semiconductor layer includes a P-type semiconductor layer, a quantum well layer (MQW) and an N-type semiconductor layer, and the P-type semiconductor layer is disposed on the conductive substrate On the substrate, the quantum well layer (MQW) is arranged on the P-type semiconductor layer, and the N-type semiconductor layer is arranged on the quantum well layer. The ohmic contact metal layer is disposed at the center of the N-type semiconductor layer and ohmically contacts the N-type semiconductor layer. The N-type electrode bridging structure has a bridging insulating layer and a bridging conductive layer, the bridging insulating layer is disposed across the N-type semiconductor layer and the side region of the conductive substrate, and the bridging insulating layer The layer is adjacent to the ohmic contact metal layer, and the bridge conductive layer is disposed on the bridge insulation layer, and one end of the bridge conductive layer is connected to the ohmic contact metal layer, and the other end of the bridge conductive layer extends to the conductive substrate. the side area. The N-type electrode is used for the wire bonding process, and the N-type electrode is disposed on the bridge conductive layer and located above the side region.
據此,本發明相較習知技術的優點在於,採用垂直式發光二極體的結構設計,具有高軸向光特性;且該N型電極設置於該側邊區之上方,並將工作電流導引至該N型半導體層的中心處為起始點進行擴散,具高電流分散性,可避免該N型電極置中造成之封裝體金導線干擾以及該N型電極置放於邊緣設計所產生之局部高電流問題;另該N型電極下方未設置該發光半導體層,該發光半導體層於打線製程時沒有受到應力破壞而脆裂的問題,後 續製程也沒有打線牽扯而造成該發光半導體層裂痕或分離之風險,而可增加信賴度。 Accordingly, the advantages of the present invention compared with the prior art are that the structure design of the vertical light emitting diode is adopted, which has high axial light characteristics; Leading to the center of the N-type semiconductor layer is the starting point for diffusion, with high current dispersion, which can avoid the interference of the gold wires of the package caused by the centering of the N-type electrode and the placement of the N-type electrode at the edge of the design. The resulting local high current problem; in addition, the light-emitting semiconductor layer is not disposed under the N-type electrode, and the light-emitting semiconductor layer is not damaged by stress during the wire bonding process. There is no risk of cracking or separation of the light-emitting semiconductor layer caused by wire bonding in the subsequent process, thereby increasing reliability.
I:工作電流 I: working current
P1、P2、P3:電流密度等高線 P1, P2, P3: Current density contours
L:激發光 L: Excitation light
10:P型電極 10: P-type electrode
101:P型子電極 101: P-type sub-electrode
11:絕緣隔離道 11: Insulation isolation road
12:P型導電線路 12: P-type conductive line
20:導電基板 20: Conductive substrate
21:中央區 21: Central District
22:側邊區 22: Side Zone
23:緩衝層 23: Buffer layer
24:結合層 24: Bonding layer
25:替代基板 25: Alternative substrates
30:發光半導體層 30: Light-emitting semiconductor layer
31:P型半導體層 31: P-type semiconductor layer
32:量子井層 32: Quantum Well Layer
33:N型半導體層 33: N-type semiconductor layer
40:歐姆接觸金屬層 40: Ohmic contact metal layer
42:輔助導電線路 42: Auxiliary conductive line
421:輔助歐姆接觸金屬層 421: Auxiliary Ohmic Contact Metal Layer
50:N型電極跨接結構 50: N-type electrode jumper structure
51:跨接絕緣層 51: Jumper insulation
52:跨接導電層 52: Jumper conductive layer
60:N型電極 60: N-type electrode
70:輔助P型電極 70: Auxiliary P-type electrode
80:導電金屬光反射層 80: Conductive metal light reflection layer
81:電極反射層 81: Electrode reflection layer
82:跨接反射層 82: Bridge the reflective layer
90:輔助N型電極 90: Auxiliary N-type electrode
901:輔助歐姆接觸金屬層 901: Auxiliary Ohmic Contact Metal Layer
91:N型電極導電線路 91: N-type electrode conductive line
92:線路絕緣層 92: Line insulation
圖1,為本發明結構斷面示意圖。 Figure 1 is a schematic cross-sectional view of the structure of the present invention.
圖2,為本發明結構俯視示意圖。 FIG. 2 is a schematic top view of the structure of the present invention.
圖3,為本發明另一實施例的結構俯視示意圖。 FIG. 3 is a schematic top view of the structure of another embodiment of the present invention.
圖4,為本發明使用中小電流的電路路徑示意圖。 FIG. 4 is a schematic diagram of the circuit path of the present invention using medium and small currents.
圖5,為本發明使用大電流的電路路徑示意圖。 FIG. 5 is a schematic diagram of a circuit path of the present invention using a large current.
圖6,為本發明電流密度等高線示意圖。 FIG. 6 is a schematic diagram of the current density contour line of the present invention.
圖7,為本發明激發光反射路徑示意圖。 FIG. 7 is a schematic diagram of the reflection path of excitation light in the present invention.
圖8,為本發明另一實施例的激發光反射路徑示意圖。 FIG. 8 is a schematic diagram of a reflection path of excitation light according to another embodiment of the present invention.
圖9,為本發明又一實施例的激發光反射路徑示意圖。 FIG. 9 is a schematic diagram of a reflection path of excitation light according to another embodiment of the present invention.
圖10,為本發明大尺寸晶片N電極的結構俯視示意圖。 FIG. 10 is a schematic top view of the structure of an N electrode of a large-sized wafer according to the present invention.
圖11,為本發明大尺寸晶片P電極的結構仰視示意圖。 FIG. 11 is a schematic bottom view of the structure of the large-size wafer P electrode of the present invention.
為俾使 貴委員對本發明之特徵、目的及功效,有著更加深入之瞭解與認同,茲列舉一較佳實施例並配合圖式說明如後:請參閱圖1與圖2所示,本發明為一種具高電流分散性且高信賴度的垂直式發光二極體結構,其包含一P型電極10、一導電基板20、一發光半導體層30、一歐姆接觸金屬層40、一N型電極跨接結構50以及一N型電極60。其中該導電基板20的一側設置該P型電極10,而該導電基板20的另一側具有一中央區21與一側邊區22,且該側邊區22相鄰該中央區21。
In order to enable your members to have a more in-depth understanding and recognition of the features, purposes and effects of the present invention, a preferred embodiment is listed and described in conjunction with the drawings as follows: please refer to FIG. 1 and FIG. 2, the present invention is as follows: A vertical light-emitting diode structure with high current dispersion and high reliability, which includes a P-
該發光半導體層30設置於該導電基板20的該中央區21上,且該發光半導體層30包含一P型半導體層31、一量子井層32(MQW)與一N型半導體層33,該P型半導體層31設置於該導電基板20上,該量子井層32(MQW)設置於該P型半導體層31上,該N型半導體層33設置於該量子井層32上。
The light-emitting
該歐姆接觸金屬層40設置於該N型半導體層33的中心處且歐姆接觸該N型半導體層33。該N型電極跨接結構50具有一跨接絕緣層51與一跨接導電層52,該跨接絕緣層51橫跨設置於該N型半導體層33與該導電基板20的該側邊區22上,且該跨接絕緣層51緊鄰該歐姆接觸金屬層40,而該跨接導電層52設置於該跨接絕緣層51上,且該跨接導電層52一端連接該歐姆接觸金屬層40,該跨接導電層52另一端延伸至該導電基板20的該側邊區22。而該N型電極60為供打線製程使用,該N型電極60設置於該跨接導電層52上且位於該側邊區22的上方。
The ohmic
在一較佳實施例中,該導電基板20可以包含一緩衝層23、一結合層24與一替代基板25,該跨接絕緣層51與該發光半導體層30設置於該緩衝層23上,該P型電極10設置於該替代基板25,而該結合層24黏結固定該緩衝層23與該替代基板25。
In a preferred embodiment, the
另,本發明更可以包含一輔助P型電極70,該輔助P型電極70設置於該導電基板20的該側邊區22上。且該側邊區22為圍繞該中央區21,且該輔助P型電極70與該N型電極60位於該中央區21不同側的該側邊區22上,如圖2所示。
In addition, the present invention may further include an auxiliary P-
在另一實施例中,該側邊區22同樣圍繞該中央區21,而該輔助P型電極70與該N型電極60位於該中央區21相同側的該側邊區22上,如圖3所示。
In another embodiment, the
請參閱圖4所示,當要驅使該發光半導體層30發光時,需要於該發光半導體層30中產生一工作電流I,如圖1所示的結構,當該工作電流I僅需中小電流(低亮度使用)時,可以選擇該P型電極10與該輔助P型電極70的任一個作為一第一極(圖4所示為選擇該P型電極10),並讓該N型電極60作為一第二極,並於該第一極與該第二極之間供給一工作電壓(圖未示),即可以產生該工作電流I,由該歐姆接觸金屬層40進入該發光半導體層30。
Please refer to FIG. 4 , when the light-emitting
請再參閱圖5所示,當該工作電流I需要高亮度使用時,則可以讓該P型電極10與該輔助P型電極70皆作為一第一極,並讓該N型電極60作為一第二極,並於該第一極與該第二極之間供給大電壓的該工作電壓,以產生大電流的該工作電流I,但由於大電流的該工作電流I有兩個路徑,因此會分散而藉以降低該工作電流I的電流密度,避免局部高溫而導致元件提早老化甚至燒毀的問題。
Please refer to FIG. 5 again, when the working current I requires high brightness, both the P-
請再參閱圖2或圖3所示,為了讓進一步分散電流,以更分散且均勻的通過該發光半導體層30,本發明更可以包含至少一輔助導電線路42,該至少一輔助導電線路42設置於該N型半導體層33上且連接該歐姆接觸金屬層40(如圖1所示),並該至少一輔助導電線路42分別透過一輔助歐姆接觸金屬層421連接該N型半導體層33。在一實施例中,該至少一輔助導電線路42為複數個並朝四周發散。如圖6所示,為繪製有電流密度等高線P1、P2,其中電流密度等高線P1大於電流密度等高線P2,亦即電流密度在該N型半導體層33的中心處為最高,並朝四周逐漸降低。
Please refer to FIG. 2 or FIG. 3 again, in order to further disperse the current and pass the light-emitting
並請一併參閱圖7、圖8與圖9所示,另為了增加亮度,該導電基板20於相鄰該發光半導體層30的區域可以設置一與該P型半導體31歐姆接觸之導電金屬光反射層80,且該歐姆接觸金屬層40與該N型半導體層33的接觸
面可以設置一朝該N型半導體層33外凸的電極反射層81,該電極反射層81的構成為該歐姆接觸金屬層40為高反射性金屬搭配下方的N型半導體層33而做成外凸反射面。其中該電極反射層81的外形為選自單一凸面反射鏡(如圖7所示)、連續凸面反射鏡(如圖8所示)與多重微斜反射鏡(如圖9所示)的任一種。透過該導電金屬光反射層80與該電極反射層81的搭配設置,在該發光半導體層30產生一激發光L時,原本被該歐姆接觸金屬層40遮蔽的該激發光L,可以透過該導電金屬光反射層80與該電極反射層81的多次反射而由該發光半導體層30的一光射出面射出,可增加該激發光L的光取出率,進而提升發光亮度。同樣的,N型電極跨接結構50亦可以此方法減少遮光,該跨接導電層52與該跨接絕緣層51之接觸面可以設置一朝該跨接絕緣層51外凸的跨接反射層82。詳細的做法為使用高反射率之金屬作為該跨接導電層52,同時使用高透光之絕緣材料(如SiO2,SiN)作為該跨接絕緣層51,將該跨接絕緣層51(透明絕緣層)上方與該跨接導電層52接觸之平面製作成向下凸面結構(如蝕刻方式),搭配上方之該跨接導電層52作為高反射金屬,即讓該N型電極跨接結構50形成反射鏡,其形狀可以為選自單一凸面柱反射鏡、連續凸面反射鏡與多重微斜反射鏡的任一種,藉以利用該導電金屬光反射層80與該跨接反射層82的多次反射,增加該激發光L的光取出率。
Please also refer to FIG. 7 , FIG. 8 and FIG. 9 . In addition, in order to increase the brightness, the
請再參閱圖10所示,當該發光半導體層30為更大尺寸的晶片時(例如3mmx3mm),可利用模塊擴充概念來配置線路,更詳細的說,本發明可以更包含複數輔助N型電極90,該複數輔助N型電極90以該歐姆接觸金屬層40為中心並散佈地設置於該N型半導體層33上,且該複數輔助N型電極90分別藉由一設置於該N型半導體層33上的N型電極導電線路91連接該歐姆接觸金屬層40,且為了清楚表示該歐姆接觸金屬層40與該N型電極導電線路91
的連接關係,該歐姆接觸金屬層40上方的該跨接導電層52為省略未繪製。並該複數輔助N型電極90分別透過一輔助歐姆接觸金屬層901連接該N型半導體層33。且為了讓工作電流(未繪製於圖10中)更加分散,該複數N型電極導電線路91與該N型半導體層33的接觸面可以分別具有一線路絕緣層92,也就是說,工作電流僅能由該歐姆接觸金屬層40與該複數輔助N型電極90之處進入該N型半導體層33,由工作電流的電流密度等高線P3可知,可以讓部分的工作電流導引到該N型半導體層33的四周,即該複數輔助N型電極90之處,因而可以提升發光均勻度。
Please refer to FIG. 10 again, when the light-emitting
請再參閱圖11所示,在大尺寸晶片的應用上,如圖1所示,同樣可以包含該輔助P型電極70,該輔助P型電極70設置於該導電基板20的該側邊區22上。且為了進一步分散電流,該P型電極10與該導電基板20(圖11中沒有繪製)可以被複數絕緣隔離道11分割,該複數絕緣隔離道11可以利用半導體的蝕刻製程形成間隙而達到絕緣的效果,該複數絕緣隔離道11可以使該P型電極10分割形成複數P型子電極101,且讓該複數P型子電極101的位置分別對應該複數輔助N型電極90,同時其中一個該P型子電極101為連接該輔助P型電極70,又連接該輔助P型電極70的該P型子電極101,透過複數設置於該複數絕緣隔離道11的P型導電線路12選擇性的連接該複數P型子電極101,讓連接該輔助P型電極70的該複數P型子電極101為間隔排列。也就是說,僅有部分的該複數P型子電極101電性連接至該輔助P型電極70,故當需要更高電流操作與更強制P側電流分散使用時,可指定電流只通過P型電極10或該輔助P型電極70,搭配該歐姆接觸金屬層40產生工作電流,可進一步強制分散電流,提升熱源分散度,以增加散熱效果。
Please refer to FIG. 11 again. In the application of large-sized wafers, as shown in FIG. 1 , the auxiliary P-
如上所述,本發明的特點至少包含: As mentioned above, the features of the present invention include at least:
1.採用垂直式發光二極體的結構設計,具有高軸向光特性。 1. The structure design of vertical light-emitting diodes is adopted, which has high axial light characteristics.
2.利用N型電極跨接結構的設置,可讓該N型電極設置於該側邊區之上方,並將工作電流導引至該N型半導體層的中心處為起始點進行擴散,具高電流分散性,可避免該N型電極置中造成之封裝體金導線干擾以及該N型電極置放於邊緣設計所產生之局部高電流問題,除可提升發光效率外,也能增加元件信賴度。 2. Using the arrangement of the N-type electrode bridging structure, the N-type electrode can be arranged above the side region, and the operating current can be guided to the center of the N-type semiconductor layer as the starting point for diffusion. High current dispersion can avoid the interference of gold wires in the package caused by the placement of the N-type electrode in the center and the local high current problem caused by the placement of the N-type electrode on the edge design, which can not only improve the luminous efficiency, but also increase the reliability of components Spend.
3.透過該電極反射層與該跨接反射層的設置,搭配該導電金屬光反射層,將本來被遮蔽的光利用多次反射,由該光射出面射出,增加該激發光的光取出率。 3. Through the setting of the electrode reflection layer and the bridge reflection layer, and the conductive metal light reflection layer, the originally shielded light is reflected multiple times and emitted from the light exit surface to increase the light extraction rate of the excitation light .
4.該N型電極下方未設置該發光半導體層,該發光半導體層於打線製程時沒有受到應力破壞而脆裂的問題,可避免打線打傷該N型半導體層,同時可使打線力道安全值增加,有利打線良好接合,能大幅減少長期信賴性風險。 4. The light-emitting semiconductor layer is not provided under the N-type electrode, and the light-emitting semiconductor layer is not damaged by stress during the wire bonding process and becomes brittle, which can prevent the N-type semiconductor layer from being damaged by wire bonding, and can make the wire bonding strength safe. The increase is beneficial to the good bonding of wire bonding, which can greatly reduce the long-term reliability risk.
5.後續封裝製程的封裝膠有應力產生時,沒有打線牽扯而造成該發光半導體層裂痕或分離之風險。 5. When the encapsulant of the subsequent encapsulation process is under stress, there is no risk of cracking or separation of the light-emitting semiconductor layer caused by wire bonding.
6.利用該P型電極與該輔助P型電極的雙電極設計,有效分散工作電流,有利更高電流操作,可有效改善該P型電極與該輔助P型電極與封裝體連結不平整或存在過多孔隙時,造成之局部高熱、元件失效之風險。 6. Using the double-electrode design of the P-type electrode and the auxiliary P-type electrode can effectively disperse the working current, which is conducive to higher current operation, and can effectively improve the unevenness or existence of the connection between the P-type electrode and the auxiliary P-type electrode and the package body. When there are too many pores, the risk of local high heat and component failure is caused.
7.當該發光半導體層為更大尺寸的晶片時(例如3mm x 3mm),可利用模塊擴充概念,透過該複數輔助N型電極、該複數N型電極導電線路與該複數線路絕緣層的設置,分散導引工作電流由該歐姆接觸金屬層與該複數輔助N型電極之處進入該N型半導體層,而有效分散工作電流以提升發光均勻度。 7. When the light-emitting semiconductor layer is a larger size chip (eg 3mm x 3mm), the concept of module expansion can be used, through the arrangement of the plurality of auxiliary N-type electrodes, the plurality of N-type electrode conductive lines and the plurality of line insulating layers , disperse and guide the working current into the N-type semiconductor layer from the ohmic contact metal layer and the plurality of auxiliary N-type electrodes, and effectively disperse the working current to improve the uniformity of light emission.
8.相較美國專利第US8319250號專利而言,本發明製程相對簡單、成本低,且具有更好的結構強度,更耐物理性外力破壞;亦增加了P型電極之電流分散功效。 8. Compared with US Patent No. US8319250, the present invention has a relatively simple manufacturing process, low cost, better structural strength, and greater resistance to physical external force damage; it also increases the current dispersion effect of the P-type electrode.
10:P型電極 10: P-type electrode
20:導電基板 20: Conductive substrate
21:中央區 21: Central District
22:側邊區 22: Side Zone
23:緩衝層 23: Buffer layer
24:結合層 24: Bonding layer
25:替代基板 25: Alternative substrates
30:發光半導體層 30: Light-emitting semiconductor layer
31:P型半導體層 31: P-type semiconductor layer
32:量子井層 32: Quantum Well Layer
33:N型半導體層 33: N-type semiconductor layer
40:歐姆接觸金屬層 40: Ohmic contact metal layer
50:N型電極跨接結構 50: N-type electrode jumper structure
51:跨接絕緣層 51: Jumper insulation
52:跨接導電層 52: Jumper conductive layer
60:N型電極 60: N-type electrode
70:輔助P型電極 70: Auxiliary P-type electrode
80:導電金屬光反射層 80: Conductive metal light reflection layer
81:電極反射層 81: Electrode reflection layer
82:跨接反射層 82: Bridge the reflective layer
Claims (17)
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TW201010131A (en) * | 2008-08-27 | 2010-03-01 | Ledarts Opto Corp | Structure and method for manufacturing GaN LED with highly reflective film |
TW201135972A (en) * | 2010-04-13 | 2011-10-16 | Univ Nat Cheng Kung | Light emitting diode |
US20140103291A1 (en) * | 2010-12-17 | 2014-04-17 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy | Inverted Light-Emitting Diode Having Plasmonically Enhanced Emission |
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TW201010131A (en) * | 2008-08-27 | 2010-03-01 | Ledarts Opto Corp | Structure and method for manufacturing GaN LED with highly reflective film |
TW201135972A (en) * | 2010-04-13 | 2011-10-16 | Univ Nat Cheng Kung | Light emitting diode |
US20140103291A1 (en) * | 2010-12-17 | 2014-04-17 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy | Inverted Light-Emitting Diode Having Plasmonically Enhanced Emission |
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