[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

TWI603447B - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

Info

Publication number
TWI603447B
TWI603447B TW104143814A TW104143814A TWI603447B TW I603447 B TWI603447 B TW I603447B TW 104143814 A TW104143814 A TW 104143814A TW 104143814 A TW104143814 A TW 104143814A TW I603447 B TWI603447 B TW I603447B
Authority
TW
Taiwan
Prior art keywords
blocking structure
chip package
laser
laser blocking
insulating layer
Prior art date
Application number
TW104143814A
Other languages
English (en)
Other versions
TW201624653A (zh
Inventor
溫英男
劉建宏
李士儀
姚皓然
Original Assignee
精材科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 精材科技股份有限公司 filed Critical 精材科技股份有限公司
Publication of TW201624653A publication Critical patent/TW201624653A/zh
Application granted granted Critical
Publication of TWI603447B publication Critical patent/TWI603447B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31127Etching organic layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0235Shape of the redistribution layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02372Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02377Fan-in arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02381Side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/03001Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03002Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/031Manufacture and pre-treatment of the bonding area preform
    • H01L2224/0311Shaping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346Plating
    • H01L2224/03462Electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346Plating
    • H01L2224/03464Electroless plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/039Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391Forming a passivation layer after forming the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05025Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • H01L2224/05548Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05567Disposition the external layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13022Disposition the bump connector being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13024Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14678Contact-type imagers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Laser Beam Processing (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Geometry (AREA)

Description

晶片封裝體及其製造方法
本發明是有關一種晶片封裝體及其製造方法。
指紋感測裝置(finger print sensor)或射頻感測裝置(RF sensor)需利用平坦的感測面來偵測訊號。若感測面不平整,會影響感測裝置偵測時的準確度。舉例來說,當指頭按壓於指紋感測裝置的感測面時,若感測面不平整,將難以偵測到完整的指紋。
此外,上述的感測裝置在製作時,會先於晶圓中形成矽穿孔(Through Silicon Via;TSV),使焊墊從矽穿孔裸露。接著,會以化學氣相沉積法(Chemical Vapor Deposition;CVD)在焊墊上與矽穿孔的壁面上形成絕緣層。之後,還需透過圖案化製程於焊墊上的絕緣層形成開口。一般而言圖案化製程包含曝光、顯影與蝕刻製程。在後續製程中,重佈線層便可形成在絕緣層上並電性連接絕緣層開口中的焊墊。
然而,化學氣相沉積與圖案化製程均需耗費大量的製程時間與機台的成本。
本發明之一態樣係提供一種晶片封裝體,包含一晶片。晶片具有一導電墊,以及相對之一第一表面與一第二表面,其中導電墊位於第一表面。一第一穿孔自第二表面朝第一表面延伸,並暴露出導電墊,而一雷射阻擋結構,位於第一穿孔中的導電墊上,且雷射阻擋結構之一上表面位於第二表面上。一第一絕緣層位於第二表面與雷射阻擋結構上,並具有相對於第二表面的一第三表面,而一第二穿孔自第三表面朝第二表面延伸,並暴露雷射阻擋結構。一導電層,位於第三表面上與第二穿孔中,並接觸雷射阻擋結構。
根據本發明部分實施方式,更包含一保護層,位於第三表面上與導電層上,並具有一開口暴露出導電層,而一外部導電連結位於此開口中並接觸導電層。
根據本發明部分實施方式,第二穿孔的孔徑小於第一穿孔的孔徑。
根據本發明部分實施方式,第二穿孔只暴露出雷射阻擋結構。
根據本發明部分實施方式,雷射阻擋結構為一實心結構或一空心結構。
根據本發明部分實施方式,第二穿孔的一孔壁為一粗糙面。
根據本發明部分實施方式,雷射阻擋結構之材質為銅。
根據本發明部分實施方式,第一絕緣層之材質包含環氧樹脂。
根據本發明部分實施方式,導電層在第一絕緣層之第三表面上的厚度大於導電層在第二穿孔的孔壁上的厚度。
根據本發明部分實施方式,導電層在第二穿孔的孔壁上的厚度大於導電層在雷射阻檔結構上的厚度。
本發明之另一態樣係提供一種晶片封裝體的製造方法,包含下述步驟。先提供暫時接合的一晶圓與一支撐件,其中晶圓包含一第一表面以及相對於第一表面之一第二表面,一導電墊位於第一表面上,其中支撐件覆蓋第一表面與導電墊,而一雷射阻擋結構位於晶圓中,並位於導電墊上。接著研磨晶圓令使第二表面低於雷射阻擋結構之一上表面,再形成一第一絕緣層於第二表面上並覆蓋雷射阻擋結構之上表面,其中第一絕緣層具有相對第二表面的一第三表面。然後使用一雷射移除部分第一絕緣層以形成一第二穿孔,其中雷射停止於雷射阻擋結構。最後形成一導電層於第三表面上與第二穿孔中的雷射阻擋結構上。
根據本發明部分實施方式,更包含形成一保護層於第一絕緣層的第三表面與導電層上,接著圖案化保護層以形成一開口暴露導電層。
根據本發明部分實施方式,更包含形成一外部導電連結於開口中並接觸導電層。
根據本發明部分實施方式,更包含移除支撐件,接著沿著一切割道切割晶圓、第一絕緣層與保護層,以形成一晶片封裝體。
根據本發明部分實施方式,使用雷射移除第一絕緣層時,雷射對準雷射阻擋結構。
根據本發明部分實施方式,提供晶圓包含下述步驟。形成一第一穿孔自第二表面朝第一表面延伸,以暴露導電墊。接著形成雷射阻擋結構於第一穿孔中的導電墊上。
根據本發明部分實施方式,係以電鍍形成雷射阻擋結構於第一穿孔中。
根據本發明部分實施方式,係以印刷、塗佈形成第一絕緣層於第二表面上。
根據本發明部分實施方式,形成第一絕緣層於第二表面上更包含塗佈、壓印、製模或研磨第一絕緣層之第三表面。
100‧‧‧晶片封裝體
110‧‧‧晶片
112‧‧‧第一表面
114‧‧‧第二表面
116‧‧‧導電墊
117‧‧‧第二絕緣層
118‧‧‧第一穿孔
400‧‧‧晶片封裝體
410‧‧‧晶片
412‧‧‧第一表面
414‧‧‧第二表面
416‧‧‧導電墊
417‧‧‧第二絕緣層
424‧‧‧空穴
120‧‧‧雷射阻擋結構
122‧‧‧上表面
130‧‧‧第一絕緣層
132‧‧‧第三表面
134‧‧‧第二穿孔
135‧‧‧孔壁
136‧‧‧底部
140‧‧‧導電層
150‧‧‧保護層
152‧‧‧開口
160‧‧‧外部導電連結
D1、D2‧‧‧孔徑
T1、T2、T3‧‧‧厚度
418‧‧‧第一穿孔
420‧‧‧雷射阻擋結構
422‧‧‧上表面
430‧‧‧第一絕緣層
432‧‧‧第三表面
434‧‧‧第二穿孔
435‧‧‧孔壁
436‧‧‧底部
440‧‧‧導電層
450‧‧‧保護層
452‧‧‧開口
460‧‧‧外部導電連結
610~670‧‧‧步驟
700‧‧‧晶圓
710‧‧‧支撐件
720‧‧‧切割道
800‧‧‧晶圓
810‧‧‧支撐件
820‧‧‧切割道
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之詳細說明如下:第1圖繪示根據本發明部分實施方式之一種晶片封裝體的上視圖;第2圖繪示根據本發明部分實施方式中,第1圖之晶片封裝體沿線段A-A的剖面圖; 第3圖繪示根據本發明部分實施方式中,第2圖之晶片封裝體的局部放大圖;第4圖繪示根據本發明其他部分實施方式中,第1圖之晶片封裝體沿線段A-A的剖面圖;第5圖繪示根據本發明部分實施方式中,第4圖之晶片封裝體的局部放大圖;第6圖繪示根據本發明部分實施方式中晶片封裝體的製造方法流程圖;第7A-7G繪示本發明部分實施方式中,第2圖的晶片封裝體在製程各個階段的剖面圖;以及第8A-8I繪示本發明部分實施方式中,第4圖的晶片封裝體在製程各個階段的剖面圖。
以下將以圖式揭露本發明之複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
請先參閱第1圖,第1圖繪示根據本發明部分實施方式之一種晶片封裝體的上視圖,而第2圖繪示第1圖之晶片封裝體沿線段A-A的剖面圖。請同時參閱第1圖與第2圖,晶片封裝體100包含一晶片110、一雷射阻擋結構120、一第一絕緣層 130、一導電層140、一保護層150與一外部導電連結160。晶片110為一感測晶片,具有相對的一第一表面112與一第二表面114,其中第一表面112係作為感測面,且一導電墊116位於晶片110的第一表面114上。在本發明之部分實施例中,晶片110之材質為矽(silicon)、鍺(Germanium)或III-V族元素,但不以此為限。晶片的第二表面114具有一第一穿孔118自第二表面114朝第一表面112延伸,並暴露導電墊116。一雷射阻擋結構120位於此第一穿孔118中的導電墊116上,且雷射阻擋結構120的一上表面122位於第二表面114上。在本發明之部分實施例中,雷射阻擋結構120為實心結構,代表雷射阻擋結構120完全填滿第一穿孔118。在本發明之部分實施例中,一第二絕緣層117位於第一穿孔118中,並環繞雷射阻擋結構120。其中,第二絕緣層117所使用的材料為氧化矽、氮化矽、氮氧化矽或其它合適之絕緣材料。
請繼續參閱第1圖與第2圖,第一絕緣層130位於第二表面114與雷射阻擋結構120上。其中,第一絕緣層130之材質為環氧樹脂(epoxy)。第一絕緣層130更具有相對於第二表面114的一第三表面132,一第二穿孔134自第三表面132朝第二表面114延伸,並暴露出雷射阻擋結構120。其中此第二穿孔134為一雷射穿孔,更詳細的說,係使用一雷射來貫穿第一絕緣層130以形成第二穿孔134,而雷射阻擋結構120作為雷射的終點。藉由雷射的使用,第二穿孔134的孔徑D2可小於第一穿孔118的孔徑D1,對於微小化設計有所助益。在本發明之部分實施例中,第二穿孔134中只暴露出雷射阻擋結構120。 在本發明之其他部分實施例中,雷射阻擋結構120之材質選用能阻擋雷射的導電材料,例如銅。
請繼續參閱第1圖與第2圖,一導電層140位於第一絕緣層130的第三表面132上,且部分的導電層140位於第二穿孔134中,並接觸暴露於第二穿孔134中的雷射阻擋結構120。一保護層150位於第一絕緣層130的第三表面132與導電層140上,且保護層150具有一開口152暴露出導電層140。此外,外部導電連結160設置於開口152中,並接觸導電層140。外部導電連結160透過導電層140,雷射阻擋結構120電性連接至導電墊116。
在本發明之其他部分實施例中,外部導電連結160為焊球、凸塊等業界熟知之結構,且形狀可以為圓形、橢圓形、方形、長方形,並不用以限制本發明。在本發明之其他部分實施例中,導電層140之材質選用導電材料,例如銅。
在本發明之其他部分實施例中,晶片封裝體100可以為指紋感測裝置(finger print sensor)或射頻感測裝置(RF sensor),但並不用以限制本發明。
第3圖繪示第2圖之晶片封裝體100的局部放大圖。如第2圖所示,在使用雷射形成第二穿孔134時,雷射阻擋結構120作為雷射的終點。雖有部分的雷射阻擋結構120被移除,但雷射無法貫穿雷射阻擋結構120。由於係以雷射形成第二穿孔134,第二穿孔134的孔壁135與底部136均為一粗糙面,且雷射阻擋結構120暴露於第二穿孔134的底部136。
在第二穿孔134形成後,接著形成導電層140於第一絕緣層130的第三表面132、第二穿孔134的孔壁135與底部136上,使得導電層140電性連接至雷射阻擋結構120。由於導電層140係以電鍍形成,其在第一絕緣層130之第三表面132上的厚度T1大於導電層140在第二穿孔134的孔壁135上的厚度T2,且導電層140在第二穿孔134的孔壁135上的厚度T2大於導電層140在第二穿孔134的底部136上的厚度T3。
請繼續參閱第4圖,第4圖為本發明其他部分實施方式中,第1圖之晶片封裝體沿線段A-A的剖面圖。此處需注意的是相同元件之材質並不再做詳述。
如第4圖所示,晶片封裝體400包含一晶片410、一雷射阻擋結構420、一第一絕緣層430、一導電層440、一保護層450與一外部導電連結460。晶片410為一感測晶片,具有相對的一第一表面412與一第二表面414,其中第一表面412係作為感測面,且一導電墊416位於晶片410的第一表面412上。晶片的第二表面414具有一第一穿孔418自第二表面414朝第一表面412延伸,並暴露導電墊416。雷射阻擋結構420位於此第一穿孔418中,且雷射阻擋結構420的一上表面422位於第二表面414上。在本發明之部分實施例中,一第二絕緣層417位於第一穿孔418中,並環繞雷射阻擋結構420。其中,第二絕緣層417所使用的材料為氧化矽、氮化矽、氮氧化矽或其它合適之絕緣材料。在本發明之其他部分實施例中,雷射阻擋結構420為空心結構,意指雷射阻擋結構420並未完全填滿第一穿孔418,而有一空穴424於雷射阻擋結構420中。
請繼續參閱第4圖,第一絕緣層430位於第二表面414與雷射阻擋結構420上。第一絕緣層430更具有相對於第二表面414的一第三表面432,一第二穿孔434自第三表面432朝第二表面414延伸,並暴露出雷射阻擋結構420。其中此第二穿孔434為一雷射穿孔,更詳細的說,係使用一雷射來貫穿第一絕緣層430以形成第二穿孔434,而雷射阻擋結構420作為雷射的終點。藉由雷射的使用,第二穿孔434的孔徑D2可小於第一穿孔418的孔徑D1,對於微小化設計有所助益。在本發明之部分實施例中,第二穿孔434中只暴露出雷射阻擋結構420。
請繼續參閱第4圖,一導電層440位於第一絕緣層430的第三表面432上,且部分的導電層440位於第二穿孔434中,並接觸暴露於第二穿孔434中的雷射阻擋結構420。保護層450位於第一絕緣層430的第三表面432與導電層440上,且保護層450具有一開口452暴露出導電層440。此外,外部導電連結460位於開口452中,並接觸導電層440,外部導電連結460透過導電層440,雷射阻擋結構420電性連接至導電墊416。
在本發明之其他部分實施例中,晶片封裝體400可以為指紋感測裝置(finger print sensor)或射頻感測裝置(RF sensor),但並不用以限制本發明。
第5圖繪示第4圖之晶片封裝體400的局部放大圖。如第5圖所示,在使用雷射形成第二穿孔434時,雷射阻擋結構420作為雷射的終點。雖有部分的雷射阻擋結構420被移除,但雷射並無法貫穿雷射阻擋結構420。由於係以雷射形 成第二穿孔434,第二穿孔434的孔壁435與底部436均為一粗糙面,且雷射阻擋結構420暴露於第二穿孔434的底部436。
在第二穿孔434形成後,接著形成導電層440於第一絕緣層430的第三表面432、第二穿孔434的孔壁435與底部436上,使得導電層440電性連接至雷射阻擋結構420。由於導電層440係以電鍍形成,其在第一絕緣層430之第三表面432上的厚度T1大於導電層440在第二穿孔434的孔壁435上的厚度T2,且導電層440在第二穿孔434的孔壁435上的厚度T2大於導電層440在第二穿孔434的底部436上的厚度T3。
請接著參閱第6圖,第6圖繪示根據本發明部分實施方式之晶片封裝體的製造方法流程圖。請同時參閱第7A-7G圖以進一步理解晶片封裝體的製造方法,第7A-7G繪示第2圖的晶片封裝體在製程各個階段的剖面圖。
請先參閱步驟610與第7A圖,提供暫時接合的一晶圓700與一支撐件710,其中晶圓700包含一導電墊116、以及相對之一第一表面112與一第二表面114,導電墊116位於第一表面112上,而支撐件710覆蓋第一表面112與導電墊116。此外,一雷射阻擋結構120位於晶圓700中的導電墊116上。晶圓700意指切割後可形成複數個第2圖的晶片110之半導體基板,而支撐件710可提供晶圓700支撐力,防止晶圓700在後續製程中因受力而破裂。在本實施例中,係直接使用內部已具有雷射阻擋結構120的晶圓700,而第二絕緣層117環繞著雷射阻擋結構120。在此需說明的是,雖第7A圖繪示的雷射阻擋結構 120為一實心結構,但並不以此為限,雷射阻擋結構120亦可為一空心結構。
請繼續參閱步驟620與第7B圖,研磨晶圓700令使第二表面114低於雷射阻擋結構120之一上表面122。對晶圓700的第二表面114進行研磨以減少晶圓700的厚度,而硬度較高的雷射阻擋結構120在研磨的過程中會逐漸凸出第二表面114,使雷射阻擋結構120之上表面122暴露出來。
請繼續參閱步驟630與第7C圖,形成一第一絕緣層130於第二表面114上並覆蓋雷射阻擋結構120之上表面122,其中第一絕緣層130具有相對第二表面114的一第三表面132。在此步驟中,印刷、塗佈環氧樹酯於晶圓700之第二表面114上,並覆蓋凸出第二表面114的雷射阻擋結構120,以形成第一絕緣層130。在本發明之部分實施例中,在形成第一絕緣層130後,可依製程需求塗佈、壓印、製模或研磨第一絕緣層130的第三表面132,以減少第一絕緣層130的厚度。
請繼續參閱步驟640與第7D圖,使用一雷射移除部分的第一絕緣層130以形成一第二穿孔134,其中雷射停止於雷射阻擋結構120,並暴露雷射阻擋結構120。在此步驟中,雷射對準雷射阻擋結構120之上表面122發射,並貫穿上表面122上方的第一絕緣層130。而雷射阻擋結構120作為雷射之終點,使雷射阻擋結構120之上表面122於第二穿孔134中暴露出來。在本發明之部分實施例中,第二穿孔134只暴露出雷射阻擋結構120之上表面122。
請繼續參閱步驟650與第7E圖,形成一導電層140於第三表面132與第二穿孔134中的雷射阻擋結構120上。待第二穿孔134形成於第一絕緣層130中後,可化鍍加電鍍導電材料於第一絕緣層130的第三表面132、第二穿孔134的孔壁與第二穿孔133中的雷射阻擋結構120上,以形成導電層140。
請繼續參閱步驟660與第7F圖,形成一保護層150於第一絕緣層130的第三表面132與導電層140上,並圖案化保護層150以形成一開口152暴露導電層140。接著再形成一外部導電連結160於此開口152中。可藉由刷塗絕緣材料於第一絕緣層130的第三表面132與導電層140上,以形成保護層150。其中,絕緣材料可為環氧樹酯。接著,再圖案化保護層150以形成開口152,使部分的導電層140從保護層150的開口152暴露出來後,再形成外部導電連結160於此開口152中。外部導電連結160可藉由導電層140與雷射阻擋結構120與導電墊116電性連接。
在本發明之部分實施例中,可在形成保護層150後,即移除晶圓700的第一表面112上的支撐件710。在本發明之其他部分實施例中,可在形成外部導電連結160後,再移除晶圓700的第一表面112上的支撐件710。
最後請參閱步驟670與第7G圖,沿著一切割道720切割晶圓700、第一絕緣層130與保護層150,以形成一晶片封裝體。沿著切割道720將晶圓600分割,以分離晶圓700上的數個晶片,形成如第2圖所示之晶片封裝體100。
請繼續參閱第8A-8I圖以進一步理解本發明其他部分實施方式的晶片封裝體製造方法,第8A-8I圖繪示第4圖的晶片封裝體在製程各個階段的剖面圖。
請先參閱第8A圖,提供暫時接合的一晶圓800與一支撐件810,其中晶圓800包含一導電墊416、以及相對之一第一表面412與一第二表面414,導電墊416位於第一表面412上,而支撐件710覆蓋第一表面412與導電墊116。晶圓800意指切割後可形成複數個第4圖的晶片410之半導體基板,而支撐件810可提供晶圓800支撐力,防止晶圓800在後續製程中因受力而破裂。在本實施例中,使用的晶圓800內部並不具有雷射阻擋結構,需再於後續步驟中形成雷射阻擋結構於晶圓800中。
請繼續參閱第8B圖,形成一第一穿孔418自第二表面414朝該第一表面412延伸,並暴露導電墊416。形成第一穿孔418的方式例如可以是以微影蝕刻,但不以此為限。在本發明之其他部分實施例中,會再沉積絕緣材料覆蓋第一穿孔418的孔壁與底部。接著再使用微影蝕刻的方式移除第一穿孔418底部的絕緣材料,以形成第二絕緣層417,使導電墊416在第一穿孔418中暴露。
請繼續參閱第8C圖,形成一雷射阻擋結構420於第一穿孔418中的導電墊416上。在此步驟中,可利用例如是濺鍍(sputtering)、蒸鍍(evaporating)、電鍍(electroplating)或無電鍍(electroless plating)的方式沉積導電材料來形成雷射阻擋結構420。在本實施例中,雷射阻擋結構420並未完全 填滿第一穿孔418,而有一空穴424位於雷射阻擋結構420中。在此需說明的是,雖第8C圖繪示的雷射阻擋結構420為一空心結構,但並不以此為限,雷射阻擋結構420亦可為一實心結構。在本發明之部分實施例中,雷射阻擋結構422的上表面422可低於晶圓800的第二表面414,或如第8C圖所示與第二表面414齊平。
請繼續參閱第8D圖,研磨晶圓800的第二表面414令使第二表面414低於雷射阻擋結構420之上表面422。對晶圓800的第二表面414進行研磨以減少晶圓800的厚度,而硬度較高的雷射阻擋結構420在研磨的過程中會逐漸凸出第二表面414,使雷射阻擋結構420之上表面422暴露出來。在研磨晶圓800之第二表面414的同時也會移除部分的第二絕緣層417。
請繼續參閱第8E圖,形成一第一絕緣層430於第二表面414上並覆蓋雷射阻擋結構420之上表面422,其中第一絕緣層430具有相對第二表面414的一第三表面432。在此步驟中,印刷、塗佈環氧樹酯於晶圓800之第二表面414,並覆蓋凸出第二表面414的雷射阻擋結構420,以形成第一絕緣層430。在本發明之部分實施例中,在形成第一絕緣層430後,可依製程需求塗佈、壓印、製模或研磨第一絕緣層430的第三表面432,以減少第一絕緣層430的厚度。
請繼續參閱第8F圖,使用一雷射移除部分的第一絕緣層430以形成一第二穿孔434,其中雷射停止於雷射阻擋結構420,並暴露雷射阻擋結構420。在此步驟中,雷射對準雷射阻擋結構420之上表面422發射,並貫穿上表面422上方的 第一絕緣層430。而雷射阻擋結構420作為雷射之終點,使雷射阻擋結構420之上表面422於第二穿孔434中暴露出來。在本發明之部分實施例中,第二穿孔434只暴露出雷射阻擋結構420之上表面422。
請繼續參閱第8G圖,形成一導電層440於第三表面432上與第二穿孔434中的雷射阻擋結構420上。待第二穿孔434形成於第一絕緣層430中後,可化鍍加電鍍導電材料於第一絕緣層430的第三表面432、第二穿孔434的孔壁與第二穿孔434中的雷射阻擋結構420上,以形成導電層440。
請繼續參閱第8H圖,形成一保護層450於第一絕緣層430的第三表面432與導電層440上,並圖案化保護層450以形成一開口452暴露導電層440。接著再形成一外部導電連結460於此開口452中。可藉由刷塗絕緣材料於第一絕緣層430的第三表面432與導電層440上,以形成保護層450。其中,絕緣材料可為環氧樹酯。接著,再圖案化保護層450以形成開口452,使部分的導電層440從保護層450的開口452暴露出來後,再形成外部導電連結460於此開口452中。外部導電連結460可藉由導電層440與雷射阻擋結構420與導電墊416電性連接。
在本發明之部分實施例中,可在形成保護層450後,即移除晶圓800的第一表面412上的支撐件810。在本發明之其他部分實施例中,可在形成外部導電連結460後,再移除晶圓800的第一表面412上的支撐件810。
最後請參閱第8I圖,沿著一切割道820切割晶圓800、第一絕緣層430與保護層450,以形成一晶片封裝體。沿著切割道820將晶圓800分割,以分離晶圓800上的數個晶片,形成如第4圖所示之晶片封裝體400。
由上述本發明實施例可知,本發明具有下列優點。本發明之晶片封裝體與其製備方法可省略習知化學氣相沉積絕緣層與圖案化絕緣層的製程。此外,使用雷射更能縮小穿孔的孔徑,對於微小化設計有所助益,進而節省製程的時間與機台的成本。且晶片的第一表面未經額外的加工,因此平坦性佳,可提升晶片封裝體偵測時的準確度。
雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧晶片封裝體
110‧‧‧晶片
112‧‧‧第一表面
114‧‧‧第二表面
116‧‧‧導電墊
117‧‧‧第二絕緣層
118‧‧‧第一穿孔
120‧‧‧雷射阻擋結構
122‧‧‧上表面
130‧‧‧第一絕緣層
132‧‧‧第三表面
134‧‧‧第二穿孔
140‧‧‧導電層
150‧‧‧保護層
152‧‧‧開口
160‧‧‧外部導電連結
D1、D2‧‧‧孔徑

Claims (19)

  1. 一種晶片封裝體,包含:一晶片,包含一導電墊,以及相對之一第一表面與一第二表面,其中該導電墊位於該第一表面上;一第一穿孔自該第二表面朝該第一表面延伸,並暴露出該導電墊;一雷射阻擋結構,位於該第一穿孔中的該導電墊上,其中該雷射阻擋結構之一上表面位於該第二表面上,且該上表面背對於該導電墊;一第一絕緣層,位於該第二表面與該雷射阻擋結構上,該第一絕緣層具有相對於該第二表面的一第三表面;一第二穿孔自該第三表面朝該第二表面延伸,並暴露該雷射阻擋結構,使得該雷射阻擋結構的該上表面位於該第二穿孔中;以及一導電層,位於該第三表面上與該第一絕緣層朝向該第二穿孔的壁面上,並接觸位在該第二穿孔中的該雷射阻擋結構的該上表面。
  2. 如請求項1所述之晶片封裝體,更包含:一保護層,位於該第三表面與該導電層上,該保護層具有一開口暴露出該導電層;以及一外部導電連結,位於該開口中並接觸該導電層。
  3. 如請求項1所述之晶片封裝體,其中該第二穿孔的孔徑小於該第一穿孔的孔徑。
  4. 如請求項1所述之晶片封裝體,其中該第二穿孔只暴露出該雷射阻擋結構。
  5. 如請求項1所述之晶片封裝體,其中該雷射阻擋結構為一實心結構或一空心結構。
  6. 如請求項1所述之晶片封裝體,其中該第二穿孔的一孔壁與一底部為一粗糙面。
  7. 如請求項1所述之晶片封裝體,其中該雷射阻擋結構之材質為銅。
  8. 如請求項1所述之晶片封裝體,其中該第一絕緣層之材質包含環氧樹脂。
  9. 如請求項1所述之晶片封裝體,其中該導電層在該第一絕緣層之該第三表面上的厚度大於該導電層在該第二穿孔的一孔壁上的厚度。
  10. 如請求項1所述之晶片封裝體,其中該導電層在該第二穿孔的一孔壁上的厚度大於該導電層在該雷射阻檔結構上的厚度。
  11. 一種晶片封裝體的製造方法,包含: 提供暫時接合的一晶圓與一支撐件,該晶圓包含:一第一表面以及相對於該第一表面之一第二表面;一導電墊位於該第一表面上,其中該支撐件覆蓋該第一表面與該導電墊;以及一雷射阻擋結構位於該晶圓中的該導電墊上;研磨該晶圓令使該第二表面低於該雷射阻擋結構之一上表面;形成一第一絕緣層於該第二表面上並覆蓋該雷射阻擋結構之該上表面,其中該第一絕緣層具有相對該第二表面的一第三表面;使用一雷射移除部分該第一絕緣層以形成一第二穿孔,其中該雷射停止於該雷射阻擋結構;以及形成一導電層於該第三表面上與該第二穿孔中的該雷射阻擋結構上。
  12. 如請求項11所述之晶片封裝體的製造方法,更包含:形成一保護層於該第一絕緣層的該第三表面與該導電層上;以及圖案化該保護層以形成一開口暴露該導電層。
  13. 如請求項12所述之晶片封裝體的製造方法,更包含形成一外部導電連結於該開口中並接觸該導電層。
  14. 如請求項13所述之晶片封裝體的製造方法,更包含:移除該支撐層;以及沿著一切割道切割該晶圓、該第一絕緣層與該保護層,以形成一晶片封裝體。
  15. 如請求項11所述之晶片封裝體的製造方法,其中使用該雷射移除該第一絕緣層時,該雷射對準該雷射阻擋結構。
  16. 如請求項11所述之晶片封裝體的製造方法,其中提供該晶圓包含:形成一第一穿孔自該第二表面朝該第一表面延伸,以暴露該導電墊;以及形成該雷射阻擋結構於該第一穿孔中的該導電墊上。
  17. 如請求項16所述之晶片封裝體的製造方法,其中係以電鍍形成該雷射阻擋結構於該第一穿孔中。
  18. 如請求項11所述之晶片封裝體的製造方法,其中係以印刷、塗佈形成該第一絕緣層於該第二表面上。
  19. 如請求項11所述之晶片封裝體的製造方法,其中形成該第一絕緣層於該第二表面上更包含:塗佈、壓印、製模或研磨該第一絕緣層之該第三表面。
TW104143814A 2014-12-30 2015-12-25 晶片封裝體及其製造方法 TWI603447B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201462098179P 2014-12-30 2014-12-30

Publications (2)

Publication Number Publication Date
TW201624653A TW201624653A (zh) 2016-07-01
TWI603447B true TWI603447B (zh) 2017-10-21

Family

ID=56165087

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104143814A TWI603447B (zh) 2014-12-30 2015-12-25 晶片封裝體及其製造方法

Country Status (3)

Country Link
US (2) US9640405B2 (zh)
CN (1) CN105742254B (zh)
TW (1) TWI603447B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI581325B (zh) * 2014-11-12 2017-05-01 精材科技股份有限公司 晶片封裝體及其製造方法
JP6640780B2 (ja) * 2017-03-22 2020-02-05 キオクシア株式会社 半導体装置の製造方法および半導体装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100112579A1 (en) * 2007-03-26 2010-05-06 Fundacion Gaiker Method and device for the detection of genetic material by polymerase chain reaction
TW201044500A (en) * 2009-03-26 2010-12-16 Stats Chippac Ltd Semiconductor device and method of forming a thin wafer without a carrier
US20120168792A1 (en) * 2010-12-31 2012-07-05 Samsung Electronics Co., Ltd. Heterojunction structures of different substrates joined and methods of fabricating the same
TW201344884A (zh) * 2012-04-27 2013-11-01 Taiwan Semiconductor Mfg 半導體裝置及其製造方法
TW201428946A (zh) * 2013-01-10 2014-07-16 Xintec Inc 影像感測晶片封裝體及其製作方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6222276B1 (en) * 1998-04-07 2001-04-24 International Business Machines Corporation Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
KR20090055316A (ko) * 2007-11-28 2009-06-02 삼성전자주식회사 반도체 패키지와, 이를 구비하는 전자 기기 및 반도체패키지의 제조방법
US8236609B2 (en) * 2008-08-01 2012-08-07 Freescale Semiconductor, Inc. Packaging an integrated circuit die with backside metallization
US8890268B2 (en) * 2010-02-26 2014-11-18 Yu-Lung Huang Chip package and fabrication method thereof
US8536672B2 (en) * 2010-03-19 2013-09-17 Xintec, Inc. Image sensor package and fabrication method thereof
KR101718011B1 (ko) * 2010-11-01 2017-03-21 삼성전자주식회사 반도체 패키지 및 그 제조방법
CN102623426B (zh) * 2012-03-31 2015-04-22 苏州晶方半导体科技股份有限公司 半导体封装方法
TWI569400B (zh) * 2012-06-11 2017-02-01 精材科技股份有限公司 晶片封裝體及其形成方法
TWI512930B (zh) * 2012-09-25 2015-12-11 Xintex Inc 晶片封裝體及其形成方法
US9935090B2 (en) * 2014-02-14 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US10026671B2 (en) * 2014-02-14 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
TWI582918B (zh) * 2014-11-12 2017-05-11 精材科技股份有限公司 晶片封裝體及其製造方法
TWI581325B (zh) * 2014-11-12 2017-05-01 精材科技股份有限公司 晶片封裝體及其製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100112579A1 (en) * 2007-03-26 2010-05-06 Fundacion Gaiker Method and device for the detection of genetic material by polymerase chain reaction
TW201044500A (en) * 2009-03-26 2010-12-16 Stats Chippac Ltd Semiconductor device and method of forming a thin wafer without a carrier
US20120168792A1 (en) * 2010-12-31 2012-07-05 Samsung Electronics Co., Ltd. Heterojunction structures of different substrates joined and methods of fabricating the same
TW201344884A (zh) * 2012-04-27 2013-11-01 Taiwan Semiconductor Mfg 半導體裝置及其製造方法
TW201428946A (zh) * 2013-01-10 2014-07-16 Xintec Inc 影像感測晶片封裝體及其製作方法

Also Published As

Publication number Publication date
US20170047300A1 (en) 2017-02-16
US9780050B2 (en) 2017-10-03
CN105742254A (zh) 2016-07-06
US20160190063A1 (en) 2016-06-30
US9640405B2 (en) 2017-05-02
TW201624653A (zh) 2016-07-01
CN105742254B (zh) 2018-11-02

Similar Documents

Publication Publication Date Title
TWI458071B (zh) 晶片封裝體及其製造方法
TWI591764B (zh) 晶片封裝體及其製造方法
TWI459485B (zh) 晶片封裝體的形成方法
TWI534969B (zh) 晶片封裝體及其製造方法
TWI511253B (zh) 晶片封裝體
KR101177885B1 (ko) 웨이퍼 레벨 패키징 캡 및 그 제조방법
TWI505413B (zh) 晶片封裝體及其製造方法
TWI429023B (zh) 半導體裝置及其半導體製程
TW201539678A (zh) 封裝半導體裝置以及形成封裝半導體裝置之方法
TWI500132B (zh) 半導體裝置之製法、基材穿孔製程及其結構
TWI581325B (zh) 晶片封裝體及其製造方法
US8178977B2 (en) Semiconductor device and method of manufacturing the same
TWI600125B (zh) 晶片封裝體及其製造方法
JP2009124042A (ja) 半導体装置
TWI582918B (zh) 晶片封裝體及其製造方法
JP6058268B2 (ja) インターポーザ及びその形成方法
TWI540655B (zh) 半導體結構及其製造方法
US20160355393A1 (en) Chip package and manufacturing method thereof
TWI603407B (zh) 晶片封裝體及其製造方法
JP2007036060A (ja) 半導体装置及びその製造方法
TWI603447B (zh) 晶片封裝體及其製造方法
JP5361264B2 (ja) 半導体装置
JP5313294B2 (ja) 半導体装置
JP2007088163A (ja) 半導体チップの製造方法
JP2013239756A (ja) 半導体装置